Method for preparing heterojunction solar cell, and heterojunction solar cell

Abstract

The present application belongs to the field of solar cell preparation. Disclosed are a method for preparing a heterojunction solar cell, and a heterojunction solar cell. The method for preparing a heterojunction solar cell comprises: performing texturing treatment on an illuminated surface and an unilluminated surface of a semiconductor substrate, so as to respectively form a first textured structure and a second textured structure on the illuminated surface and the unilluminated surface; forming a mask layer on the first textured structure; performing wet chemical treatment on the second textured structure, and performing leveling treatment on at least part of a pyramid structure of the second textured structure, so as to obtain a refined micro-structure; removing the mask layer; forming a second intrinsic passivation layer on the refined micro-structure, and forming a first intrinsic passivation layer on the first textured structure; and forming a first-conductivity-type doped layer on the first intrinsic passivation layer, and forming a second-conductivity-type doped layer on the second intrinsic passivation layer. By means of the present application, the passivation effect can be improved, the coating process time for a back face of a battery is reduced, and a functional layer on the back face is thinned, thereby improving the battery performance.

Description

Preparation method of heterojunction solar cell and heterojunction solar cell Technical Field

[0001] The present application belongs to the technical field of solar cell preparation, and specifically relates to a preparation method of a heterojunction solar cell and a heterojunction solar cell. Background Art

[0002] Heterojunction (HJT) solar cells are a highly efficient type of crystalline silicon solar cell, offering advantages such as a simple manufacturing process, low process temperature, high photoelectric conversion efficiency, and ease of thinning. The existing HJT solar cell manufacturing process includes texturing the silicon wafer, forming a second intrinsic passivation layer, a first intrinsic passivation layer, a first conductivity type doped layer, a second conductivity type doped layer, a double-sided TCO film, and screen printing electrodes. The texturing process is typically a wet process, which removes mechanical damage, increases surface area, significantly reduces reflectivity, and removes impurities.

[0003] However, existing heterojunction solar cell fabrication methods still have certain shortcomings. For example, the texturing method results in the same textured structure on both sides of the cell. The textured structure on the back of the existing cell increases the coating surface area, requiring longer coating times and placing greater demands on the anti-epitaxial effect. Therefore, there is an urgent need to find effective technical solutions to address or alleviate one or more of these issues. Summary of the Invention

[0004] In view of the above-mentioned problems, the present invention aims to at least partially solve one of the technical problems in the related art. To this end, the present invention provides a method for preparing a heterojunction solar cell and a heterojunction solar cell, which are primarily used to alleviate the problems of the current back-side textured structure, such as the poor passivation effect and long back-side coating process time. The present invention can improve the passivation effect, reduce the back-side coating process time of the cell, and thus improve cell performance.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] According to one aspect of the present application, an embodiment of the present application provides a method for preparing a heterojunction solar cell, the method comprising:

[0007] Performing texturing on the light-receiving surface and the backlight surface of the semiconductor substrate to form a first textured surface structure and a second textured surface structure on the light-receiving surface and the backlight surface, respectively; the first textured surface structure and the second textured surface structure both have a pyramid structure;

[0008] forming a mask layer on the first textured structure;

[0009] performing a wet chemical treatment on the second velvet structure to flatten at least a portion of the pyramid structure of the second velvet structure to obtain a refined microstructure;

[0010] removing the mask layer;

[0011] forming a second intrinsic passivation layer on the refined microstructure and forming a first intrinsic passivation layer on the first textured structure;

[0012] A first conductive type doping layer is formed on the first intrinsic passivation layer, and a second conductive type doping layer is formed on the second intrinsic passivation layer.

[0013] In addition, the method for preparing a heterojunction solar cell according to the present application may also have the following additional technical features:

[0014] In some embodiments, the first velvet structure is a pyramidal velvet structure;

[0015] The refined microstructure includes a plurality of block structures, wherein at least some of the surfaces of the block structures are overlapped.

[0016] In some embodiments, the size of the block structure is 0.1 μm to 20 μm.

[0017] In some embodiments, the wet chemical treatment uses an alkaline solution, which includes a KOH solution or a NaOH solution. The mass percentage concentration of the alkaline solution is 1% to 10%, and the treatment temperature is 40° C. to 80° C.

[0018] In some embodiments, the alkaline solution is a KOH solution;

[0019] The mass percentage concentration of the alkaline solution is 3% to 7%;

[0020] The treatment temperature is 45°C to 78°C.

[0021] In some embodiments, the material of the mask layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride;

[0022] And / or, the thickness of the mask layer is ≤100 nm.

[0023] In some embodiments, the mask layer is made of a silicon oxide film, and the silicon oxide film is a UV silicon oxide film obtained through a UV oxidation process.

[0024] In some embodiments, the mask layer is removed by using an acidic solution at a temperature of 25° C. to 45° C.

[0025] In some embodiments, the acidic solution includes an HF solution, and the mass percent concentration of the acidic solution is 5% to 10%.

[0026] In some embodiments, after forming the second conductive type doped layer on the second intrinsic passivation layer, the method further includes:

[0027] forming a first transparent conductive layer on the first conductive type doped layer, and forming a second transparent conductive layer on the second conductive type doped layer;

[0028] A first electrode is formed on the first transparent conductive layer, and a second electrode is formed on the second transparent conductive layer.

[0029] In some embodiments, the second conductive type doped layer is a microcrystalline P layer, the thickness of the microcrystalline P layer is 10 nm to 50 nm, and the thickness of the second transparent conductive layer is 50 nm to 200 nm.

[0030] According to another aspect of the present application, an embodiment of the present application provides a heterojunction solar cell, wherein the heterojunction solar cell is manufactured using the aforementioned method for manufacturing a heterojunction solar cell, and the heterojunction solar cell comprises:

[0031] A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, the first surface being a light-receiving surface and the second surface being a light-backed surface;

[0032] a first velvet structure located on the light-receiving surface, a first intrinsic passivation layer located on the first velvet structure, a first conductive type doped layer located on the first intrinsic passivation layer, a first transparent conductive layer located on the first conductive type doped layer, and a first electrode located on the first transparent conductive layer;

[0033] A refined microstructure located on the backlight surface, a second intrinsic passivation layer located on the refined microstructure, a second conductive type doped layer located on the second intrinsic passivation layer, a second transparent conductive layer located on the second conductive type doped layer, and a second electrode located on the second transparent conductive layer.

[0034] The implementation of the technical solution of the present invention has at least the following beneficial effects:

[0035] In an embodiment of the present application, a method for preparing a heterojunction solar cell is provided, in which, after texturing the double sides of the semiconductor substrate, a light-receiving surface is protected, that is, a mask layer is formed on the light-receiving surface, and then a wet chemical treatment is performed on the second velvet structure on the backlight surface to remove at least part of the pyramid structure in the second velvet structure, so that the second velvet structure is flattened and refined to obtain a refined microstructure; and then the mask layer is removed. In this way, by performing a wet chemical treatment on the backlight side of the battery, the velvet structures on both sides of the battery are different, that is, the light-receiving side of the battery is a velvet light-trapping structure, and the backlight side is a refined microstructure surface, which can increase the passivation effect. Compared with ordinary velvet, the refined microstructure has a better anti-epitaxial passivation effect, which can reduce the coating process time of the battery backlight side, thereby increasing battery performance, and can also reduce the coating process cavity, thereby saving equipment costs; the refined microstructure surface of the backlight side can reduce the surface area of ​​the backlight side accordingly compared to the pyramid-shaped velvet structure, which in turn helps to reduce the thickness of the various functional layers of the backlight side, such as the doping layer, the transparent conductive layer, etc., to a certain extent. In addition, the refined microstructure surface of the backlight side provides sufficient adhesion for the subsequent printed grid lines, which can alleviate the problem of grid delamination caused by direct polishing on the back side; the refined microstructure of the backlight side is easier to passivate, which has an effect on improving the battery opening voltage, such as increasing the battery efficiency by more than 0.2%.

[0036] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG1 is a schematic flow chart of a method for preparing a heterojunction solar cell according to some exemplary embodiments of the present application;

[0038] FIG2 is a schematic structural diagram of a heterojunction solar cell provided by some exemplary embodiments of the present application;

[0039] FIG3 is a schematic diagram showing the size of the blocks on the backlight surface under different wet processing conditions.

[0040] Description of reference numerals:

[0041] 10- semiconductor substrate;

[0042] 11-first suede structure; 12-first intrinsic passivation layer; 13-first conductive type doped layer; 14-first transparent conductive layer; 15-first electrode;

[0043] 21 - refined microstructure; 22 - second intrinsic passivation layer; 23 - second conductivity type doped layer; 24 - second transparent conductive layer; 25 - second electrode. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0045] As shown in FIG1 and FIG2 , in some embodiments, a method for preparing a heterojunction solar cell is provided, the method comprising:

[0046] A semiconductor substrate 10 (e.g., a silicon substrate) is provided. The semiconductor substrate 10 includes a first surface and a second surface disposed opposite each other. The semiconductor substrate 10 includes two opposing surfaces, namely, the first surface and the second surface, also known as the front and back surfaces. The front surface of the semiconductor substrate is the surface facing the sun (i.e., the surface exposed to sunlight), and the back surface of the semiconductor substrate is the surface facing away from the sun. For example, the first surface of the semiconductor substrate may be the front surface, also known as the light-receiving surface (the N-type doped surface or N-face); the second surface of the semiconductor substrate may be the back surface, also known as the surface facing away from the sun (the P-type doped surface or P-face).

[0047] It should be noted that the preparation method of this embodiment is not limited to the specific type of semiconductor substrate (e.g., silicon wafer). For example, it can be a single-crystal silicon substrate, a polycrystalline silicon substrate, or a quasi-single-crystal silicon substrate. The silicon substrate can be P-type doped or N-type doped. In other words, the silicon substrate can be an N-type silicon wafer or a P-type silicon wafer. Optionally, this embodiment uses an N-type single-crystal silicon wafer as the silicon substrate.

[0048] The light-receiving surface and the backlight surface of the semiconductor substrate 10 are textured to form a first texture structure 11 and a second texture structure on the light-receiving surface and the backlight surface, respectively; that is, the first texture structure 11 is formed on the light-receiving surface, and the second texture structure is formed on the backlight surface; the first texture structure 11 and the second texture structure both have a pyramid structure.

[0049] A mask layer is formed on the first textured structure 11 ; that is, the first textured structure on the light-receiving surface is mask-protected, and a mask protection layer is provided on the first textured structure.

[0050] The second velvet structure is subjected to wet chemical treatment, and at least part of the pyramid structure of the second velvet structure is flattened to obtain a refined microstructure 21; by performing wet chemical treatment on the second velvet structure on the backlight side, at least part of the pyramid structure of the second velvet structure can be removed, flattened, refined, or the surface of the refined microstructure is flat.

[0051] Then, the mask layer on the first textured structure 11 is removed;

[0052] Then, a double-sided intrinsic passivation layer is prepared, a second intrinsic passivation layer 22 is formed on the refined microstructure 21, and a first intrinsic passivation layer 12 is formed on the first velvet structure 11; then, a doping layer is prepared, a first conductive type doping layer 13 is formed on the first intrinsic passivation layer 12, and a second conductive type doping layer 23 is formed on the second intrinsic passivation layer 22.

[0053] By adopting the technical solution of the preparation method of the heterojunction solar cell provided in this embodiment, after the texturing treatment, by adding the process steps of front mask protection, back wet chemical treatment, and mask removal, the front and back of the battery have different surface structures, that is, the front of the battery cell has a velvet light-trapping structure, and the back has a refined microstructure surface, thereby increasing the passivation effect, reducing the coating process time of the back of the battery, and thinning the thickness of the functional layers on the back of the battery, such as the doping layer and the transparent conductive layer, thereby increasing the battery performance, reducing the battery weight, reducing the coating process cavity, and saving equipment costs.

[0054] At the same time, the heterojunction battery preparation method of the embodiment of the present invention has a simple process and is easy to implement. The prepared refined microstructure has a better anti-epitaxial passivation effect than the ordinary velvet surface, and exhibits a 1mV Voc gain effect on the battery cell. Moreover, the refined microstructure of the backlight surface has sufficient adhesion for the subsequent printing of the grid line, which can alleviate the grid delamination problem caused by direct polishing on the back. The prepared refined microstructure is easier to passivate, which has an effect on improving the battery opening voltage, thereby increasing the battery efficiency by more than 0.2%. The refined microstructure of the backlight surface can reduce the surface area of ​​the back side, and the coating time can be greatly shortened.

[0055] By forming a refined microstructure on the backlight side, the backlight side's surface area can be reduced compared to a pyramid-shaped velvet surface, which can appropriately shorten deposition time and, while ensuring battery performance, reduce the thickness of functional layers on the backlight side, such as the doping layer and transparent conductive layer. This application has demonstrated through practical experimental examples that the microcrystalline P layer can be thinned by approximately 40%, and the back TCO layer can be thinned by over 50%.

[0056] In some specific embodiments, the method for preparing a heterojunction solar cell comprises the following steps:

[0057] S100: Provide a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite each other; wherein the first surface may be a light-receiving surface (N-surface), and the second surface may be a light-backed surface (P-surface). Of course, in other embodiments, the first surface may also be a light-backed surface (P-surface), and the second surface may be a light-receiving surface (N-surface), which will not be further described herein.

[0058] The light-receiving surface and the backlight surface of the semiconductor substrate are textured to form a first texture structure and a second texture structure on the light-receiving surface and the backlight surface respectively; that is, the first texture structure is formed on the light-receiving surface and the second texture structure is formed on the backlight surface; the first texture structure and the second texture structure both have a pyramid structure.

[0059] Optionally, the first velvet structure is a pyramid-shaped velvet structure. The second velvet structure may also be a pyramid-shaped velvet structure. Generally, pyramid-shaped velvet structures all have a pyramid structure.

[0060] By texturing the semiconductor substrate on both sides, the light-receiving surface can be provided with a uniform textured light-trapping structure. For example, the light-trapping structure can be a pyramid-shaped textured structure formed by alkaline etching. That is, the front side of the semiconductor substrate has an anti-reflective textured surface, and the anti-reflective textured surface is pyramid-shaped.

[0061] It should be noted that the specific operation mode and process conditions of the above-mentioned texturing treatment can be selected and regulated by those skilled in the art according to actual conditions. For example, a texturing cleaning machine is used to place the semiconductor substrate in an alkaline texturing solution using an alkali texturing method for texturing treatment. Optionally, the alkaline texturing solution includes a KOH solution or a NaOH solution, and the mass percentage concentration of the alkaline texturing solution needs to be controlled below 10%, preferably 1% to 5%, for example, it can be 1%, 2%, 3%, 4%, 5%, etc.; the texturing time is 3min to 30min, for example, it can be 3min, 4min, 5min, 6min, 8min, 10min, 20min, etc.; the reaction temperature is 50 to 85°C, for example, it can be 50°C, 60°C, 70°C, 80°C, 85°C, etc. Optionally, the texturing treatment also uses a texturing additive, and the mass percentage concentration of the texturing additive is 0.5% to 5%. Among them, the texturing additive can regulate the etching effect of the alkaline solution on the texturing surface.

[0062] S200 , forming a mask layer on the first textured structure to perform mask protection on the light-receiving surface.

[0063] In this embodiment, a semiconductor substrate (such as a single-crystal silicon wafer) that has been textured on both sides is masked on one side, that is, the front side is masked, resulting in a double-sided textured single-crystal silicon wafer protected by a single-side mask. The primary function of this masking layer is to protect the first textured surface structure from corrosion during subsequent wet chemical treatment.

[0064] For example, at least one of silicon nitride, silicon oxynitride, and silicon oxide is deposited on the first textured structure on the light-receiving surface of the semiconductor substrate using plasma chemical vapor deposition or high-temperature chemical vapor deposition to form a mask layer. The mask layer can be formed using a deposition technique such as plasma chemical vapor deposition, and operating conditions such as deposition temperature and time can be adjusted based on actual process conditions.

[0065] Optionally, the material of the mask layer includes silicon oxide (SiO X ), silicon nitride (SiN X ) or silicon oxynitride (SiN X O X ) at least one; for example, the mask layer may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a stacked structure of two or more of the above film layers.

[0066] Preferably, the mask layer of this embodiment is made of a silicon oxide film, which is a UV silicon oxide film obtained through a UV oxidation process. Specifically, through UV lamp irradiation, oxygen in the air is converted into highly oxidizing substances such as reactive oxygen free radicals. These highly oxidizing substances oxidize the Si on the semiconductor surface, forming a silicon oxide film, thereby acting as a mask. Regarding the material of the mask layer, the inventors of this application have demonstrated through multiple optimizations that, compared to ordinary materials such as silicon oxide or silicon nitride, the use of a UV silicon oxide film as a mask layer can achieve a superior masking effect, and can better form a mask protection effect on the first velvet structure.

[0067] Optionally, the thickness of the mask layer is ≤100 nm. For example, the thickness of the mask layer can be 1 nm to 100 nm, and further can be 5 nm to 50 nm. For example, the thickness of the mask layer can be 1 nm, 2 nm, 3 nm, 5 nm, 6 nm, 8 nm, 10 nm, 20 nm, 30 nm, 50 nm, 60 nm, 100 nm, etc. If the thickness of the mask layer is too thin, its protective capability is poor. If the thickness of the mask layer is too thick, such as exceeding 100 nm, the cost is significantly increased.

[0068] S300: Performing a wet chemical treatment on the second velvet structure on the backlight side to flatten at least a portion of the pyramidal structures of the second velvet structure. For example, the tips of the second velvet structure are removed to make the surface structure smoother, thereby obtaining a refined microstructure. In this embodiment, a double-sided velvet-treated single-crystalline silicon wafer protected by a single-side mask is placed in a chemical solution and subjected to a backside chemical treatment, thereby forming a microstructure with the mask-protected velvet surface on the light-exposed side and the chemically treated surface on the backlight side.

[0069] In the related art, the light-receiving surface and the back-light surface of some silicon wafers have the same velvet structure, or the light-receiving surface of some silicon wafers has a velvet structure while the back-light surface is a polished surface. In the present application, the velvet surface of the back-light surface is refined, and the light-receiving surface and the back-light surface of the silicon wafer have different velvet structures, and the back-light surface is a non-polished surface, and the back-light surface has a refined microstructure surface. Therefore, compared with the existing battery cells with the same velvet structure on both sides or the polished surface on the back, the present application can effectively increase the passivation effect by forming a refined microstructure on the back-light surface. It has a better anti-epitaxial passivation effect than the existing back-light surface structure, and exhibits a Voc gain effect of 1mV on the battery cell. In addition, a large number of experiments have found that when the back is a polished surface, the solder strip is easy to debond during the subsequent component packaging process. Therefore, the refined microstructure of the back-light surface can have sufficient adhesion to the subsequent printed grid line, which can alleviate the debonding problem caused by direct polishing of the back; its structure is flatter, which has an improvement effect on the battery opening voltage, and can increase the battery efficiency by more than 0.2%. In addition, the refined microstructure of the backlight surface can reduce the surface area of ​​the back side, significantly shorten the coating time, and enable the various functional layers of the backlight surface to be thinned to a certain extent. In addition, actual experimental examples have shown that the back microcrystalline doping layer can be thinned by about 40%, and the back TCO layer can be thinned by more than 50%, effectively improving the economic benefits of production.

[0070] Optionally, the refined microstructure includes a plurality of block structures, wherein at least some of the surfaces of the block structures are overlapped.

[0071] In this embodiment, after wet chemical treatment of the second textured structure, the resulting surface features a fine, small-block structure—a microstructured surface composed of multiple small blocks, some of which overlap, resulting in a flatter structure. This reduces the back surface area and makes passivation easier. Thus, compared to existing pyramidal or polished back surface structures, the refined, small-block microstructured back surface of this embodiment exhibits superior anti-epitaxial passivation effects and possesses sufficient adhesion, helping to improve battery performance and shorten backside coating time.

[0072] Optionally, the size of the block structure is 0.1μm to 20μm. That is, in the multiple blocks, the size of each independent unit is 0.1μm to 20μm. This size refers to the average length or average width of the square cross-section of the block. Preferably, the size of the block structure is 1μm to 10μm; more preferably, the size of the block structure is 1μm to 2μm; for example, the size of the block structure can be 0.1μm, 0.5μm, 1μm, 1.5μm, 2μm, 3μm, 5μm, 6μm, 8μm, 10μm, 12μm, 15μm, 20μm, etc. By making the size of the block within the above range, it is helpful to obtain a more suitable reflectivity, improve the utilization rate of light, and also improve adhesion, ensure the reliability of the structure, and further help to improve the performance of the battery.

[0073] Optionally, the wet chemical treatment utilizes an alkaline solution, including a KOH solution or a NaOH solution, with a mass concentration of 1% to 10% and a treatment temperature of 40°C to 80°C. During the wet chemical treatment, the alkaline solution can be a KOH solution or a NaOH solution. Preferably, considering the actual alkaline treatment effect, the alkaline solution is a KOH solution. Preferably, the mass concentration of KOH in the alkaline solution is 3% to 7%, further preferably 4% to 6%; for example, the mass concentration of KOH can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, etc. Preferably, the treatment temperature used in the wet chemical treatment is 40°C to 80°C, further preferably 45°C to 78°C, for example, 40°C, 45°C, 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 78°C, 80°C, etc.

[0074] Therefore, the double-sided textured single-crystalline silicon wafer protected by a single-sided mask is placed in an alkaline solution of KOH with a mass concentration of 3% to 7%, such as 5%, at 40°C to 80°C for chemical treatment on the back side of the texture, forming a single-crystalline silicon wafer with a textured surface protected by a mask on one side and a chemically treated microstructure on the other side. The back surface after wet chemical treatment is characterized by a fine small square structure with a square size of 1μm to 10μm, preferably 1μm to 2μm.

[0075] S400: removing the mask layer on the first textured structure.

[0076] After the wet chemical treatment, the mask layer on the first textured structure on the light-receiving side is removed to reveal the first textured structure. Optionally, the mask layer is removed using an acidic solution at a temperature of 25°C to 45°C, such as 25°C, 30°C, 35°C, or 40°C. For example, a single-sided masked single-crystal silicon wafer is placed in an acidic solution at 25°C to 30°C to remove the protective mask layer, thereby forming a single-crystal silicon wafer with a microstructure on the back-light side.

[0077] The acidic solution may be, for example, a fluorine-containing acidic solution, i.e., the mask layer is removed using a fluorine-containing acidic solution. Furthermore, the acidic solution may be an HF solution, and the mass percentage concentration of the acidic solution may be 5% to 10%, further 6% to 8%, for example, 5%, 6%, 6.5%, 7%, 8%, 9%, or 10%.

[0078] S500 , preparing a double-sided intrinsic passivation layer, forming a second intrinsic passivation layer on the refined microstructure, and forming a first intrinsic passivation layer on the first textured structure.

[0079] The first intrinsic passivation layer and the second intrinsic passivation layer can be prepared by deposition methods such as plasma chemical vapor deposition (PECVD) or catalytic chemical vapor deposition (CAT-CVD). The specific operation method and operating conditions can be selected and set by those skilled in the art according to actual conditions.

[0080] S600 , preparing a doping layer: forming a first conductive type doping layer on the first intrinsic passivation layer, and forming a second conductive type doping layer on the second intrinsic passivation layer.

[0081] Optionally, chemical vapor deposition is used to prepare the first conductive type doping layer and the second conductive type doping layer, wherein the first conductive type doping layer is an N-type doping layer, and the second conductive type doping layer is a P-type doping layer. Preferably, the second conductive type doping layer is a microcrystalline P layer.

[0082] Preferably, the P-type doped layer is a microcrystalline P layer, that is, a P-type microcrystalline silicon thin film layer. Methods for forming the first conductive type doped layer and the second conductive type doped layer, that is, the N-type doped layer and the P-type doped layer, include amorphous silicon thin film processes, microcrystalline silicon thin film processes, microcrystalline silicon carbide thin film processes, microcrystalline silicon oxide thin film processes, microcrystalline silicon oxycarbon thin film processes, and other N / P-type doped semiconductor material processes. In this embodiment, the material of the P-type doped layer is preferably a microcrystalline silicon thin film, that is, the P-type doped layer is preferably a microcrystalline P layer. This helps to reduce the thickness of the P-type doped layer to a certain extent while ensuring battery performance, thereby helping to reduce the weight of the battery.

[0083] S700 , preparing a transparent conductive layer (TCO layer): forming a first transparent conductive layer on the first conductive type doped layer, and forming a second transparent conductive layer on the second conductive type doped layer.

[0084] A transparent conductive layer (TCO) refers to a film layer of a transparent conductive oxide. TCO is a general term for a series of semiconductor materials that are both light-transmitting and conductive, mainly including ITO (indium tin oxide), IWO (tungsten-doped indium oxide), AZO (aluminum-doped zinc oxide), etc. This embodiment does not limit the specific material of the transparent conductive layer.

[0085] The equipment and method for preparing the transparent conductive layer may include, but are not limited to, a magnetron sputtering equipment (PVD) and a reactive plasma deposition equipment (RPD).

[0086] Preferably, the thickness of the microcrystalline P layer is 10nm to 50nm, and the thickness of the second transparent conductive layer is 50nm to 200nm. For example, the thickness of the microcrystalline P layer can be 10nm, 20nm, 30nm, 40nm, 50nm, etc.; the thickness of the second transparent conductive layer can be 50nm, 60nm, 80nm, 100nm, 120nm, 150nm, 200nm, etc. The embodiment of the present application forms a refined microstructure on the back side, which can reduce the thickness of the microcrystalline P layer and the second transparent conductive layer compared to the thickness of the conventional doping layer and conductive layer, thereby helping to reduce the weight of the battery.

[0087] S800: Prepare metal electrodes. Form a first electrode on the first transparent conductive layer and a second electrode on the second transparent conductive layer. Both the first electrode and the second electrode are metal electrodes.

[0088] Alternatively, electrodes can be prepared using screen printing. For example, a silicon wafer is screen-printed with a low-temperature silver paste, and then the screen-printed single-crystal silicon wafer is placed in a curing furnace for curing at 190°C, enabling power generation on both sides.

[0089] In this embodiment, after removing the mask layer, the backlight side microstructured single crystal silicon wafer can be subjected to enhanced plasma chemical vapor deposition, physical vapor deposition, and screen printing to form a heterojunction solar cell with an intrinsic passivation layer.

[0090] It should be pointed out here that in the preparation method of the heterojunction solar cell, the specific processes of preparing the doping layer, preparing the transparent conductive layer, preparing the electrode, etc. can refer to the existing technology and adopt conventional production process flow or operation mode. This embodiment does not limit this and will not be described in detail here.

[0091] Based on the same inventive concept, the present invention also provides a heterojunction solar cell, which can be manufactured using the aforementioned method for manufacturing a heterojunction solar cell. As shown in FIG2 , the heterojunction solar cell comprises:

[0092] The semiconductor substrate 10 includes a first surface and a second surface opposite to each other, wherein the first surface is a light-receiving surface and the second surface is a backlight surface;

[0093] A first velvet structure 11 located on the light-receiving surface;

[0094] a first intrinsic passivation layer 12 located on the first textured structure 11;

[0095] a first conductive type doped layer 13 located on the first intrinsic passivation layer 12;

[0096] a first transparent conductive layer 14 located on the first conductive type doped layer 13;

[0097] a first electrode 15 located on the first transparent conductive layer 14;

[0098] A refined microstructure 21 located on the backlit surface;

[0099] a second intrinsic passivation layer 22 located on the refined microstructure 21;

[0100] a second conductive type doped layer 23 located on the second intrinsic passivation layer 22;

[0101] a second transparent conductive layer 24 located on the second conductive type doped layer 23;

[0102] The second electrode 25 is located on the second transparent conductive layer 24 .

[0103] The first conductive type doped layer may be an N-type doped layer, and the second conductive type doped layer may be a P-type doped layer.

[0104] It should be understood that the heterojunction solar cell of this embodiment and the aforementioned method for preparing a heterojunction solar cell are based on the same inventive concept, and thus have at least all the features and advantages of the method for preparing a heterojunction solar cell, which will not be described in detail here.

[0105] Therefore, based on the above settings, compared to the existing heterojunction solar cells, the velvet surface on one side of the double-sided textured single-crystalline silicon wafer of the present application is masked for protection, and the textured single-crystalline silicon wafer is subjected to wet chemical treatment to obtain a single-crystalline silicon wafer with a backlight microstructure. For the backlight side microstructure cell, the backlight side microstructure is easier to passivate, which has an improvement effect on the battery opening voltage, and can increase the battery efficiency by more than 0.2%. In addition, the microstructure of the backlight side reduces the surface area of ​​the back side, and the coating time can be greatly shortened. Experiments have shown that the second conductive type doped layer 23, such as the microcrystalline P layer, can be thinned by about 40%, and the back TCO layer, i.e., the second transparent conductive layer 24, can be thinned by more than 50%.

[0106] The present invention improves the back structure of the battery by forming a refined microstructure on the backlight surface, achieving a better passivation effect, and taking into account the secondary reflection effect of sunlight on the front pyramid velvet surface and the secondary reflection absorption of incident light by the backlight surface, thereby increasing the battery current.

[0107] In order to verify the effect of the method for preparing a heterojunction solar cell provided by the embodiment of the present invention, the present invention also carried out some specific examples and comparative experiments.

[0108] Example 1

[0109] A method for preparing a heterojunction solar cell, comprising:

[0110] First, the semiconductor substrate (such as a single-crystal silicon wafer) is subjected to double-sided texturing treatment, and then the light-receiving surface is protected by a mask, that is, a mask layer is formed on the first texturing structure of the light-receiving surface, and then the backlight surface is subjected to wet chemical treatment at different temperatures. For example, the double-sided texturing single-crystal silicon wafer protected by a single-side mask is placed in a chemical solution with a mass concentration of 5% KOH at 45°C (implementation 1), 50°C (implementation 2), 65°C (implementation 3), and 78°C (implementation 4) for chemical treatment on the back side of the texturing surface to achieve different surface morphologies on the backlight surface; then the subsequent removal of the mask layer, the preparation of the double-sided intrinsic passivation layer, the doping layer, the transparent conductive layer and the metal electrode is carried out.

[0111] Comparative Example 1

[0112] The preparation method of heterojunction solar cells includes: first performing double-sided texturing treatment on a semiconductor substrate (such as a single-crystal silicon wafer), and then subsequently preparing a double-sided intrinsic passivation layer, a doping layer, a transparent conductive layer and a metal electrode.

[0113] Compared with Example 1, Comparative Example 1 omits the steps of setting the mask layer, wet chemical treatment on the back side and removing the mask layer, that is, the subsequent intrinsic passivation layer and the like are directly prepared on the prepared double-sided pyramid-shaped textured structure.

[0114] Comparative Example 2

[0115] The preparation method of heterojunction solar cells includes: first performing double-sided texturing treatment on a semiconductor substrate (such as a single-crystal silicon wafer), then polishing the backlight side, and then subsequently preparing a double-sided intrinsic passivation layer, a doping layer, a transparent conductive layer and a metal electrode.

[0116] Compared with Example 1, Comparative Example 2 omits the steps of setting the mask layer, wet chemical treatment of the back side and removal of the mask layer, and adds the step of polishing the backlight surface to form a polished surface on the backlight surface, and then performs subsequent preparation of the intrinsic passivation layer on the pyramid-shaped velvet structure on the front side and the polished surface on the back side.

[0117] The performance tests were conducted on the heterojunction batteries prepared in Example 1 and Comparative Examples 1-2. The results are shown in Table 1 below.

[0118] Table 1

[0119]

[0120] The experimental data in Table 1 shows that, using the double-sided velvet surface as a baseline for comparison, the preferred backside microstructure of the present invention achieves the best efficiency. Comparing the double-sided velvet surface experimental group, we also found varying degrees of increase in Voc. This is due to the performance gain achieved by the micro-processed velvet surface increasing the surface passivation of the cell and reducing defects in the second passivation layer.

[0121] In addition, tensile tests were performed on batteries treated under different wet conditions, especially at different temperatures. The test results are shown in Table 2 below.

[0122] Figure 3 shows the electron microscope scanning images of the back square size under different wet conditions, as well as the electron microscope scanning images of the reference velvet surface and the back polished surface: Figure 3 (a) is the reference velvet surface (double-sided pyramid velvet structure) without squares; the square size in Figure 3 (b) is 0.1μm~1μm, and its reflectivity after 45℃ treatment is 25.23%; the square size in Figure 3 (c) is 1.5μm~2.5μm, and its reflectivity after 50℃ treatment is 31.64%; the square size in Figure 3 (d) is 4μm~6μm, and its reflectivity after 65℃ treatment is 33.42%; the square size in Figure 3 (e) is 15μm~25μm, and its reflectivity after 78℃ treatment is 34.48%; the back of Figure 3 (f) is the polished surface, without squares, and the reflectivity of the polished surface without squares is ≥38%.

[0123] Table 2

[0124]

[0125] It can be seen from Table 2 that the refined square microstructure of the backlight surface of the embodiment of the present invention has sufficient adhesion for the subsequent printing of grid lines, and can solve the problem of grid delamination caused by direct polishing of the back surface.

[0126] Example 2

[0127] In order to verify the advantages of the refined microstructure of the backlight surface of the present application, such as the ability to reduce the thickness of some functional layers of the backlight surface to a certain extent, the present application also carried out Example 2.

[0128] For the thinning of the second conductive type doped layer (microcrystalline P-type) and the second transparent conductive layer (back TCO layer), this application varied the coating process time of the second conductive type doped layer in the PECVD machine to obtain experimental groups with different second conductive type doped layer thicknesses, and varied the coating time of the back TCO layer in the PVD machine to obtain experimental groups with different back TCO layer thicknesses. It should be noted that in this example, the single-side micro-processing conditions were preferably 1.5-2.5 μm, with all other conditions remaining the same.

[0129] It should also be noted that this application illustrates an example in which the second doped layer is a P-type doped layer. Furthermore, in other embodiments, the same applies to battery structures in which the second doped layer is an N-type doped layer. That is, when the second doped layer is an N-type doped layer, its thickness can also be reduced to a similar degree.

[0130] The thickness of the second conductivity type doped layer is preferably in the range of 10 nm to 50 nm, and more preferably in the range of 25 nm to 35 nm. The film thickness can be measured using ellipsometer fitting. The baseline thickness of the second conductivity type doped layer (microcrystalline P-type) mentioned in this embodiment is 33.2 nm. The second conductivity type doped layer is thinned by 33% to 21 nm, and the second conductivity type doped layer is thinned by 49% to 17 nm. Further battery data is provided for illustration.

[0131] For comparison, in a cell with a double-sided velvet surface, that is, a pyramid-shaped velvet structure on both sides, the cell performance was tested by varying the thickness of the second conductive type doped layer, including providing the second conductive type doped layer (microcrystalline P-type) with a baseline thickness, reducing the thickness by 33%, and reducing the thickness by 49%. Simultaneously, using the method provided in this application, in a cell with a refined microstructure on the backlight side, the cell performance was tested by varying the thickness of the second conductive type doped layer, including providing the second conductive type doped layer (microcrystalline P-type) with a baseline thickness, reducing the thickness by 33%, and reducing the thickness by 49%. The test results are shown in Table 3 below.

[0132] Table 3

[0133]

[0134] The experimental data in Table 3 show that when a cell uses a double-sided velvet finish, a 33% decrease in the thickness of the second conductivity type doped layer will result in a 0.5% decrease in cell efficiency. However, under single-sided micro-processing experimental conditions, i.e., using the refined microstructure of the backlight side obtained by wet chemical treatment as provided in this application, a 49% decrease in the thickness of the second conductivity type doped layer will not result in a decrease in cell performance, indicating that the second conductivity type doped layer can be correspondingly thinned after the backlight side is micro-processed (wet chemical treatment). This is because after the backlight side is micro-processed (i.e., wet chemical treatment), the surface junction of the backlight side is reduced compared to that of a conventional velvet finish, which can appropriately reduce the deposition time and help reduce the thickness of the second conductivity type doped layer. In addition, the second conductivity type doped layer is a microcrystalline P layer, which uses a microcrystalline silicon growth process. After micro-processing, the entire second velvet surface, i.e., the entire backlight side, is in a relatively flat state, which is conducive to the deposition and growth of microcrystalline silicon, and can achieve good crystal growth in a relatively thin state.

[0135] Therefore, compared with the existing pyramid velvet structure, the refined microstructure setting of the embodiment of the present application can reduce the thickness of the second conductive type doping layer to a certain extent while ensuring the battery performance. That is, within a certain range of thinning, the electrical performance of the battery can be guaranteed, the cost can be reduced, and the economic benefits can be improved.

[0136] Furthermore, the thickness of the second transparent conductive layer is preferably in the range of 50 nm to 200 nm, and more preferably in the range of 90 nm to 110 nm. In this embodiment, the base thickness of the second transparent conductive layer is 104 nm. The thickness of the second transparent conductive layer is reduced by 50% to 52 nm, reduced by 60% to 41 nm, and reduced by 80% to 18 nm. Further battery data is provided for further illustration.

[0137] For comparison, in a battery with a double-sided velvet surface, i.e., a pyramid-shaped velvet structure on both sides, the battery performance was tested by varying the thickness of the second transparent conductive layer, including providing a baseline thickness, reducing the thickness by 50%, reducing the thickness by 60%, and reducing the thickness by 80%. Simultaneously, using the method provided in this application, i.e., in a battery with a refined microstructure on the backlight side, the battery performance was tested by varying the thickness of the second transparent conductive layer, including providing a baseline thickness, reducing the thickness by 50%, reducing the thickness by 60%, and reducing the thickness by 80%. The test results are shown in Table 4 below.

[0138] Table 4

[0139]

[0140] The experimental data in Table 4 show that, in the case of a double-sided suede surface, a 50% decrease in the thickness of the second transparent conductive layer will cause a 0.37% decrease in battery efficiency. However, under the experimental conditions of single-sided micro-processing, that is, using the refined microstructure of the backlight surface obtained after the wet chemical treatment provided by the present application, a 60% decrease in the thickness of the second transparent conductive layer will not lead to a decrease in battery performance. This shows that the second transparent conductive layer can be correspondingly thinned after the suede micro-processing, thereby achieving the purpose of improving production economic benefits.

[0141] Therefore, compared with the existing pyramid velvet structure, the refined microstructure setting of the embodiment of the present application can reduce the thickness of the second transparent conductive layer to a certain extent while ensuring the battery performance. That is, within a certain range of thinning, the electrical performance of the battery can be guaranteed, the cost can be reduced, and the economic benefits can be improved.

[0142] Parts not described in detail in the specification of the present invention are well known to those skilled in the art.

[0143] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. It should be noted that the terms "and / or" or " / " used in this article are merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for preparing a heterojunction solar cell, characterized in that: The method comprises: Performing a texturing process on the light-receiving surface and the backlight surface of the semiconductor substrate to form a first texturing structure and a second texturing structure on the light-receiving surface and the backlight surface respectively; the first texturing structure and the second texturing structure both have a pyramid structure; forming a mask layer on the first textured structure; Performing a wet chemical treatment on the second velvet structure to flatten at least a portion of the pyramid structure of the second velvet structure to obtain a refined microstructure; removing the mask layer; forming a second intrinsic passivation layer on the refined microstructure, and forming a first intrinsic passivation layer on the first suede structure; A first conductive type doping layer is formed on the first intrinsic passivation layer, and a second conductive type doping layer is formed on the second intrinsic passivation layer.

2. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The first velvet structure is a pyramid-shaped velvet structure; The refined microstructure includes a plurality of block structures, wherein at least some of the surfaces of some of the block structures are overlapped.

3. The method for preparing a heterojunction solar cell according to claim 2, characterized in that: The size of the block structure is 0.1 μm to 20 μm.

4. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The wet chemical treatment uses an alkaline solution, which includes a KOH solution or a NaOH solution. The mass percentage concentration of the alkaline solution is 1% to 10%, and the treatment temperature is 40° C. to 80° C.

5. The method for preparing a heterojunction solar cell according to claim 4, characterized in that: The alkaline solution is a KOH solution; The mass percentage concentration of the alkaline solution is 3% to 7%; The treatment temperature is 45°C to 78°C.

6. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The material of the mask layer includes at least one of silicon oxide, silicon nitride or silicon oxynitride; And / or, the thickness of the mask layer is ≤100 nm.

7. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The material of the mask layer is a silicon oxide film, and the silicon oxide film is a UV silicon oxide film obtained through a UV oxidation process.

8. The method for preparing a heterojunction solar cell according to claim 1, characterized in that: The mask layer is removed by using an acidic solution at a temperature of 25° C. to 45° C.

9. The method for preparing a heterojunction solar cell according to claim 8, characterized in that: The acidic solution includes HF solution, and the mass percentage concentration of the acidic solution is 5% to 10%.

10. The method for preparing a heterojunction solar cell according to any one of claims 1 to 9, characterized in that: After forming a second conductive type doping layer on the second intrinsic passivation layer, the method further includes: forming a first transparent conductive layer on the first conductive type doped layer, and forming a second transparent conductive layer on the second conductive type doped layer; A first electrode is formed on the first transparent conductive layer, and a second electrode is formed on the second transparent conductive layer.

11. The method for preparing a heterojunction solar cell according to claim 10, characterized in that: The second conductive type doped layer is a microcrystalline P layer, the thickness of the microcrystalline P layer is 10 nm to 50 nm, and the thickness of the second transparent conductive layer is 50 nm to 200 nm.

12. A heterojunction solar cell, characterized in that: The heterojunction solar cell is manufactured by the method for manufacturing a heterojunction solar cell according to any one of claims 1 to 11, and the heterojunction solar cell comprises: A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface arranged opposite to each other, the first surface being a light-receiving surface, and the second surface being a light-receiving surface; A first velvet structure located on the light-receiving surface, a first intrinsic passivation layer located on the first velvet structure, a first conductive type doped layer located on the first intrinsic passivation layer, a first transparent conductive layer located on the first conductive type doped layer, and a first electrode located on the first transparent conductive layer; A refined microstructure located on the backlight surface, a second intrinsic passivation layer located on the refined microstructure, a second conductive type doped layer located on the second intrinsic passivation layer, a second transparent conductive layer located on the second conductive type doped layer, and a second electrode located on the second transparent conductive layer.

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