Semiconductor package structure and semiconductor packaging process

Abstract

Embodiments of the present application provide a semiconductor package structure and a semiconductor packaging process. The semiconductor packaging process comprises: fixing a first element to be packaged onto the bottom wall of a first recess of an upper mold, fixing a second element to be packaged onto the bottom wall of a second recess of a lower mold, and performing demolding after mold closing and molding to obtain a first molded body; and preparing an interconnection structure for the first molded body to obtain a semiconductor package structure. According to the packaging process, a plurality of elements to be packaged can be packaged in a stacked mode, thereby reducing the frequency of molding of the elements to be packaged, reducing the influence of the molding process on the elements to be packaged, and improving the yield of electronic products; in addition, the production period of the semiconductor package structure is shortened, and the production efficiency is improved; further, the design of adding a metal circuit layer can be directly realized, without the operations of sputtering or chemical plating deposition and electroplating thickening to obtain a metal layer; and an integrated molded structure can be formed, and the packaging reliability is improved.

Description

Semiconductor packaging structure and semiconductor packaging process

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 30, 2023, with application number 202311626876.2 and application name “Semiconductor Packaging Structure and Semiconductor Packaging Process”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor packaging technology, and in particular, to a semiconductor packaging structure and a semiconductor packaging process. Background Art

[0003] Traditional semiconductor packaging involves encapsulating electronic components such as chips using molds and molding compounds through steps such as injection molding and demolding. With the continuous advancement of electronic information technology, the demand for higher levels of integration in electronic products is increasing. This has led to higher demands for semiconductor packaging density, increasing the number of electronic components that need to be packaged together, and stacking has become a viable approach to achieving high integration. To achieve stacked packaging of devices, the electronic components to be stacked are typically stacked one by one. Each time a new component is added to the stack, the previously encapsulated component and the newly added component are encapsulated again. These multiple encapsulation operations subject the first stacked components to multiple subsequent encapsulation and pressing operations, reducing product yield and impacting the reliability of the electronic product packaging. Furthermore, the long production cycle affects production efficiency, making it unsuitable for industrial production. Furthermore, to achieve layer-up designs for metal circuits, metallization is typically achieved through sputtering or electroless plating, followed by electroplating to thicken the metal layer. This complex process is detrimental to production efficiency. In other words, the existing plastic encapsulation process can only simply achieve the packaging function, and cannot achieve the addition of devices and metal circuits in one step by the plastic encapsulation process alone. Summary of the Invention

[0004] In view of this, an embodiment of the present application provides a semiconductor packaging process, which can realize the stacked packaging of multiple parts to be packaged only by using the packaging process, reduce the number of times the parts to be packaged undergo plastic packaging, reduce the impact of the plastic packaging process on the parts to be packaged, and improve the yield of electronic products; at the same time, it is beneficial to shorten the production cycle of the semiconductor packaging structure and improve production efficiency; it can also directly realize the layer-added design of metal circuits, eliminating the operations of sputtering or chemical plating deposition and electroplating thickening to obtain the metal layer; and it can form an integrated plastic packaging structure to improve packaging reliability.

[0005] A first aspect of an embodiment of the present application provides a semiconductor packaging process, including:

[0006] Providing a first plastic encapsulation mold, the first plastic encapsulation mold comprising an upper mold and a lower mold that match each other, the upper mold having a first groove, the lower mold having a second groove, the first groove and the second groove being arranged correspondingly;

[0007] The first component to be packaged is fixed on the bottom wall of the first groove of the upper mold, and the second component to be packaged is fixed on the bottom wall of the second groove of the lower mold. After the molds are closed and plastic-sealed, the molds are demolded to obtain a first plastic-sealed body; the first plastic-sealed body includes a first plastic-sealed layer and a stacked first component to be packaged and a second component to be packaged; the first component to be packaged and the second component to be packaged are embedded in the first plastic-sealed layer at intervals, and a surface of the first component to be packaged facing away from the second component to be packaged is exposed to the first plastic-sealed layer, and a surface of the second component to be packaged facing away from the first component to be packaged is exposed to the first plastic-sealed layer;

[0008] The first plastic package body is subjected to an interconnection structure preparation to obtain a semiconductor packaging structure, wherein the interconnection structure is used to realize electrical interconnection between the first component to be packaged and the second component to be packaged.

[0009] In an embodiment of the present application, the size of the first groove is larger than the size of the first to-be-encapsulated component. When the first to-be-encapsulated component is fixed to the bottom wall of the first groove of the upper mold, a first gap is formed between the first to-be-encapsulated component and the side wall of the first groove. The plane where the notch of the first groove is located is higher than the surface of the first to-be-encapsulated component on the side facing away from the bottom wall of the first groove.

[0010] The size of the second groove is larger than the size of the second part to be packaged, and when the second part to be packaged is fixed to the bottom wall of the second groove of the lower mold, a second gap is formed between the second part to be packaged and the side wall of the second groove, and the plane where the notch of the second groove is located is higher than the surface of the second part to be packaged on the side facing away from the bottom wall of the second groove;

[0011] The first plastic packaging layer includes a spacing portion provided between the first component to be packaged and the second component to be packaged, and an edge portion located on a side surface of the first plastic packaging body. The first plastic packaging layer is an integrated structure.

[0012] In the embodiment of the present application, the semiconductor packaging process further includes:

[0013] After obtaining the first plastic package body, a circuit layer is prepared on the exposed surface of the first component to be packaged and / or the second component to be packaged.

[0014] In the embodiment of the present application, the preparation of the interconnected structure of the first plastic package body is specifically as follows:

[0015] A through hole is prepared through the first plastic packaging body along the thickness direction of the first plastic packaging body, and a conductive material is filled in the through hole to achieve vertical electrical interconnection between the first to-be-packaged component and the second to-be-packaged component.

[0016] In the embodiment of the present application, the first to-be-packaged component and the second to-be-packaged component are respectively selected from any one of a chip, a module, a PCB, a PCBA, a lead frame, a ceramic substrate, and a copper foil.

[0017] In the embodiment of the present application, the module includes at least one packaging substructure, and the preparation of the packaging substructure includes:

[0018] The first component is fixed to the top wall of the inner wall of the upper mold of the second plastic encapsulation mold, and the second component is fixed to the bottom wall of the inner wall of the lower mold of the second plastic encapsulation mold. After the molds are closed and encapsulated, the molds are demolded to obtain a second plastic encapsulation body; the second plastic encapsulation body includes a second plastic encapsulation layer and a first component and a second component stacked thereon; the first component and the second component are embedded in the second plastic encapsulation layer with a space between them, and a surface of the first component facing away from the second component is exposed to the second plastic encapsulation layer, and a surface of the second component facing away from the first component is exposed to the second plastic encapsulation layer; the first component and the second component are respectively selected from any one of a chip, a PCB, a PCBA, a lead frame, a ceramic substrate, and copper foil;

[0019] The second plastic package body is provided with an interconnection structure to obtain a package substructure, wherein the interconnection structure penetrates the second plastic package layer and is used to electrically interconnect the first component and the second component.

[0020] In the embodiment of the present application, the semiconductor packaging process further includes:

[0021] After obtaining the second plastic package body, a circuit layer is prepared on the exposed surface of the first component and / or the second component.

[0022] In the embodiment of the present application, the module includes a plurality of packaging substructures, and the preparation of the module includes:

[0023] preparing a plurality of the package substructures, and preparing the plurality of package substructures into a package substructure stack; each of the package substructure stacks includes at least one package substructure;

[0024] Fixing one package substructure stack to the top wall of the inner wall of the upper mold of the third plastic encapsulation mold, fixing another package substructure stack to the bottom wall of the inner wall of the lower mold of the third plastic encapsulation mold, closing the molds and encapsulating, and then demolding to obtain a third plastic encapsulation body;

[0025] The third plastic package body is subjected to an interconnection structure preparation to obtain a module, and the interconnection structure is used to electrically interconnect the first package substructure stack and the second package substructure stack.

[0026] The semiconductor packaging process provided in the embodiment of the present application is a double-sided packaging process, which can realize the stacked packaging of multiple parts to be packaged, reduce the number of times the parts to be packaged undergo plastic packaging, reduce the impact of the plastic packaging process on the packaged parts, and improve the yield of electronic products; at the same time, it is beneficial to shorten the production cycle of the semiconductor packaging structure and improve production efficiency; it can also directly realize the layer-added design of metal circuits, eliminating the operations of sputtering or chemical plating deposition and electroplating thickening to obtain the metal layer; and it can form an integrated plastic packaging structure to improve packaging reliability.

[0027] A second aspect of an embodiment of the present application provides a semiconductor packaging structure, comprising a first plastic packaging layer, and a first layer of components to be packaged and a second layer of components to be packaged stacked together;

[0028] The first plastic encapsulation layer is an integrated plastic encapsulation structure, the first layer of components to be encapsulated and the second layer of components to be encapsulated are embedded in the first plastic encapsulation layer at intervals, and the surface of the first layer of components to be encapsulated facing away from the second layer of components to be encapsulated is exposed to the first plastic encapsulation layer, and the surface of the second layer of components to be encapsulated facing away from the first layer of components to be encapsulated is exposed to the first plastic encapsulation layer; the first layer of components to be encapsulated and the second layer of components to be encapsulated are electrically interconnected through an interconnection structure that penetrates the first plastic encapsulation layer; the first layer of components to be encapsulated includes a first component to be encapsulated, and the second layer of components to be encapsulated includes a second component to be encapsulated.

[0029] In an embodiment of the present application, the first part to be packaged and the second part to be packaged are respectively selected from any one of a chip, a module, a PCB, a PCBA, a lead frame, a ceramic substrate, and a copper foil; the first plastic packaging layer includes a spacer portion arranged between the first part to be packaged and the second part to be packaged, and a edging portion located on the side of the first plastic packaging body, and the first plastic packaging layer is an integrated structure.

[0030] The semiconductor packaging structure provided in this application has a stable structure and a high product yield, and can realize the stacked assembly of multiple components, better meeting people's requirements for multi-function and high reliability of electronic products.

[0031] An embodiment of the present application further provides a semiconductor device, which includes a packaging structure manufactured by the semiconductor packaging process described in the first aspect of the present application, or includes the semiconductor packaging structure described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a flow chart of a semiconductor packaging process according to an embodiment of the present application;

[0033] FIG2 is a schematic diagram of a process flow of a semiconductor packaging process according to an embodiment of the present application;

[0034] FIG3 is a schematic diagram of preparing an interconnection structure 50 of the first plastic package body 1 in one embodiment of the present application;

[0035] 4A and 4B are schematic diagrams of a preparation process of a first packaging substructure according to an embodiment of the present application;

[0036] 5A and 5B are schematic diagrams of the preparation process of the second packaging substructure in an embodiment of the present application;

[0037] 6A, 6B and 6C are schematic flow diagrams of a packaging process in one embodiment of the present application;

[0038] FIG7 is a schematic cross-sectional view of a semiconductor package structure 100 according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The embodiments of the present application will be described below with reference to the accompanying drawings.

[0040] Referring to Figures 1 and 2, Figure 1 is a flow chart of a semiconductor packaging process according to an embodiment of the present application, and Figure 2 is a schematic flow chart of a semiconductor packaging process according to an embodiment of the present application. The semiconductor packaging process provided in the present application is a double-sided packaging process, which includes:

[0041] S10, providing a first plastic encapsulation mold 41, the first plastic encapsulation mold 41 comprising an upper mold 411 and a lower mold 412 that match each other, the upper mold 411 having a first groove 401, the lower mold 412 having a second groove 402, the first groove 401 and the second groove 402 being arranged correspondingly;

[0042] S20, fixing the first component to be packaged 10 on the bottom wall of the first groove 401 of the upper mold 411 of the first plastic encapsulation mold 41, fixing the second component to be packaged 20 on the bottom wall of the second groove 402 of the lower mold 412 of the first plastic encapsulation mold 41, closing the molds and performing plastic encapsulation, and then demolding to obtain a first plastic encapsulation body 1; the first plastic encapsulation body 1 includes a first plastic encapsulation layer 30, and the first component to be packaged 10 and the second component to be packaged 20 stacked; the first component to be packaged 10 and the second component to be packaged 20 are embedded in the first plastic encapsulation layer 30 at intervals, and the surface of the first component to be packaged 10 on the side facing away from the second component to be packaged 20 is exposed to the first plastic encapsulation layer 30, and the surface of the second component to be packaged 20 on the side facing away from the first component to be packaged 20 is exposed to the first plastic encapsulation layer 30;

[0043] S30 , preparing an interconnection structure 50 on the first plastic package body 1 to obtain a semiconductor packaging structure. The interconnection structure 50 is used to achieve electrical interconnection between the first component to be packaged 10 and the second component to be packaged 20 .

[0044] The semiconductor packaging process provided in the embodiment of the present application uses double-sided packaging to stack and plastic-seal the first to-be-packaged component 10 and the second to-be-packaged component 20 into a whole. The first plastic-sealing layer 30 is an integrated plastic-sealing structure, which can improve the packaging reliability. The packaging process can realize the stacking packaging of multiple components to be packaged, reduce the number of times the components to be packaged undergo plastic sealing, reduce the impact of the plastic-sealing process on the components to be packaged, and improve the yield of electronic products. At the same time, it is beneficial to shorten the production cycle of the semiconductor packaging structure and improve production efficiency. It can also directly realize the layer-added design of the metal circuit, eliminating the operations of sputtering or chemical plating deposition and electroplating thickening to obtain the metal layer; and it can form an integrated plastic-sealed structure to improve the packaging reliability.

[0045] In the present application, in steps S10 and S20, the size of the first groove 401 is larger than the size of the first part to be packaged 10, and the size of the second groove 402 is larger than the size of the second part to be packaged 20. When the first part to be packaged 10 is fixed on the bottom wall of the first groove 401 of the upper mold 411, the first part to be packaged 10 and the side wall of the first groove 401 have a first gap, and the plane where the notch of the first groove 401 is located is higher than the surface of the first part to be packaged 10 on the side facing away from the bottom wall of the first groove 401; when the second part to be packaged 20 is fixed on the bottom wall of the second groove 402 of the lower mold 412, the second part to be packaged 20 and the side wall of the second groove 402 have a second gap, and the plane where the notch of the second groove 402 is located is higher than the surface of the second part to be packaged 20 on the side facing away from the bottom wall of the second groove 402.

[0046] When the mold is closed, the bottom wall of the first groove 401 of the upper mold 411 of the first plastic encapsulation mold 41 is opposite to the bottom wall of the second groove 402 of the lower mold 412, and the first to-be-encapsulated part 10 is opposite to the second to-be-encapsulated part 20. After the mold is closed, the first groove 401 of the upper mold 411 and the second groove 402 of the lower mold 412 form a closed cavity, and the first to-be-encapsulated part 10 and the second to-be-encapsulated part 20 are accommodated in the cavity, and there is a first gap between the first to-be-encapsulated part 10 and the side wall of the first groove 401 of the upper mold 411, and there is a second gap between the second to-be-encapsulated part 20 and the side wall of the second groove 402 of the lower mold 412. Due to the height difference between the notch of the first groove 401 and the surface of the first to-be-encapsulated part 10, and the height difference between the notch of the second groove 402 and the surface of the second to-be-encapsulated part 20, there is also a gap between the first to-be-encapsulated part 10 and the second to-be-encapsulated part 20. After plastic encapsulation, these gaps are filled with plastic encapsulation material to form a first plastic encapsulation layer 30 with an integrated structure. The molding material can be any of various molding materials available in the field of semiconductor packaging. Its specific composition is not limited as long as it can achieve reliable and effective packaging. In some embodiments, the molding material can be an epoxy molding material. Accordingly, the first molding layer 30 is an epoxy molding layer, and the first molding layer 30 includes a cured epoxy molding material.

[0047] In the present application, the first plastic-encapsulated body 1 obtained by plastic encapsulation is covered by a first plastic-encapsulation layer 30 except for the surface in contact with the first plastic-encapsulation mold 41. Specifically, the first plastic-encapsulation layer 30 includes a spacer 31 provided between the first component to be encapsulated 10 and the second component to be encapsulated 20, and a rim portion 32 located on the side of the first plastic-encapsulated body 1. The rim portion 32 wraps around the first component to be encapsulated 10 and the second component to be encapsulated 20, and includes a first end face and a second end face opposite to each other. The first end face is flush with the surface of the first component to be encapsulated 10 on the side facing away from the second component to be encapsulated 20, and the second end face is flush with the surface of the second component to be encapsulated 20 on the side facing away from the first component to be encapsulated 10. Under the encapsulation effect of the first plastic encapsulation layer 30 of the integrated structure formed by the spacer portion 31 and the edging portion 32, the first component to be encapsulated 10 and the second component to be encapsulated 20 are firmly combined into a whole, and the surfaces of the first component to be encapsulated 10 and the second component to be encapsulated 20 that need to be plastic encapsulated are effectively covered, thereby effectively protecting the first component to be encapsulated 10 and the second component to be encapsulated 20.

[0048] It should be noted that the size of the first groove 401 is slightly larger than the size of the first part to be packaged 10, and the size of the second groove 402 is slightly larger than the size of the second part to be packaged 20, as long as the first part to be packaged 10 and the second part to be packaged 20 can be firmly plastic-sealed as one body, and the insulation design requirements can be achieved. That is, the specific widths of the first gap and the second gap, as well as the specific height difference between the notch of the first groove 401 and the surface of the first part to be packaged 10, and the specific height difference between the notch of the second groove 402 and the surface of the second part to be packaged 20 can be set so as to achieve the firm integral plastic sealing of the first part to be packaged 10 and the second part to be packaged 20, and the insulation design requirements.

[0049] In the present application, in step S30, the specific method of preparing the interconnection structure 50 of the first plastic package body 1 is not limited, as long as the interconnection structure 50 can realize the electrical interconnection between the first to-be-packaged component 10 and the second to-be-packaged component 20. The first plastic package body 1 can be opened or grooved, and then metallized and filled, such as copper, tungsten, etc., to achieve electrical interconnection, or electrical interconnection can be achieved through silicon vias. When opening or grooved, blind holes or through holes can be opened according to actual needs. The metallization filling can be first formed by sputtering or chemical plating to form a metal seed layer, and then electroplated with metal to fill it. In some embodiments, the metallization filling is achieved by copper plating.

[0050] Referring to FIG. 3 , FIG. 3 is a schematic diagram of preparing an interconnection structure 50 from the first plastic package body 1 in one embodiment of the present application.

[0051] In this application, the first plastic package body 1 is used to prepare the interconnection structure 50, specifically as follows:

[0052] A through hole 51 is prepared along the thickness direction of the first plastic package body 1 and passes through the first plastic package body 1, and a conductive material is filled in the through hole 51 to achieve vertical electrical interconnection between the first component to be packaged 10 and the second component to be packaged 20. The conductive material can be copper, tungsten, polysilicon, etc. In some embodiments, copper can be electroplated in the through hole 51. During the copper electroplating process, an in-hole copper layer can be formed in the through hole 51, as well as a surface copper cladding layer covering the exposed surface of the first component to be packaged 10 and / or the second component to be packaged 20. The surface copper cladding layer can be further processed to form a circuit layer 60. The exposed surface of the first component to be packaged 10 is the surface of the first component to be packaged 10 facing away from the second component to be packaged 20; the exposed surface of the second component to be packaged 20 is the surface of the second component to be packaged 20 facing away from the first component to be packaged 10.

[0053] In some embodiments of the present application, the semiconductor packaging process further includes:

[0054] After obtaining the first plastic package body 1, a circuit layer 60 is prepared on the exposed surface of the first component to be packaged 10 and / or the second component to be packaged 20. The specific structure of the circuit layer 60 can be set according to the actual needs of the product.

[0055] The semiconductor packaging process of the present application can be used for the packaging of various semiconductor components. For example, the first part to be packaged 10 and the second part to be packaged 20 can be any one selected from chips, modules, PCBs, PCBAs, lead frames, ceramic substrates, and copper foils. Among them, the module can be assembled from any one or more of chips, modules, PCBs, PCBAs, lead frames, ceramic substrates, and copper foils. In some embodiments of the present application, the first part to be packaged 10 is a first chip, and the second part to be packaged 20 is a second chip. In some embodiments of the present application, the first part to be packaged 10 is a first module, and the second part to be packaged 20 is a second module. In some embodiments of the present application, the first part to be packaged 10 is a lead frame, and the second part to be packaged 20 is a ceramic substrate. In some embodiments of the present application, the first part to be packaged 10 is a copper foil, and the second part to be packaged 20 is a PCB. It is understandable that when the first component to be packaged 10 is copper foil, the metal layer stacking can be achieved through the packaging process, thereby realizing the layer-building design of the metal circuit, thereby avoiding the operation of obtaining the metal layer through sputtering or chemical plating deposition and electroplating thickening in the prior art.

[0056] In the present application, when the first component to be packaged 10 and the second component to be packaged 20 are a packaging structure composed of multiple components stacked and packaged, the process of stacking and packaging multiple components in the packaging structure is not limited. In some embodiments, the process of stacking and packaging multiple components in the packaging structure adopts the double-sided packaging process mentioned above in the present application.

[0057] In the embodiments of the present application, a module is obtained by packaging multiple components together. The process for packaging the components constituting the module is not limited. In some embodiments, the process for packaging the components constituting the module can adopt the double-sided packaging process described above in the present application.

[0058] In this application, the module includes at least one packaging substructure, and the preparation of each packaging substructure includes:

[0059] The first component is fixed to the top wall of the inner wall of the upper mold of the second plastic encapsulation mold, and the second component is fixed to the bottom wall of the inner wall of the lower mold of the second plastic encapsulation mold. After the molds are closed and encapsulated, the molds are demolded to obtain a second plastic encapsulation body; the second plastic encapsulation body includes a second plastic encapsulation layer and a first component and a second component stacked thereon; the first component and the second component are embedded in the second plastic encapsulation layer with a side surface of the first component facing away from the second component exposed to the second plastic encapsulation layer, and a side surface of the second component facing away from the first component is exposed to the second plastic encapsulation layer; the first component and the second component are respectively selected from any one of a chip, a PCB, a PCBA, a lead frame, a ceramic substrate, and a copper foil;

[0060] The second plastic package body is subjected to an interconnection structure to obtain a package substructure. The interconnection structure penetrates the second plastic package layer and is used to electrically interconnect the first component and the second component.

[0061] It is understandable that the preparation process of the above-mentioned packaging substructure can be the same as the preparation process of the aforementioned semiconductor packaging structure, and will not be repeated here. Specifically, the first element and the second element can be regarded as the first component to be packaged 10 and the second component to be packaged 20, and the second plastic sealing layer can be regarded as the first plastic sealing layer 30. The second plastic sealing layer is also an integrated plastic sealing structure. In some embodiments, the second plastic sealing layer is an epoxy resin plastic sealing layer, and the second plastic sealing layer includes a cured epoxy resin plastic sealing material. The preparation of the interconnection structure can also refer to the preparation method of the interconnection structure 50 mentioned above.

[0062] It should be noted that the first element and the second element in each package substructure may be the same element or different elements. For example, the package substructure may include a first chip and a second chip in a stacked package, or may include a copper foil and a PCB in a stacked package, or may include a lead frame and a ceramic substrate in a stacked package.

[0063] In some embodiments of the present application, the semiconductor packaging process further includes:

[0064] After obtaining the second plastic package, a circuit layer is prepared on the exposed surface of the first component and / or the second component. The specific preparation method of the circuit layer can refer to the preparation method of the circuit layer 60 mentioned above.

[0065] In some embodiments of the present application, the module includes multiple packaging substructures. In this case, the preparation of the module includes:

[0066] Prepare a plurality of the above-mentioned package substructures, and prepare the plurality of package substructures into a package substructure stack; each package substructure stack includes at least one package substructure;

[0067] The first encapsulation substructure stack is fixed to the top wall of the inner wall of the upper mold of the third plastic encapsulation mold, and the second encapsulation substructure stack is fixed to the bottom wall of the inner wall of the lower mold of the third plastic encapsulation mold. After the molds are closed and encapsulated, the third plastic encapsulation body is obtained by demolding. The third plastic encapsulation body includes a third plastic encapsulation layer, and the stacked first encapsulation substructure stack and the second encapsulation substructure stack. The first encapsulation substructure stack and the second encapsulation substructure stack are embedded in the third plastic encapsulation layer at intervals, and the surface of the first encapsulation substructure stack facing away from the second encapsulation substructure stack is exposed to the third plastic encapsulation layer, and the surface of the second encapsulation substructure stack facing away from the first encapsulation substructure stack is exposed to the third plastic encapsulation layer.

[0068] The third plastic package body is subjected to an interconnection structure preparation to obtain a module, and the interconnection structure is used to electrically interconnect the first package substructure stack and the second package substructure stack.

[0069] The package substructure stack may include one or more package substructures. When the package substructure stack includes multiple package substructures, it may be packaged using the above-mentioned double-sided packaging process.

[0070] It is understandable that the preparation process of the above-mentioned module can be the same as the preparation process of the aforementioned semiconductor packaging structure, and will not be repeated here. Specifically, the first packaging substructure stack and the second packaging substructure stack can be regarded as the first to-be-packaged part 10 and the second to-be-packaged part 20, and the third plastic sealing layer can be regarded as the first plastic sealing layer 30. The third plastic sealing layer is also an integrated plastic sealing structure. In some embodiments, the third plastic sealing layer is an epoxy resin plastic sealing layer, and the third plastic sealing layer includes a cured epoxy resin plastic sealing material. The preparation of the interconnection structure can also refer to the preparation method of the interconnection structure 50 mentioned above.

[0071] In some embodiments of the present application, the semiconductor packaging process further includes:

[0072] After obtaining the third plastic package, a circuit layer is prepared on the exposed surface of the first package substructure stack and / or the second package substructure stack. The specific preparation method of the circuit layer can refer to the preparation method of the circuit layer 60 above.

[0073] It should be noted that the structure of each package substructure stack can be the same or different. Multiple package substructures can have the same structure or different structures. For example, in some embodiments, each module includes a package substructure, such as a package substructure including copper foil and a PCB for a stacked package, or a package substructure including a lead frame and a ceramic substrate for a stacked package.

[0074] The following uses the packaging of two modules as an example to further illustrate the packaging process of this application:

[0075] The first module includes a first package substructure including copper foil and a PCB, and the second module includes a second package substructure including a lead frame and a ceramic substrate. The ceramic substrate may be a ceramic substrate with a double-sided metal layer, such as a double-sided copper-clad ceramic substrate.

[0076] 4A and 4B , which are schematic diagrams of a process for preparing a first package substructure in an embodiment of the present application, the preparation of the first package substructure includes:

[0077] S101, fixing the copper foil 11 to the top wall of the inner wall of the upper mold 421 of the plastic molding mold 42, fixing the PCB 21 to the bottom wall of the inner wall of the lower mold 422 of the plastic molding mold 42, closing the molds and performing plastic molding to form a plastic molding layer 301, and then demolding to obtain a plastic molding body 1a;

[0078] S102, laser drilling or grooving is performed on the plastic package body 1a to form a hole 511, and then metallization filling is performed to form a metal layer 501. The metal layer 501 can be a hole filling layer including the filling hole 511 and a surface covering layer covering the surfaces on both sides of the plastic package body 1a; the metal layer 501 is then used to make a circuit to form a circuit layer, thereby obtaining a first packaging substructure 13.

[0079] The metallization filling may be performed by first forming a seed layer by sputtering or chemical plating, and then filling the layer by electroplating. The metallization may be performed by copper plating, wherein the metal layer 501 is a copper layer, and the copper layer may include a copper layer inside the hole 511 and a surface copper layer covering both sides of the plastic package body 1a.

[0080] 5A and 5B , which are schematic diagrams of a process for preparing a second package substructure in an embodiment of the present application, the preparation of the second package substructure includes:

[0081] S201, fixing the lead frame 12 to the top wall of the inner wall of the upper mold 431 of the plastic molding mold 43, fixing the ceramic substrate 22 to the bottom wall of the inner wall of the lower mold 432 of the plastic molding mold 43, closing the molds to form a plastic molding layer 302, and then demolding to obtain a plastic molding body 1b;

[0082] S202, laser drilling is performed on the plastic package body 1b, and copper plating is performed to form a copper layer. The copper layer may include a filling layer in the hole and a surface covering layer covering the surfaces on both sides of the plastic package body 1b; the plated copper layer is then used to make circuits to form a circuit layer, thereby obtaining a second packaging substructure 23.

[0083] 6A, 6B and 6C are schematic flow charts of a packaging process in one embodiment of the present application. The packaging process includes:

[0084] S301, fixing the first encapsulation substructure 13 to the top wall of the inner wall of the upper mold 441 of the plastic encapsulation mold 44, fixing the second encapsulation substructure 23 to the bottom wall of the inner wall of the lower mold 442 of the plastic encapsulation mold 44, closing the molds to form a plastic encapsulation layer 303, and then demolding to obtain a plastic encapsulation body 1c;

[0085] S302, laser drilling is performed on the plastic package body 1c, and copper plating is performed to form a copper layer, where the copper layer may include a filling layer in the hole and a surface covering layer covering both sides of the plastic package body 1c;

[0086] S303 , the copper layer is then used to fabricate circuits to form a circuit layer, thereby obtaining a semiconductor packaging structure 14 .

[0087] It can be understood that when the semiconductor packaging structure includes more packaging sub-structures, the double-sided packaging process of the present application can be used to perform stacking packaging of the packaging sub-structures.

[0088] The double-sided packaging process of the embodiment of the present application is used for stacked packaging of multiple components. Since the multiple components can be packaged in pairs and then combined, the packaging cycle can be greatly saved and the packaging efficiency can be improved by completing the packaging in pairs simultaneously. It can also significantly reduce the number of times each component undergoes packaging, reduce the impact on the components, and improve the product yield. In addition, each packaging is equivalent to forming an integrated plastic packaging structure. The formation of a multi-level integrated plastic packaging structure is conducive to improving the stability of the final semiconductor packaging structure and increasing the service life.

[0089] For example, when packaging components A, B, C, D, E, F, G, and H using the double-sided packaging process of the present invention, the following steps can be performed simultaneously: packaging components A and B to obtain a packaging substructure M1, packaging components C and D to obtain a packaging substructure M2, packaging components E and F to obtain a packaging substructure M3, and packaging components G and H to obtain a packaging substructure M4; then, packaging substructures M1 and M2 are packaged simultaneously to obtain a packaging substructure stack Y1, packaging substructures M3 and M4 to obtain a packaging substructure stack Y2; and finally, packaging substructure stack Y1 and Y2 are packaged to obtain the final semiconductor package structure product. However, according to the prior art, sequential stacking packaging requires stacking components B, C, D, E, F, G, and H on component A in sequence for packaging. Clearly, the double-sided packaging process of the present invention significantly reduces packaging time and the number of times a component undergoes packaging, thereby shortening the production cycle of semiconductor packaging structures and improving production efficiency. When the component is copper foil, the present packaging process can also directly implement a build-up layer design for metal circuits, eliminating the conventional sputtering or chemical plating deposition and electroplating thickening operations required to obtain the metal layer.

[0090] It is understandable that the plastic encapsulation mold required for this application can be designed according to the actual needs of the semiconductor packaging structure to be prepared.

[0091] 7, which is a schematic cross-sectional view of a semiconductor package structure 100 according to an embodiment of the present application. The semiconductor package structure 100 according to an embodiment of the present application includes a first plastic encapsulation layer 30, and a first layer of components to be packaged 110 and a second layer of components to be packaged 120 stacked together;

[0092] The first plastic sealing layer 30 is an integrated plastic sealing structure, and the first component layer to be packaged 110 and the second component layer to be packaged 120 are embedded in the first plastic sealing layer 30 at intervals, and the surface of the first component to be packaged 110 facing away from the second component layer to be packaged 120 is exposed to the first plastic sealing layer 30, and the surface of the second component layer to be packaged 120 facing away from the first component layer to be packaged 110 is exposed to the first plastic sealing layer 30; the first component layer to be packaged 110 and the second component layer to be packaged 120 are electrically interconnected through the interconnection structure 50 that penetrates the first plastic sealing layer 30; the first component layer to be packaged 110 includes the first component to be packaged 10, and the second component layer to be packaged 120 includes the second component to be packaged 20.

[0093] In the embodiment of the present application, the first component to be packaged 10 and the second component to be packaged 20 are respectively selected from any one of a chip, a module, a PCB, a PCBA, a lead frame, a ceramic substrate, and a copper foil.

[0094] In the embodiment of the present application, the first plastic encapsulation layer 30 includes a spacer 31 provided between the first component to be encapsulated 10 and the second component to be encapsulated 20, and a rim 32 located on the side of the first plastic encapsulation body 1. The rim 32 wraps around the first component to be encapsulated 10 and the second component to be encapsulated 20. The rim 32 includes a first end face and a second end face opposite each other. The first end face is flush with the surface of the first component to be encapsulated 10 on the side facing away from the second component to be encapsulated 20, and the second end face is flush with the surface of the second component to be encapsulated 20 on the side facing away from the first component to be encapsulated 10. Under the encapsulation effect of the first plastic encapsulation layer 30, which is an integrated structure formed by the spacer 31 and the rim 32, the first component to be encapsulated 10 and the second component to be encapsulated 20 are firmly combined into a whole, and the surfaces of the first component to be encapsulated 10 and the second component to be encapsulated 20 that need to be encapsulated are effectively covered, thereby effectively protecting the first component to be encapsulated 10 and the second component to be encapsulated 20.

[0095] In some embodiments of the present application, the first component layer 110 to be packaged also includes a circuit layer 60 arranged on the surface of the first component to be packaged 10 facing away from the second component to be packaged 20; and / or the second component layer 120 to be packaged also includes a circuit layer 60 arranged on the surface of the second component to be packaged 20 facing away from the first component to be packaged 10.

[0096] In the semiconductor packaging structure 100 of the embodiment of the present application, the specific descriptions of the first component to be packaged 10, the second component to be packaged 20, the first plastic layer 30, the interconnection structure 50, and the circuit layer 60 can be found in the previous description and will not be repeated here.

[0097] It can be understood that the packaging substructure and packaging substructure stack described above in this application all belong to the semiconductor packaging structure of this application.

[0098] The semiconductor packaging structure provided in this application has a stable structure and a high product yield, and can realize the stacked assembly of multiple components, better meeting people's requirements for multi-function and high reliability of electronic products.

[0099] The present application also provides a semiconductor device, comprising a semiconductor packaging structure produced by the semiconductor packaging process described above, or comprising the semiconductor packaging structure described above. The semiconductor device includes, but is not limited to, discrete devices, optoelectronic semiconductor devices, logic ICs, analog ICs, and memories. Discrete devices may be, for example, diodes and transistors, and optoelectronic semiconductor devices may be electroluminescent devices, laser semiconductors, light-receiving devices, optocouplers, and the like.

[0100] It should be understood that the first, second and various numerical numbers involved in this document are only distinguished for the convenience of description and are not intended to limit the scope of this application.

[0101] In this application, "and / or" describes the relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the related objects are in an "or" relationship.

[0102] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, "at least one of a, b, or c", or "at least one of a, b, and c" can all mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, and c can be single or multiple.

[0103] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. Some or all of the steps can be executed in parallel or sequentially. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Claims

1. A semiconductor packaging process, characterized in that: include: Providing a first plastic encapsulation mold, the first plastic encapsulation mold comprising an upper mold and a lower mold that match each other, the upper mold having a first groove, the lower mold having a second groove, the first groove and the second groove being arranged correspondingly; The first part to be packaged is fixed on the bottom wall of the first groove of the upper mold, and the second part to be packaged is fixed on the bottom wall of the second groove of the lower mold. After the molds are closed and plastic-sealed, a first plastic-sealed body is obtained by demolding; the first plastic-sealed body includes a first plastic-sealed layer, and the first part to be packaged and the second part to be packaged are stacked; the first part to be packaged and the second part to be packaged are embedded in the first plastic-sealed layer at intervals, and the surface of the first part to be packaged on one side facing away from the second part to be packaged is exposed to the first plastic-sealed layer, and the surface of the second part to be packaged on one side facing away from the first part to be packaged is exposed to the first plastic-sealed layer; The first plastic package body is subjected to an interconnection structure preparation to obtain a semiconductor packaging structure, wherein the interconnection structure is used to realize electrical interconnection between the first to-be-packaged component and the second to-be-packaged component.

2. The semiconductor packaging process according to claim 1, characterized in that: The size of the first groove is larger than the size of the first to-be-packaged object. When the first to-be-packaged object is fixed on the bottom wall of the first groove of the upper mold, a first gap exists between the first to-be-packaged object and the side wall of the first groove. The plane where the notch of the first groove is located is higher than the surface of the first to-be-packaged object on the side away from the bottom wall of the first groove. The size of the second groove is larger than the size of the second part to be packaged, and when the second part to be packaged is fixed on the bottom wall of the second groove of the lower mold, a second gap exists between the second part to be packaged and the side wall of the second groove, and the plane where the notch of the second groove is located is higher than the surface of the second part to be packaged on the side away from the bottom wall of the second groove; The first plastic encapsulation layer includes a spacing portion arranged between the first to-be-encapsulated component and the second to-be-encapsulated component, and an edge portion located on a side surface of the first plastic encapsulation body, and the first plastic encapsulation layer is an integral structure.

3. The semiconductor packaging process according to claim 1 or 2, characterized in that: Also includes: After obtaining the first plastic package body, a circuit layer is prepared on the exposed surface of the first component to be packaged and / or the second component to be packaged.

4. The semiconductor packaging process according to any one of claims 1 to 3, characterized in that: The preparation of the interconnection structure of the first plastic package body is specifically as follows: A through hole penetrating the first plastic packaging body is prepared along the thickness direction of the first plastic packaging body, and a conductive material is filled in the through hole to achieve vertical electrical interconnection between the first to-be-packaged component and the second to-be-packaged component.

5. The semiconductor packaging process according to any one of claims 1 to 3, characterized in that: The first component to be packaged and the second component to be packaged are respectively selected from any one of a chip, a module, a PCB, a PCBA, a lead frame, a ceramic substrate, and a copper foil.

6. The semiconductor packaging process according to claim 5, characterized in that: The module includes at least one packaging substructure, and the preparation of the packaging substructure includes: The first component is fixed to the top wall of the inner wall of the upper mold of the second plastic sealing mold, and the second component is fixed to the bottom wall of the inner wall of the lower mold of the second plastic sealing mold. After the molds are closed and sealed, the second plastic sealing body is obtained by demolding; the second plastic sealing body includes a second plastic sealing layer, and a first component and a second component stacked; the first component and the second component are embedded in the second plastic sealing layer at intervals, and a surface of the first component facing away from the second component is exposed to the second plastic sealing layer, and a surface of the second component facing away from the first component is exposed to the second plastic sealing layer; the first component and the second component are respectively selected from any one of a chip, a PCB, a PCBA, a lead frame, a ceramic substrate, and a copper foil; The second plastic package body is provided with an interconnection structure to obtain a package substructure, wherein the interconnection structure penetrates the second plastic package layer and is used to electrically interconnect the first component and the second component.

7. The semiconductor packaging process according to claim 5, characterized in that: The module includes a plurality of packaging substructures, and the preparation of the module includes: Prepare a plurality of the encapsulation substructures, and prepare the plurality of the encapsulation substructures into an encapsulation substructure stack; each of the encapsulation substructure stacks includes at least one encapsulation substructure; Fixing one package substructure stack to the top wall of the inner wall of the upper mold of the third plastic packaging mold, fixing another package substructure stack to the bottom wall of the inner wall of the lower mold of the third plastic packaging mold, closing the molds and plastic packaging, and then demolding to obtain a third plastic packaging body; The third plastic package body is subjected to an interconnection structure to obtain a module, wherein the interconnection structure is used to electrically interconnect the first package substructure stack and the second package substructure stack.

8. A semiconductor packaging structure, characterized in that: It includes a first plastic sealing layer, and a first layer of components to be packaged and a second layer of components to be packaged stacked together; The first plastic encapsulation layer is an integrated plastic encapsulation structure, the first component layer to be encapsulated and the second component layer to be encapsulated are embedded in the first plastic encapsulation layer at intervals, and a surface of the first component layer to be encapsulated facing away from the second component layer to be encapsulated is exposed to the first plastic encapsulation layer, and a surface of the second component layer to be encapsulated facing away from the first component layer to be encapsulated is exposed to the first plastic encapsulation layer; The first layer of components to be packaged and the second layer of components to be packaged are electrically interconnected via an interconnection structure penetrating the first plastic encapsulation layer; the first layer of components to be packaged includes a first component to be packaged, and the second layer of components to be packaged includes a second component to be packaged.

9. The semiconductor package structure according to claim 8, wherein: The first component to be packaged and the second component to be packaged are respectively selected from any one of a chip, a module, a PCB, a PCBA, a lead frame, a ceramic substrate, and a copper foil; the first plastic packaging layer includes a spacing portion arranged between the first component to be packaged and the second component to be packaged, and a edging portion located on the side of the first plastic packaging body, and the first plastic packaging layer is an integrated structure.

10. A semiconductor device, characterized in that: The semiconductor device comprises a packaging structure manufactured by the semiconductor packaging process according to any one of claims 1 to 7, or comprises a semiconductor packaging structure according to any one of claims 8 to 9.

Images