Die packaging structure and electronic device

Abstract

The present application relates to the technical field of dies, and provides a die packaging structure and an electronic device, capable of welding connectors and dies on a same side of an interposer. The die packaging structure comprises an interposer (10), at least one first chip (D1), at least one electronic component (20), vertical interconnects (C), and first connectors (21). The first die (D1) is arranged on the front surface of the interposer (10) and is connected to the front surface of the interposer (10). The electronic component (20) is located on the back surface (the side distant from the first die (D1)) of the interposer (10) and is electrically connected to the back surface of the interposer (10). The electronic component (20) is directly connected to the interposer (10), and can also be connected to the interposer (10) by means of a substrate (30). The vertical interconnects (C) and the first die (D1) are encapsulated within a molding layer (M1), and the bottom of each vertical interconnect (C) is electrically connected to the front surface or the back surface of the interposer (10). Each first connector (21) is located on the side of the molding layer (M1) distant from the interposer (10), and the first connector (21) is located at the top of the vertical interconnect (C) and is electrically connected to the top of the vertical interconnect (C), so that the first connector (21) is electrically connected to the interposer (10) by means of the vertical interconnect (C).

Description

Chip packaging structure and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on November 30, 2023, with application number 202311638487.1 and invention name “Chip packaging structure and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of chip technology, and in particular to a chip packaging structure and electronic equipment. Background Art

[0003] System-in-a-package (SiP) technology is an integrated circuit packaging technology that integrates multiple bare chips (dies) and passive components into a single package. In the post-Moore era, system-in-package (SiP) technology can help finished chips increase integration, reduce size, and lower power consumption. As chip manufacturing capabilities continue to evolve and the number of integrated chips continues to increase, more and more signals need to be processed, and more data needs to be transmitted externally through connectors from input and output chips (IO dies). However, the current speed of connector upgrades in the industry cannot meet the simultaneous improvement of signal transmission capabilities under the same area occupancy. Therefore, it is necessary to layout more connectors in the packaging structure to transmit data externally.

[0004] In the current new system integration packaging structure, the power supply requirements of each KGD (known good die) are met by the power supply module mounted vertically on its back, while the signal transmission requirements of each IO die are transmitted to the outside by a circle of connectors on the back. However, since the integration of the die and the adapter board is achieved through semiconductor technology, after welding multiple dies, it is necessary to fill the bottom of the multiple dies with glue and the surrounding areas with molding material for protection. This semiconductor process is incompatible with large-size connectors. Therefore, the current process cannot weld the connector and die to the same side of the adapter board. Multiple dies can only be welded on the front of the adapter board and the connector on the back of the adapter board. In this mode, the layout of a large number of connectors will occupy the area of ​​the adapter board, which will not only increase the cost, but also increase the distance between the connector and the IO die, causing severe signal attenuation. Therefore, if the connector can be assembled on both sides of the adapter board, it is of great significance to save the area of ​​the adapter board. Summary of the Invention

[0005] The present application provides a chip packaging structure and an electronic device, which can weld a connector and a chip (die) on the same side of an adapter board.

[0006] The present application provides a chip packaging structure, which includes an adapter board, at least one first chip (which may be simply referred to as a chip), at least one electronic component, a connector, and a first connector. The first chip is arranged on the front of the adapter board and is connected to the front of the adapter board. The electronic component is located on the back of the adapter board (the side away from the first chip) and is electrically connected to the back of the adapter board; the electronic component is directly connected to the adapter board or can be connected through a substrate. The connector and the first chip are both plastic-encapsulated in a plastic layer, and the bottom of the connector is electrically connected to the front or back of the adapter board. The first connector is located at the top of the connector and is electrically connected to the top of the connector, so that the first connector is electrically connected to the adapter board through the connector.

[0007] In this chip packaging structure, a feedthrough is provided below the first connector, and the feedthrough serves as an intermediate connection structure to lead the signal on the adapter board to the first connector above. In this case, the feedthrough and the chip can be encapsulated in a plastic layer. In this way, the feedthrough serves as an intermediate connection structure to lead the signal to the first connector above, while avoiding the plastic layer wrapping around the first connector, thereby ensuring that the first connector can transmit the chip (such as an IO die) signal outward through the feedthrough, solving various problems caused by the inability to mount the connector and the chip on the same side of the adapter board in the prior art.

[0008] In some possible implementations, the top of the communicating vessel is flush with the surface of the first chip on a side away from the transfer board.

[0009] In some possible implementations, the communicating vessel includes a support plate, a first metal connecting structure, and a second metal connecting structure. An intermediate metal connecting structure is disposed within the support plate. The first metal connecting structure is disposed on top of the support plate and connected to the intermediate metal connecting structure, while the second metal connecting structure is disposed on the bottom of the support plate and connected to the intermediate metal connecting structure. The communicating vessel is connected to the first connector via the first metal connecting structure and to the adapter plate via the second metal connecting structure.

[0010] In some possible implementations, the chip packaging structure further includes a second connector; the second connector and the first connector are arranged on different sides of the adapter board, and the second connector is directly connected to the back side of the adapter board or connected through a substrate. In other words, the first connector and the second connector are respectively arranged on the front and back sides of the adapter board, so that the connectors are arranged on both sides of the adapter board. In this way, the number of connectors arranged can be multiplied, and the system's ability to transmit data to the outside can be multiplied. At the same time, placing multiple connectors on both sides of the adapter board also avoids the problem of increased costs due to increased area of ​​the adapter board, as well as the problem of signal attenuation due to increased distance between the chip and the connector.

[0011] In some possible implementations, the feed-through and the first chip are located on the same side of the adapter board, that is, both are disposed on the front surface of the adapter board, with the bottom of the feed-through electrically connected to the front surface of the adapter board. In this case, the first connector can be electrically connected to the front surface of the adapter board through the feed-through, thereby enabling external transmission of the chip's signals.

[0012] In some possible implementations, the adapter board includes: a silicon interposer and a redistribution layer. The front side of the silicon interposer has a metal routing layer, and a through silicon via (TSV) is provided in the silicon interposer. The redistribution layer is provided on the back side of the silicon interposer and is electrically connected to the through silicon via. The first chip is provided on the front side of the silicon interposer. The edge of the redistribution layer extends beyond the edge of the silicon interposer, and the connecting pipe is provided on the surface of the redistribution layer around the silicon interposer and is electrically connected to the redistribution layer. In this case, the first connector is electrically connected to the redistribution layer through the connecting pipe, thereby enabling the chip signal to be transmitted outward. In addition, multiple first chips are interconnected through the metal routing layer on the front side of the silicon interposer, and the silicon interposer can be processed by silicon-based technology, which can meet the high bandwidth density interconnection requirements between multiple chips, such as an interconnection bandwidth density of more than 2Tbps / mm. On the back of the adapter board, multiple electronic components are connected to the redistribution layer. The redistribution layer can use thick metal layers and thick dielectric layers with better current sharing capabilities, thereby meeting the electronic components' demand for high-speed serdes (serializer / deserializer) driving with large current sharing capabilities, low impedance, and long distances. As shown, the line width, line spacing, and line thickness of the metal traces in the metal trace layer on the front of the silicon interposer are all less than 5μm. The line width, line spacing, and line thickness of the metal traces in the redistribution layer are all greater than 5μm.

[0013] In some possible implementations, the adapter board includes: a first redistribution layer and a second redistribution layer stacked together. The chip is disposed on the surface of the first redistribution layer. A feedthrough is disposed on the surface of the first redistribution layer, such that a first connector is electrically connected to the first redistribution layer via the feedthrough, thereby enabling external transmission of chip signals. Alternatively, the edge of the second redistribution layer extends beyond the edge of the first redistribution layer, and the feedthrough is disposed on the surface of the second redistribution layer surrounding the first redistribution layer, thereby enabling external transmission of chip signals. Furthermore, the first redistribution layer can utilize thin metal and dielectric layers to meet the requirements of high-bandwidth interconnection between multiple chips; the second redistribution layer can utilize thick metal and dielectric layers with improved current sharing capabilities to meet the electronic components' requirements for high-current sharing, low impedance, and long-distance high-speed SerDes (SerDes) driving. For example, the line width, line spacing, and line thickness of the metal traces in the first redistribution layer are all less than 5μm; while the line width, line spacing, and line thickness of the metal traces in the second redistribution layer are all greater than 5μm.

[0014] In some possible implementations, the connector is located on the side of the adapter board, and the bottom of the connector is electrically connected to the back side of the adapter board (that is, the side where the electronic components are provided) through the substrate. In this way, the first connector is electrically connected to the back side of the adapter board through the connector, thereby enabling the chip signal to be transmitted outward.

[0015] In some possible implementations, an adapter board includes a silicon interposer and a redistribution layer. The front of the silicon interposer has a metal routing layer, and through-silicon vias (TSVs) are provided within the silicon interposer. The redistribution layer is provided on the back of the silicon interposer and is electrically connected to the TSVs. A first chip is provided on the front of the silicon interposer. In this case, the edges of the silicon interposer and the redistribution layer can be flush or nearly flush, and a feedthrough is provided on the sides of the silicon interposer and the redistribution layer. The bottom of the feedthrough is electrically connected to the back of the redistribution layer (i.e., the side away from the silicon interposer) through the substrate, thereby electrically connecting the first connector to the back of the redistribution layer through the feedthrough, thereby enabling the chip's signal to be transmitted externally. In addition, multiple chips are interconnected via the metal routing layer on the surface of the silicon interposer, and the silicon interposer is processed using a silicon-based process, which can meet the high-bandwidth density interconnection requirements between multiple chips. On the back of the adapter board, multiple electronic components are connected to the redistribution layer. The redistribution layer can use thick metal layers and thick dielectric layers with better current sharing capabilities, thereby meeting the electronic components' requirements for high current sharing capabilities, low impedance, and long-distance high-speed SerDes driving.

[0016] In some possible implementations, the adapter board includes: a first redistribution layer and a second redistribution layer arranged in a stacked manner. The chip is arranged on the surface of the first redistribution layer. The connecting pipe is arranged on the side of the first redistribution layer and the second redistribution layer; the connecting pipe is electrically connected to the back of the second redistribution layer through the substrate, so that the first connector can be electrically connected to the back of the second redistribution layer through the connecting pipe, thereby enabling the chip signal to be transmitted outward. In addition, the first redistribution layer can adopt a thin metal layer and a thin dielectric layer to meet the high-bandwidth density interconnection requirements between multiple chips; the second redistribution layer can adopt a thick metal layer and a thick dielectric layer with better current sharing capability, so as to meet the electronic components' requirements for large current sharing capability, low impedance, long-distance high-speed serdes drive. Schematically, the line width, line spacing, and line thickness of the metal traces in the first redistribution layer are all less than 5μm; the line width, line spacing, and line thickness of the metal traces in the second redistribution layer are all greater than 5μm.

[0017] In some possible implementations, the adapter board may further include a glass wafer disposed between the first redistribution layer and the second redistribution layer, wherein the glass wafer is provided with through glass vias (TGVs), and the second redistribution layer through glass vias are electrically connected to the first redistribution layer.

[0018] In some possible implementations, the adapter board further includes a bridge chip; the glass wafer is provided with a groove, into which the bridge chip is embedded, and the active surface of the bridge chip is electrically connected to the first chip via a first redistribution layer. In this case, because the bridge chip can be manufactured using a silicon-based process, the line width, line spacing, and line thickness on the bridge chip surface can meet the requirements of high-bandwidth interconnection density between multiple chips.

[0019] In some possible implementations, the adapter board is further provided with a bridge chip and metal pillars. The bridge chip and the metal pillars are connected between the first redistribution layer and the second redistribution layer and are encapsulated in the plastic encapsulation layer. The second redistribution layer is electrically connected to the first redistribution layer via the metal pillars, and the active surface of the bridge chip is electrically connected to the first chip via the first redistribution layer. Because the bridge chip can be manufactured using a silicon-based process, the line width, line spacing, and line thickness on the bridge chip surface can meet the high-bandwidth density interconnect requirements between multiple chips.

[0020] In some possible implementations, the at least one first chip may include one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

[0021] In some possible implementations, the at least one electronic component includes one or more of a power supply module, a control module, a connector, a clock device, a rectifier, and a resistor, capacitor, and inductor.

[0022] In some possible implementations, the chip packaging structure includes: a plurality of first chips and a plurality of electronic components.

[0023] In some possible implementations, the multiple electronic components include multiple power supply modules, which are respectively disposed opposite to the multiple first chips. The power supply modules are electrically connected to the oppositely disposed first chips via an adapter board and supply power to the corresponding first chips.

[0024] In some possible implementations, the chip packaging structure includes: multiple substrates; the substrates are located on the back of an adapter board. Multiple devices located on the back of the adapter board are connected to the adapter board via the multiple substrates; the multiple devices may include one or more of electronic components, connectors, and second connectors. This allows for flexible selection of multiple substrate types based on the electrical requirements of the devices to improve overall system performance. Furthermore, the use of multiple discrete substrates can mitigate mechanical stress caused by thermal mismatch during assembly and service scenarios brought about by a single, continuous substrate, improving system assembly and service reliability.

[0025] In some possible implementations, the multiple substrates are encapsulated in a molding layer to protect the multiple substrates through the molding layer.

[0026] In some possible implementations, the chip packaging structure further includes a first heat sink and a second heat sink. The first heat sink is disposed on a side of the first chip away from the adapter plate, and the second heat sink is disposed on a side of the electronic component away from the adapter plate. The two heat sinks ensure heat dissipation in the chip packaging structure.

[0027] In some possible implementations, the chip packaging structure further includes: a fixing structure; the fixing structure penetrates and securely fixes the first heat sink, the adapter plate, and the second heat sink.

[0028] In some possible implementations, the chip packaging structure also includes a first electronic device located on the side of the plastic layer away from the adapter board. The first electrode device can be a device other than the connector, such as a power supply module, etc. The first electronic device can be electrically connected to the adapter board through a connector.

[0029] The present application also provides an electronic device, which includes a circuit board and a chip packaging structure provided in any of the possible implementation methods described above, wherein the chip packaging structure is electrically connected to the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic plan view of a chip packaging structure provided in an embodiment of the present application;

[0031] FIG2 is a schematic cross-sectional view of FIG1 along the AA' position;

[0032] FIG3 a is a schematic plan view of a chip packaging structure provided in the prior art;

[0033] FIG3 b is a schematic cross-sectional view of FIG3 b ;

[0034] FIG4 is a plan view of a chip packaging structure provided in an embodiment of the present application;

[0035] FIG5 is a plan view of a chip packaging structure provided in an embodiment of the present application;

[0036] FIG6 is a plan view of a chip packaging structure provided in an embodiment of the present application;

[0037] FIG7 is a schematic structural diagram of a communicating vessel provided in an embodiment of the present application;

[0038] FIG8 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0039] FIG9 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0040] FIG10 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0041] FIG11 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0042] FIG12 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0043] FIG13 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0044] FIG14 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0045] FIG15 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0046] FIG16 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0047] FIG17 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0048] FIG18 is a schematic diagram of a chip packaging structure during the manufacturing process provided by an embodiment of the present application;

[0049] FIG19 is a schematic diagram of a chip packaging structure during the manufacturing process provided by an embodiment of the present application;

[0050] FIG20 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application during the manufacturing process;

[0051] FIG21 is a schematic diagram of a chip packaging structure during the manufacturing process provided by an embodiment of the present application;

[0052] FIG22 is a schematic diagram of a chip packaging structure during the manufacturing process provided by an embodiment of the present application;

[0053] FIG23 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0054] FIG24 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0055] FIG25 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0056] FIG26 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0057] FIG27 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0058] FIG28 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0060] The terms "first", "second", etc. in the specification, embodiments, claims, and drawings of this application are only used for the purpose of distinguishing descriptions and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "Installation", "connection", "connected", etc. should be understood in a broad sense, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection between two elements. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products, or devices are not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to the processes, methods, products, or devices. "Up," "down," "left," "right," etc. are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts and are used for relative description and clarification. They may change accordingly depending on the orientation of the components in the drawings.

[0061] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, etc., and the present application does not impose any restrictions on this.

[0062] For example, the above-mentioned consumer electronic products may include mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products may include smart door locks, televisions, smart speakers, refrigerators, robot vacuums, etc. Car-mounted electronic products may include car navigation systems, car displays, etc. Financial terminal products may include automated teller machines (ATMs) and electronic devices for self-service transactions, etc. Communication electronic products may include communication equipment such as servers, storage devices, radars, and base stations.

[0063] The electronic device includes a printed circuit board (PCB) and a chip packaging structure electrically connected to the PCB. This chip packaging structure employs a novel structure that allows the connector and die to be soldered to the same side of the adapter board. For example, the chip packaging structure of the present application may be a system-in-package (SIP) structure.

[0064] The chip packaging structure of this application enables connectors to be placed on both sides of the adapter board, exponentially increasing the number of connectors that can be placed and the system's ability to transmit external data. Furthermore, placing connectors on both sides of the adapter board avoids the cost increase associated with increased board area and the signal attenuation caused by the increased distance between the input / output chip (IO die) and the connector.

[0065] This application does not limit the application scenarios of the above chip packaging structure. For example, the chip packaging structure can be used in scenarios such as large servers, high-bandwidth switches, and supercomputers for AI computing.

[0066] The chip packaging structure provided in this application is described in detail below through specific embodiments.

[0067] Example 1

[0068] FIG1 is a schematic plan view of a chip packaging structure provided in accordance with the first embodiment of the present invention, and FIG2 is a schematic cross-sectional view taken along line AA′ in FIG1 .

[0069] Schematically, as shown in Figures 1 and 2, this embodiment provides a chip packaging structure, which includes an adapter board 10, at least one chip D, one or more feedthroughs C, and one or more first connectors 21. The chip D, feedthroughs C, and first connectors 21 are arranged on the same layer of the adapter board 10.

[0070] FIG1 is merely a schematic illustration of a chip package structure comprising multiple chips D, multiple first connectors 21, and multiple feedthroughs C. The distribution of the chip D array shown in FIG1 is merely a reference; in practice, the multiple chips D may be distributed in different ways as needed, and the D chips themselves may also be composed of multiple chip types. FIG2 omits the smaller chips surrounding the larger chip array in FIG1 , and this applies to all subsequent figures.

[0071] The above-mentioned multiple chips D can be a central processing unit (CPU), a graphics processing unit (GPU), a memory, an input and output chip (IO die), an integrated passive device (IPD), etc., or they can be integrated with other packaged functional modules, such as HBM (high bandwidth memory), DOI (die on silicon interposer), FOI (fan out RDL interpose), etc. In practice, multiple chips D can be set as needed.

[0072] Schematically, referring to FIG1 , the multiple chips D in the chip package structure may include: multiple larger first chips D1 and multiple smaller second chips D2. The multiple first chips D1 may be located in the center of the adapter board 10, and the multiple second chips D2 may be distributed around the multiple first chips D1. The multiple first chips D1 may be chips for logic, computing, data exchange, and other fields, and the multiple second chips D2 may be input / output chips (i.e., IO chips), integrated passive devices (IPDs), etc., but the present application is not limited thereto.

[0073] Schematically, referring to Figures 1 and 2, multiple chips D and multiple connectors C are arranged on the upper surface of the adapter board 10 and are electrically connected to the adapter board 10. The first connector 21 is arranged above the connector C (that is, on the side away from the adapter board 10) and is connected to the top of the connector C, that is, the bottom of the connector C is connected to the adapter board 10, and the top of the connector C is connected to the first connector 21. The first connector 21 is electrically connected to the adapter board 10 through the connector C. In this case, the multiple connectors C and the multiple chips D can be plastic-encapsulated in the plastic layer M1, and the tops of the multiple connectors C can be flush with the tops of the multiple chips D and expose the plastic layer M1. The connector C, as an intermediate connection structure, can lead the signal to the first connector 21 above to ensure that the first connector 21 can transmit the signal of the chip D (such as IO die) to the outside through the connector C and the adapter board 10, thereby solving the various problems caused by the inability to mount the connector and the chip on the same side of the adapter board in the prior art.

[0074] It should be noted that the first connector 21 can be directly connected to the top of the communicating vessel C or connected through other connecting parts. For example, the first connector 21 can be connected to the top of the communicating vessel C through a substrate (also called a connector substrate). This application does not impose any restrictions on this, and it can be set up as needed in practice.

[0075] The substrate involved in this application can be manufactured using one or more of the following processes: substrate process, carrier-like process, printed circuit board (PCB) process, or other intermediate transition board processes, and this application does not impose any restrictions on this.

[0076] The present application does not limit the specific positions of the chip D and the connector C on the upper surface of the adapter plate 10 , and they can be arranged as needed. For example, in some possible implementations, the connector C can be arranged at the edge area of ​​the adapter plate 10 .

[0077] On this basis, in order to realize the layout of connectors on both the front and back sides of the adapter board 10, as shown in Figure 2, in some possible implementation methods, the chip packaging structure may also include one or more second connectors 22, which are located below the adapter board 10 and are directly connected to the lower surface of the adapter board 10 or connected through the substrate 30. In this way, by setting the first connector on the front side of the adapter board 10 and the second connector 22 on the back side, the number of connectors (21, 22) can be multiplied, and the system data transmission capability can be multiplied. At the same time, the layout of multiple connectors (21, 22) on both the front and back sides of the adapter board 10 also avoids the problem of cost increase caused by increasing the area of ​​the adapter board 10, and the problem of signal attenuation caused by the increased distance between the chip D and the connector (21, 22).

[0078] For illustration, it is taken as an example that 16 connectors need to be provided in the chip packaging structure.

[0079] Figures 3a and 3b are plan and cross-sectional views of a conventional method of single-sided mounting connectors on the back of an adapter board. Referring to Figures 3a and 3b, placing all 16 connectors on the back of the adapter board increases the board's area and the distance between the connectors and chip D.

[0080] In contrast, as shown in reference figures 1 and 2, the present application can arrange 16 connectors on the front and back sides of the adapter board 10, and can arrange 8 first connectors 21 on the front side of the adapter board 10, and 8 second connectors 22 on the back side of the adapter board 10. This not only reduces the area of ​​the adapter board and reduces the cost, but also shortens the distance between the chip D and the connectors (21, 22), making the signal transmission better.

[0081] Of course, if the number of connectors in the chip package structure is small, in some possible implementations, the chip package structure can be provided with the aforementioned first connector 21 only on the same side of the chip D to meet signal transmission requirements. The following embodiments are all described using the example of layout of connectors on both the front and back sides of the adapter board 10.

[0082] The following describes the configuration of the connecting vessel C.

[0083] First, in the chip packaging structure, the connection between the connecting vessel C and the first connector 21 can be one-to-one or one-to-many, and this application does not impose any restrictions on this.

[0084] For example, as shown in FIG4 , in some possible implementations, in the chip packaging structure, different connectors C may be provided for different first connectors 21 , that is, different first connectors 21 are electrically connected to the adapter board 10 through different connectors C, respectively.

[0085] For another example, as shown in FIG5 , in some possible implementations, in the chip packaging structure, different connectors C may be respectively arranged on different sides of the adapter board 10. In this case, multiple first connectors 21 located on the same side may be electrically connected to the adapter board 10 through the same connector C.

[0086] For another example, as shown in FIG6 , in some possible implementations, only one feed-through C may be provided in the chip packaging structure, and all first connectors 21 are electrically connected to the adapter board 10 through the same feed-through C. Schematically, the feed-through C may be a ring-shaped structure (or a frame-shaped structure).

[0087] It should be understood that Figures 4, 5 and 6 only illustrate the eight first connectors 21 located on the front side of the adapter board 10 and arranged on the same side as the chip D. The back side of the adapter board 10 can be provided with one or more second connectors 22 according to actual needs. For example, eight second connectors 22 can be provided on the back side of the adapter board 10.

[0088] Furthermore, the structure of the feedthrough C itself is primarily characterized by the electrical connection between the bottom and top, without limiting its compositional materials. For example, a metal connection structure with a metallized design can be used. There are various ways to implement this feedthrough C, such as using a plate with a through-hole process or a through-glass via (TGV) process.

[0089] Schematically, as shown in FIG7 , in some possible implementations, a feed-through C includes a support plate 301, a first metal connection structure P1 disposed on the top of the support plate 301, a second metal connection structure P2 disposed on the bottom, and an intermediate metal connection structure 302 disposed within the support plate 301. The first metal connection structure P1 and the second metal connection structure P2 are connected via the intermediate metal connection structure 302. In this case, the feed-through C can be connected to the first connector 21 via the first metal connection structure P1 and to the adapter board 10 via the second metal connection structure P2, thereby achieving electrical connection between the first connector 21 and the adapter board 10 through the feed-through C.

[0090] Illustratively, the first metal connection structure P1 and the second metal connection structure P2 may be metal pads or metal pillars, but are not limited thereto and may be configured as required in practice.

[0091] As shown, the intermediate metal connection structure 302 may be a copper via or a multi-layer metal trace, but is not limited thereto and may be configured as required in practice.

[0092] For example, in some embodiments, the first metal connection structure P1 and the second metal connection structure P2 may be copper pillars or copper pads, and the intermediate metal connection structure 302 may be a copper via.

[0093] In addition, referring to FIG. 2 , during the fabrication of the chip packaging structure, a thermosetting material is typically used to fill the bottoms and gaps of the multiple chips D and the multiple vias C. After filling, the back surfaces of the chips D and the connection structures (e.g., pads) on the surfaces of the vias C are exposed by grinding to form a mold layer M1 to protect the multiple chips D and the multiple vias C. In this case, the top surfaces of the multiple chips D and the multiple vias C (i.e., the surfaces away from the adapter board 10) are flush.

[0094] Of course, the filling of the bottoms and gaps of the multiple chips D and the multiple communicating vessels C can be a single filling process or a double filling process. This application does not impose any restrictions on this, and it can be set as needed in practice.

[0095] The thermosetting materials mentioned in this application may include underfill (UF), molded underfill (MUF), epoxy molding compound, etc. The thermosetting materials mentioned below are all the same and will not be described in detail.

[0096] In addition, according to actual needs, as shown in Figure 2, the chip packaging structure can also be provided with multiple electronic components 20 on the side of the adapter board 10 where the second connector 22 is provided, and the electronic components 20 are directly connected to the adapter board 10 or connected through the substrate 30.

[0097] The aforementioned multiple electronic components 20 may include power supply modules, control modules, connectors, clock components, rectifiers, resistors, capacitors, and inductors. The power supply module may be a voltage regulator module (VRM) or other modules related to electrical transmission, voltage transformation, and rectification. The connector may be an electrical connector for transmitting electrical signals or an optoelectronic connector for transmitting optical signals. In practice, multiple electronic components 20 may be provided as needed.

[0098] As shown, in some possible implementations, the multiple electronic components 20 below the adapter board 10 may include multiple power supply modules, and the multiple power supply modules are respectively arranged opposite to the multiple chips above, that is, the multiple power supply modules are respectively located entirely below the multiple chips, or the projections of the power supply modules and the relatively arranged chips on the adapter board 10 overlap (partially or completely), and the multiple power supply modules are electrically connected to the multiple chips D above through the adapter board 10, so that vertical power supply can be provided to the chips D located above through the power supply modules.

[0099] This application does not limit the connection method between the electronic component 20, the second connector 22 and the adapter board 10. The electronic component 20 and the second connector 22 can be directly connected to the adapter board 10, or they can be indirectly connected through other components such as a substrate or a printed circuit board (PCB). In practice, they can be set as needed.

[0100] In order to meet the electrical requirements of different devices, in some possible implementation methods, as shown in Figure 8, multiple discrete substrates 30 can be used under the adapter board 10, and the number of layers and specifications of the multiple substrates 30 may not be exactly the same. In this case, multiple electronic components 20 and multiple second connectors 22 can be connected to the redistribution layer RDL through multiple discrete substrates 30. This application does not impose any restrictions on this, and in practice it can be set as needed. For example, one electronic component 20 or one second connector 22 can be installed on a single substrate 30, or multiple electronic components 20 or multiple second connectors 22 can be installed, or electronic components 20 and second connectors 22 can be installed at the same time.

[0101] By providing multiple discrete substrates 30, the types of the multiple substrates 30 can be flexibly selected according to the electrical requirements of the devices (20, 22) to improve the performance of the entire system. For example, a multi-layer substrate can be configured only for electronic components 20 that require a complex multi-layer substrate, while a simple substrate can be configured for electronic components 20 that require a simple substrate.

[0102] In addition, the use of multiple discrete substrates 30 can also alleviate the mechanical stress caused by thermal mismatch in assembly and service scenarios brought about by a large continuous substrate, which is more friendly to system assembly and service reliability.

[0103] The present application does not impose any restrictions on the electrical connection method between the substrate 30 and the adapter board 10 , and it can be set as needed in practice.

[0104] As an illustration, in some possible implementations, the plurality of substrates 30 and the adapter plate 10 may be connected to each other by one or a combination of connection methods such as welding, crimping, and plugging.

[0105] The above-mentioned multiple substrates 30 can be manufactured using one or more of the following processes: substrate process, carrier-like process, printed circuit board (PCB) process or other intermediate transition board processes, and this application does not impose any restrictions on this.

[0106] On this basis, as shown in FIG8 , in some possible implementation methods, a thermosetting material can be used to fill the bottom and gaps of multiple substrates 30 , and after filling, the back side of the substrate 30 and the connection structure (such as Cu Stud) can be exposed by grinding to form a mold layer M2 to protect the multiple substrates 30 .

[0107] In addition, in some possible implementations, as shown in FIG8 , a first heat sink 41 and a second heat sink 42 may be further provided in the chip packaging structure. The first heat sink 41 is provided on a side of the plurality of chips D away from the adapter plate 10, and the second heat sink 42 is provided on a side of the plurality of electronic components 20 away from the adapter plate 10. The provision of two heat sinks (41, 42) satisfies the heat dissipation requirements of the chip packaging structure.

[0108] As shown, the gap between the chip D and the first heat sink 41 can be filled with thermal interface materials (TIM). The TIM can be a heat dissipation medium such as thermal gel, thermal grease, graphene, or liquid metal, and is not limited here. Similarly, the gap between the electronic component 20 and the second heat sink 42 can also be filled with TIM.

[0109] The present application does not impose any restrictions on the arrangement of the heat dissipation plates (41, 42), which can be arranged as needed in practice.

[0110] For example, in some possible implementations, the heat dissipation plates (41, 42) may be metal cover plates.

[0111] For another example, in some possible implementations, the heat sinks (41, 42) may be hollow structures to support water cooling or liquid cooling.

[0112] For another example, the heat sink (41, 42) may have a hollow structure such as a through-hole structure or a grid. In this case, the heat sink can meet the heat dissipation requirements while supporting the external power supply system to be vertically interconnected with the electrical components 20 on the back of the chip through the hollow area.

[0113] In the packaging structure, the thickness, material, and structure of the first heat dissipation plate 41 and the second heat dissipation plate 42 may be the same or different, and this application does not impose any limitation thereto.

[0114] In addition, as shown in Figure 8, in some possible implementation methods, in order to ensure balanced force inside the chip packaging structure, a support frame 43 can be provided in the chip packaging structure. The support frame 43 is located in the gap between the electronic components 20, and the upper end of the support frame 43 can be in contact with the substrate 30, and the lower end can be in contact with the second heat dissipation plate 42.

[0115] On this basis, in order to fix the first heat sink 41, the second heat sink 42 and the packaging system, as shown in Figure 8, in some possible implementation methods, a fixing structure 50 can be set in the chip packaging structure. The fixing structure 50 passes through the first heat sink 41, the second heat sink 42 and the adapter plate 10, and supports and fixes the first heat sink 41, the second heat sink 42 and the adapter plate 10.

[0116] Schematically, as shown in FIG8 , in some possible implementations, the fixing structure 50 may include bolts and nuts, with the bolts passing through the first heat sink 41, the second heat sink 42, and the adapter plate 10, and the nuts being fixed at one end of the bolts, thereby securing the first heat sink 41, the second heat sink 42, and the adapter plate 10. In this case, the first heat sink 41 and the second heat sink 42 not only provide heat dissipation but also stabilize the structure.

[0117] In addition, the present application does not impose any restrictions on the configuration of the adapter board 10 in the chip packaging structure, and it can be configured as needed in practice.

[0118] The following provides a plurality of adapter plates 10 with different configuration structures.

[0119] The configuration structure of the adapter plate 10

[0120] Schematically, as shown in FIG9 , in some possible implementations, the adapter board 10 may include a silicon interposer 1 (Si interposer) and a redistribution layer RDL (redistribution layer).

[0121] As shown in Figure 9, silicon interposer 1 includes a silicon wafer a1 and a metal routing layer a2 disposed on the surface of silicon wafer a1 (the surface away from the RDL). Silicon wafer a1 is provided with multiple through silicon vias (TSVs). Metal routing layer a2 is connected to the multiple TSVs.

[0122] As shown, the line width, line spacing and line thickness of the metal wiring in the metal wiring layer a2 may be less than 5 μm.

[0123] Illustratively, the apertures of the plurality of through silicon vias (TSVs) may be in the range of 1 μm to 30 μm.

[0124] Illustratively, the thickness of the silicon interposer 1 may be in the range of 5 μm to 200 μm.

[0125] In the application, the front side of the silicon interposer is the surface on the side where the metal trace layer a2 is provided. The back side of the silicon interposer is the surface on the side of the silicon wafer a1 where the metal trace layer a2 is not provided, that is, the back side of the silicon wafer a1 (the surface away from the metal trace layer a2).

[0126] The redistribution layer (RDL) is located on the backside of silicon wafer a1 (i.e., the surface away from metal trace layer a2). It connects to metal trace layer a2 via multiple through-silicon vias (TSVs) in silicon wafer a1. The line width, line spacing, and line thickness of the metal traces in the RDL can be greater than 5μm.

[0127] A plurality of chips D are disposed on the upper surface of a silicon interposer and are electrically connected to the metal wiring layer a2.

[0128] The edge of the RDL can extend beyond the edge of the silicon interposer 1 (Si interposer). Multiple vias C are disposed around the RDL surface around the Si interposer and electrically connected to the RDL. In this case, the first connector 21 is electrically connected to the RDL through the vias C.

[0129] It should be understood that in the present application, the connector C can provide the chip D with a power or signal transmission path to the back side of the wafer. According to actual needs, other electronic devices (such as power supply modules, etc.) can also be provided to be electrically connected to the redistribution layer RDL through the connector C. Multiple electronic components 20 and multiple second connectors 22 are arranged below the redistribution layer RDL and are connected to the redistribution layer RDL through different substrates 30.

[0130] In this case, as shown in FIG9 , the signal transmission path between chip D and first connector 21 is: chip D → silicon interposer → redistribution layer (RDL) → connector C → connector substrate (optional, not shown in FIG9 ) → first connector 21. The signal transmission path between chip D and second connector 22 is: chip D → silicon interposer → redistribution layer (RDL) → connector substrate 30 (optional) → second connector 22. This allows data within the chip to be simultaneously transmitted to connectors (21, 22) on both sides of the adapter board 10.

[0131] The following briefly describes the related settings of the metal routing layer a2 and the redistribution layer RDL.

[0132] The metal routing layer a2 on the surface of the silicon interposer 1 can be processed through a silicon-based process, so that the line width, line spacing, and line thickness of the metal routing in the metal routing layer a2 are less than 5μm, thereby meeting the high bandwidth density interconnection requirements between multiple chips D, such as an interconnection bandwidth density of more than 2Tbps / mm.

[0133] For example, in some possible implementations, the metal wiring layer a2 may be implemented using a damascene process including deposition, exposure, etching, electroplating, chemical mechanical polishing (CMP), and other processes.

[0134] As shown, the line width / line spacing / line thickness in the metal routing layer a2 can reach 0.4 μm, and the number of layers can be processed to more than 3 layers.

[0135] Illustratively, the wiring layer in the metal wiring layer a2 may be made of copper (Cu), but is not limited thereto.

[0136] Illustratively, the dielectric layer in the metal wiring layer a2 can be made of one or more insulating dielectric materials such as polyimide (PI), polybenzoxazoles (PBO), silicon dioxide SiO2, silicon nitride SiN, and silicon carbon nitride SiCN, but is not limited thereto.

[0137] The above-mentioned redistribution layer RDL can adopt a thick metal layer and a thick dielectric layer with better current sharing capability. For example, the line width / line spacing / line thickness of the redistribution layer RDL can be above 5μm, thereby being able to meet the electronic component 20's high-speed serdes (serializer / deserializer, serializer / deserializer) driving requirements for large current sharing capability, low impedance, and long distance (such as above 5mm).

[0138] For example, in some possible implementations, the redistribution layer (RDL) may be implemented through a yellow light process including steps such as coating / filming, exposure, development, and curing.

[0139] Illustratively, the wiring layer in the redistribution layer RDL may be made of copper (Cu), but is not limited thereto.

[0140] For example, the dielectric layer in the redistribution layer RDL may be made of one or more dielectric materials such as polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO), but is not limited thereto.

[0141] Setting structure 2 of adapter plate 10

[0142] 10 , in some possible implementations, the interposer 10 may include: a first redistribution layer RDL1 and a second redistribution layer RDL2. The first redistribution layer RDL1 is closer to the chip D than the second redistribution layer RDL2.

[0143] The chips D and the connectors C are disposed on the upper surface of the first redistribution layer RDL1 (i.e., the surface away from the second redistribution layer RDL2) and are electrically connected to the first redistribution layer RDL1. The first connector 21 is electrically connected to the first redistribution layer RDL1 through the connectors C.

[0144] The plurality of electronic components 20 and the plurality of second connectors 22 are located below the second redistribution layer RDL2 (ie, away from the first redistribution layer RDL1 ), and are electrically connected to the second redistribution layer RDL2 through different substrates 30 .

[0145] In this case, as shown in FIG10 , the signal transmission path between chip D and first connector 21 is: chip D → first redistribution layer RDL1 → feedthrough C → connector substrate (optional, not shown in FIG10 ) → first connector 21. The signal transmission path between chip D and second connector 22 is: chip D → first redistribution layer RDL1 → second redistribution layer RDL2 → connector substrate 30 (optional) → second connector 22. This allows data within the chip to be simultaneously transmitted to connectors (21, 22) on the front and back sides of adapter board 10.

[0146] The first redistribution layer RDL1 and the second redistribution layer RDL2 are briefly described below.

[0147] The first redistribution layer (RDL1) can be constructed using thin metal and dielectric layers, with line widths, line spacing, and line thicknesses of less than 5μm. In this case, the first redistribution layer (RDL1) can extend the connection pads on the bridge chip (BG) surface in the bridge chip (BG) region, enabling the high-bandwidth interconnection requirements between chips D to be met through the bridge chip (BG).

[0148] Illustratively, the first redistribution layer RDL1 may be implemented by a damascene process including deposition, exposure, etching, electroplating, and CMP.

[0149] The second redistribution layer RDL2 can be configured to use a thick metal layer and a thick dielectric layer. For example, the line width / line spacing / line thickness can be above 5 μm, thereby meeting the requirements of large current sharing and long routing capabilities of the electronic component 20.

[0150] Illustratively, the wiring layers in the first redistribution layer RDL1 and the second redistribution layer RDL2 may be made of copper (Cu), but the present invention is not limited thereto.

[0151] Illustratively, the second redistribution layer RDL2 may be implemented by a yellow light process including coating / filming, exposure, development, and curing.

[0152] Illustratively, the dielectric layers in the first redistribution layer RDL1 and the second redistribution layer RDL2 may be made of one or more dielectric materials such as polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO), but are not limited thereto.

[0153] Setting structure 3 of adapter plate 10

[0154] Schematically, as shown in FIG11 , in some possible implementations, the adapter board 10 can be similar to the adapter board in the second configuration, with the only difference being that the edge of the second redistribution layer RDL2 extends beyond the edge of the first redistribution layer RDL1. In this case, the feedthrough C can be disposed on the surface of the second redistribution layer RDL2 around the first redistribution layer RDL1.

[0155] For other related settings, please refer to the instructions in Setting Structure 2 and will not be repeated here.

[0156] In this configuration, as shown in FIG11 , the signal transmission path from chip D to first connector 21 is: chip D → first redistribution layer RDL1 → second redistribution layer RDL2 → feedthrough C → connector substrate (optional, not shown in FIG11 ) → first connector 21. The signal transmission path from chip D to second connector 22 is: chip D → first redistribution layer RDL1 → second redistribution layer RDL2 → connector substrate 30 (optional) → second connector 22. This allows data within the chip to be simultaneously transmitted to connectors (21, 22) on both sides of adapter board 10.

[0157] The setting structure of the adapter plate 10

[0158] Schematically, as shown in FIG. 12 , in some possible implementations, the transfer board 10 may include: a first redistribution layer RDL1 , a second redistribution layer RDL2 , and a molded interposer 100 .

[0159] The settings of the first redistribution layer RDL1 and the second redistribution layer RDL2 are basically the same as those in the second setting structure. For details, please refer to the corresponding description in the second setting structure, which will not be repeated here.

[0160] The molded interposer 100 includes at least one bridge die (BG) and multiple metal pillars P (e.g., copper pillars, Cu posts) encapsulated within the molded layer. The second redistribution layer (RDL2) is electrically connected to the first redistribution layer (RDL1) via the bridge die (BG) and the metal pillars P. Depending on actual needs, the bridge die (BG) may be provided with through-silicon vias (TSVs) to electrically connect to the second redistribution layer (RDL2).

[0161] It should be understood that the bridge chip BG has a similar structure to the aforementioned Si interposer. Since the bridge chip BG can be manufactured using a silicon-based process, the line width / line spacing / line thickness can meet the high-bandwidth density interconnection requirements between multiple chips D. Under this setting, referring to FIG12 , the signal transmission path between chip D and the first connector 21 is: chip D → first redistribution layer RDL1 → metal pillar P → connector C → connector substrate (optional, not shown in FIG12 ) → first connector 21. The signal transmission path between chip D and the second connector 22 is: chip D → first redistribution layer RDL1 → metal pillar P → second redistribution layer RDL2 → connector substrate 30 (optional) → second connector 22. In this way, the data in the chip can be simultaneously transmitted to the connectors (21, 22) on the front and back sides of the adapter board 10.

[0162] The setting structure of the adapter plate 10 is five

[0163] Schematically, as shown in FIG13 , this adapter board 10 is similar to the adapter board in configuration 4, differing only in that the edge of the second redistribution layer RDL2 extends beyond the edge of the first redistribution layer RDL1. In this case, feedthroughs C can be provided on the surface of the second redistribution layer RDL2 that is exposed around the first redistribution layer RDL1.

[0164] In this configuration, as shown in FIG13 , the signal transmission path between chip D and first connector 21 is: chip D → first redistribution layer RDL1 → molded interposer 100 → second redistribution layer RDL2 → feedthrough C → connector substrate (optional, not shown in FIG13 ) → first connector 21. The signal transmission path between chip D and second connector 22 is: chip D → first redistribution layer RDL1 → molded interposer 100 → second redistribution layer RDL2 → connector substrate 30 (optional) → second connector 22. This allows data within the chip to be simultaneously transmitted to connectors (21, 22) on both sides of the adapter board 10.

[0165] Setting structure 6 of adapter plate 10

[0166] Schematically, as shown in FIG. 14 , the adapter board 10 may include: a first redistribution layer RDL1 , a second redistribution layer RDL2 , and a glass interposer 200 .

[0167] The settings of the first redistribution layer RDL1 and the second redistribution layer RDL2 are basically the same as those in the second setting structure. For details, please refer to the corresponding description in the second setting structure, which will not be repeated here.

[0168] The glass interposer 12 includes multiple through-glass vias (TGVs) and at least one bridge die (BG). The bridge die (BG) is embedded in a trench on the glass wafer. The second redistribution layer (RDL2) is electrically connected to the first redistribution layer (RDL1) via the bridge die (BG) and the through-glass vias (TGVs).

[0169] It should be understood that the bridge chip BG has a similar structure to the aforementioned Si interposer. Since the bridge chip BG can be manufactured using a silicon-based process, the line width / line spacing / line thickness can meet the high-bandwidth density interconnection requirements between multiple chips D.

[0170] Of course, as another possible implementation method, as shown in FIG15 , the glass interposer 12 may be provided with no bridge chip BG but only with through glass vias TGV.

[0171] In this configuration, as shown in Figures 14 and 15 , the signal transmission path from chip D to first connector 21 is: chip D → first redistribution layer RDL1 → feedthrough C → connector substrate (optional, not shown in Figures 14 and 15 ) → first connector 21. The signal transmission path from chip D to second connector 22 is: chip D → first redistribution layer RDL1 → through-glass via TGV → second redistribution layer RDL2 → connector substrate 30 (optional) → second connector 22. This allows data within the chip to be simultaneously transmitted to connectors (21, 22) on both sides of the adapter board 10.

[0172] Setting structure of adapter plate 10

[0173] Schematically, as shown in Figures 16 and 17, the adapter board 10 is similar to the adapter board in setting structure four, with the only difference being that the edge of the second redistribution layer RDL2 exceeds the edge of the first redistribution layer RDL1. In this case, the communicating vessel C can be arranged on the surface of the second redistribution layer RDL2 exposed around the first redistribution layer RDL1.

[0174] In this configuration, as shown in Figures 16 and 17 , the signal transmission path from chip D to first connector 21 is: chip D → first redistribution layer RDL1 → through-glass via TGV → second redistribution layer RDL2 → feedthrough C → connector substrate (optional, not shown in Figures 16 and 17 ) → first connector 21. The signal transmission path from chip D to second connector 22 is: chip D → first redistribution layer RDL1 → through-glass via TGV → second redistribution layer RDL2 → connector substrate 30 (optional) → second connector 22. This allows data within the chip to be simultaneously transmitted to connectors (21, 22) on both sides of the adapter board 10.

[0175] In addition, for the chip packaging structures of different structures provided in the aforementioned embodiments, a suitable process can be selected for production according to needs, and this application does not impose any restrictions on this.

[0176] For illustration, the following describes a method for manufacturing the chip packaging structure in FIG9 , and the specific process steps are as follows:

[0177] 1. Chip Preparation: Chips D with different functions can include single chips such as CPU, GPU, memory, IO die, and IPD. Alternatively, pre-packaged integrated modules such as HBM, DOI, and FOI can be used. They are cut into individual chips. Microbumps are located on the front of the chip for interconnection, and the pad pitch can range from 20μm to 200μm.

[0178] 2. Wafer preparation:

[0179] First, referring to FIG18(a), a silicon wafer a1 is provided. Multiple through-silicon vias (TSVs) are fabricated in the silicon wafer a1. A Damascene process, including deposition, exposure, etching, electroplating, and CMP, is then used to fabricate a metal wiring layer a2 on the surface of the silicon wafer a1, thereby forming a silicon interposer. Micro pads are formed on the surface of the metal wiring layer a2. Depending on actual needs, active devices, such as deep trench capacitors (DTCs) and metal-insulator-metal (MIM) capacitors, can also be fabricated in the silicon interposer.

[0180] Next, referring to FIG. 18( b ), the silicon interposer is temporarily bonded to the first carrier 01 on the side of the metal wiring layer a2 .

[0181] The carriers involved in this application (such as the first carrier, the second carrier, the third carrier, the fourth carrier, etc.) can be metal plates, glass and other supports. This application does not impose any restrictions on this, and in practice, they can be set as needed.

[0182] The temporary bonding involved in this application can be performed by temporary bonding glue, but it is not limited to this. In practice, it can be set as needed.

[0183] Next, referring to (b) in FIG18 , the back side of the silicon wafer a1 is thinned to expose the through silicon vias (TSV). The specific process may include: grinding - chemical mechanical polishing (CMP) - Si etching to expose copper - insulating dielectric material deposition - CMP to expose copper, etc.

[0184] Next, referring to FIG. 18( c ), the side of the silicon interposer with the through silicon via (TSV) exposed is temporarily bonded to the second carrier 02 , and the first carrier 01 is debonded to expose the micro pads on the surface of the metal trace layer a2 .

[0185] The debonding and separation involved in this application can be laser debonding, thermal debonding, etc., but is not limited thereto and can be set as needed in practice.

[0186] 3. DOI (die on silicon interposer, silicon transfer board module) chip last process:

[0187] First, referring to FIG19 (a), multiple chips D (CPU, GPU, memory, IO die, IPD, HBM and other chips and chip modules) are mounted on the front of the silicon interposer. The chips D are connected to the micro pads on the surface of the metal wiring layer a2 through micro bumps.

[0188] Next, as shown in FIG19(a), a thermosetting material is used to fill the bottoms and gaps of the chips D, and then the molding compound is ground. The thermosetting material may include underfill, molding compound, or molding underfill.

[0189] Next, referring to FIG. 19( b ), the second carrier 02 and the Si interposer are debonded and a dicing tape is applied thereto. The dicing is then performed using a blade saw to form individual DOI units.

[0190] 4. FOP (fan out RDL interpose, RDL adapter board module) chip first process:

[0191] First, a communicating vessel C is provided. The main feature of the communicating vessel C is that an electrical connection structure is formed between the bottom and the top. For the specific configuration of the communicating vessel C, reference may be made to the relevant description above.

[0192] Then, referring to FIG. 20 ( a ), the DOI unit and a plurality of connecting vessels C formed by the aforementioned process are mounted on a third carrier 03 (eg, a metal carrier).

[0193] Next, referring to FIG20(b), a secondary molding process is performed using a thermosetting material to wrap the DOI unit and multiple connecting vessels C as a whole, and to fill the gaps between the chip and the connecting vessels C. The molding compound is then ground to thin the chip D and the connecting vessels C, exposing the connection structure (e.g., Cu stud) between the back of the chip D and the connecting vessels C.

[0194] Next, referring to FIG20( c ), the back surface of the chip D can be temporarily bonded to the fourth carrier 04, and the third carrier 03 can be debonded. Of course, in other possible implementations, the fourth carrier 04 may not be required, and the third carrier 03 can be directly debonded.

[0195] Next, referring to Figure 21 (a), a redistribution layer (RDL) is fabricated on the side of silicon wafer a1 where the TSV is exposed, to lead out the TSV signal. The number of routing layers in the RDL can be increased to 3 to 6. The fabrication process for a single routing layer may include: surface pretreatment, organic material coating - exposure - development - curing - seed layer deposition - organic material coating - exposure - development - electroplating - photoresist removal - seed layer etching, etc. After the last routing layer is completed, a metal pad is fabricated as an interface for subsequent external interconnection.

[0196] Next, referring to FIG21(b), a through hole K is machined on the adapter board system using a laser or other mechanical method. This allows a fixing structure 50 (such as a bolt) to pass through the through hole K to provide reliable mechanical support during subsequent system assembly. Of course, the location of the through hole K should reasonably avoid the chip layout.

[0197] Next, the ineffective areas of the adapter plate 10 and the plastic package structure are removed, and the effective areas are cut and separated.

[0198] 5. Mounting and mechanical fixation of connectors and electronic components:

[0199] First, referring to (a) in FIG22 , multiple substrates 30 are welded to the pads exposed on the surface of the redistribution layer RDL. Among them, the multiple substrates 30 can be processed by the substrate process of the substrate factory, or they can be obtained by the process of the PCB board factory, and the morphology, number of layers, and material of different substrates 30 may be different, which depends on the electrical characteristics of the device to be connected to the substrate 30. Of course, according to actual needs, after welding the multiple substrates 30 to the pads on the surface of the redistribution layer RDL, in some possible implementation methods, a thermosetting material can be used to fill the bottom of the multiple substrates 30 and the gaps between the substrates 30, and the multiple substrates 30 are plastic-encapsulated in the plastic layer M2 for protection. Of course, the plastic layer M2 is also opened at the position of the through hole K.

[0200] Next, referring to FIG22 (a), multiple electronic components 20 (such as power modules, clocks, passive components and other functional modules) are welded to the back of multiple substrates 30. For example, by welding multiple power modules, the vertical power supply of the front chip can be interconnected.

[0201] Next, referring to FIG22 (a), the front and back of the connector are assembled. Part of the connector (22) is assembled to the back of the discrete substrate 30 in the reserved position on the back of the adapter board by welding or crimping; the other part of the connector (21) is assembled to the port of the connector C on the front of the adapter board by welding or crimping.

[0202] Next, referring to (a) in FIG22 , a support frame 43 that matches the size of the adapter board system (i.e., a system containing multiple chips D, an adapter board 10, multiple connectors 21 and 22, multiple electronic components 20, and multiple substrates 30) can be used to support the adapter board system.

[0203] Next, referring to FIG22 (a), with the support of the support frame 43, a first heat sink 41 is mounted on the side of the hybrid adapter plate system located on the chip D, and a second heat sink 42 is mounted on the side of the electronic component 20. The heat sinks (41, 42) and the support frame 43 are also opened at the position where the through hole K is set in the adapter plate system. Bolts (50) are passed through the adapter plate system, the support frame 43, the first heat sink 41, and the second heat sink 42 at the through hole position and fixed. In this case, the heat sinks (41, 42) not only play the role of heat dissipation, but also play the role of stabilizing the structure. Of course, as needed, a thermal interface material can be filled between the back of the chip and the heat sink, and the thickness can be in the range of 50μm to 150μm.

[0204] Next, bolts, clamps and other components are used to fasten the front heat sink, plastic packaging structure and back heat sink to finally obtain a system-level packaging structure.

[0205] Example 2

[0206] The second embodiment provides another chip packaging structure, which differs from the chip packaging structure of the first embodiment mainly in the different arrangement of the connecting vessel C. The following mainly describes the differences between the second embodiment and the first embodiment.

[0207] As shown in Figure 23 , in this second embodiment, feed-through C is located on the side of the adapter board 10, with the top of feed-through C flush with the top of the chip D. A first connector 21 is positioned above and connected to the top of feed-through C. The bottom of feed-through C extends downward to the back surface of the adapter board 10 (i.e., the surface away from the chip D) and is electrically connected to the back surface of the adapter board 10 (i.e., the side where the electronic component 20 is located) through the substrate 30. In this way, the first connector 21 is electrically connected to the adapter board 10 through the feed-through C.

[0208] In this case, the multiple feedthroughs C and the multiple chips D can be separately encapsulated using two encapsulation processes, and the tops of the multiple feedthroughs C can be flush with the tops of the multiple chips D, with the plastic encapsulation layer exposed. As an intermediate connection structure, the feedthroughs C can lead signals to the first connector 21 above, ensuring that the first connector 21 can transmit the signals of the chip D (such as an IO die) to the outside through the feedthroughs C and the adapter board 10, thereby solving various problems caused by the inability to mount the connector and the chip on the same side of the adapter board in the prior art.

[0209] In the second embodiment, the plurality of chips D and the transfer board 10 are integrated together by a primary molding process, and then the chips D and the transfer board 10 are integrated together by a secondary molding process.

[0210] Furthermore, in this second embodiment, to implement connectors on both the front and back surfaces of the adapter board 10, as shown in FIG23 , in some possible implementations, the chip packaging structure may further include one or more second connectors 22. The second connectors 22 are located below the adapter board 10 and are directly connected to the lower surface of the adapter board 10 or connected through the substrate 30. In this case, after the substrate 30 extracts the signal from the adapter board 10, a portion of the signal is output to the second connector 22, and a portion is output to the first connector 21 through the connector C.

[0211] By arranging a first connector on the front side of the adapter board 10 and a second connector 22 on the back side, the number of connectors (21, 22) can be multiplied, thereby multiplying the system's ability to transmit external data. Furthermore, arranging multiple connectors (21, 22) on both the front and back sides of the adapter board 10 avoids the problem of increased costs due to an increase in the area of ​​the adapter board 10, and the problem of signal attenuation due to an increased distance between the chip D and the connectors (21, 22).

[0212] In this second embodiment, the signal transmission path between chip D and the first connector 21 is: chip D → adapter board 10 → connector substrate 30 → feedthrough C → connector substrate 30 (optional, not shown in FIG23 ) → first connector 21. The signal transmission path between chip D and the second connector 22 is: chip D → adapter board 10 → connector substrate 30 (optional) → second connector 22. This allows data within the chip to be simultaneously transmitted to the connectors (21, 22) on both sides of the adapter board 10.

[0213] Compared with the first embodiment in which the communicating vessel C is arranged on the surface of the adapter plate 10, the second embodiment of the present application arranges the communicating vessel C on the side of the adapter plate 10, which can save the area cost of the adapter plate 10 and thus reduce the manufacturing cost.

[0214] In the second embodiment, there is no limitation on the internal structure of the adapter plate 10 , and it can be configured as needed in practice.

[0215] For illustration, the internal structure of the adapter plate 10 in the second embodiment may be similar to that in the first embodiment.

[0216] For example, referring to Figure 24, in some possible implementation methods, the internal structure of the adapter board 10 can be similar to the "setting structure one of the adapter board 10" in Example 1. The adapter board 10 can include a silicon interposer 1 (Si interposer) and a redistribution layer RDL. In this Example 2, the area of ​​the redistribution layer RDL can be reduced, and the edge of the redistribution layer RDL can be flush or nearly flush with the edge of the silicon interposer 1, and the connecting vessel C is set on the side of the silicon interposer 1 (Si interposer) and the redistribution layer RDL.

[0217] Schematically, as shown in FIG24 , in the actual manufacturing process, multiple differentiated chips D and the adapter board 10 (including Si interposer and RDL) can be integrated together through a molding process according to product requirements; and then cut to form a unit. Next, the unit and the connecting device C located on its side are secondary molded through a molding process, and the surface is thinned and flattened to expose the terminals of the connecting device C (such as pads, Cu columns, etc.), and the first connector 21 is connected to the exposed terminals. In this case, in the final package structure, the connecting device C is arranged on the side of the silicon interposer 1 (Si interposer) and the redistribution layer RDL, and the edges of the silicon interposer 1 (Si interposer) and the redistribution layer RDL are flush, and the area is smaller than the area of ​​the package outline.

[0218] For other related settings of the silicon interposer 1 and the redistribution layer RDL, reference may be made to “Setting Structure 1 of the Adapter Board 10 ” and related descriptions in the first embodiment, which will not be repeated here.

[0219] For another example, referring to Figure 25, in some possible implementation methods, the internal structure of the adapter board 10 may be similar to the "setting structure two of the adapter board 10" in Example 1. The adapter board 10 may include a first rewiring layer RDL1 and a second rewiring layer RDL2. The edges of the first rewiring layer RDL1 and the second rewiring layer RDL2 are flush or nearly flush, and the connecting vessel C is arranged on the sides of the first rewiring layer RDL1 and the second rewiring layer RDL2.

[0220] In this configuration, multiple chips D and the adapter board 10 (including RDL1 and RDL2) are integrated together through a molding process; they are then cut to form a unit. Next, the unit and the via C located on its side are molded for a second time, and the surface is thinned and flattened to expose the terminals of the via C (such as pads, Cu columns, etc.), and the first connector 21 is connected to the exposed terminals. In this case, in the final package structure, the via C is arranged on the sides of the first redistribution layer RDL1 and the second redistribution layer RDL2, and the edges of the first redistribution layer RDL1 and the second redistribution layer RDL2 are flush, and the area is smaller than the area of ​​the package outline.

[0221] For other related settings of the first redistribution layer RDL1 and the second redistribution layer RDL2, reference may be made to "Setting Structure 2 of the Adapter Board 10" and related descriptions in the first embodiment, which will not be repeated here.

[0222] For another example, referring to FIG26 , in some possible implementations, the internal structure of the adapter board 10 may be similar to the “arrangement structure four of the adapter board 10” in the first embodiment. The adapter board 10 may include a first redistribution layer RDL1, a second redistribution layer RDL2, and a molded interposer 100 disposed between the first redistribution layer RDL1 and the second redistribution layer RDL2. The molded interposer 100 includes at least one bridge chip BG and a plurality of metal pillars P encapsulated in the molded layer. In this case, the edges of the first redistribution layer RDL1, the molded interposer 100, and the second redistribution layer RDL2 are flush or nearly flush, and the connecting vessel C is disposed on the side of the adapter board 10 formed by the first redistribution layer RDL1, the molded interposer 100, and the second redistribution layer RDL2.

[0223] In this setting mode, multiple chips D and the adapter board 10 (including RDL1, 100, and RDL2) are integrated together through a molding process; then they are cut to form a unit. Next, the unit and the connecting device C located on its side are molded for a second time through a molding process, and the surface is thinned and flattened to expose the terminals of the connecting device C (such as pads, Cu columns, etc.), and the first connector 21 is connected to the exposed terminals. In this case, in the final package structure, the connecting device C is arranged on the side of the first redistribution layer RDL1, the molded interposer 100, and the second redistribution layer RDL2. The edges of the first redistribution layer RDL1, the molded interposer 100, and the second redistribution layer RDL2 are flush, and the area is smaller than the area of ​​the package outline.

[0224] Regarding the related settings of the first redistribution layer RDL1, the molded interposer 100, the second redistribution layer RDL2, the bridge chip BG, the metal pillar P, etc., please refer to the "Setting Structure Four of the Adapter Board 10" and related instructions in Example 1, and no further details will be given here.

[0225] For another example, referring to Figures 27 and 28, in some possible implementations, the internal structure of the adapter board 10 can be similar to the "Configuration Structure 6 of the Adapter Board 10" in Example 1. The adapter board 10 can include a first redistribution layer RDL1, a second redistribution layer RDL2, and a glass interposer 200 disposed between the first redistribution layer RDL1 and the second redistribution layer RDL2. The glass interposer 12 can be provided with a plurality of through-glass vias (TGVs) and at least one bridge chip (BG) (Figure 27). Alternatively, only a plurality of through-glass vias (TGVs) can be provided (Figure 28). In this case, the edges of the first redistribution layer RDL1, the glass interposer 200, and the second redistribution layer RDL2 are flush or nearly flush, and the connecting device C is provided on the side of the adapter board 10 formed by the first redistribution layer RDL1, the glass interposer 200, and the second redistribution layer RDL2.

[0226] In this configuration, multiple chips D and the adapter board 10 (including RDL1, 200, and RDL2) are integrated together through a molding process; they are then cut to form a unit. Next, the unit and the connecting device C located on its side are molded for a second time, and the surface is thinned and flattened to expose the terminals of the connecting device C (such as pads, Cu columns, etc.), and the first connector 21 is connected to the exposed terminals. In this case, in the final package structure, the connecting device C is arranged on the side of the first redistribution layer RDL1, the glass interposer 200, and the second redistribution layer RDL2. The edges of the first redistribution layer RDL1, the glass interposer 200, and the second redistribution layer RDL2 are flush, and the area is smaller than the area of ​​the package outline.

[0227] Regarding the related settings of the first redistribution layer RDL1, the glass interposer 200, the second redistribution layer RDL2, the bridge chip BG, the through glass via TGV, etc., please refer to the "Setting Structure Six of the Adapter Board 10" and related instructions in Example 1, and no further details will be given here.

[0228] In addition, regarding the settings of other parts in the chip packaging structure provided in this embodiment 2, such as the chip D, the electronic component 20, the substrate 30, the first connector 21, the second connector 22, the first heat sink 41, the second heat sink 42, the fixing structure 50, etc., you can refer to the aforementioned embodiment 1 accordingly and will not repeat them here.

[0229] It should be noted that, with reference to Figures 23 to 28, in this second embodiment, the substrate 30 located below the feed-through C needs to extend from the bottom of the feed-through C to the surface of the adapter plate 10 to be electrically connected to the adapter plate 10. In this case, when setting a fixing structure at the edge of the packaging system to open a hole, the substrate 30 below the feed-through C can be avoided. As long as the packaging system is fixed, this application does not impose any restrictions on this. The manufacturing method of the chip packaging structure provided in this second embodiment can refer to the aforementioned embodiment 1 and related technologies, and can select an appropriate process for manufacturing. This application does not impose any restrictions on this.

[0230] It should be understood that the sequence of the production processes involved in the embodiments of the present application should be determined by their functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0231] For other relevant contents in the manufacturing method in each embodiment, you can refer to the corresponding parts in the chip packaging structure, which will not be repeated here; for other setting structures in the aforementioned chip packaging structure embodiment, you can refer to the above-mentioned manufacturing method and related manufacturing methods for adjustment, which will not be repeated here one by one.

[0232] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that: include: Adapter plate; At least one first chip is disposed on the adapter board and electrically connected to the adapter board; A connecting vessel, which is plastic-encapsulated with the first chip in a plastic-encapsulation layer, and the bottom of the connecting vessel is electrically connected to the adapter board; A first connector is located at a side of the plastic packaging layer away from the adapter board and is electrically connected to the adapter board through the connecting vessel; At least one electronic component is located on a side of the adapter board away from the first chip and is connected to the adapter board or connected to the adapter board through a substrate.

2. The chip packaging structure according to claim 1, characterized in that: The top of the connecting vessel is flush with the surface of the first chip at a side away from the adapter board.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The communicating vessel comprises: A support plate, wherein an intermediate metal connection structure is provided in the support plate; A first metal connection structure, disposed on top of the support plate and connected to the intermediate metal connection structure; A second metal connection structure, disposed at the bottom of the support plate and connected to the intermediate metal connection structure; The communicating vessel is connected to the first connector via the first metal connecting structure, and is connected to the adapter plate via the second metal connecting structure.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure also includes a second connector; The second connector is located on a side of the adapter board away from the first connector, and is connected to the adapter board or connected to the adapter board through a substrate.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The connector and the first chip are located on the same side of the adapter board. The connector is arranged on the adapter board and is electrically connected to the adapter board.

6. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The communicating vessel is located on a side of the adapter plate, and the bottom of the communicating vessel is connected to a side of the adapter plate where the electronic components are arranged through a substrate.

7. The chip packaging structure according to claim 5, characterized in that: The adapter board includes: a silicon interposer and a redistribution layer; The front side of the silicon interposer has a metal wiring layer, and a through silicon via TSV is arranged in the silicon interposer; the redistribution layer is arranged on the back side of the silicon interposer and is electrically connected to the through silicon via; The first chip is arranged on the front side of the silicon interposer; The edge of the redistribution layer exceeds the edge of the silicon interposer, and the connecting vessel is arranged on the surface of the redistribution layer around the silicon interposer and is electrically connected to the redistribution layer.

8. The chip packaging structure according to claim 5, characterized in that: The adapter board comprises: a first redistribution layer and a second redistribution layer which are stacked; The first chip is disposed on the first redistribution surface and is electrically connected to the first redistribution; The connecting vessel is arranged on the surface of the first redistribution layer; or, the edge of the second redistribution layer exceeds the edge of the first redistribution layer, and the connecting vessel is arranged on the surface of the second redistribution layer around the first redistribution layer.

9. The chip packaging structure according to claim 6, characterized in that: The adapter board includes: a silicon interposer and a redistribution layer; The front side of the silicon interposer has a metal wiring layer, and a through silicon via TSV is arranged in the silicon interposer; the redistribution layer is arranged on the back side of the silicon interposer and is electrically connected to the through silicon via; The first chip is arranged on the front side of the silicon interposer; The bottom of the connecting vessel is connected to the redistribution layer through the substrate.

10. The chip packaging structure according to claim 6, characterized in that: The adapter board comprises: a first redistribution layer and a second redistribution layer which are stacked; The first chip is disposed on the first redistribution surface and is electrically connected to the first redistribution; The bottom of the connecting vessel is connected to the redistribution layer through the substrate.

11. The chip packaging structure according to claim 8 or 10, characterized in that: The line width, line spacing and line thickness of the metal routing in the first redistribution layer are all less than 5 μm; the line width, line spacing and line thickness of the metal routing in the second redistribution layer are all greater than 5 μm.

12. The chip packaging structure according to claim 8, 10 or 11, characterized in that: The adapter plate further includes: a glass wafer; The glass wafer is arranged between the first redistribution layer and the second redistribution layer, and a through glass via TGV is arranged in the glass wafer; The second redistribution layer is electrically connected to the first redistribution layer through the through glass via TGV.

13. The chip packaging structure according to claim 12, characterized in that: The adapter board also includes: a bridge chip; A groove is provided in the glass wafer, the bridge chip is embedded in the groove, and the active surface of the bridge chip is electrically connected to the first chip through the first redistribution layer.

14. The chip packaging structure according to claim 8, 10 or 11, characterized in that: The adapter board also includes: a bridge chip and a metal column; The bridge chip and the metal pillar are connected between the first redistribution layer and the second redistribution layer, and are plastic-encapsulated in the plastic encapsulation layer; The second redistribution layer is electrically connected to the first redistribution layer through the metal pillar, and the active surface of the bridge chip is electrically connected to the first chip through the first redistribution layer.

15. The chip packaging structure according to any one of claims 1 to 14, characterized in that: The at least one first chip includes: one or more of a central processing unit, a graphics processing unit, a memory, an input / output chip, an integrated passive device, and a packaged functional module.

16. The chip packaging structure according to any one of claims 1 to 15, characterized in that: The at least one electronic component includes: one or more of a power supply module, a control module, a connector, a clock device, a rectifier, and a resistor, capacitor, and inductor.

17. The chip packaging structure according to any one of claims 1 to 16, characterized in that: The chip packaging structure includes: a plurality of the first chips and a plurality of the electronic components.

18. The chip packaging structure according to claim 17, characterized in that: The plurality of electronic components include a plurality of power supply modules, and the plurality of power supply modules are respectively arranged opposite to the plurality of first chips; The power supply module is electrically connected to the first chip arranged opposite to it through the adapter board, and supplies power to the first chip.

19. The chip packaging structure according to any one of claims 1 to 18, characterized in that: The chip packaging structure comprises: a plurality of substrates; the substrates are located on a side of the adapter plate away from the first chip, A plurality of devices located on a side of the adapter board away from the first chip are connected to the adapter board through a plurality of the substrates; wherein the plurality of devices include one or more of the electronic components, the connecting device, and the second connector.

20. The chip packaging structure according to any one of claims 1 to 19, characterized in that: The chip packaging structure further includes: a first heat dissipation plate and a second heat dissipation plate; The first heat sink is disposed on a side of the first chip away from the adapter board, and the second heat sink is disposed on a side of the electronic component away from the adapter board.

21. The chip packaging structure according to any one of claims 1 to 20, characterized in that: The chip packaging structure further includes a first electronic device, which is located on a side of the plastic packaging layer away from the adapter board and is electrically connected to the adapter board through the connecting vessel.

22. An electronic device, characterized in that: It comprises a circuit board and a chip packaging structure as claimed in any one of claims 1 to 21, wherein the chip packaging structure is electrically connected to the circuit board.

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