Integrated circuit package and method of forming same

Abstract

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and an integrated circuit die on the interposer, the integrated circuit die including a plurality of transistors. The carrier die is coupled to a top surface of the integrated circuit die. The integrated circuit die includes a plurality of top metal structures at a top surface of the integrated circuit die. The carrier die includes a plurality of dummy contact pads. The carrier die is bonded to the integrated circuit die by a bonding layer such that each dummy contact pad is directly over one or more of the top metal structures with the bonding layer between the dummy contact pads and the top metal structures. Embodiments of the present disclosure also relate to a method of forming an integrated circuit package.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to integrated circuit packages and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have produced multiple generations of integrated circuits, with each generation having smaller and more complex circuits than the previous one. During the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per die area) generally increases, while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. This scaling process generally provides benefits by increasing production efficiency and reducing related costs. This scaling also increases the complexity of processing and manufacturing integrated circuits.

[0003] As integrated circuit components are scaled down, various efforts have also been made to address issues associated with the packaging of integrated circuits. In some cases, an integrated circuit package includes a substrate, one or more integrated circuit dies, and an interposer located between the substrate and the integrated circuit die. However, there are many difficulties associated with such packaging, which may lead to wafer scrap or other drawbacks. Summary of the Invention

[0004] Embodiments of the present disclosure provide an integrated circuit package, comprising:

[0005] a substrate;

[0006] a first integrated circuit die located on the substrate, and the first integrated circuit die includes: a plurality of transistors; a plurality of first top metal structures located above the transistors; and a plurality of first bottom metal structures located below the transistors;

[0007] a carrier die bonded to the top surface of the first integrated circuit die, and the carrier die includes a plurality of pseudo contact pads, each of the pseudo contact pads being directly located above one or more of the first top metal structures; and

[0008] a bonding layer located between the carrier die and the first integrated circuit die, and the bonding layer is in direct contact with the first top metal structures and the pseudo contact pads.

[0009] Another embodiment of the present disclosure provides a method of forming an integrated circuit package, including: coupling a first integrated circuit die to a top surface of an interposer, the first integrated circuit die including a plurality of transistors and a plurality of first top metal structures located above the transistors at the top surface of the first integrated circuit die; coupling a carrier die to the top surface of the first integrated circuit die using a bonding layer such that each of a plurality of pseudo contact pads of the carrier die is directly located above one or more of the first top metal structures, wherein the bonding layer is in direct contact with the first top metal structures and the pseudo contact pads; and coupling the interposer to a top surface of a substrate.

[0010] Yet another embodiment of the present disclosure provides a method of forming an integrated circuit package, including: forming a plurality of trenches in a first side of a carrier die; forming a plurality of pseudo contact pads in the trenches by depositing metal in the trenches and performing a chemical mechanical planarization process; exposing the pseudo contact pads at a second side of the carrier die opposite the first side by thinning the carrier die from the second side; and coupling the carrier die to a top surface of an integrated circuit die including a plurality of transistors using a bonding layer.

[0011] Embodiments of the present application relate to 3D integrated circuit packages with efficient heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be increased or decreased arbitrarily for the sake of clarity of discussion.

[0013] Figure 1A is an illustration of an integrated circuit package according to some embodiments.

[0014] Figure 1B is according to some embodiments Figure 1A top view of a carrier die of an integrated circuit package.

[0015] Figures 2A to 2M is a view of an integrated circuit package at various processing stages according to some embodiments.

[0016] Figure 3 is an illustration of an integrated circuit package according to some embodiments.

[0017] Figure 4 is an illustration of an integrated circuit package according to some embodiments.

[0018] Figure 5 is a flowchart of a method according to some embodiments.

[0019] Figure 6 is a flowchart of a method according to some embodiments. Detailed implementation

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device in use or operation. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0022] Terms indicating relative degree (such as "about", "substantially", etc.) should be interpreted as terms that would be understood by a person of ordinary skill in the art in accordance with the current technical specifications.

[0023] Embodiments of the present disclosure provide an integrated circuit package with improved heat dissipation. The integrated circuit package includes an integrated circuit die located on top of an interposer. The interposer is in turn located on a substrate. One or more memory dies are also located on the interposer or the substrate. The integrated circuit die includes a plurality of transistors that, in operation, can generate a large amount of heat. The integrated circuit die includes a front-side metal interconnect structure that includes conductive vias and metal lines located above the transistors. The integrated circuit die includes a back-side metal interconnect structure that includes conductive vias and metal lines located below the transistors. The front side of the back-side metal interconnect structure is electrically connected through one or more through-holes. The front-side interconnect structure includes a top metal layer patterned into a plurality of contact pads. To facilitate heat dissipation, the package includes a carrier die and is coupled to the top surface of the front side of the integrated circuit. The carrier die includes a plurality of pseudo-contact pads located directly above the contact pads on the front side of the integrated circuit die. The carrier die is thinned such that the thickness of the carrier die corresponds to the thickness of the pseudo-contact pads. A non-conductive bonding layer is located between the integrated circuit die and the carrier die.

[0024] The presence of the carrier die and the pseudo-contact pads greatly improves heat dissipation. Heat from the transistors of the integrated circuit die flows upward through the front-side metal interconnects to the contact pads. The heat flows to the pseudo-contact pads of the carrier die and is effectively dissipated from the pseudo-contact pads. Heat is also dissipated to a lesser extent through the back-side metal interconnects. However, the presence of the front-side interconnects and the pseudo-contact pads of the carrier die results in efficient upward heat dissipation of the transistors. This reduces the likelihood of component damage in the package. This also provides higher performance for the transistors and other components of the package. This also results in a higher package yield and fewer discarded packages.

[0025] Figure 1A FIG. is a diagram of an integrated circuit package 100 according to some embodiments. The components of the integrated circuit package 100 include an integrated circuit die 102, an interposer 104, a substrate 106, a second integrated circuit die 108, and a carrier die 110. As will be elaborated in more detail below, the components of the integrated circuit package 100 and the arrangement of the components facilitate efficient heat dissipation within the integrated circuit package 100.

[0026] The integrated circuit die 102 includes an active device region 114, a front side 116 located above the active device region 114, and a back side 118 located below the active device region 114. The integrated circuit die 102 can correspond to a processor, a microcontroller, a logic circuit, or other types of circuits. The integrated circuit die 102 can correspond to a system-on-chip (SoC) or other types of integrated circuit dies.

[0027] The active device region 114 includes a plurality of transistors 120. The transistors 120 may be formed in combination with a semiconductor substrate or one or more semiconductor layers of the active device region 114. The transistors 120 may include all-around gate transistors, each having a plurality of stacked channels, where a gate metal wraps around each stacked channel. The transistors 120 may include FinFET transistors. The transistors 120 may include other types of transistors. The transistors 120 may include source / drain regions, gate electrodes, source / drain contacts, and other components. The transistors 120 may be arranged in a complex circuit architecture to produce processing circuitry, logic circuitry, or other types of circuitry capable of performing complex operations.

[0028] The active device region 114 includes a plurality of top conductive vias 124. The top conductive vias 124 contact the top-side structures of the transistors 120. The top conductive vias 124 may include source / drain contacts, gate contacts, or other types of metal structures. The top conductive vias 124 electrically connect the transistors 120 to the metal interconnect structures on the front side 116.

[0029] The active device region 114 includes a plurality of bottom conductive vias 126. The bottom conductive vias 126 contact the bottom structures of the transistors 120, or contact the structures of the transistors 120 by extending upward to the upper structures of the transistors 120. The bottom conductive vias 126 may include source / drain contacts, gate contacts, or other types of metal structures. The bottom conductive vias 126 electrically connect the transistors 120 to the metal interconnect structures on the back side 118.

[0030] In some embodiments, the top conductive vias 124 are laterally wider or vertically thicker than the bottom conductive vias 126. This may help the top conductive vias 124 preferentially conduct heat from the transistors 120 upward to the front side 116. In some embodiments, the top conductive vias 124 include tungsten or another highly conductive material. In some embodiments, the bottom conductive vias 126 include molybdenum or ruthenium. Thus, in some embodiments, the top conductive vias 124 include a different material than the bottom conductive vias 126. Optionally, the top conductive vias 124 and the bottom conductive vias 126 may include the same material and may include materials other than those described above.

[0031] In operation, the transistors 120 may generate a large amount of heat. Heat is generated when the transistors 120 operate at a high switching speed, during which the transistors turn on and off. A relatively small current may flow through each individual transistor 120. The presence of a large number of transistors 120 operating at a high switching speed (millions or billions of transistors in some embodiments) can result in the generation of a relatively large amount of heat. In practice, the hottest part of the integrated circuit package 100 may be the active device region 114.

[0032] Heat from the transistor 120 can flow or dissipate upward and downward (and laterally). In practice, a large amount of heat can flow upward into the front side 116. A relatively small amount of heat can flow downward into the back side 118. As will be described in more detail below, heat can flow from the front side to the back side through vias (extending through the active device region 114 between the front side 116 and the back side 118). However, as will be elaborated in more detail below, a more efficient path for the heat to travel is to dissipate upward through the front side 116.

[0033] The front side 116 includes a plurality of stacked dielectric layers 117. Metal interconnect structures are formed in the stack of dielectric layers 117. The metal interconnect structures include a plurality of metal lines 128 and conductive vias 129. More specifically, each dielectric layer 117 may include a layer of metal lines 129 formed therein and a plurality of conductive vias 129 landing on a later metal line 128. The lowermost layer of the metal lines 128 is in direct contact with the top conductive via 124 of the transistor 120 connected to the active device region 114. The lowermost layer of the metal lines 128 may be referred to as metal 0 or M0. The next layer of metal lines 128 is formed in the next interlayer dielectric layer 117 and may correspond to metal 1 or M1, where the corresponding conductive vias 129 land on the next layer of metal lines 128. Figure 1A Six layers of metal lines 128 (e.g., M0 - M5) are shown, each formed in a dielectric layer 117. In practice, each dielectric layer 117 may include a plurality of dielectric sub - layers.

[0034] In some embodiments, the metal lines 128 include one or more of tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. The conductive vias 129 include one or more of aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. Each dielectric layer 117 may include one or more layers of one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials.

[0035] The front side 116 includes a top metal layer that includes a top metal structure 130. In practice, the top metal structure 130 may be formed of a material different from that of the metal lines 128. In one example, the top metal structure 130 includes copper. Optionally, the top metal structure 130 may include the same metal or material as the metal lines 128. The top metal structure 130 may be much thicker than the metal lines 128. The bottom surface of each metal structure 130 may be in contact with the conductive vias 129 of the next lower layer.

[0036] In some embodiments, the top dielectric layer 117 corresponds to the passivation layer of the integrated circuit die 102. The passivation layer may include SiN, SiON, SiOCN, SiOC, SiCN, or other suitable dielectric layers. Although Figure 1A the passivation layer is shown as a single passivation layer, in practice, the passivation layer may include multiple layers.

[0037] In some embodiments, the top metal structure 130 corresponds to the non-active contact pads of the integrated circuit die 102. However, the contact pads are non-active because they do not physically contact electronic components external to the integrated circuit die 102 from above. In this sense, the top metal structure 130 may correspond to pseudo-contact pads. As will be described in more detail below, the integrated circuit package 100 utilizes the top metal structure 130 to bond with the carrier die 110 to effectively dissipate heat from the transistors 120.

[0038] The package 100 includes a carrier die 110 located on top of the front side 116 of the integrated circuit die 102. The carrier die 110 is bonded to the front side 116 of the integrated circuit die 102 via a bonding layer 112. The bonding layer 112 makes direct physical contact with the top surface of the top metal structure 130 of the front side 116. The bonding layer 112 includes a non-conductive material so as not to electrically short all of the top metal structures 130. In some embodiments, the bonding layer 112 includes silicon oxide. However, other bonding layers 112 may include other dielectric materials without departing from the scope of the present disclosure.

[0039] In some embodiments, the carrier die 110 is a semiconductor die. The carrier die 110 may include silicon, silicon germanium, or other suitable semiconductor materials. Optionally, the carrier die 110 may include dielectric materials or other types of materials.

[0040] The carrier die 110 includes a plurality of metal structures 131 embedded therein. In some embodiments, the metal structures 131 are pseudo-contact pads having the shade, materials, and thickness utilized in contact pads. The metal structures 131 may be referred to as pseudo-contact pads because in some embodiments, the metal structures 131 are not electrically connected to external structures. For example, working contact pads are typically connected to solder bumps, solder balls, reflow layers, bond wires, or other conductive structures that electrically connect the contact pads to external devices. However, in some embodiments, the pseudo-contact pads do not contact any such structures. Instead, as will be elaborated in more detail below, the function of the pseudo-contact pads is to enhance heat dissipation from the front side 116.

[0041] In some embodiments, each metal structure 131 of the carrier die 110 is directly located above a corresponding top metal structure 130 of the front side 116 of the integrated circuit die 102. When heat flows upward through the metal interconnect structure 116, the heat can ultimately flow from the top metal structure 130 through the thin bonding layer 112 to the metal structure 131 of the carrier die 110. Since each metal structure 131 is directly located above the metal structure 130, heat can effectively flow from the top metal structure 130 to the metal structure 131 of the carrier die 110.

[0042] In some embodiments, the total vertical thickness of the carrier die 110 is substantially the same as the vertical thickness of the metal structures 131. As will be described in more detail below, after the metal structures 131 and the carrier die 110 are formed, the thickness of the carrier die 100 is reduced to be substantially equal to the thickness of the metal structures 131. Thus, the top surface of the metal structures 131 is substantially coplanar with the top surface of the carrier die 110. The bottom surface of the metal structures 131 is substantially coplanar with the bottom surface of the carrier die 110.

[0043] In some embodiments, the pattern of the metal structures 131 is substantially the same as the pattern of the top metal structures 130 of the front side 116. In other words, each metal structure 131 is directly located above a corresponding top metal structure 130 and has substantially the same lateral dimensions as the corresponding top metal structure 130. Thus, a second mask can be utilized to pattern the top of the structures 130 and the metal structures 131.

[0044] In some embodiments, the metal structures 131 have a different pattern than the top structures 130. For example, the metal structures 131 can have a larger surface area, a smaller surface area, different shapes, and different patterns and configurations than the top metal structures 130. Various configurations of the metal structures 131 and the top metal structures 130 can be utilized without departing from the scope of the present disclosure.

[0045] The back side 118 includes a plurality of stacked dielectric layers 119. Metal interconnect structures are formed in the stack of dielectric layers 119. The metal interconnect structures include a plurality of metal lines 132 and conductive vias 133. More specifically, each dielectric layer 119 can include a layer of metal lines 132 formed therein and a plurality of conductive vias 133 landing on the metal lines 128 of that layer. The topmost layer of the metal lines 132 is in direct contact with the bottom conductive via 126 of the transistor 120 connected to the active device region 114. The topmost layer of the metal lines 132 can be referred to as metal 0 or M0 of the back side. The next layer of metal lines 132 is formed in the next interlayer dielectric layer 119 and can correspond to metal 1 or M1 of the back side, where the corresponding conductive vias 133 land on the next layer of metal lines 132. Figure 1AShows three layers of metal lines 132 (e.g., backside M0 - M2), each formed in a dielectric layer 119. In practice, each dielectric layer 119 may include multiple dielectric sub - layers.

[0046] In some embodiments, the metal lines 132 include one or more of tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. The conductive vias 133 include one or more of aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. Each dielectric layer 119 may include one or more layers of one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials.

[0047] The backside 118 includes a bottom metal layer that includes a bottom metal structure 134. In practice, the bottom metal structure 134 may be formed of a material different from that of the metal lines 132. In one example, the bottom metal structure 134 includes copper. Optionally, the bottom metal structure 134 may include the same metal or material as the metal lines 132. The bottom metal structure 134 may be much thicker than the metal lines 132. The bottom surface of each metal structure 134 may contact a conductive via 133 of a higher layer.

[0048] In some embodiments, the bottom dielectric layer 119 corresponds to the passivation layer of the integrated circuit die 102. The passivation layer may include SiN, SiON, SiOCN, SiOC, SiCN, or other suitable dielectric layers. Although Figure 1A the passivation layer is shown as a single passivation layer, in practice, the passivation layer may include multiple layers.

[0049] In some embodiments, the bottom metal structure 134 corresponds to the bottom contact pad of the integrated circuit die 102. As will be described in more detail below, the bottom metal structure 134 is connected to a corresponding conductive structure of the interposer 104 by a hybrid bond 141.

[0050] In some embodiments, since the top conductive structure 130 of the front side 116 is not electrically connected to an external device, a higher density of bottom metal structures 134 is required to electrically connect to the interposer 104. This is because both the front - side interconnects and the back - side interconnects will be electrically connected to the interposer 104. Thus, in some embodiments, each bottom metal structure 134 is electrically connected to a corresponding top metal structure 138 of the interposer 104 using a hybrid bond 141. The hybrid bond enables a much higher connection density between the backside 118 and the interposer 104 than solder bumps or other types of connectors.

[0051] Hybrid bond 141 is formed by performing a hybrid bonding process. In some embodiments, the hybrid bonding process includes slightly recessing surface metal structures relative to the surrounding dielectric material (such as silicon oxide or another suitable dielectric material). This is performed on two dies on which the hybrid bonding process will be executed. Then the two dies are pressed together face to face such that the recessed surface metal structures are aligned with each other. Then a thermal annealing process is performed in which the two dies are slowly heated. This causes the metal material of the opposing surface metal structures to expand in the gap. As a result, the opposing surface metal structures are in physical contact with each other, thereby forming a physical connection and an electrical connection. Thus, in some embodiments, hybrid bond 141 corresponds to the direct physical contact of opposing surface metal structures. In some embodiments, each of the opposing surface metal structures is made of copper, but other materials can be utilized without departing from the scope of the present disclosure.

[0052] Interposer 104 can correspond to a semiconductor integrated circuit die or a semiconductor die. Interposer 104 includes semiconductor substrate 135. Interposer 104 includes a front-side dielectric stack 137 located on semiconductor substrate 135. Interposer 104 includes a back-side dielectric stack 139 located under the substrate.

[0053] Semiconductor substrate 135 can include silicon, silicon germanium, or other suitable semiconductor materials. Although Figure 1A not shown, in some embodiments, transistors can be formed in combination with semiconductor substrate 135.

[0054] In some embodiments, front-side dielectric stack 137 corresponds to a plurality of interlayer dielectric layers 140 formed on semiconductor substrate 135. Interlayer dielectric layers 140 can include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials.

[0055] Multiple metal lines 142 are formed in front-side dielectric stack 137. Each interlayer dielectric layer 140 (or a group of interlayer dielectric layers 140) can include a layer of metal lines 142 embedded therein. Additionally, conductive vias 144 can land on metal lines 142. Although Figure 1A only a single layer of metal lines 142 is shown, in practice, multiple layers of metal lines 142 can be included in a manner similar to the front side 116 of integrated circuit die 102. In an exemplary embodiment, metal lines 142 include copper. However, metal lines 142 can include tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. Conductive vias 144 can include copper, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials.

[0056] The front-side dielectric stack 137 includes a top metal structure 138 in a top dielectric layer 140. The top dielectric layer 140 corresponds to a passivation layer or a set of passivation layers. The passivation layer may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials. The top metal structure 138 may include one or more of copper tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. As previously described, the top metal structure 138 is electrically connected to the bottom metal structure 134 on the back side 118 of the integrated circuit die 102 through a hybrid bond 141.

[0057] In some embodiments, the back-side dielectric stack 139 corresponds to a plurality of interlayer dielectric layers 145 formed under the semiconductor substrate 135. The interlayer dielectric layers 145 may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials.

[0058] A plurality of metal lines 146 are formed in the back-side dielectric stack 139. Each interlayer dielectric layer 145 (or a set of interlayer dielectric layers 145) may include a layer of metal lines 146 embedded therein. Additionally, conductive vias 148 may land on the metal lines 146. Although Figure 1A only a single layer of metal lines 146 is shown, in practice, multiple layers of metal lines 146 may be included in a manner similar to the front side 116 of the integrated circuit die 102. In an exemplary embodiment, the metal lines 146 include copper. However, the metal lines 146 may include tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials. The conductive vias 148 may include copper, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials.

[0059] The back-side dielectric stack 139 includes a bottom metal structure 150 in a bottom dielectric layer 145. The bottom dielectric layer 145 corresponds to a passivation layer or a set of passivation layers. The passivation layer may include one or more of SiO, SiN, SiON, SiOCN, SiOC, SiCN, AlO, or other suitable dielectric materials. The bottom metal structure 150 may include one or more of copper tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive materials.

[0060] Returning to the semiconductor substrate 135, the semiconductor substrate 135 may include a plurality of through-silicon vias (TSVs) 152. Each TSV 152 extends between the metal lines 142 of the front-side dielectric stack 137 and the metal lines 146 of the back-side dielectric stack 139. In this way, the TSV 152 electrically connects the interconnect structure of the front-side dielectric stack 137 to the interconnect structure of the back-side dielectric stack 139.

[0061] The substrate 106 may include a package substrate, such as a PCB substrate, an organic substrate, or other types of substrates. Although Figure 1A is not shown, the substrate 106 may include a plurality of upper metal structures. The upper metal structure 155. The upper metal structure facilitates electrical connection to the interposer 104. Specifically, each bottom metal structure 150 of the interposer 104 is coupled to a corresponding top metal structure 155 of the substrate 106 through an external interconnect structure 154. The external interconnect structure 154 may include C4 copper bumps, solder bumps, or other types of conductive structures.

[0062] In some embodiments, the substrate 106 includes bottom metal structures 157 located on the bottom surface of the substrate 106. Although Figure 1A is not shown, the substrate 106 may include package traces or other internal interconnect structures that provide electrical connection between the top metal structure 155 and the bottom metal structure 157. Package balls 156 may be coupled to the bottom of the substrate 106 to enable electrical connection to a circuit board, and the package 100 may be mounted on the circuit board. Without departing from the scope of the present disclosure, various other conductive structures may be utilized. The package balls 156 may correspond to a ball grid array.

[0063] Figure 1A A metal interconnect structure 159 is shown that electrically couples one or more top metal structures 155 electrically coupled to the interposer 104 to the top metal structure 155 (electrically coupled to the second integrated circuit die 108). In some embodiments, the second integrated circuit die is a memory die. The metal interconnect structure 159 may include multiple metal lines, conductive vias, signal traces, or other types of interconnect structures. This enables communication between the integrated circuit die 102 and the integrated circuit die 108 via the substrate 106. As will be described in more detail below, in some embodiments, the integrated circuit die 108 is located on the top surface of the interposer 104 rather than on the top surface of the substrate 106. The metal interconnect structure 159 may be placed at a very tight pitch between the interposer 104 and the integrated circuit die 108. The integrated circuit die 108 may be connected to the integrated circuit die 102 via the interposer 104 or the substrate 106 having a local silicon or an embedded silicon bridge.

[0064] Integrated circuit die 108 includes memory array 158. Memory array 158 may correspond to an array of dynamic random access memory (DRAM) cells, static random access memory (SRAM) cells, flash memory cells, or other types of memory cells. In an exemplary embodiment, memory array 158 includes a DRAM array. Integrated circuit die 108 may include multiple individual stacked memory dies, each memory die including a portion of memory array 158. Integrated circuit die 108 may include bottom metal structures 161, each bottom metal structure 161 coupled to external interconnect structure 154.

[0065] After assembling integrated circuit package 100, integrated circuit package 100 may be mounted on a circuit board of an electronic device. The surface-level interconnect structures on the bottom of substrate 106 may be coupled to corresponding structures on the circuit board. Signals may be transmitted from the circuit board through substrate 106 to integrated circuit die 102 and integrated circuit die 108. Similarly, signals may be transmitted from integrated circuit die 102 and integrated circuit die 108 through substrate 106 to the circuit board.

[0066] Although Figure 1A not shown, in some embodiments, multiple integrated circuit dies 102 may be located on interposer 104. Each integrated circuit die 102 may be coupled to interposer 104 including metal structures 139 to improve heat dissipation.

[0067] Although Figure 1A not shown, after assembling the components of integrated circuit package 100, sealing may be performed. In other words, integrated circuit package 100 may include a seal on the substrate surrounding interposer 104, integrated circuit die 102, and integrated circuit die 108. The seal may be in direct contact with the top surface of metal structures 131 of carrier die 110. The seal may include one or more of molding compound, dielectric housing, or other structures to protect integrated circuit die 102, interposer 104, and integrated circuit die 108.

[0068] The principles of the present disclosure may be extended to various types of integrated circuit packages. Thus, integrated circuit package 100 may include an interposer-based package, a local silicon interconnect (LSI)-based package, an integrated fan-out (InFO)-based package, a chip-on-wafer-on-substrate (CoWoS)-based package, an integrated system-on-chip (SoIC)-based package, and a wafer-on-wafer (WoW)-based package or other types of packages.

[0069] Figure 1Bis a top view of a carrier die 110 according to some embodiments. The top view of the carrier die 110 shows the shape and location of the top metal structure 131. As previously elaborated, in some embodiments, the layout of the top metal structure 131 can be substantially the same as the layout of the top metal structure 130 of the integrated circuit die 102. Alternatively, in some embodiments, the layout of the top metal structure 131 can be different from the layout of the top metal structure 130.

[0070] Figures 2A to 2M is a view of the components of the integrated circuit package 100 at various assembly stages according to some embodiments. Figures 2A to 2M shows a process for forming Figure 1A the integrated circuit package 100 according to some embodiments.

[0071] Figure 2A is a cross-sectional view of a carrier die 110 according to some embodiments. According to some embodiments, the carrier die 110 is an example of a carrier die 100 at an intermediate stage of processing. As previously mentioned, the carrier die 110 can include semiconductor material. However, in some embodiments, the carrier die 110 can include dielectric material or other types of materials. Figure 1A In

[0072] In Figure 2B according to some embodiments, an etching process has been performed to form trenches 162 in the carrier die 110. The trenches 162 can be formed by first forming a hard mask having a pattern of the trenches 162 in combination with a lithography process. Then, the trenches 162 can be formed by timed etching in the presence of the hard mask. The timed etching is selected to form the trenches to a selected depth corresponding to the desired thickness of the metal structure 131.

[0073] In Figure 2C according to some embodiments, a metal material layer 164 has been deposited on the carrier die 110 and in the trenches 162. The material of the metal layer 164 is Figure 1A the material of the metal structure 131. Thus, the metal layer 164 can have the material previously described with respect to the metal structure 131. The metal layer 164 can be deposited by electroless plating (ECP), physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0074] In Figure 2D according to some embodiments, a chemical mechanical planarization (CMP) process has been performed on the carrier die 110. The CMP process removes the metal layer 164 from the top surface of the carrier die 110. As a result, the top metal structure 131 is formed from the metal layer 164. In addition, the top surface of the base material of the carrier die 110 is coplanar with the top surface of the metal structure 131.

[0075] Figure 2E is a cross-sectional view of an integrated circuit die 102 to be included in an integrated circuit package 100 according to some embodiments. At the Figure 2E processing stage shown, transistors 120 have been formed in the active device region 114 of the integrated circuit die 102. As previously described, the active device region 114 may include one or more semiconductor layers, and the transistors 120 are formed in combination with these semiconductor layers.

[0076] At Figure 2F According to some embodiments, the front vias 124 and the front-side dielectric stack 116 of the integrated circuit die 102 have been formed. The front vias 124 can be formed by depositing an interlayer dielectric layer over the transistors 120, patterning the interlayer dielectric layer to form holes for the front vias 123, filling the holes with the metal material of the front vias 24, and performing a CMP process.

[0077] At Figure 2F the dielectric layer 117, the metal lines 128, and the conductive vias 129 of the front side 116 have been formed. In addition, the top metal structure 130 has been formed. The first portion of the interlayer dielectric layer 117 can be deposited, patterned in the pattern of the metal lines 128 to be formed therein, the metal material for the metal lines 128 is deposited over the first portion of the interlayer dielectric layer 117, and a CMP process is performed to form each layer of the metal lines 128. The conductive vias 129 for each interlayer dielectric layer 117 can be formed by depositing the second portion of the interlayer dielectric layer 117 over the metal lines 128, patterning the second portion of the interlayer dielectric layer 117 to form holes (in which the conductive vias 129 will be formed), depositing the metal material of the conductive vias 129 in the holes, and performing a CMP process. This can be repeated until the desired number of layers of the metal lines 128 and the conductive vias 129 have been formed. Finally, the top metal structure 130 and the top dielectric layer 117 corresponding to the passivation layer can be formed in a similar manner.

[0078] At Figure 2G According to some embodiments, the bonding layer 112 has been formed on the front side 116 of the integrated circuit die 102. The bonding layer can be formed by a CVD process, an ALD process, a PVD process, or other suitable processes. The bonding layer 112 can have the materials and thicknesses previously described.

[0079] At Figure 2H According to some embodiments, the carrier die 110 (from Figure 2DThe processing stage shown) has been attached to the top of the integrated circuit die 102 via the bonding layer 112. The flip-chip carrier die 110 is flipped such that the metal structure 131 faces and is close to the metal structure 130 of the integrated circuit die 102. At this processing stage, the carrier die 110 has not been thinned.

[0080] In Figure 2I , according to some embodiments, the integrated circuit die 102 has been flipped such that the carrier die 110 is at the bottom and the active device region 114 is at the top. A thinning process has been performed to reduce the thickness of the back side of the active device region 114.

[0081] In Figure 2J , according to some embodiments, the bottom vias 126, TSVs 127, and the back side 118 have been formed. According to some embodiments, as described above, the bottom vias 126 can be formed in a manner similar to the top vias 124 and with different materials. The TSVs 127 can be formed by forming trenches in the active device region to expose selected portions of the metal lines 128 on the front side 116, depositing a metal material in the trenches, and performing a CMP process. The back side 118 including the dielectric layer 119, metal layer 132, conductive vias 133, and bottom metal structure 134 can be formed in a manner substantially similar to that described with respect to the front side 116.

[0082] In Figure 2K , according to some embodiments, the carrier die 168 has been attached to the back side 118 of the integrated circuit die 102. At the processing stage shown in Figure 2A , the carrier die 168 can be substantially similar to the carrier die 110. The integrated circuit die 102 has been flipped such that the carrier die 110 is at the top again.

[0083] In Figure 2L , according to some embodiments, a thinning process has been performed to reduce the thickness of the carrier die 110. The thinning process can include one or more of a grinding process, an etching process, and a CMP process. As a result of the thinning process, the thickness of the carrier die 110 is the same as the thickness of the metal structure 131. In addition, the top surface of the carrier die 110 is substantially coplanar with the top surface of the metal structure 131.

[0084] In Figure 2L , according to some embodiments, the integrated circuit die 102 has been attached to the interposer 104. Attaching the integrated circuit die 102 to the interposer 104 can include electrically connecting the bottom metal structure 134 of the integrated circuit die 102 to the top metal structure 138 of the interposer 104. In addition, a hybrid bond 141 is formed at the interface between the metal structure 134 and the metal structure 138. As described above, the hybrid bond makes the pattern of the metal structure 134 denser.

[0085] In Figure 2M , according to some embodiments, the interposer 104 and the integrated circuit die 108 have been attached to the top surface of the substrate 106. This results in the integrated circuit package 100 as shown and described with respect to Figure 1A . As previously described, the bottom metal structure 150 and the bottom metal structure 161 of the integrated circuit die 108 are connected to the top metal structure 155 through the connection structure 154. The substrate can utilize a local silicon interposer or an embedded multi-die interconnect bridge (EMIB). This enables the interconnect structure 159 to have a tight pitch between the interposer 104 and the integrated circuit die 108 to meet high-performance specifications. Other configurations and components can be utilized without departing from the scope of the present disclosure.

[0086] Figure 3 is an illustration of an integrated circuit package 100 according to some embodiments. Figure 3 The integrated circuit package 100 of Figure 1A is substantially similar in many aspects to the integrated circuit package 100 of Figure 3 . However, in Figure 3 , the integrated circuit die 108 includes a plurality of individual memory dies 170 stacked together, and each memory die 170 includes a portion of the memory array 108. The bottom die 170 includes the bottom metal structure 161. The stacked dies are connected through TSVs 172 and external connectors 174. In some embodiments, the integrated circuit die 108 can include up to 16 or more stacked dies 170.

[0087] The integrated circuit die 108 is located on the top surface of the interposer 104. This is different from the integrated circuit die 108 of Figure 1A , where the memory die is located on the top surface of the substrate 106. The bottom die 170 corresponds to the base die within the integrated circuit die 108. The bottom metal structure 161 of the base die 170 is connected to the top metal structure 138 of the interposer 104 through hybrid bonding. In addition, the electrical connectors 139 of the interposer 104 are electrically connected to the bottom metal structure 134 of the integrated circuit die 102 and the bottom metal structure 161 of the base die 170 of the integrated circuit die 108. The electrical connectors 139 can correspond to the shortest distance between the integrated circuit die 102 and the integrated circuit die 108.

[0088] The interposer 104 is an extended area with respect to the interposer 104 of Figure 1A . In addition, Figure 3The interposer 104 includes TSVs 176. One or more TSVs 176 extend from the bottom structure 134 of the integrated circuit die 102 to the bottom metal structure 150 of the interposer 104. One or more TSVs 176 of the interposer 104 extend from the bottom metal structure 161 of the base die 170 to the external interconnects 154 on the bottom surface of the interposer 104.

[0089] Figure 4 is a diagram of an integrated circuit package 100 according to some embodiments. Figure 4 The integrated circuit package 100 of Figure 1A is substantially similar to the integrated circuit package 100 of

[0090] Figure 5 is a flowchart of a method 500 according to some embodiments. The method 500 may utilize the processes, components, and systems described with respect to the foregoing figures. At 502, the method 500 includes coupling a first integrated circuit die to the top surface of an interposer, the first integrated circuit die including a plurality of transistors and a plurality of first top metal structures located above the transistors at the top surface of the first integrated die. An example of the first integrated circuit die is Figure 1A the integrated circuit die 102 of Figure 1A An example of a transistor is Figure 1A the interposer 104 of Figure 1A An example of a first top metal structure is Figure 1A the bonding layer 112 of Figure 1A An example of a carrier die is Figure 1A the pseudo-contact pads 131 of Figure 1A the substrate 106 of

[0091] Figure 6is a flow chart of a method 600 according to some embodiments. Method 600 may utilize the processes, components, and systems described with respect to the foregoing figures. At 602, method 600 includes forming a plurality of trenches in a first side of a carrier die. An example of a carrier die is Figure 2A the carrier die 110. An example of a trench is Figure 2B the trench 162 in. At 604, method 600 includes forming a plurality of pseudo contact pads in the trenches by depositing metal in the trenches and performing a chemical mechanical planarization process. An example of the metal is Figure 2C the metal 164. An example of a pseudo contact pad is Figure 2D the pseudo contact pad 131. At 606, method 600 includes exposing the pseudo contact pads at a second side of the carrier die opposite the first side by thinning the carrier die from the second side. At 608, method 600 includes coupling the carrier die to a top surface of an integrated circuit die including a plurality of transistors using a bonding layer. An example of the bonding layer is Figure 1A the bonding layer 112. An example of an integrated circuit die is Figure 1A the integrated circuit die 102. An example of a transistor is Figure 1A the transistor 120.

[0092] Embodiments of the present disclosure provide an integrated circuit package having improved heat dissipation. The integrated circuit package includes an integrated circuit die located on top of an interposer. The interposer is in turn located on a substrate. One or more memory dies are also located on the interposer or the substrate. The integrated circuit die includes a plurality of transistors, which may generate a large amount of heat during operation. The integrated circuit die includes a front side metal interconnect structure that includes conductive vias and metal lines located above the transistors. The integrated circuit die includes a back side metal interconnect structure that includes conductive vias and metal lines located below the transistors. The front side of the back side metal interconnect structure is electrically connected through one or more through holes. The front side interconnect structure includes a top metal layer patterned as a plurality of contact pads. To facilitate heat dissipation, the package includes a carrier die and is coupled to the top surface of the front side of the integrated circuit. The carrier die includes a plurality of pseudo contact pads located directly above the contact pads on the front side of the integrated circuit die. The carrier die is thinned such that the thickness of the carrier die corresponds to the thickness of the pseudo contact pads. A non-conductive bonding layer is located between the integrated circuit die and the carrier die.

[0093] The presence of the carrier die and the dummy contact pads results in significantly improved heat dissipation. Heat from the transistors of the integrated circuit die flows upward through the front-side metal interconnects to the contact pads. Heat flows to the dummy contact pads of the carrier die and is effectively dissipated from the dummy contact pads. Heat is also dissipated to a lesser extent through the back-side metal interconnects. However, the presence of the front-side interconnects and the dummy contact pads of the carrier die results in efficient upward heat dissipation of the transistors. This reduces the likelihood of component damage in the package. This also provides higher performance for the transistors and other components of the package. This also results in a higher package yield and fewer discarded packages.

[0094] In some embodiments, an integrated circuit package includes a substrate and a first integrated circuit die located on the substrate. The first integrated circuit die includes a plurality of transistors, a plurality of first top metal structures located over the transistors, and a plurality of first bottom metal structures located under the transistors. The package includes a carrier die bonded to the top surface of the first integrated circuit die, and the carrier die includes a plurality of dummy contact pads, each directly located over one or more of the first top metal structures. The package includes a bonding layer located between the carrier die and the first integrated circuit die and in direct contact with the first top metal structures and the dummy contact pads.

[0095] In some embodiments, the carrier die has the same vertical thickness as the dummy contact pads.

[0096] In some embodiments, the dummy contact pads and the first top metal structures have the same layout.

[0097] In some embodiments, the dummy contact pads have a different layout from the first top metal structures.

[0098] In some embodiments, the dummy contact pads have a larger overall layout area than the first top metal structures.

[0099] In some embodiments, an integrated circuit package includes an interposer located on the top surface of the substrate, and the interposer includes: a semiconductor layer, a second top metal structure located over the semiconductor layer, and a plurality of semiconductor vias extending through the semiconductor layer.

[0100] In some embodiments, the first integrated circuit die is located on the top surface of the interposer, wherein each of the first bottom metal structures is bonded to a corresponding second top metal structure of the interposer using hybrid bonding.

[0101] In some embodiments, the integrated circuit package includes a second integrated circuit die, the second integrated circuit die including a memory array and located on the substrate laterally adjacent to the interposer.

[0102] In some embodiments, the integrated circuit package includes a second integrated circuit die that includes a memory array and is located on the top surface of the interposer, and the second integrated circuit die includes a plurality of second bottom metal structures, each of which is bonded to a corresponding second top metal structure of the interposer by hybrid bonding.

[0103] In some embodiments, the second integrated circuit die includes a stack of memory dies.

[0104] In some embodiments, a method includes coupling a first integrated circuit die to the top surface of an interposer. The first integrated circuit die includes a plurality of transistors and a plurality of first top metal structures located above the transistors at the top surface of the first integrated die. The method includes coupling a carrier die to the top surface of the first integrated circuit die using a bonding layer such that each of a plurality of pseudo-contact pads of the carrier die is directly located above one or more of the first top metal structures, wherein the bonding layer is in direct contact with the first top metal structures and the pseudo-contact pads. The method includes coupling the interposer to the top surface of a substrate.

[0105] In some embodiments, coupling the first integrated circuit die to the top surface of the interposer includes performing a first hybrid bonding process that bonds each of a plurality of first bottom metal structures of the first integrated circuit die to a corresponding second top metal structure of the interposer.

[0106] In some embodiments, a method includes coupling a second integrated circuit die to the top surface of the interposer.

[0107] In some embodiments, coupling the second integrated circuit die to the top surface of the interposer includes: bonding each of a plurality of second bottom metal structures of the second integrated circuit die to a corresponding second top metal structure of the interposer using a first hybrid bonding process or a second hybrid bonding process.

[0108] In some embodiments, the carrier die has the same total thickness as the pseudo-contact pads.

[0109] In some embodiments, coupling the interposer to the top surface of the substrate includes coupling each of a plurality of micro-bumps between a corresponding bottom metal structure of the interposer and a corresponding second top metal structure of the substrate.

[0110] In some embodiments, the interposer includes a plurality of semiconductor vias.

[0111] In some embodiments, the method includes forming a plurality of trenches in a first side of a carrier die and forming a plurality of pseudo contact pads in the trenches by depositing metal in the trenches and performing a chemical mechanical planarization process. The method includes: exposing the pseudo contact pads at a second side of the carrier die opposite the first side by thinning the carrier die from the second side, and coupling the carrier die to a top surface of an integrated circuit die including a plurality of transistors using a bonding layer.

[0112] In some embodiments, the bonding layer is a dielectric layer.

[0113] In some embodiments, after coupling the carrier die to the integrated circuit die, each of the pseudo contact pads is directly located above one or more top metal structures at the top surface of the integrated circuit die.

[0114] The features of several embodiments are outlined above so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit package, comprising: A substrate; A first integrated circuit die, located on top of the substrate and comprising: A plurality of transistors; A plurality of first top metal structures, located on top of the transistors; and A plurality of first bottom metal structures, located below the transistors; A carrier die, bonded to the top surface of the first integrated circuit die, and the carrier die comprises a plurality of pseudo-contact pads, each of the pseudo-contact pads being directly above one or more of the first top metal structures; and A bonding layer, located between the carrier die and the first integrated circuit die, and the bonding layer is in direct contact with the first top metal structures and the pseudo-contact pads.

2. The integrated circuit package according to claim 1, wherein, The carrier die has the same vertical thickness as the pseudo-contact pads.

3. The integrated circuit package according to claim 1, wherein, The pseudo-contact pads and the first top metal structures have the same layout.

4. The integrated circuit package according to claim 1, wherein The pseudo-contact pads have a different layout from the first top metal structures.

5. The integrated circuit package according to claim 4, wherein, The pseudo-contact pads have a larger overall layout area than the first top metal structures.

6. The integrated circuit package according to claim 1, comprising: An interposer, located on the top surface of the substrate and comprising: A semiconductor layer; A second top metal structure, located on top of the semiconductor layer; and A plurality of semiconductor vias, extending through the semiconductor layer.

7. The integrated circuit package according to claim 6, wherein, The first integrated circuit die is located on the top surface of the interposer, wherein each of the first bottom metal structures is bonded to a corresponding second top metal structure of the interposer by hybrid bonding.

8. The integrated circuit package according to claim 7, comprising a second integrated circuit die, the second integrated circuit die comprising a memory array and being located on the substrate laterally adjacent to the interposer.

9. A method of forming an integrated circuit package, comprising: Coupling a first integrated circuit die to the top surface of an interposer, the first integrated circuit die comprising a plurality of transistors and a plurality of first top metal structures located on top of the transistors at the top surface of the first integrated circuit die; Coupling a carrier die to the top surface of the first integrated circuit die using a bonding layer such that each of the plurality of pseudo-contact pads of the carrier die is directly above one or more of the first top metal structures, wherein the bonding layer is in direct contact with the first top metal structures and the pseudo-contact pads; And Coupling the interposer to the top surface of a substrate.

10. A method of forming an integrated circuit package, comprising: Forming a plurality of trenches in a first side of a carrier die; Forming a plurality of pseudo-contact pads in the trenches by depositing metal in the trenches and performing a chemical mechanical planarization process; Exposing the pseudo-contact pads at a second side of the carrier die opposite to the first side by thinning the carrier die from the second side; And Coupling the carrier die to the top surface of an integrated circuit die comprising a plurality of transistors using a bonding layer.

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