Heterojunction solar cell and preparation method therefor

Abstract

The present application discloses a heterojunction solar cell and a preparation method therefor. The preparation method comprises the following steps: cleaning and texturing a silicon substrate; respectively preparing intrinsic amorphous silicon layers on two surfaces of the silicon substrate; preparing an N-type doped layer on a front intrinsic amorphous silicon layer; preparing a P-type doped layer on a back intrinsic amorphous silicon layer; using an RPD device to prepare a back indium-containing TCO seed layer on the P-type doped layer, and using a PVD device to prepare a back indium-free TCO thin film on the back indium-containing TCO seed layer; using the PVD device to prepare a front indium-containing TCO seed layer on the N-type doped layer, and preparing a front indium-free TCO thin film on the front indium-containing TCO seed layer; and respectively preparing back electrodes and front electrodes. According to the present application, the normal operation time and effective operation time of an RPD and PVD combination device can be effectively increased, the effective productivity of the device is increased, and battery manufacturing costs are reduced.

Description

Heterojunction solar cell and preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 2023116194612, filed on November 30, 2023, entitled “Heterojunction Solar Cell and Its Preparation Method,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a heterojunction solar cell and a preparation method thereof. Background Art

[0004] Heterojunction (SHJ) solar cell technology has achieved a conversion efficiency of 25.6%. Heterojunction back contact (HBC) cells, developed based on HJ cells, have achieved a conversion efficiency of 26.67%. Currently, some HJ solar cells have reached a world record conversion efficiency of 26.81%. HJ solar cells are bifacial cells with numerous advantages, including a simple process flow, high conversion efficiency, low temperature coefficient, energy-saving low-temperature manufacturing, suitability for thin-film production, natural bifacial power generation, and excellent low-light response. They have rapidly developed in the photovoltaic field. Improving the efficiency of HJ solar cells, reducing their manufacturing costs, and ultimately translating them into power generation benefits are key priorities in the current HJ industrialization.

[0005] It should be noted that the transparent conductive oxide (TCO) film in the heterojunction solar cell that set the world efficiency record of 26.81% was deposited using reactive ion deposition (RPD) equipment. The TCO film in mass-produced heterojunction solar cells is essentially deposited using physical vapor deposition (PVD) equipment. Currently, a very small number of heterojunction cells utilize a combination of RPD and PVD equipment to co-deposit the TCO film, giving rise to the corresponding PAR equipment (PVD and RPD). PAR equipment utilizes RPD equipment for the lower cell coating (back TCO film), while PVD equipment is used for the upper cell coating (front TCO film). Although heterojunction cells utilize PAR equipment for co-deposition of the TCO film, the thickness of the back TCO film deposited by RPD equipment is generally 100nm-120nm to ensure conductivity and back reflection, resulting in low RPD production capacity. The inherent dust generation during the RPD process results in short maintenance (PM) cycles, significantly reducing overall equipment utilization. Furthermore, the target materials required for RPD coating are significantly more expensive than those for PVD, and RPD target utilization is low, typically below 40%. These factors combined result in heterojunction solar cells fabricated using a combination of RPD and PVD, while offering certain efficiency advantages, at the expense of high costs, hindering their industrialization. Summary of the Invention

[0006] Based on this, it is necessary to provide a method for preparing a heterojunction solar cell and a heterojunction solar cell.

[0007] An embodiment of the present application provides a method for preparing a heterojunction solar cell, comprising the following steps:

[0008] Cleaning and texturing the silicon substrate;

[0009] Intrinsic amorphous silicon layers are respectively prepared on two surfaces of a silicon substrate;

[0010] preparing an N-type doped layer on the front intrinsic amorphous silicon layer of the silicon substrate;

[0011] preparing a P-type doped layer on the intrinsic amorphous silicon layer on the back side of the silicon substrate;

[0012] A back-side indium-containing TCO seed layer is prepared on the P-type doped layer using an RPD device, and a back-side indium-free TCO film is prepared on the back-side indium-containing TCO seed layer using a PVD device;

[0013] Using a PVD device to prepare a front indium-containing TCO seed layer on the N-type doped layer, and preparing a front indium-free TCO film on the front indium-containing TCO seed layer; and

[0014] A back electrode is prepared on the back indium-free TCO film, and a front electrode is prepared on the front indium-free TCO film.

[0015] In some embodiments, the silicon substrate is an N-type single crystal silicon wafer, the thickness of the silicon substrate is 60 μm to 180 μm, and the resistivity is 0.2 Ω.cm to 5 Ω.cm.

[0016] In some embodiments, cleaning and texturing the silicon substrate comprises the following steps:

[0017] The silicon substrate is treated with gettering equipment using a high-temperature tubular phosphorus diffusion or chain gettering equipment. The sheet resistance of the silicon substrate after gettering is 20Ω / □ to 40Ω / □.

[0018] A tank-type wet acid solution is used to remove the PSG layer on the surface of the silicon substrate after gettering.

[0019] The silicon substrate is textured on the surface using an alkaline solution, so that both sides of the silicon substrate have a pyramid-shaped surface light trapping structure, and

[0020] The silicon substrate is cleaned to remove the surface oxide layer.

[0021] In some embodiments, cleaning the silicon substrate to remove the surface oxide layer includes the following steps:

[0022] Perform RCA cleaning on silicon substrates;

[0023] Cleaning the silicon substrate with an HF solution to remove the surface oxide layer; and

[0024] The silicon substrate was cleaned with deionized water and the surface of the silicon substrate was dried.

[0025] In some embodiments, forming intrinsic amorphous silicon layers on two surfaces of a silicon substrate comprises the following steps:

[0026] The intrinsic amorphous silicon layer is deposited by RF-PECVD equipment; wherein the power frequency of the RF-PECVD equipment is 13.56MHz~40MHz, the process gas contains one or more of SiH4, H2, CO2, CH4, N2O, the deposition temperature is 160℃~220℃, and the deposition pressure is 0.2mbar~2mbar.

[0027] In some embodiments, the thickness of the intrinsic amorphous silicon layer is 2 nm to 10 nm.

[0028] In some embodiments, the N-type doped layer is an N-type doped amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer;

[0029] And / or, the thickness of the N-type doping layer is 5 nm to 20 nm.

[0030] In some embodiments, forming an N-type doped layer on the front intrinsic amorphous silicon layer of a silicon substrate includes the following steps:

[0031] An N-type doped layer is deposited on the front intrinsic amorphous silicon layer of the silicon substrate by using an RF-CVD device or a VHF-CVD device; the power frequency of the RF-CVD device or the VHF-CVD device is 13.56 MHz to 40 MHz, and the process gas contains one or more of SiH4, H2, CO2, CH4, N2O, and PH3; the deposition temperature is 160°C to 200°C, and the deposition pressure is 0.5 mbar to 5 mbar.

[0032] In some embodiments, the P-type doped layer is a P-type doped amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer;

[0033] And / or, the thickness of the P-type doping layer is 5 nm to 30 nm.

[0034] In some embodiments, forming a P-type doped layer on the back intrinsic amorphous silicon layer of the silicon substrate includes the following steps:

[0035] A p-type doped layer is deposited on the intrinsic amorphous silicon layer on the back side of the silicon substrate by an RF-CVD device or a VHF-CVD device; the power frequency of the RF-CVD device or the VHF-CVD device is 13.56 MHz to 40 MHz, the process gas contains one or more of SiH4, H2, CO2, CH4, N2O, B2H6, TMB, the deposition temperature is 160°C to 200°C, and the deposition pressure is 0.5 mbar to 5 mbar.

[0036] In some embodiments, the back indium-containing TCO seed layer is an ITO film, a VTTO film, a SCOT film, an IWO film, an ICO film, or an IMO film;

[0037] And / or, the thickness of the back indium-containing TCO seed layer is 1 nm to 20 nm.

[0038] In some of the embodiments, the RPD equipment is used to prepare the back indium-containing TCO seed layer on the P-type doped layer to meet the following conditions: the process temperature is 0-200°C, the process pressure is 0.3Pa-0.8Pa, and the process gas is Ar / O2 and Ar / H2 or H2O, among which Ar / O2 is a necessary process gas and the rest are non-essential process gases.

[0039] In some embodiments, the back-side indium-free TCO film has a thickness of 80 nm to 120 nm;

[0040] And / or, the back indium-free TCO film is a SnO2 film, a ZnO film, an AZO film, a GZO film or a GAZO film.

[0041] In some embodiments, the PVD device is a magnetron sputtering device, and the back-side indium-free TCO film is prepared on the back-side indium-containing TCO seed layer using the PVD device to meet the following conditions: the power density is 2KW / m 2 ~8KW / m 2 The process gases are Ar / O2 and Ar / H2 or H2O, among which Ar / O2 is a necessary process gas and the rest are non-essential process gases. The process pressure is 0.3Pa~0.8Pa and the process temperature is 0-100℃.

[0042] In some embodiments, the front indium-containing TCO seed layer is an ITO film, a VTTO film, a SCOT film, an IWO film, an ICO film, or an IMO film;

[0043] And / or, the thickness of the front indium-containing TCO seed layer is 5 nm to 50 nm.

[0044] In some embodiments, a PVD device is used to prepare a front indium-containing TCO seed layer on the N-type doped layer, and a front indium-free TCO film is prepared on the front indium-containing TCO seed layer to meet the following conditions: a power density of 2KW / m 2 ~8KW / m 2 The process gases are Ar / O2 and Ar / H2 or H2O, among which Ar / O2 is a necessary process gas and the rest are non-essential process gases. The process pressure is 0.3Pa~0.8Pa and the process temperature is 0-100℃.

[0045] In some embodiments, the thickness of the front-side indium-free TCO film is 40 nm to 100 nm;

[0046] And / or, the front indium-free TCO film is a SnO2 film, a ZnO film, an AZO film, a GZO film or a GAZO film.

[0047] In some embodiments, the back electrode is formed on the back indium-free TCO film and the front electrode is formed on the front indium-free TCO film, respectively and independently selected from one or more of the following methods:

[0048] (1) preparing the back electrode or the front electrode by screen printing or laser transfer of one or more of low-temperature silver paste, low-temperature copper paste, and silver-coated copper paste;

[0049] (2) The back electrode or the front electrode is prepared by forming a patterned metal grid line by electroplating one or more alloys of Al, Ti, Ni, Co, Ag, Cu and Sn.

[0050] An embodiment of the present application further provides a heterojunction solar cell, which is prepared using the preparation method.

[0051] The preparation method of the heterojunction solar cell described in the embodiment of the present application can reduce the coating thickness of the RPD device, shorten its PM cycle, and improve its production capacity. At the same time, the combination of indium-free materials can further reduce the TCO film cost of the heterojunction solar cell, maximize the battery conversion efficiency, and facilitate industrial development. The preparation method of the heterojunction solar cell described in the embodiment of the present application can effectively increase the normal operation time and effective operation time of the RPD and PVD combined equipment, increase the effective production capacity of the equipment, reduce the TCO film manufacturing cost and raw material cost, maximize the technical advantages of the RPD device itself in the coating, ensure battery efficiency, reduce the manufacturing cost of heterojunction solar cells, and facilitate its large-scale manufacturing production. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0053] FIG1 is a schematic diagram of a method for preparing a heterojunction solar cell according to an embodiment of the present application.

[0054] FIG2 is a schematic diagram of the structure of a heterojunction solar cell prepared by the method for preparing a heterojunction solar cell according to an embodiment of the present application.

[0055] Description of Reference Numerals

[0056] 10. Heterojunction solar cell; 100. Silicon substrate; 201, 202. Intrinsic amorphous silicon layer; 301. N-type doped layer; 302. P-type doped layer; 401. Front-side indium-containing TCO seed layer; 501. Front-side indium-free TCO film; 402. Back-side indium-containing TCO seed layer; 502. Back-side indium-free TCO film; 601. Front electrode; 602. Back electrode. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0058] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0059] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0060] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0061] In the description of this application, "several" means more than one, "plurality" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0062] In this article, unless otherwise indicated, each reaction step may be carried out in the order in which it is presented, or may be carried out out of the order in which it is presented. For example, other steps may be included between each reaction step, and the order of the reaction steps may be appropriately reversed. This is something that can be determined by a skilled person based on conventional knowledge and experience. Alternatively, the reaction methods herein are carried out sequentially.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0064] Unless otherwise defined, the thickness in this application refers to the thickness of the film layer tested on a polished wafer substrate.

[0065] In traditional technology, when preparing heterojunction solar cells, the RPD equipment has too low production capacity. The RPD equipment itself is prone to generating dust during the process, resulting in a short PM cycle, which greatly shortens the overall equipment utilization rate. At the same time, the target material required for RPD coating is much more expensive than the PVD target material, and the RPD equipment target material utilization rate is low, resulting in a high cost for heterojunction solar cells prepared by combining RPD and PVD, which is not conducive to industrial development.

[0066] In response to the above problems, an embodiment of the present application provides a method for preparing a heterojunction solar cell 10, which can reduce the coating thickness of the RPD device, shorten its PM cycle, and improve its production capacity. At the same time, combined with indium-free materials, it can further reduce the TCO film cost of the heterojunction solar cell, maximize the battery conversion efficiency, and facilitate industrial development.

[0067] For example, please refer to FIG1 , which is a schematic diagram of a process flow of a method for preparing a heterojunction solar cell 10 provided in an embodiment of the present application.

[0068] The method for preparing the heterojunction solar cell 10 provided in the embodiment of the present application includes the following steps:

[0069] S1, cleaning and texturing the silicon substrate 101;

[0070] S2, forming intrinsic amorphous silicon layers 201 and 202 on two surfaces of the silicon substrate 101 respectively;

[0071] S3, forming an N-type doped layer 301 on the front intrinsic amorphous silicon layer 201 of the silicon substrate 101;

[0072] S4, forming a P-type doped layer 302 on the intrinsic amorphous silicon layer 202 on the back side of the silicon substrate 101;

[0073] S5, using a reactive plasma deposition (RPD) device to form a back-side indium-containing TCO seed layer 402 on the P-type doped layer 302, and using a physical vapor deposition (PVD) device to form a back-side indium-free TCO film 502 on the back-side indium-containing TCO seed layer 402;

[0074] S6, using a PVD device to form a front indium-containing TCO seed layer 401 on the N-type doped layer 301, and to form a front indium-free TCO film 501 on the front indium-containing TCO seed layer 401;

[0075] S7 , preparing a back electrode 602 on the back indium-free TCO film 502 and preparing a front electrode 601 on the front indium-free TCO film 501 .

[0076] The above-mentioned preparation method of the heterojunction solar cell 10 can reduce the coating thickness of the RPD device, shorten its PM cycle, and improve its production capacity. At the same time, the combination of indium-free materials can further reduce the TCO film cost of the heterojunction solar cell, maximize the battery conversion efficiency, and facilitate industrial development. The preparation method of the heterojunction solar cell described in the embodiment of the present application can effectively increase the normal operation time and effective operation time of the RPD and PVD combined equipment, increase the effective production capacity of the equipment, reduce the TCO film manufacturing cost and raw material cost, maximize the technical advantages of the RPD device's own coating, ensure battery efficiency, reduce the manufacturing cost of heterojunction solar cells, and facilitate their large-scale manufacturing production.

[0077] In the method for preparing a heterojunction solar cell described in an embodiment of the present application, a TCO film is deposited on the front side of a silicon substrate 101 using conventional PVD equipment. The front TCO film is a combination of a front indium-containing TCO seed layer 401 and a front indium-free TCO film 501. Specifically, the front indium-containing TCO seed layer 401 and the front indium-free TCO film 501 are deposited using PVD equipment. The front indium-containing TCO seed layer 401 is primarily used to match the p-face doped semiconductor (i.e., p-type semiconductor), while the front indium-free TCO film 501 is primarily intended to reduce the overall TCO cost.

[0078] A relatively thin back-side indium-containing TCO seed layer 402 is first deposited on the back side of the silicon substrate 101 using an RPD device, followed by the deposition of a back-side indium-free TCO film 502 using a PVD device. The back-side RPD device and PVD device chambers are connected, meaning that after RPD coating, the vacuum does not need to be broken and the film can be directly deposited in the PVD chamber for subsequent coating. Using the RPD device to initially form the back-side indium-containing TCO seed layer 402 ensures high density and no ion damage to the back-side passivation structure. Furthermore, the indium-containing TCO seed layer 402 provides better bandgap and work function matching with the P-type doped conductive layer 302. This also promotes crystallization of the subsequent back-side indium-free TCO film 502, enhancing its carrier mobility and improving its electrical properties. Since the RPD device only deposits the back-side indium-containing TCO seed layer 402, it effectively increases RPD device capacity, increases utilization, and reduces PM cycles. This also reduces the use of expensive RPD targets, reducing production costs.

[0079] The working principle of physical vapor deposition (PVD) is: in a vacuum environment, through the combined action of voltage and magnetic field, the target material is bombarded with ionized inert gas ions, causing the target material to be ejected in the form of ions, atoms or molecules and deposited on the substrate to form a thin film.

[0080] The reactive plasma deposition (RPD) equipment mainly consists of a vacuum chamber, a hollow cathode ion gun, an ion beam controller, a magnetic focusing cold water crucible (source placement area), a flow controller system, a static suspension workpiece holder, a cooling water system, etc. For example, the working principle of RPD is as follows: (1) After the vacuum chamber is evacuated to the background vacuum, Ar gas is introduced into the tantalum tube of the cathode plasma gun. After the plasma power is turned on, arc discharge is first generated in the tantalum tube. After the Ar in the tube is ionized, the Ar + Bombarding the tantalum tube, under the hollow cathode effect, the tantalum tube is + The bombardment causes rapid heating, emitting high-density plasma dominated by thermal electrons, and the gas discharge mode is arc discharge. (2) Ar + When the plasma reaches the vacuum chamber, it is bent and focused downward by the action of the magnetic poles and electromagnetic coils near the crucible, and then incident on the evaporation source material in the anode crucible. The kinetic energy of the Ar plasma is converted into thermal energy, heating and evaporating the solid evaporation source material. (3) As the evaporation source moves toward the target substrate, it interacts with the plasma above the crucible and produces partial ionization, which greatly enhances the chemical activity of the evaporated material. In particular, a few centimeters above the crucible, the upward-moving evaporation source and the downward-moving Ar plasma interact strongly, forming an intense plasma region.

[0081] In some embodiments, the silicon substrate 101 is an N-type single crystal silicon wafer, the thickness of the silicon substrate 101 is 60 μm to 180 μm, and the resistivity of the silicon substrate 101 is 0.2 Ω.cm to 5 Ω.cm.

[0082] In some embodiments, S1, performing a cleaning and texturing process on the silicon substrate 101 includes the following steps:

[0083] Gettering treatment is performed on silicon substrate 101 using a high-temperature tubular phosphorus diffusion or chain gettering equipment. The primary purpose is to remove metal ion impurities from the silicon wafer and improve the quality of silicon substrate 101. After gettering, the sheet resistance of silicon substrate 101 is reduced to 20Ω / □ to 40Ω / □. A bath-type wet acid solution is then used to remove the phosphosilicate glass (PSG) layer on the surface of silicon substrate 101 after gettering. An alkaline solution is then used to texture the surface of silicon substrate 101, creating a pyramid-shaped light-trapping structure on both sides of silicon substrate 101. Silicon substrate 101 is then cleaned to remove the surface oxide layer.

[0084] In some embodiments, the cleaning of the silicon substrate 101 includes the following steps: performing RCA cleaning (or a solution formulation equivalent to RCA cleaning) on ​​the silicon substrate 101, then using a hydrofluoric acid (HF) solution to clean the silicon substrate 101 to remove the surface oxide layer, and finally cleaning with deionized water and drying the surface.

[0085] In some embodiments, S2, forming intrinsic amorphous silicon layers 201 and 202 on two surfaces of the silicon substrate 101, respectively, specifically comprises the following steps:

[0086] The intrinsic amorphous silicon layers 201 and 202 are deposited by radio frequency plasma enhanced chemical vapor deposition (RF-PECVD) equipment; in the RF-PECVD process, the equipment power frequency adopts 13.56MHz~40MHz, for example, 13.56MHz, 26MHz or 40MHz, etc., and 13.56MHz is adopted in some embodiments, and the process gas comprises one or more of SiH4, H2, CO2, CH4, N2O, the deposition temperature is 160℃~220℃, and the deposition pressure is 0.2mbar~2mbar.

[0087] In some embodiments, the thickness of the intrinsic amorphous silicon layers 201 and 202 is 2 nm to 10 nm.

[0088] In some embodiments, the N-type doped layer 301 is an N-type doped amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer.

[0089] In some embodiments, the thickness of the N-type doped layer 301 is 5 nm to 20 nm.

[0090] In some embodiments, S3, forming an N-type doped layer 301 on the front intrinsic amorphous silicon layer 201 of the silicon substrate 101 includes the following steps:

[0091] An N-type doped layer 301 is deposited on the front intrinsic amorphous silicon layer 201 of the silicon substrate 101 by radio frequency chemical vapor deposition (RF-CVD) or very high frequency chemical vapor deposition (VHF-CVD). The power supply frequency of the RF-CVD or VHF-CVD equipment is 13.56 MHz to 40 MHz, such as 13.56 MHz, 26 MHz, or 40 MHz. In some embodiments, the RF-CVD equipment uses 13.56 MHz and the VHF-CVD equipment uses 40 MHz. The process gas of the RF-CVD or VHF-CVD equipment includes one or more of SiH4, H2, CO2, CH4, N2O, and PH3. The deposition temperature is 160°C to 200°C, and the deposition pressure is 0.5 mbar to 5 mbar.

[0092] In some embodiments, the P-type doped layer 302 is a P-type doped amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer.

[0093] In some embodiments, the thickness of the P-type doped layer 302 is 5 nm to 30 nm.

[0094] In some embodiments, S4, forming a P-type doped layer 302 on the back intrinsic amorphous silicon layer 202 of the silicon substrate 101 includes the following steps:

[0095] A P-type doped layer 302 is deposited on the intrinsic amorphous silicon layer 202 on the back side of the silicon substrate 101 using an RF-CVD device or a VHF-CVD device. The RF-CVD device or the VHF-CVD device uses a power supply of 13.56 MHz to 40 MHz, such as 13.56 MHz, 26 MHz, or 40 MHz. In some embodiments, the RF-CVD device uses 13.56 MHz and the VHF-CVD device uses 40 MHz. The process gas of the RF-CVD device or the VHF-CVD device includes one or more of SiH4, H2, CO2, CH4, N2O, B2H6, and TMB (trimethylboron, chemical formula C3H9B). The deposition temperature is 160°C to 200°C, and the deposition pressure is 0.5 mbar to 5 mbar.

[0096] In some embodiments, the back indium-containing TCO seed layer 402 is a tin-doped indium oxide (ITO) film, a zirconium-titanium-calcium-doped indium oxide (SCOT) film, a tungsten-doped indium oxide (IWO) film, a cerium-doped indium oxide (ICO) film, or a molybdenum-doped indium oxide (IMO) film.

[0097] In some embodiments, the back-side indium-containing TCO seed layer 402 has a thickness of 1 nm to 20 nm.

[0098] In some of the embodiments, in S5, the RPD equipment is used to prepare the back indium-containing TCO seed layer 402 on the P-type doped layer 302 to meet the following conditions: the process temperature is 0-200°C, the process pressure is 0.3Pa-0.8Pa, and the process gas is Ar / O2 and Ar / H2 or H2O, among which Ar / O2 is a necessary process gas and the rest are non-essential process gases.

[0099] In some embodiments, the thickness of the back-side indium-free TCO film 502 is 80 nm to 120 nm.

[0100] In some embodiments, the back-side indium-free TCO film 502 is a tin oxide (SnO2) film, a zinc oxide (ZnO) film, an aluminum-doped zinc oxide (AZO) film, a gallium-doped zinc oxide (GZO) film, or an aluminum-gallium co-doped zinc oxide (GAZO) film.

[0101] In some embodiments, in S5, the PVD device is a magnetron sputtering device, and the back-side indium-free TCO film 502 is prepared on the back-side indium-containing TCO seed layer 402 by using the PVD device to meet the following conditions: the power density is 2KW / m 2 ~8KW / m 2 The process gases are Ar / O2 and Ar / H2 or H2O, among which Ar / O2 is a necessary process gas and the others are non-essential process gases. The process pressure is 0.3Pa~0.8Pa and the process temperature is 0-100℃.

[0102] In some embodiments, the front indium-containing TCO seed layer 401 is an ITO film, a VTTO film, a SCOT film, an IWO film, an ICO film, or an IMO film.

[0103] In some embodiments, the thickness of the front-side indium-containing TCO seed layer 401 is 5 nm to 50 nm.

[0104] The front indium-containing TCO seed layer 401 and the front indium-free TCO film 501 are both formed using PVD equipment. In some embodiments, in S6, the front indium-containing TCO seed layer 401 is formed on the N-type doped layer 301, and the front indium-free TCO film 501 is formed on the front indium-containing TCO seed layer 401 using PVD equipment to meet the following conditions: the power density is 2KW / m 2 ~8KW / m 2 The process gases are Ar / O2 and Ar / H2 or H2O, among which Ar / O2 is a necessary process gas and the rest are non-essential process gases. The process pressure is 0.3Pa~0.8Pa and the process temperature is 0-100℃.

[0105] In some embodiments, the thickness of the front-side indium-free TCO film 501 is 40 nm to 100 nm.

[0106] In some embodiments, the front-side indium-free TCO film 501 is a SnO 2 film, a ZnO film, an AZO film, a GZO film, or a GAZO film.

[0107] In some embodiments, in S7, the steps of preparing the back electrode 602 on the back indium-free TCO film 502 and the front electrode 601 on the front indium-free TCO film 501 are independently selected from one or more of the following methods:

[0108] (1) preparing the back electrode 602 or the front electrode 601 by screen printing or laser transfer of one or more of low-temperature silver paste, low-temperature copper paste, and silver-coated copper paste;

[0109] (2) A patterned metal grid line is formed by electroplating one or more alloys of Al, Ti, Ni, Co, Ag, Cu and Sn to prepare the back electrode 602 or the front electrode 601.

[0110] The present application also provides a heterojunction solar cell 10, which is prepared using the above-mentioned preparation method. Referring to FIG2 , FIG2 is a schematic structural diagram of the heterojunction solar cell 10 provided in one embodiment of the present application. The heterojunction solar cell 10 includes a silicon substrate 101, an intrinsic amorphous silicon layer 201, an N-type doped layer 301, a front indium-containing TCO seed layer 401, a front indium-free TCO film 501, and a front electrode 601 stacked sequentially on the front surface of the silicon substrate 101, and an intrinsic amorphous silicon layer 202, a P-type doped layer 302, a back indium-containing TCO seed layer 402, a back indium-free TCO film 502, and a back electrode 602 stacked sequentially on the back surface of the silicon substrate 101.

[0111] Example 1

[0112] This embodiment provides a heterojunction solar cell 10. The heterojunction solar cell 10 is manufactured by the following manufacturing method.

[0113] A method for preparing a heterojunction solar cell 10 comprises the following steps:

[0114] (1) An N-type single crystal silicon wafer is used as the silicon substrate 101 . The thickness of the silicon substrate 101 is 100 μm, and the resistivity of the silicon substrate 101 is 1 Ω·cm.

[0115] The silicon substrate 101 was cleaned and textured, and then treated with a chain-type gettering device. After gettering, the sheet resistance of the silicon substrate 101 was 30Ω / □. The PSG layer on the surface of the silicon substrate 101 after gettering was then removed using a tank-type wet acid solution. The surface of the silicon substrate 101 was textured using an alkaline solution, resulting in a pyramid-shaped surface light-trapping structure on both sides of the silicon substrate 101.

[0116] After the silicon substrate 101 is cleaned with RCA (or a solution formula equivalent to RCA cleaning), the silicon substrate 101 is cleaned with HF solution to remove the surface oxide layer, and finally cleaned with deionized water and the surface is dried.

[0117] (2) Intrinsic amorphous silicon layers 201 and 202 are formed on both surfaces of the silicon substrate 101 by an RF-PECVD process. The RF-PECVD process uses a 13.56 MHz power supply, SiH4 as the process gas, a deposition temperature of 180° C., a deposition pressure of 1 mbar, and a thickness of 8 nm for the intrinsic amorphous silicon layers 201 and 202.

[0118] (3) An N-type doped layer 301 is deposited on the front intrinsic amorphous silicon layer 201 of the silicon substrate 101 using an RF-CVD device. The N-type doped layer 301 is an N-type doped amorphous silicon layer. The RF-CVD device uses a 13.56 MHz power supply, a process gas containing SiH 4 , a deposition temperature of 180° C., a deposition pressure of 1 mbar, and a deposition thickness of 10 nm for the N-type doped layer 301 .

[0119] (4) A P-type doped layer 302 is deposited on the intrinsic amorphous silicon layer 202 on the back side of the silicon substrate 101 using an RF-CVD device. The P-type doped layer 302 is a P-type doped amorphous silicon layer. The RF-CVD device uses a 13.56 MHz power supply. The RF-CVD device process gases include SiH4 and TMB. The deposition temperature is 180°C, the deposition pressure is 1 mbar, and the thickness of the P-type doped layer 302 is 20 nm.

[0120] (5) An ITO film was prepared on the P-type doped layer 302 using an RPD device as a back-side indium-containing TCO seed layer 402. The thickness of the back-side indium-containing TCO seed layer 402 was 5 nm. During deposition, the process temperature was 100°C, the process pressure was 0.5 Pa, and the process gases were Ar / O2 and Ar / H2. A SnO2 film was prepared on the back-side indium-containing TCO seed layer 402 using a magnetron sputtering device as a back-side indium-free TCO film 502. The thickness of the back-side indium-free TCO film 502 was 100 nm. During deposition, the power density was 5 KW / m 2 , the process gases are Ar / O2 and Ar / H2, the process pressure is 0.5Pa, and the process temperature is 60℃.

[0121] (6) Using a PVD device, an ITO film is prepared on the N-type doped layer 301 as a front indium-containing TCO seed layer 401. The thickness of the front indium-containing TCO seed layer 401 is 10 nm. A SnO2 film is also prepared on the front indium-containing TCO seed layer 401 as a front indium-free TCO film 501. The thickness of the front indium-free TCO film 501 is 80 nm. During the PVD deposition, the power density is 5 KW / m 2 , the process gases are Ar / O2 and Ar / H2, the process pressure is 0.5Pa, and the process temperature is 60℃.

[0122] (7) A back electrode 602 is prepared on the back indium-free TCO film 502 by screen printing a low-temperature silver paste, and a front electrode 601 is prepared on the front indium-free TCO film 501.

[0123] Example 2

[0124] This embodiment provides a heterojunction solar cell 10. The heterojunction solar cell 10 is manufactured by the following manufacturing method.

[0125] A method for preparing a heterojunction solar cell 10 comprises the following steps:

[0126] (1) An N-type single crystal silicon wafer is used as the silicon substrate 101 . The thickness of the silicon substrate 101 is 180 μm, and the resistivity of the silicon substrate 101 is 5 Ω·cm.

[0127] The silicon substrate 101 was cleaned and textured, and then subjected to gettering using a high-temperature tubular phosphorus diffusion process. After gettering, the sheet resistance of the silicon substrate 101 was 40Ω / □. The PSG layer on the surface of the silicon substrate 101 after gettering was then removed using a tank-type wet acid solution. The surface of the silicon substrate 101 was textured using an alkaline solution, resulting in a pyramid-shaped surface light-trapping structure on both sides of the silicon substrate 101.

[0128] After the silicon substrate 101 is cleaned by RCA, the silicon substrate 101 is cleaned with HF solution to remove the surface oxide layer, and finally cleaned with deionized water and the surface is dried.

[0129] (2) Intrinsic amorphous silicon layers 201 and 202 are formed on both surfaces of the silicon substrate 101 by an RF-PECVD process. The RF-PECVD process uses a 13.56 MHz power supply, process gases include SiH4 and H2, a deposition temperature of 200°C, a deposition pressure of 2 mbar, and a thickness of 10 nm for the intrinsic amorphous silicon layers 201 and 202.

[0130] (3) An N-type doped layer 301 is deposited on the front intrinsic amorphous silicon layer 201 of the silicon substrate 101 using a VHF-CVD device. The N-type doped layer 301 is an N-type doped microcrystalline silicon layer. The VHF-CVD device power supply uses 40 MHz, and the VHF-CVD device process gases include SiH4 and H2. The deposition temperature is 200° C., the deposition pressure is 5 mbar, and the deposition thickness of the N-type doped layer 301 is 20 nm.

[0131] (4) A P-type doped layer 302 is deposited on the intrinsic amorphous silicon layer 202 on the back side of the silicon substrate 101 using a VHF-CVD device. The P-type doped layer 302 is a P-type doped microcrystalline silicon layer. The VHF-CVD device uses a 40 MHz power supply. The process gases used in the VHF-CVD device include SiH4, H2, and TMB. The deposition temperature is 200° C., the deposition pressure is 5 mbar, and the thickness of the P-type doped layer 302 is 30 nm.

[0132] (5) An ITO film was prepared on the P-type doped layer 302 using an RPD device as a back-side indium-containing TCO seed layer 402. The thickness of the back-side indium-containing TCO seed layer 402 was 20 nm. During deposition, the process temperature was 200°C, the process pressure was 0.8 Pa, and the process gases were Ar / O2 and Ar / H2. A SnO2 film was prepared on the back-side indium-containing TCO seed layer 402 using a magnetron sputtering device as a back-side indium-free TCO film 502. The thickness of the back-side indium-free TCO film 502 was 120 nm. During deposition, the power density was 8 KW / m 2 , the process gases are Ar / O2 and Ar / H, the process pressure is 0.8Pa, and the process temperature is 100℃.

[0133] (6) Using a PVD device, an ITO film is prepared on the N-type doped layer 301 as a front indium-containing TCO seed layer 401. The thickness of the front indium-containing TCO seed layer 401 is 50 nm. A SnO2 film is also prepared on the front indium-containing TCO seed layer 401 as a front indium-free TCO film 501. The thickness of the front indium-free TCO film 501 is 100 nm. During the PVD deposition, the power density is 8 KW / m 2, the process gases are Ar / O2 and Ar / H2, the process pressure is 0.8Pa, and the process temperature is 100℃.

[0134] (7) A back electrode 602 is prepared on the back indium-free TCO film 502 by laser transfer of silver-coated copper paste, and a front electrode 601 is prepared on the front indium-free TCO film 501.

[0135] The heterojunction solar cells 10 in Examples 1 and 2 were subjected to performance tests. The test results are shown in Table 1. As can be seen from Table 1, all performance parameters of the heterojunction solar cells 10 in Examples 1 and 2 of the present application meet the requirements.

[0136] Table 1

[0137] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0138] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0139] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a heterojunction solar cell, comprising the following steps: Cleaning and texturing the silicon substrate; Intrinsic amorphous silicon layers are respectively prepared on two surfaces of a silicon substrate; Preparing an N-type doped layer on the front intrinsic amorphous silicon layer of the silicon substrate; Preparing a P-type doped layer on the back intrinsic amorphous silicon layer of the silicon substrate; A back indium-containing transparent conductive oxide (TCO) seed layer is prepared on the P-type doped layer by using a reactive plasma deposition (RPD) device, and a back indium-free TCO film is prepared on the back indium-containing TCO seed layer by using a physical vapor deposition (PVD) device; Preparing a front indium-containing TCO seed layer on the N-type doped layer using a PVD device, and preparing a front indium-free TCO film on the front indium-containing TCO seed layer; and A back electrode is prepared on the back indium-free TCO film, and a front electrode is prepared on the front indium-free TCO film.

2. The method for preparing a heterojunction solar cell according to claim 1, wherein: The silicon substrate is an N-type single crystal silicon wafer, the thickness of the silicon substrate is 60 μm to 180 μm, and the resistivity is 0.2 Ω.cm to 5 Ω.cm.

3. The method for preparing a heterojunction solar cell according to claim 1 or 2, wherein: The cleaning and texturing process of the silicon substrate includes the following steps: The silicon substrate is treated with gettering equipment using a high-temperature tubular phosphorus diffusion or chain gettering equipment. The square resistance of the silicon substrate after gettering is 20Ω / □~40Ω / □; A trough-type wet acid solution is used to remove the phosphorus-silicon glass layer on the surface of the silicon substrate after the doping; Using an alkaline solution to texture the surface of a silicon substrate, so that both sides of the silicon substrate have a pyramid-shaped surface light-trapping structure; and The silicon substrate is cleaned to remove the surface oxide layer.

4. The method for preparing a heterojunction solar cell according to claim 3, wherein: Cleaning the silicon substrate to remove the surface oxide layer includes the following steps: RCA cleaning of silicon substrates, Cleaning the silicon substrate with a hydrofluoric acid solution to remove the surface oxide layer; and The silicon substrate was cleaned with deionized water and the surface of the silicon substrate was dried.

5. The method for preparing a heterojunction solar cell according to any one of claims 1 to 4, wherein: The steps of preparing intrinsic amorphous silicon layers on two surfaces of a silicon substrate include: The intrinsic amorphous silicon layer is deposited by radio frequency plasma enhanced chemical vapor deposition (RF-CVD) equipment, wherein the power frequency of the RF-PECVD equipment is 13.56MHz~40MHz, the process gas contains one or more of SiH4, H2, CO2, CH4, N2O, the deposition temperature is 160℃~220℃, and the deposition pressure is 0.2mbar~2mbar.

6. The method for preparing a heterojunction solar cell according to any one of claims 1 to 5, wherein: The thickness of the intrinsic amorphous silicon layer is 2nm-10nm.

7. The method for preparing a heterojunction solar cell according to any one of claims 1 to 6, wherein: The N-type doped layer is an N-type doped amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer; And / or, the thickness of the N-type doping layer is 5 nm to 20 nm.

8. The method for preparing a heterojunction solar cell according to any one of claims 1 to 7, wherein: The steps of preparing an N-type doped layer on the front intrinsic amorphous silicon layer of a silicon substrate include: An N-type doped layer is deposited on the front intrinsic amorphous silicon layer of a silicon substrate by RF-CVD equipment or very high frequency chemical vapor deposition (VHF-CVD) equipment; wherein the power frequency of the RF-CVD equipment or the VHF-CVD equipment is 13.56 MHz to 40 MHz, and the process gas contains one or more of SiH4, H2, CO2, CH4, N2O, and PH3; the deposition temperature is 160°C to 200°C, and the deposition pressure is 0.5 mbar to 5 mbar.

9. The method for preparing a heterojunction solar cell according to any one of claims 1 to 8, wherein: The P-type doped layer is a P-type doped amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer; And / or, the thickness of the P-type doping layer is 5 nm to 30 nm.

10. The method for preparing a heterojunction solar cell according to any one of claims 1 to 9, wherein: The steps of preparing a P-type doped layer on the back intrinsic amorphous silicon layer of a silicon substrate include: A P-type doped layer is deposited on the intrinsic amorphous silicon layer on the back side of a silicon substrate by using an RF-CVD device or a VHF-CVD device; wherein the power frequency of the RF-CVD device or the VHF-CVD device is 13.56 MHz to 40 MHz, the process gas comprises one or more of SiH4, H2, CO2, CH4, N2O, B2H6, and trimethylboron, the deposition temperature is 160°C to 200°C, and the deposition pressure is 0.5 mbar to 5 mbar.

11. The method for preparing a heterojunction solar cell according to any one of claims 1 to 10, wherein: The back indium-containing TCO seed layer is a tin-doped indium oxide film, a zirconium-titanium-calcium-doped indium oxide film, a tungsten-doped indium oxide film, a cerium-doped indium oxide film or a molybdenum-doped indium oxide film; And / or, the thickness of the back indium-containing TCO seed layer is 1 nm to 20 nm.

12. The method for preparing a heterojunction solar cell according to any one of claims 1 to 11, wherein: The RPD equipment is used to prepare the back indium-containing TCO seed layer on the P-type doped layer to meet the following conditions: the process temperature is 0-200°C, the process pressure is 0.3Pa-0.8Pa, and the process gas is Ar / O2 and Ar / H2 or H2O, among which Ar / O2 is a necessary process gas and the rest are non-essential process gases.

13. The method for preparing a heterojunction solar cell according to any one of claims 1 to 12, wherein: The thickness of the back indium-free TCO film is 80nm to 120nm; And / or, the back-side indium-free TCO film is a SnO2 film, a ZnO film, an aluminum-doped zinc oxide film, a gallium-doped zinc oxide film or an aluminum-gallium co-doped zinc oxide film.

14. The method for preparing a heterojunction solar cell according to any one of claims 1 to 13, wherein: The PVD device is a magnetron sputtering device. The PVD device is used to prepare the back-side indium-free TCO film on the back-side indium-containing TCO seed layer to meet the following conditions: the power density is 2KW / m 2 ~8KW / m 2 The process gases are Ar / O2 and Ar / H2 or H2O, among which Ar / O2 is a necessary process gas and the rest are non-essential process gases. The process pressure is 0.3Pa~0.8Pa and the process temperature is 0-100℃.

15. The method for preparing a heterojunction solar cell according to any one of claims 1 to 14, wherein: The front indium-containing TCO seed layer is a tin-doped indium oxide film, a zirconium-titanium-calcium-doped indium oxide film, a tungsten-doped indium oxide film, a cerium-doped indium oxide film or a molybdenum-doped indium oxide film; And / or, the thickness of the front indium-containing TCO seed layer is 5 nm to 50 nm.

16. The method for preparing a heterojunction solar cell according to any one of claims 1 to 15, wherein: The front indium-containing TCO seed layer is prepared on the N-type doped layer by using a PVD device, and the front indium-free TCO film is prepared on the front indium-containing TCO seed layer to meet the following conditions: the power density is 2KW / m 2 ~8KW / m 2 The process gases are Ar / O2 and Ar / H2 or H2O, among which Ar / O2 is a necessary process gas and the rest are non-essential process gases. The process pressure is 0.3Pa~0.8Pa and the process temperature is 0-100℃.

17. The method for preparing a heterojunction solar cell according to any one of claims 1 to 16, wherein: The thickness of the front indium-free TCO film is 40nm to 100nm; And / or, the front indium-free TCO film is a SnO2 film, a ZnO film, an AZO film, a GZO film or a GAZO film.

18. The method for preparing a heterojunction solar cell according to any one of claims 1 to 17, wherein: The preparation of the back electrode on the back indium-free TCO film and the preparation of the front electrode on the front indium-free TCO film are independently selected from one or more of the following methods: (1) preparing the back electrode or the front electrode by screen printing or laser transfer of one or more of low-temperature silver paste, low-temperature copper paste and silver-coated copper paste; (2) The back electrode or the front electrode is prepared by forming a patterned metal grid line by electroplating one or more alloys of Al, Ti, Ni, Co, Ag, Cu and Sn.

19. A heterojunction solar cell prepared by the preparation method according to any one of claims 1 to 18.

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