Semiconductor device, module member, and circuit board

Abstract

Provided is a semiconductor device capable of reducing the effects of noise on a capacitive part. The semiconductor device comprises: a semiconductor substrate that has one main surface and another main surface which is positioned at a distance from the one main surface in the thickness direction and faces the opposite side from the one main surface in the thickness direction, the semiconductor substrate having at least one trench provided in the one main surface, and a hole provided so as to extend in the thickness direction, be open in at least one of the main surface and the other surface, and have a larger surface area than one trench when viewed in the thickness direction; a capacitive part that is provided in at least the interior of a trench and has a dielectric layer and two electrode layers that sandwich the dielectric layer; and a filling part that is provided on the interior of the hole and contains a conductive material.

Description

Semiconductor device, module member, and circuit board

[0001] The present disclosure relates to a semiconductor device in which a capacitance section is provided inside a trench section.

[0002] As an example of a semiconductor device having a capacitance portion provided inside a trench portion, Patent Document 1 discloses a capacitor having a substrate having a recess on its surface, and a dielectric film and a conductive film provided inside the recess.

[0003] Patent No. 7052867

[0004] In a semiconductor device in which a capacitance section is provided inside a trench section, there is still room for improvement in terms of reducing the influence of noise on the capacitance section.

[0005] Therefore, an object of the present disclosure is to solve the above-mentioned problems and to provide a semiconductor device, a module member, and a circuit board that can reduce the influence of noise on a capacitance section.

[0006] In order to achieve the above-mentioned object, the semiconductor device according to the present disclosure comprises: a semiconductor substrate having one main surface and another main surface that is spaced apart from the one main surface in the thickness direction and faces the opposite side of the one main surface in the thickness direction, wherein at least one trench portion is provided in the one main surface and a hole portion that extends along the thickness direction, opens to at least one of the one main surface and the other main surface, and has a larger area than one of the trench portions when viewed along the thickness direction; a capacitance portion that is provided at least inside the trench portion and has a dielectric layer and two electrode layers sandwiching the dielectric layer; and a filling portion that is provided inside the hole portion and contains a conductive material.

[0007] In addition, in order to achieve the above-mentioned object, the module member according to the present disclosure comprises: the semiconductor device; an electronic component; and a mounting substrate on which the semiconductor device is provided, the mounting substrate having a front mounting surface on which the electronic component is mounted and a back mounting surface that is the back side of the front mounting surface.

[0008] In addition, in order to achieve the above object, the circuit board according to the present disclosure comprises: the module member; and a main board on whose surface the module member is mounted, and the semiconductor device is located between the mounting board and the main board.

[0009] According to the present disclosure, it is possible to provide a semiconductor device, a module member, and a circuit board that can reduce the influence of noise on a capacitance section.

[0010] 1A and 1B are plan views of semiconductor devices according to embodiments of the present disclosure; Schematic cross-sectional views illustrating cross sections II-II in FIG. 1A and 1B are equivalent circuit diagrams of semiconductor devices according to embodiments of the present disclosure; Schematic cross-sectional views illustrating a method for manufacturing a semiconductor device ... modified example of a semiconductor device according to embodiments of the present disclosure; Schematic cross-sectional views of a modified example of a semiconductor device according to embodiments of the present disclosure; Schematic cross-sectional views of a module member according to embodiments of the present disclosure; Schematic cross-sectional views of a modified example of a module member according to embodiments of the present disclosure; Schematic cross-sectional views of a circuit board according to embodiments of the present disclosure;

[0011] An example of the present disclosure will now be described with reference to the accompanying drawings. Note that the following description is merely illustrative in nature and is not intended to limit the present disclosure, its applications, or its uses. The drawings are schematic, and the ratios of dimensions and the like do not necessarily correspond to reality. Furthermore, in the following description, terms indicating specific directions or positions (e.g., terms including "upper," "lower," "right," "left," "front," and "rear") are used as necessary. However, the use of terms indicating specific directions or positions is intended to facilitate understanding of the present disclosure with reference to the drawings, and the meanings of these terms do not limit the technical scope of the present disclosure.

[0012] <Semiconductor Device> Fig. 1 is a plan view of a semiconductor device according to an embodiment of the present disclosure, and Fig. 2 is a schematic cross-sectional view showing a cross section taken along line II-II of Fig. 1.

[0013] As shown in FIGS. 1 and 2 , the semiconductor device 10 includes a semiconductor substrate 20 , a capacitance portion 30 , a filling portion 40 , a first insulating layer 53 , a second insulating layer 54 , and an external terminal 51 .

[0014] The semiconductor substrate 20 is, for example, a silicon (Si) substrate, and is formed from insulating, high-resistivity Si.

[0015] The semiconductor substrate 20 has one main surface 20A and the other main surface 20B. The one main surface 20A and the other main surface 20B are spaced apart from each other in the thickness direction 101 of the semiconductor substrate 20. The one main surface 20A and the other main surface 20B face in opposite directions from each other in the thickness direction 101.

[0016] The semiconductor substrate 20 has a recess 20E and four trench portions 20C.

[0017] The recess 20E is filled with a first electrode layer 321 of the capacitance section 30, which will be described later. The first electrode layer 321 forms a part of one main surface 20A of the semiconductor substrate 20. In this embodiment, the first electrode layer 321 is a part of the capacitance section 30 and also a part of the semiconductor substrate 20.

[0018] 2, one recess 20E is shown, but the number of recesses 20E included in the semiconductor substrate 20 is not limited to one. The semiconductor substrate 20 may have a plurality of recesses 20E.

[0019] The four trench portions 20C are provided in a portion of the first electrode layer 321 that constitutes part of the one main surface 20A, and are recessed in the thickness direction 101. In other words, each of the four trench portions 20C is a recess provided in the one main surface 20A.

[0020] The trench portion 20C may have any shape. For example, the trench portion 20C may be circular or rectangular when viewed along the thickness direction 101, or may be a narrow groove that extends in a curved or straight line. This groove may branch into multiple parts. Each of the four trench portions 20C may have the same shape or different shapes.

[0021] 2, four trench portions 20C are shown, but the number of trench portions 20C included in the semiconductor substrate 20 is not limited to four. The semiconductor substrate 20 only needs to include at least one trench portion 20C.

[0022] In FIG. 2, the recess 20E and the trench portion 20C are provided on one main surface 20A, but the recess 20E and the trench portion 20C may be provided on the other main surface 20B, or may be provided on both the one main surface 20A and the other main surface 20B.

[0023] The semiconductor substrate 20 has a hole 20D. The hole 20D penetrates the semiconductor substrate 20 in the thickness direction 101. That is, the hole 20D extends in the thickness direction 101 and opens to one main surface 20A and the other main surface 20B. The hole 20D has a side surface 20Da. The hole 20D is circular when viewed along the thickness direction 101. That is, the hole 20D is cylindrical.

[0024] The hole 20D does not have to penetrate the semiconductor substrate 20 in the thickness direction 101. That is, the hole 20D may be open to only one of the first main surface 20A and the second main surface 20B. For example, the hole 20D may be a recess provided in the first main surface 20A, as in the modified example shown in FIG. 13 (described later). Alternatively, the hole 20D may be a recess provided in the second main surface 20B.

[0025] The shape of the hole 20D is arbitrary, similar to the shape of the trench 20C. For example, the hole 20D may be circular or rectangular when viewed along the thickness direction 101, or may be a narrow groove that extends in a curved or straight line. This groove may branch into multiple parts.

[0026] When viewed along the thickness direction 101, the hole portion 20D has a larger area than each of the four trench portions 20C. In other words, when viewed along the thickness direction 101, the hole portion 20D has a larger area than one trench portion 20C.

[0027] The width of the hole 20D is greater than the width of each of the four trench portions 20C. Here, the width of the hole 20D is defined, for example, as follows: When the hole 20D is circular as viewed along the thickness direction 101, the width of the hole 20D is the diameter of the circle. When the hole 20D is rectangular as viewed along the thickness direction 101, the width of the hole 20D is the length of the short side of the rectangle. When the hole 20D is a narrow groove as viewed along the thickness direction 101, the width of the hole 20D is the direction perpendicular to the direction in which the groove extends. The above definitions also apply to the width of the trench portion 20C.

[0028] The width of the hole 20D is at least twice the width of each of the four trenches 20C (see FIG. 2). Preferably, the width of the hole 20D is at least five times the width of each of the four trenches 20C. More preferably, the width of the hole 20D is at least ten times the width of each of the four trenches 20C (see FIG. 11).

[0029] 2, one hole 20D is shown, but the number of holes 20D included in the semiconductor substrate 20 is not limited to one. The semiconductor substrate 20 may have a plurality of holes 20D.

[0030] The capacitance section 30 is provided inside the recess 20E, inside the trench section 20C, and on the one main surface 20A. That is, the capacitance section 30 is provided at least inside the trench section 20C.

[0031] The capacitance section 30 has a dielectric layer and an electrode layer. In this embodiment, the capacitance section 30 includes two dielectric layers (a first dielectric layer 311 and a second dielectric layer 312) and three electrode layers (a first electrode layer 321, a second electrode layer 322, and a third electrode layer 323).

[0032] The dielectric layer includes a dielectric. In this embodiment, the dielectric layer includes silicon dioxide (SiO ２ ) and silicon nitride (Si ３ N ４ ) and hafnium oxide (HfO ２ The first dielectric layer 311 and the second dielectric layer 312 may be made of the same material or different materials.

[0033] The electrode layers include a conductor. In this embodiment, the electrode layers are made of a conductor such as a metal such as copper, low-resistivity silicon (Si) such as conductive n-type Si or p-type Si, or polysilicon (Poly-Si). The first electrode layer 321, the second electrode layer 322, and the third electrode layer 323 may be made of the same material or different materials.

[0034] The first electrode layer 321 is provided inside the recess 20E. In this embodiment, the first electrode layer 321 is made of low-resistivity silicon (Si). The first electrode layer 321 may be electrically connected to the other main surface 20B. As described above, the first electrode layer 321 has four trench portions 20C in a portion that constitutes part of the one main surface 20A.

[0035] The first dielectric layer 311 is stacked on the first electrode layer 321 and the semiconductor substrate 20, both inside and outside the four trench portions 20C. The first dielectric layer 311 is stacked on the first electrode layer 321 along the trench portions 20C, inside the four trench portions 20C. The first dielectric layer 311 is stacked on the first electrode layer 321 and one main surface 20A of the semiconductor substrate 20, outside the four trench portions 20C.

[0036] The second electrode layer 322 is stacked on the first dielectric layer 311 across the inside and outside of the four trench portions 20C. The second electrode layer 322 is stacked on the first dielectric layer 311 inside the four trench portions 20C and along the trench portions 20C.

[0037] The second dielectric layer 312 is stacked on the second electrode layer 322 across the inside and outside of the four trench portions 20C. The second dielectric layer 312 is stacked on the second electrode layer 322 inside the four trench portions 20C and along the trench portions 20C.

[0038] The third electrode layer 323 is stacked on the second dielectric layer 312 across the inside and outside of the four trench portions 20C. The third electrode layer 323 is stacked on the second dielectric layer 312 so as to fill spaces not shown in the first dielectric layer 311, the second electrode layer 322, and the second dielectric layer 312 inside the four trench portions 20C.

[0039] As a result of the dielectric layers and electrode layers being stacked as described above, the first dielectric layer 311 is sandwiched between the first electrode layer 321 and the second electrode layer 322, and the second dielectric layer 312 is sandwiched between the second electrode layer 322 and the third electrode layer 323. In other words, the capacitance unit 30 has at least a dielectric layer and two electrode layers sandwiching the dielectric layer. In this embodiment, the capacitance unit 30 has two pairs of a dielectric layer and two electrode layers sandwiching the dielectric layer. One of the two pairs is composed of the first dielectric layer 311 and the first electrode layer 321 and the second electrode layer 322 sandwiching the first dielectric layer 311. The other of the two pairs is composed of the second dielectric layer 312 and the second electrode layer 322 and the third electrode layer 323 sandwiching the second dielectric layer 312.

[0040] The capacitance section 30 may have only one set of a dielectric layer and two electrode layers sandwiching the dielectric layer, or may have three or more sets.

[0041] The filling portion 40 is provided inside the hole 20D. The filling portion 40 extends from one end to the other end in the thickness direction 101 of the hole 20D. The upper surface 40A of the filling portion 40 is a portion of the filling portion 40 located at one end of the hole 20D in the thickness direction 101. The upper surface 40A of the filling portion 40 constitutes a part of one main surface 20A of the semiconductor substrate 20. The lower surface 40B of the filling portion 40 is a portion of the filling portion 40 located at the other end of the hole 20D in the thickness direction 101. The lower surface 40B of the filling portion 40 constitutes a part of the other main surface 20B of the semiconductor substrate 20.

[0042] The filling portion 40 contains a conductive material. In this embodiment, the filling portion 40 is configured with a conductive layer 42 made of copper as the conductive material. Note that in this embodiment, the filling portion 40 is configured only with the conductive material, but the filling portion 40 may also contain a material other than the conductive material. An example in which the filling portion 40 contains a material other than the conductive material will be described later.

[0043] The first insulating layer 53 and the second insulating layer 54 are made of an insulator. The first insulating layer 53 and the second insulating layer 54 may be made of either an inorganic or organic material as long as they have high insulating properties. The first insulating layer 53 is stacked so as to cover a portion of the first electrode layer 321, the second electrode layer 322, the third electrode layer 323, the first dielectric layer 311, and the second dielectric layer 312 that are exposed on the one main surface 20A of the semiconductor substrate 20. The second insulating layer 54 is stacked so as to cover a portion of the one main surface 20A of the semiconductor substrate 20 and a portion of the second dielectric layer 312, the second electrode layer 322, and the third electrode layer 323 that are exposed on the one main surface 20A of the semiconductor substrate 20.

[0044] The external terminals 51 are provided on at least one of the first principal surface 20A and the second principal surface 20B. The external terminals 51 are made of a conductive material such as nickel (Ni) or gold (Au). In this embodiment, the external terminals 51 have a multilayer structure of copper (Cu), nickel, and gold. In this embodiment, the external terminals 51 include a first external terminal 511, a second external terminal 512, and a third external terminal 513. In this embodiment, the first external terminal 511, the second external terminal 512, and the third external terminal 513 are all provided on the first principal surface 20A side of the semiconductor substrate 20. The first external terminal 511, the second external terminal 512, and the third external terminal 513 are insulated from each other by a second insulating layer 54. In this embodiment, the first external terminal 511, the second external terminal 512, and the third external terminal 513 are made of the same material, but may be made of different materials.

[0045] The first external terminal 511 is laminated on the first electrode layer 321, the third electrode layer 323, and the first insulating layer 53. As a result, the first external terminal 511 is in contact with the first electrode layer 321 and the third electrode layer 323. In other words, the first electrode layer 321 and the third electrode layer 323 are electrically connected to each other via the first external terminal 511.

[0046] On the other hand, a first insulating layer 53 is provided between the first external terminal 511 and the first dielectric layer 311, the second electrode layer 322, and the second dielectric layer 312. As a result, the first external terminal 511 is insulated from the first dielectric layer 311, the second electrode layer 322, and the second dielectric layer 312 by the first insulating layer 53.

[0047] The second external terminal 512 is laminated on the second electrode layer 322. As a result, the second external terminal 512 and the second electrode layer 322 are in contact with each other and electrically connected.

[0048] The third external terminal 513 is laminated on the upper surface 40A of the filling portion 40. This allows the third external terminal 513 and the filling portion 40 to come into contact with each other and be electrically connected. The third external terminal 513 is an example of an external terminal.

[0049] Fig. 3 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 10 is configured as described above, thereby forming a circuit as shown in Fig. 3. Note that the equivalent circuit of the semiconductor device 10 is not limited to the circuit as shown in Fig. 3. For example, a resistor R and capacitors C1 and C2 may be connected.

[0050] 3 , a capacitor C1 is formed by a first dielectric layer 311 and a first electrode layer 321 and a second electrode layer 322 sandwiching the first dielectric layer 311. A capacitor C2 is formed by a second dielectric layer 312 and a second electrode layer 322 and a third electrode layer 323 sandwiching the second dielectric layer 312. One electrode of the capacitor C1 (first electrode layer 321) and one electrode of the capacitor C2 (third electrode layer 323) are connected to a first external terminal 511. The other electrodes of the capacitors C1 and C2 (second electrode layer 322) are connected to a second external terminal 512.

[0051] The filling portion 40 constitutes a resistor R. One end of the resistor R (the upper surface 40A of the filling portion 40) is connected to a third external terminal 513. In this embodiment, the other end of the resistor R (the lower surface 40B of the filling portion 40) is not connected to an external terminal, but may be connected to an external terminal. An example in which the lower surface 40B of the filling portion 40 is connected to an external terminal will be described later.

[0052] The semiconductor device 10 described above has the following dimensions, for example. Specifically, the length in the thickness direction 101 is 0.15 mm, the length in the width direction 103 is 0.6 mm, and the length in the depth direction, which is a direction perpendicular to the thickness direction 101 and the width direction 103, is 0.3 mm. The depth (length in the thickness direction 101) of each of the first trench portion 20Ca and the second trench portion 20Cb is 30 μm. The thickness of the electrode layers (first electrode layer 321, second electrode layer 322, and third electrode layer 323) is 1000 nm. Note that when the electrode layers are made of titanium nitride (TiN), the thickness of the electrode layers is 20 nm. The thickness of the dielectric layers (first dielectric layer 311 and second dielectric layer 312) is 10 nm.

[0053] <Method for manufacturing semiconductor device> A method for manufacturing the semiconductor device 10 according to an embodiment of the present disclosure will be described below with reference to Figures 4 to 10 and Figure 2. Figures 4 to 10 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to an embodiment of the present disclosure.

[0054] The semiconductor device 10 is manufactured by singulating a laminate into a plurality of pieces. The laminate is formed by integrating a plurality of semiconductor devices 10 in an arranged state. For ease of explanation, only a portion of the laminate corresponding to one semiconductor device 10 is shown in FIGS. 4 to 10. The manufacturing method for the semiconductor device 10 according to this embodiment includes a hole forming step, a filling portion forming step, a capacitance portion forming step (an electrode layer forming step, a dielectric layer forming step, and a trench portion forming step), a first insulating layer forming step, a second insulating layer forming step, an external terminal forming step, and a singulation step.

[0055] (Hole Forming Step) First, the hole forming step is performed. In the hole forming step, as shown in FIG. 4 , a hole 20D penetrating the semiconductor substrate 20 in the thickness direction 101 is formed in the semiconductor substrate 20. For example, a hard mask is formed on the semiconductor substrate 20, patterning is performed on the hard mask corresponding to the hole 20D, and deep silicon etching is performed, thereby forming the hole 20D in the semiconductor substrate 20. After deep silicon etching is performed, the hard mask is removed.

[0056] (Filling Portion Forming Process) Next, the filling portion forming process is performed. In the filling portion forming process, as shown in FIG. 5, a conductive paste is filled into the hole 20D. This paste corresponds to the conductive layer 42 of the filling portion 40. For example, the filling portion 40 is formed by forming a seed, performing via-filling plating, removing the seed, and planarizing. Note that the filling portion 40 may be filled by a method other than the above-described formation method. For example, a conductive material such as copper (Cu) or aluminum (Al) may be filled as the filling portion 40 by a method such as sputtering, wet plating, or paste.

[0057] (Capacitor Portion Forming Step) Next, the capacitor portion forming step is carried out. The capacitor portion forming step is divided into an electrode layer forming step, a dielectric layer forming step, and a trench portion forming step.

[0058] In the capacitance portion forming step, an electrode layer forming step and a dielectric layer forming step are alternately performed, and the trench portion forming step is performed after the first electrode layer forming step and before the first dielectric layer forming step.

[0059] 6, in the first electrode layer formation step, impurities are doped into the semiconductor substrate 20 as a high-resistance portion formed of high-resistance Si. As a result, a recess 20E is formed in the semiconductor substrate 20 as a high-resistance portion, and a first electrode layer 321 as a low-resistance portion is formed in the recess 20E. The first electrode layer 321 is formed, for example, by forming a patterned resist at the position of the recess 20E, etching the impurity-doped silicon, and removing the resist.

[0060] In the trench portion forming step, four trench portions 20C are formed in parts of one main surface 20A of the first electrode layer 321. The trench portions 20C are formed, for example, by patterning a hard mask and deep silicon etching, similar to the hole portions 20D.

[0061] Next, a dielectric layer forming process and an electrode layer forming process are alternately performed. As a result, dielectric layers and electrode layers are alternately stacked (deposited) on one major surface 20A of the semiconductor substrate 20 and on the surface constituting the trench portion 20C. In detail, as shown in FIG. 7 , a first dielectric layer 311 is formed on the semiconductor substrate 20, the filling portion 40, and the first electrode layer 321. A second electrode layer 322 is formed on the first dielectric layer 311. A second dielectric layer 312 is formed on the second electrode layer 322. A third electrode layer 323 is formed on the second dielectric layer 312. As a result, in the capacitance portion forming process, a capacitance portion having a dielectric layer and two electrode layers sandwiching the dielectric layer is formed in at least the trench portion 20C of the semiconductor substrate 20.

[0062] In the dielectric layer forming process and the electrode layer forming process, after the dielectric layers 311, 312 and the electrode layers 322, 323 are formed, photolithography and etching are performed on the dielectric layers 311, 312 and the electrode layers 322, 323. As a result, parts of the dielectric layers 311, 312 and the electrode layers 322, 323 are removed, as shown in FIG.

[0063] In this embodiment, the trench portion forming process is defined as part of the capacitance portion forming process. However, the trench portion forming process may be defined separately from the capacitance portion forming process. In this case, the capacitance portion forming process is divided into an electrode layer forming process and a dielectric layer forming process. Then, after the electrode layer forming process of the first capacitance portion forming process is performed, the trench portion forming process is performed, and then the remaining steps of the capacitance portion forming process are performed.

[0064] (First Insulating Layer Forming Process) Next, the first insulating layer forming process is performed. In the first insulating layer forming process, a first insulating layer 53 is laminated as shown in Fig. 9. In detail, the first insulating layer 53 is deposited on the upper surface (the surface on the one main surface 20A side) of Fig. 8, and is patterned by photolithography and dry etching into a position corresponding to the first insulating layer 53 in Fig. 9.

[0065] (Second Insulating Layer Forming Step) Next, the second insulating layer forming step is performed. In the second insulating layer forming step, a second insulating layer 54 is laminated as shown in Fig. 10. In detail, the second insulating layer 54 is deposited on the upper surface (the surface on the one main surface 20A side) of Fig. 9 and patterned by photolithography and dry etching into a position corresponding to the second insulating layer 54 in Fig. 10. Note that the second insulating layer forming step may be performed before the first insulating layer forming step or may be performed in parallel with the first insulating layer forming step.

[0066] The first insulating layer 53 and the second insulating layer 54 may be formed by known means other than deposition, such as CVD (Chemical Vapor Deposition), for example, spin coating or film lamination. If necessary, a protective layer, which is an insulating layer, may be provided on the second insulating layer 54. For example, the protective layer is made of an organic resin such as epoxy, polyimide, or acrylic.

[0067] (External Terminal Forming Process) Next, the external terminal forming process is performed. In the external terminal forming process, as shown in FIG. 2, external terminals 51 (first external terminal 511, second external terminal 512, and third external terminal 513) are formed. In detail, conductive layers serving as the external terminals 51 are formed at predetermined positions (positions shown in FIG. 2) on the upper surface (surface on the one main surface 20A side) of FIG. 10 by known means such as metal sputtering, electroless plating, or paste. Note that the external terminals 51 may be composed of multiple conductive layers. By forming the external terminals 51 from multiple conductive layers, the external terminals 51 have electromigration resistance and the barrier properties and solder wettability of the external terminals 51 are improved.

[0068] (Singulation Process) Next, the singulation process is performed. In the singulation process, the thickness of the semiconductor device 10 is adjusted, and the stack in which the plurality of semiconductor devices 10 are arranged is cut into the plurality of semiconductor devices 10.

[0069] According to this embodiment, the filling portion 40 containing a conductive material can function as a shield against noise. This allows the filling portion 40 to reduce noise traveling from the outside of the capacitance portion 30 toward the capacitance portion 30 via the filling portion 40.

[0070] By using the filling portion 40 as wiring in the semiconductor device 10, it is possible to reduce the amount of wiring routed around the semiconductor device 10. This makes it possible to reduce the parasitic capacitance occurring in the semiconductor device 10.

[0071] In the capacitor disclosed in Patent Document 1, since a dielectric film and a conductive film are provided on the front surface side of the substrate, it is not necessarily easy to handle signals from the back surface of the substrate. However, according to this embodiment, the hole 20D can be opened on both the one main surface 20A and the other main surface 20B, in other words, the hole 20D can penetrate the semiconductor substrate 20 in the thickness direction 101. In this case, even if the capacitance portion 30 is provided on the one main surface 20A side of the semiconductor substrate 20, it is possible to easily handle signals from the other main surface 20B.

[0072] According to this embodiment, the area of ​​the hole 20D is larger than the area of ​​one trench 20C when viewed along the thickness direction 101. This reduces manufacturing variations in the hole 20D, making it easier to fill the hole 20D with the filling portion 40.

[0073] The following describes modified examples of this embodiment, the configuration of the module member 70, and the circuit board 1. In the following description, the same reference numerals are used to designate components that have been previously described, and descriptions of those components will be omitted in principle, and will be described only when necessary.

[0074] <First Modification of Semiconductor Device> FIG. 11 is a schematic cross-sectional view of a first modification of the semiconductor device according to the embodiment of the present disclosure.

[0075] 11 , the semiconductor device 10 may include an external terminal 51 on the other main surface 20B. The semiconductor device 10 shown in FIG. 11 includes a fourth external terminal 514 as the external terminal 51 on the other main surface 20B. The semiconductor device 10 may also include a dummy terminal 52 on at least one of the one main surface 20A and the other main surface 20B. The semiconductor device 10 shown in FIG. 11 includes the dummy terminal 52 on the other main surface 20B.

[0076] The fourth external terminal 514 and the dummy terminal 52, like the first external terminal 511, are made of a conductive material such as nickel (Ni) or gold (Au).

[0077] The fourth external terminal 514 is laminated on the lower surface 40B of the filling portion 40. As a result, the fourth external terminal 514 and the filling portion 40 are in contact with each other and electrically connected.

[0078] The dummy terminal 52 is stacked on the other main surface 20B of the semiconductor substrate 20. The dummy terminal 52 is not electrically connected to other conductive parts of the semiconductor device 10. The other conductive parts are, for example, the first electrode layer 321, the second electrode layer 322, the third electrode layer 323, the filling portion 40, and the external terminal 51.

[0079] According to the first modification, when the semiconductor device 10 is mounted on a substrate via a paste such as solder, the mounting can be easily performed by applying the paste to the external terminals 51 .

[0080] According to the first modification, when mounting the semiconductor device 10 on a substrate via a paste such as solder, the mounting can be performed by applying the paste to the dummy terminals 52. In other words, according to the first modification, when mounting, more paste can be applied than in a semiconductor device that does not have the dummy terminals 52. As a result, the strength of the mounting can be increased.

[0081] <Second Modification of Semiconductor Device> FIG. 12 is a schematic cross-sectional view of a second modification of the semiconductor device according to the embodiment of the present disclosure.

[0082] 12, the filling portion 40 may include a material other than a conductive material. The filling portion 40 shown in FIG. 12 includes a buried layer 41, a barrier layer 43, and an isolation layer 44 in addition to a conductive layer 42.

[0083] The buried layer 41 is made of a resin such as epoxy. The barrier layer 43 includes a conductive material such as titanium nitride (TiN) or nickel (Ni). The isolation layer 44 is made of silicon dioxide (SiO ２ ) and silicon nitride (Si ３ N ４ 12, the filling portion 40 of the semiconductor device 10 includes a conductive layer 42 and a barrier layer 43, which are parts of the filling portion 40, and does not include a conductive material in the buried layer 41 and the isolation layer 44, which are other parts of the filling portion 40.

[0084] The buried layer 41, the conductive layer 42, the barrier layer 43, and the isolation layer 44 each penetrate the hole 20D in the thickness direction 101. In other words, the buried layer 41, the conductive layer 42, the barrier layer 43, and the isolation layer 44 each extend from one end to the other end of the hole 20D in the thickness direction 101.

[0085] When viewed along the thickness direction 101, the conductive layer 42 surrounds the buried layer 41. When viewed along the thickness direction 101, the barrier layer 43 surrounds the conductive layer 42. When viewed along the thickness direction 101, the isolation layer 44 surrounds the barrier layer 43. The outer peripheral surface of the isolation layer 44 is in contact with the side surface 20Da of the hole 20D.

[0086] The filling portion 40 may not include at least one of the buried layer 41 and the barrier layer 43. Furthermore, a magnetic layer 45 (described later) may be provided between any two adjacent layers among the buried layer 41, the conductive layer 42, the barrier layer 43, and the isolation layer 44.

[0087] According to the second modification, the isolation layer 44 is made of an insulating material. Therefore, the isolation layer 44 can block unintended propagation of an electrical signal from the conductive layer 42 to other parts such as the capacitive section 30 via the semiconductor substrate 20.

[0088] For example, there is a risk that the electrical resistance of the conductive layer 42 may change due to diffusion of the conductive material (e.g., copper) contained in the conductive layer 42. According to the second modification, the barrier layer 43 can suppress the diffusion of the conductive layer 42. Therefore, the change in the electrical resistance of the conductive layer 42 can be reduced.

[0089] According to the second modification, the barrier layer 43 contains a conductive material, and therefore, the barrier layer 43 can function as a seed layer. In addition, an electrical signal can be transmitted through the barrier layer 43.

[0090] According to the second modification, the filling portion 40 includes the buried layer 41, which can suppress unwanted voids, foreign matter contamination, and the occurrence of unevenness in the exposed portions of the filling portion 40 on the one main surface 20A and the other main surface 20B. In other words, the filling portion 40 includes the buried layer 41, which eliminates the need to fill the entire hole 20D with the conductive layer 42. This reduces the manufacturing cost of the semiconductor device 10.

[0091] <Third Modification of Semiconductor Device> FIG. 13 is a schematic cross-sectional view of a third modification of the semiconductor device according to the embodiment of the present disclosure.

[0092] As shown in FIG. 13 , the hole 20D may be open to one of the first main surface 20A and the other main surface 20B and have a bottom on the other of the first main surface 20A and the other main surface 20B. In Modification 3 shown in FIG. 13 , the hole 20D is open to the first main surface 20A and has a bottom on the other of the first main surface 20A and the other main surface 20B. The hole 20D has a side surface 20Da and a bottom surface 20Db. The side surface 20Da extends from one of the first main surface 20A and the other main surface 20B to the other. In Modification 3 shown in FIG. 13 , the side surface 20Da extends from the first main surface 20A to the other main surface 20B. The bottom surface 20Db is connected to the end of the side surface 20Da on the other side of the first main surface 20A and the other main surface 20B. 13 , the bottom surface 20Db is connected to the end of the side surface 20Da on the other main surface 20B side. In the third modification, the boundary 20Dc between the side surface 20Da and the bottom surface 20Db is a curved surface. In other words, the boundary 20Dc between the side surface 20Da and the bottom surface 20Db does not have a corner.

[0093] The hole 20D may be open to the other main surface 20B and have a bottom on the one main surface 20A side.

[0094] The hole 20D is deeper than the trench 20C. The length L1 of the hole 20D in the thickness direction 101 is longer than the length L2 of the trench 20C in the thickness direction 101.

[0095] According to Modification 3, hole 20D has a bottom. That is, hole 20D does not penetrate in thickness direction 101. Therefore, according to Modification 3, the aspect ratio of hole 20D can be made smaller than in a configuration in which hole 20D penetrates in thickness direction 101. As a result, hole 20D can be easily filled with a conductive material.

[0096] If boundary 20Dc between side surface 20Da and bottom surface 20Db of hole 20D is not a curved surface but is bent and has a corner, there is a risk that the conductive material will not be filled in the corner when filling hole 20D with conductive material, and a void will be created. According to Modification 3, boundary 20Dc between side surface 20Da and bottom surface 20Db of hole 20D is a curved surface, so that it is possible to eliminate or reduce the void when filling hole 20D with conductive material.

[0097] According to variant example 3, noise traveling from outside the capacitance section 30 to the capacitance section 30 via the filling section 40 can be reliably suppressed compared to a configuration in which the length L1 of the hole section 20D in the thickness direction 101 is less than or equal to the length L2 of the trench section 20C in the thickness direction 101.

[0098] According to the third modification, when the other main surface 20B side of the semiconductor substrate 20 is removed, the hole 20D can be opened to the other main surface 20B without opening the trench portion to the other main surface 20B. Since the trench portion 20C does not open to the other main surface 20B, it is possible to prevent the characteristics of the capacitance portion 30 (in other words, the capacitance) from being impaired.

[0099] <Variation 4 of Semiconductor Device> FIG. 14 is a schematic cross-sectional view of a variation of the semiconductor device according to the embodiment of the present disclosure.

[0100] 14, the filling portion 40 may contain a magnetic material. The filling portion 40 shown in FIG.

[0101] 14 , the filling portion 40 of the semiconductor device 10 of the fourth modification example shown in FIG. 14 includes a magnetic layer 45 that is a part of the filling portion 40 and does not include a conductive material in the conductive layer 42 other than the part.

[0102] The magnetic material is, for example, spherical metal magnetic powder. The metal magnetic powder has a maximum composition element of iron (Fe) and a median diameter D50 of 5 μm or less. The metal magnetic powder is a composite material with organic resins such as epoxy, phenol, acrylic, and polyimide. Because the metal powder is a composite material, insulation between the powder particles can be achieved, allowing the semiconductor device 10 to be provided as an inductor component with low loss.

[0103] The conductive layer 42 and the magnetic layer 45 each penetrate the hole 20D in the thickness direction 101. In other words, the conductive layer 42 and the magnetic layer 45 each extend from one end to the other end of the hole 20D in the thickness direction 101.

[0104] When viewed along the thickness direction 101, the magnetic layer 45 surrounds the conductive layer 42. In other words, the conductive layer 42 penetrates the magnetic layer 45 in the thickness direction 101. The outer peripheral surface of the magnetic layer 45 is in contact with the side surface 20Da of the hole 20D.

[0105] The conductive layer 42 does not have to penetrate the magnetic layer 45 in the thickness direction 101. For example, the conductive layer 42 may be provided on the capacitance section 30 side of the hole 20D and the magnetic layer 45 may be provided on the opposite side of the hole 20D from the capacitance section 30, so that the conductive layer 42 and the magnetic layer 45 are arranged side by side when viewed along the thickness direction 101.

[0106] According to the fourth modification, the magnetic layer 45 can function as a magnetic shield, and the filling portion 40 can function as an inductor.

[0107] According to the fourth modification, the area of ​​the hole 20D is larger than the area of ​​one trench 20C when viewed along the thickness direction 101. Therefore, according to the fourth modification, when the filling portion 40 functions as an inductor, the Q value of the inductor can be increased compared to a configuration in which the area of ​​the hole 20D is equal to or smaller than the area of ​​one trench 20C when viewed along the thickness direction 101.

[0108] <Module Component> FIG. 15 is a schematic cross-sectional view of a module component according to an embodiment of the present disclosure.

[0109] 15, a module member 70 includes a semiconductor device 10 according to any one of the above-described embodiments and modifications, an electronic component 71, and a mounting substrate 72 on which the semiconductor device 10 and the electronic component 71 are provided. When viewed along the thickness direction 101, the area of ​​the mounting substrate 72 in FIG. 15 and in FIGS. 16 to 18 described below is larger than the area of ​​the semiconductor device 10, but may be equal to or smaller than the area of ​​the semiconductor device 10.

[0110] The electronic component 71 is mounted on at least one of the front mounting surface 72A and the back mounting surface 72B of the mounting substrate 72. In the configuration shown in Fig. 15, the electronic component 71 is mounted on the front mounting surface 72A. The electronic component 71 is an integrated circuit (IC), but is not limited to an IC. For example, the electronic component 71 may be a resistor, an inductor, or the like.

[0111] The mounting substrate 72 shown in FIG. 15 is an interposer substrate. The mounting substrate 72 is made of silicon, but may be made of a material other than silicon (e.g., ceramic). The interposer substrate is formed by laminating an organic resin such as a buildup film on a base substrate while forming wiring. At this time, parts of the buildup film can be opened and components such as electronic components 71 and semiconductor devices 10 can be embedded. Finally, the buildup film and the embedded components can be ground to have the same thickness. The mounting substrate 72 (interposer substrate) shown in FIG. 15 contains glass fiber. The inclusion of glass fiber increases the strength of the mounting substrate 72, thereby suppressing warping of the substrate.

[0112] The mounting substrate 72 shown in FIG. 15 is not limited to an interposer substrate, but may be, for example, a substrate made of glass epoxy or the like (see FIG. 16) or a substrate having a core material 721 (see FIG. 17).

[0113] The mounting substrate 72 has a front mounting surface 72A and a rear mounting surface 72B that is the rear surface of the front mounting surface 72A. The front mounting surface 72A and the rear mounting surface 72B are spaced apart from each other in the thickness direction 101 of the mounting substrate 72. The front mounting surface 72A and the rear mounting surface 72B face opposite each other in the thickness direction 101.

[0114] The semiconductor device 10 is embedded in the mounting substrate 72. In the configuration shown in FIG. 15 , a portion of the semiconductor device 10 is exposed to the outside of the mounting substrate 72 on the back mounting surface 72B, and the portion of the semiconductor device 10 exposed to the outside forms part of the back mounting surface 72B. Note that the semiconductor device 10 may be completely embedded in the mounting substrate 72 so as not to be exposed to the outside of the mounting substrate 72. Alternatively, the semiconductor device 10 may be only partially embedded in the mounting substrate 72 so that a portion of the semiconductor device 10 protrudes from the outside of the mounting substrate 72. As described above, at least a portion of the semiconductor device 10 is provided inside the mounting substrate 72.

[0115] When viewed along the thickness direction 101, at least a portion of the semiconductor device 10 and at least a portion of the electronic component 71 are positioned to overlap each other. In the configuration shown in Fig. 15 and the configurations shown in Figs. 16 to 18 described below, when viewed along the thickness direction 101, the entire semiconductor device 10 is positioned to overlap with the electronic component 71.

[0116] The mounting substrate 72 includes an external electrode 725 and a through electrode 726. The external electrode 725 and the through electrode 726 are made of a conductive material such as copper.

[0117] The external electrodes 725 are provided on at least one of the front mounting surface 72 A and the back mounting surface 72 B. In the configuration shown in Fig. 15, the external electrodes 725 are provided on both the front mounting surface 72 A and the back mounting surface 72 B.

[0118] The external electrodes 725 provided on the front mounting surface 72A are electrically connected to the electronic component 71 via solder 711. In the configuration shown in Fig. 15, the external electrodes 725 provided on the rear mounting surface 72B are not electrically connected to the electronic component 71, but may be electrically connected to the electronic component 71 via solder 727.

[0119] The through electrodes 726 are filled in through holes that penetrate the mounting substrate 72 in the thickness direction 101, thereby penetrating the mounting substrate 72 in the thickness direction 101. In the configuration shown in Fig. 15, the through electrodes 726 are through-silicon vias (TSVs).

[0120] The external electrode 725, the through electrode 726, the filling portion 40 of the semiconductor device 10, and the solders 711 and 727 can be electrically connected to one another. For example, in the configuration shown in FIG. 15 , the through electrode 726 and the external electrode 725 are electrically connected, and the filling portion 40 of the semiconductor device 10 is electrically connected to the through electrode 726 and the solder 727.

[0121] According to this embodiment, the semiconductor device 10 can be provided near the electronic component 71. As a result, the signal integrity (SI) of the semiconductor device 10 can be improved.

[0122] <Modification 1 of Module Member> FIG. 16 is a schematic cross-sectional view of a modification of the module member according to an embodiment of the present disclosure.

[0123] As shown in FIG. 16, a portion of the semiconductor device 10 may be exposed to the outside of the mounting substrate 72 on both the front mounting surface 72A and the back mounting surface 72B.

[0124] 16 , the portion of the semiconductor device 10 exposed on the front mounting surface 72A constitutes a part of the front mounting surface 72A, and the portion of the semiconductor device 10 exposed on the rear mounting surface 72B constitutes a part of the rear mounting surface 72B. In other words, the length of the semiconductor device 10 in the thickness direction 101 and the length of the mounting substrate 72 in the thickness direction 101 are the same or approximately the same.

[0125] The mounting substrate 72 shown in Fig. 16 is a substrate made of glass epoxy, etc. Note that the mounting substrate 72 shown in Fig. 16 may be, for example, an interposer substrate (see Fig. 15) or a substrate including a core material 721 (see Fig. 17).

[0126] 16 includes an external electrode 725 and an internal electrode 724. The external electrode 725 and the internal electrode 724 are made of a conductive material such as copper. The internal electrode 724 is provided inside the mounting substrate 72. The filled portion 40 of the semiconductor device 10 is electrically connected to the external electrode 725 and the solder 727.

[0127] 16 , the internal electrode 724 can be connected to the external electrode 725, the filling portion 40 of the semiconductor device 10, other internal electrodes 724, etc. via the through electrode 726. The internal electrode 724, the external electrode 725, the through electrode 726, the filling portion 40 of the semiconductor device 10, and the solders 711 and 727 can be electrically connected to one another.

[0128] According to the first modification, the thickness of the semiconductor device 10 can be made the same as the thickness of the mounting substrate 72. This improves the characteristics of the capacitive section 30 more than in a configuration in which the thickness of the semiconductor device 10 is thinner than the thickness of the mounting substrate 72. For example, the electrostatic capacitance can be increased.

[0129] <Modification 2 of Module Member> FIG. 17 is a schematic cross-sectional view of a modification of the module member according to the embodiment of the present disclosure.

[0130] 17, the semiconductor device 10 may be mounted on the surface of a mounting substrate 72. In other words, the semiconductor device 10 may be provided outside the mounting substrate 72.

[0131] 17 , the electronic component 71 is mounted on the front mounting surface 72A, and the semiconductor device 10 is mounted on the rear mounting surface 72B. The electronic component 71 may be mounted on the rear mounting surface 72B, the semiconductor device 10 may be mounted on the front mounting surface 72A, or the electronic component 71 and the semiconductor device 10 may be mounted on the same mounting surface. Furthermore, each of the electronic component 71 and the semiconductor device 10 may be mounted on both the front mounting surface 72A and the rear mounting surface 72B.

[0132] The mounting substrate 72 shown in FIG. 17 includes a core material 721 and insulating substrates 722 and 723 disposed to sandwich the core material 721 in the thickness direction 101. An internal electrode 724 is provided inside the insulating substrates 722 and 723. The surface of the insulating substrate 722 opposite the surface that contacts the core material 721 is the front mounting surface 72A of the mounting substrate 72. The surface of the insulating substrate 723 opposite the surface that contacts the core material 721 is the back mounting surface 72B of the mounting substrate 72. External electrodes 725 are provided on the front mounting surface 72A and the back mounting surface 72B. A through electrode 726 can penetrate at least one of the core material 721, the insulating substrate 722, and the insulating substrate 723. The through electrode 726 can be electrically connected to the internal electrode 724 and the external electrode 725.

[0133] 17 may be, for example, an interposer substrate (see FIG. 15 ) or a substrate made of glass epoxy or the like (see FIG. 16 ). Although the semiconductor device 10 shown in FIG. 17 has a bottomed filling portion 40, it may also have a filling portion 40 that penetrates the semiconductor substrate 20 in the thickness direction 101.

[0134] According to the second modification, the semiconductor device 10 can be disposed close to the electronic component 71. This makes it possible to reduce the parasitic capacitance between the semiconductor device 10 and the electronic component 71.

[0135] <Circuit Board> FIG. 18 is a schematic cross-sectional view of a circuit board according to an embodiment of the present disclosure.

[0136] As shown in Fig. 18 , the circuit board 1 includes the module component 70 of Modification 2 shown in Fig. 17 and a main board 80 on which the module component 70 is mounted. Note that the circuit board 1 may include a module component 70 of an embodiment other than Modification 2, instead of the module component 70 shown in Fig. 17 . When viewed along the thickness direction 101, the area of ​​the main board 80 in Fig. 18 may be larger than the area of ​​the mounting board 72 but may be smaller than the area of ​​the mounting board 72. The thickness of the main board 80 in Fig. 18 may be thicker than the thickness of the mounting board 72 but may be smaller than the thickness of the mounting board 72.

[0137] 17 , the main substrate 80 includes a core material 81 and insulating substrates 82 and 83 disposed to sandwich the core material 81 in the thickness direction 101. In the configuration shown in FIG. 18 , the core material 81 has the same configuration as the core material 721 of the mounting substrate 72, and the insulating substrates 82 and 83 have the same configuration as the insulating substrates 722 and 723 of the mounting substrate 72.

[0138] The main substrate 80 may be an interposer substrate or a substrate made of glass epoxy or the like.

[0139] The main substrate 80 has a front mounting surface 80A and a back mounting surface 80B that is the back side of the front mounting surface 80A. The front mounting surface 80A and the back mounting surface 80B are spaced apart from each other in the thickness direction 101 of the main substrate 80. The front mounting surface 80A and the back mounting surface 80B face opposite each other in the thickness direction 101. The surface of the insulating substrate 82 opposite to the surface that contacts the core material 81 is the front mounting surface 80A of the main substrate 80. The surface of the insulating substrate 83 opposite to the surface that contacts the core material 81 is the back mounting surface 80B of the main substrate 80.

[0140] The main substrate 80 includes an internal electrode 84, an external electrode 85, and a through electrode 86. The internal electrode 84, the external electrode 85, and the through electrode 86 are made of a conductive material such as copper.

[0141] The internal electrode 84 is provided inside the main substrate 80, similar to the internal electrode 724 of the mounting substrate 72. The external electrode 85 is provided on at least one of the front mounting surface 80A and the back mounting surface 80B, similar to the external electrode 725 of the mounting substrate 72. The through electrode 86 can penetrate at least one of the core material 81, the insulating base material 82, and the insulating base material 83, similar to the through electrode 726 of the mounting substrate 72. The internal electrode 84, the external electrode 85, and the through electrode 86 can be electrically connected to one another.

[0142] The module component 70 can be mounted on at least one of the front mounting surface 80A and the rear mounting surface 80B. In the circuit board 1 shown in Fig. 18, the module component 70 is mounted on the front mounting surface 80A.

[0143] The semiconductor device 10 included in the module member 70 is located between the mounting substrate 72 and the main substrate 80 .

[0144] In the manufacturing process of the circuit board 1 shown in Fig. 18, a mounting process is performed in which the module member 70 shown in Fig. 17 is mounted on the main board 80. Before the mounting process, an exposure process is performed in which the filling portion 40 of the semiconductor device 10 included in the module member 70 shown in Fig. 17 is exposed.

[0145] 17, the semiconductor device 10 has a bottomed filling portion 40. In addition, a tip portion 727A of the solder 727 is located closer to the bottom surface 20Db of the hole 20D than the capacitance portion 30 in the thickness direction 101.

[0146] In the exposure step, the semiconductor device 10 and the solder 727 are ground at the position shown by the dashed line in Fig. 17. The position shown by the dashed line in Fig. 17 is between the tip 727A of the solder 727 and the capacitance section 30 in the thickness direction 101. This exposes the lower surface 40B of the filling section 40 to the outside. Furthermore, the lower surface 40B of the filling section 40 and the tip 727B of the solder 727 are located on the grinding surface (on the same plane) shown by the dashed line in Fig. 17.

[0147] In the next mounting step, the module component 70 that has undergone the exposure step is mounted on the front mounting surface 80A of the main board 80. At this time, in the exposure step, the lower surface 40B of the filling portion 40 and the tip portion 727B of the solder 727 are positioned on the same plane, making mounting easy.

[0148] By performing the exposure step, it is possible to mount a thin module component 70 on the main board 80 while maintaining ease of handling. Furthermore, by performing the exposure step, it is possible to make the height of the semiconductor device 10 mounted on the back mounting surface 72B of the mounting board 72 of the module component 70 the same as the height of the solder 727.

[0149] According to this embodiment, the semiconductor device 10 is located between the mounting substrate 72 and the main substrate 80. That is, the semiconductor device 10 and the mounting substrate 72 overlap when viewed along the thickness direction 101. Therefore, the circuit board 1 can be made smaller than in a configuration in which the semiconductor device 10 and the mounting substrate 72 do not overlap when viewed along the thickness direction 101.

[0150] According to this embodiment, since the semiconductor device 10 is located between the mounting substrate 72 and the main substrate 80, the intrusion of external noise into the semiconductor device 10 can be reduced by, for example, a shielding film provided on the mounting substrate 72 and the main substrate 80.

[0151] The semiconductor device 10, module member 70, and circuit board 1 described above can also be expressed as follows.

[0152] According to a first aspect of the present disclosure, there is provided a semiconductor device comprising: a semiconductor substrate having one main surface and another main surface that is spaced apart from the one main surface in a thickness direction and faces the opposite side of the thickness direction from the one main surface, wherein at least one trench portion is provided in the one main surface and a hole portion that extends along the thickness direction, opens to at least one of the one main surface and the other main surface, and has a larger area than one of the trench portions as viewed along the thickness direction; a capacitance portion that is provided at least inside the trench portion and has a dielectric layer and two electrode layers sandwiching the dielectric layer; and a filling portion that is provided inside the hole portion and contains a conductive material.

[0153] According to a second aspect of the present disclosure, there is provided the semiconductor device according to the first aspect, further comprising: a conductive external terminal provided on at least one of the one main surface and the other main surface, the conductive external terminal being in contact with the filling portion.

[0154] According to a third aspect of the present disclosure, there is provided the semiconductor device according to the first or second aspect, further comprising a conductive dummy terminal provided on at least one of the one main surface and the other main surface, the conductive dummy terminal not being electrically connected to other conductive portions of the semiconductor device.

[0155] According to a fourth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to third aspects, wherein the filling portion includes: a buried layer made of resin; a conductive layer containing a conductive material and surrounding the buried layer when viewed along the thickness direction; a barrier layer containing a conductive material and surrounding the conductive layer when viewed along the thickness direction; and an isolation layer made of an insulating material and surrounding the barrier layer when viewed along the thickness direction.

[0156] According to a fifth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to fourth aspects, wherein the hole portion opens to one of the one main surface and the other main surface and has a bottom on the other side of the one main surface and the other main surface.

[0157] According to a sixth aspect of the present disclosure, there is provided a semiconductor device as described in the fifth aspect, wherein the hole portion has a side surface extending from one of the one main surface and the other main surface to the other, and a bottom surface connected to the other end of the one main surface and the other main surface at the side surface, and the boundary portion between the side surface and the bottom surface is a curved surface.

[0158] According to a seventh aspect of the present disclosure, there is provided the semiconductor device according to the fifth or sixth aspect, wherein a length of the hole in the thickness direction is longer than a length of the trench in the thickness direction.

[0159] According to an eighth aspect of the present disclosure, there is provided a semiconductor device according to any one of the first to seventh aspects, wherein the filling portion comprises: a conductive layer extending from one end to the other end in the thickness direction of the hole portion and containing a conductive material; and a magnetic layer extending from one end to the other end in the thickness direction of the hole portion and containing a magnetic material.

[0160] According to a ninth aspect of the present disclosure, there is provided the semiconductor device according to the eighth aspect, wherein the conductive layer penetrates the magnetic layer in the thickness direction.

[0161] According to a tenth aspect of the present disclosure, there is provided a module member comprising: a semiconductor device according to any one of the first to ninth aspects; an electronic component; and a mounting substrate having a front mounting surface on which the electronic component is mounted and a back mounting surface that is a back surface of the front mounting surface, and on which the semiconductor device is provided.

[0162] According to an eleventh aspect of the present disclosure, there is provided the module member according to the tenth aspect, wherein at least a portion of the semiconductor device is provided inside the mounting substrate.

[0163] According to a twelfth aspect of the present disclosure, there is provided the module member according to the eleventh aspect, wherein the semiconductor device is exposed on the front mounting surface and the back mounting surface.

[0164] According to a thirteenth aspect of the present disclosure, there is provided the module member according to the tenth aspect, wherein the semiconductor device is mounted on at least one of the front mounting surface and the rear mounting surface.

[0165] According to a fourteenth aspect of the present disclosure, there is provided a module member according to any one of the tenth to thirteenth aspects, in which, when viewed along the thickness direction, at least a portion of the semiconductor device and at least a portion of the electronic component are positioned to overlap.

[0166] According to a fifteenth aspect of the present disclosure, there is provided a circuit board comprising: a module component according to any one of the tenth to fourteenth aspects; and a main board having the module component mounted on a surface thereof, wherein the semiconductor device is located between the mounting board and the main board.

[0167] Any of the various embodiments described above may be combined appropriately to achieve the effects of each of them.

[0168] While the present invention has been fully described in connection with preferred embodiments, with appropriate reference to the drawings, various changes and modifications will become apparent to those skilled in the art, and it is to be understood that such changes and modifications are included within the scope of the present invention as defined by the appended claims unless they depart therefrom.

[0169] REFERENCE SIGNS LIST 1 Circuit board 10 Semiconductor device 20 Semiconductor substrate 20A One main surface 20B Other main surface 20C Trench portion 20D Hole portion 20Da Side surface 20Db Bottom surface 20Dc Boundary portion 30 Capacitor portion 40 Filling portion 41 Buried layer 42 Conductive layer 43 Barrier layer 44 Isolation layer 45 Magnetic layer 51 External terminal 52 Dummy terminal 70 Module member 71 Electronic component 72 Mounting substrate 72A Front mounting surface 72B Back mounting surface 80 Main substrate 101 Thickness direction

Claims

1. A semiconductor device comprising: a semiconductor substrate having one main surface and another main surface that is spaced apart in the thickness direction from the one main surface and faces the opposite direction from the one main surface, wherein the one main surface has at least one trench portion provided therein, and a hole portion that extends along the thickness direction, opens to at least one of the one main surface and the other main surface and has a larger area than one of the trench portions as viewed along the thickness direction; a capacitance portion provided at least inside the trench portion, the capacitance portion having a dielectric layer and two electrode layers sandwiching the dielectric layer; and a filling portion provided inside the hole portion and containing a conductive material.

2. The semiconductor device according to claim 1, further comprising a conductive external terminal provided on at least one of said one main surface and said other main surface, said external terminal being in contact with said filling portion.

3. The semiconductor device according to claim 1 or 2, further comprising a conductive dummy terminal provided on at least one of the one main surface and the other main surface, the dummy terminal being not electrically connected to other conductive parts of the semiconductor device.

4. A semiconductor device according to any one of claims 1 to 3, wherein the filling portion comprises: an embedded layer made of resin; a conductive layer containing a conductive material and surrounding the embedded layer when viewed along the thickness direction; a barrier layer containing a conductive material and surrounding the conductive layer when viewed along the thickness direction; and an isolation layer made of an insulating material and surrounding the barrier layer when viewed along the thickness direction.

5. The semiconductor device according to claim 1, wherein the hole opens to one of the one main surface and the other main surface and has a bottom on the other side of the one main surface and the other main surface.

6. The semiconductor device according to claim 5, wherein the hole portion has a side surface extending from one of the one main surface and the other main surface to the other, and a bottom surface connected to the other end of the one main surface and the other main surface at the side surface, and the boundary between the side surface and the bottom surface is a curved surface.

7. The semiconductor device according to claim 5 or 6, wherein the length of said hole in said thickness direction is longer than the length of said trench portion in said thickness direction.

8. A semiconductor device according to any one of claims 1 to 7, wherein the filling portion comprises: a conductive layer extending from one end to the other end of the hole in the thickness direction and including a conductive material; and a magnetic layer extending from one end to the other end of the hole in the thickness direction and including a magnetic material.

9. The semiconductor device according to claim 8, wherein said conductive layer penetrates said magnetic layer in said thickness direction.

10. A module member comprising: a semiconductor device according to any one of claims 1 to 9; an electronic component; and a mounting substrate having a front mounting surface on which the electronic component is mounted and a back mounting surface that is the back surface of the front mounting surface, and on which the semiconductor device is provided.

11. The module member according to claim 10, wherein at least a portion of the semiconductor device is provided inside the mounting substrate.

12. The module member according to claim 11, wherein the semiconductor device is exposed on the front mounting surface and the back mounting surface.

13. The module member according to claim 10, wherein the semiconductor device is mounted on at least one of the front mounting surface and the back mounting surface.

14. The module member according to any one of claims 10 to 13, wherein at least a portion of the semiconductor device and at least a portion of the electronic component are positioned to overlap when viewed along the thickness direction.

15. A circuit board comprising: a module member according to any one of claims 10 to 14; and a main board having the module member mounted on a surface thereof, wherein the semiconductor device is located between the mounting board and the main board.

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