Pulse width adjustment circuit, circuit device, and electronic apparatus

Abstract

The purpose of the present invention is to provide a pulse width adjustment circuit having a configuration capable of stably reducing phase noise.　A pulse width adjustment circuit according to the present technology comprises: a delay circuit that has a plurality of cascade-connected inverters and delays an input signal; a control circuit that controls at least two inverters including one inverter among the plurality of inverters; and an output circuit that outputs, as an injection signal, a logical operation result of a signal inputted to the one inverter and a signal outputted from the one inverter or a signal equivalent to the logical operation result.

Description

Pulse width adjustment circuit, circuit device, and electronic device

[0001] The technology according to the present disclosure (hereinafter also referred to as "the technology") includes a pulse width adjustment circuit, a circuit device, and an electronic device.

[0002] Conventionally, a circuit that injects an injection signal into an oscillation circuit is known (see Patent Documents 1 and 2).

[0003] JP 2015-100006 A JP 2015-146534 A

[0004] However, conventional circuits do not have a configuration that is effective for stably reducing phase noise.

[0005] Therefore, a main object of the present technology is to provide a pulse width adjustment circuit having a configuration that is useful for stably reducing phase noise.

[0006] The present technology provides a pulse width adjustment circuit including: a delay circuit having a plurality of cascaded inverters and delaying an input signal; a control circuit controlling at least two inverters including one inverter among the plurality of inverters; and an output circuit outputting, as an injection signal, a result of a logical operation between a signal input to the one inverter and a signal output from the one inverter, or a signal equivalent to the result of the logical operation. The injection signal may be injected into an oscillation circuit having a delay element, and each of the at least two inverters may have approximately the same delay amount as the delay element. The control circuit may generate operating currents for the at least two inverters and the oscillation circuit. The period of the input signal may approximately match the product of the oscillation period of the oscillation circuit and a PLL multiplication factor. The pulse width of the injection signal may be 10% to 40% of the oscillation period of the oscillation circuit. The pulse width of the injection signal may be 20% to 30% of the oscillation period of the oscillation circuit. The pulse width of the injection signal may be 24% to 26% of the oscillation period of the oscillation circuit. The plurality of inverters may include at least one inverter above the first inverter. The at least two inverters may include at least one inverter above the first inverter. The at least two inverters may include at least two inverters above the first inverter. The plurality of inverters may include at least one inverter below the first inverter. The control value input to the control circuit may be K times a reference value. The size of each of the at least two inverters may be K times a reference size. The power supply may further include a bias application circuit connected between the first inverter and the output circuit and applying a bias to the input signal and the output signal.The present technology also provides a circuit device comprising: a pulse width adjustment circuit including a delay circuit having a plurality of cascaded inverters and delaying an input signal; a control circuit controlling at least two inverters including one of the plurality of inverters; and an output circuit outputting, as an injection signal, a result of a logical operation between an input signal input to the one inverter and a signal output from the one inverter, or a signal equivalent to the result of the logical operation; and an oscillator circuit having a delay element into which the injection signal is injected. Each of the at least two inverters may have approximately the same delay amount as the delay element. The control circuit may generate operating currents for the at least two inverters and the oscillator circuit. The period of the input signal may approximately match the product of the oscillation period of the oscillator circuit and a PLL multiplication factor. The pulse width of the injection signal may be 10% to 40% of the oscillation period of the oscillator circuit. The present technology also provides an electronic device comprising: a pulse width adjustment circuit including: a delay circuit having a plurality of cascaded inverters and delaying an input signal; a control circuit controlling at least two inverters including one inverter of the plurality of inverters; and an output circuit outputting, as an injection signal, a result of a logical operation between an input signal input to the one inverter and a signal output from the one inverter or a signal equivalent to the result of the logical operation; and an oscillation circuit into which the injection signal is injected, wherein the oscillation circuit serves as an oscillation source of a clock.

[0007] 1A and 1B are diagrams for explaining jitter reduction by injection locking. A diagram for explaining injection strength. FIGS. 3A and 3B are diagrams for explaining the significance of setting the pulse width of an injection signal to 25% of the oscillation period. FIGS. 4A to 4C are supplementary explanatory diagrams for the significance of setting the pulse width of an injection signal to 25% of the oscillation period. FIGS. 5A and 5B are diagrams for explaining a conventional pulse width adjustment circuit. A diagram showing the configuration of a pulse width adjustment circuit according to Example 1 of an embodiment of the present technology. A diagram showing the configuration of a ring oscillator into which an injection signal is injected from the pulse width adjustment circuit of FIG. 6. A diagram showing the configuration of a pulse width adjustment circuit according to Example 2 of an embodiment of the present technology. A diagram showing the configuration of a pulse width adjustment circuit according to Example 3 of an embodiment of the present technology. A diagram showing the configuration of a pulse width adjustment circuit according to Example 4 of an embodiment of the present technology. A diagram showing the configuration of a pulse width adjustment circuit according to Example 5 of an embodiment of the present technology. A diagram showing the configuration of a pulse width adjustment circuit according to Example 6 of an embodiment of the present technology. A diagram for explaining an injection method without using a logical operation circuit. FIG. 1 is a quoted diagram for explaining an injection method without using a logical operation circuit. FIG. 2 is a diagram showing a first configuration example of a frequency synthesizer including a pulse width adjustment circuit according to an embodiment of the present technology. FIG. 3 is a diagram showing a second configuration example of a frequency synthesizer including a pulse width adjustment circuit according to an embodiment of the present technology. FIG. 4 is a diagram showing a configuration of a pulse width adjustment circuit according to a first modified example of an embodiment of the present technology. FIG. 5 is a graph showing a relationship between a control value and a frequency in a pulse width adjustment circuit according to a second modified example of an embodiment of the present technology. FIG. 6 is a diagram showing a configuration of a ring oscillator into which an injection signal is injected from a pulse width adjustment circuit according to a second modified example of an embodiment of the present technology. FIG. 7 is a diagram for explaining an operation of the pulse width adjustment circuit according to the second modified example of an embodiment of the present technology.

[0008] Preferred embodiments of the present technology will be described in detail below with reference to the accompanying drawings. Note that in this specification and the drawings, components having substantially the same functional configurations are denoted by the same reference numerals, and redundant description will be omitted. The embodiments described below illustrate typical embodiments of the present technology, and the scope of the present technology should not be interpreted as being narrow. Even when it is described in this specification that a pulse width adjustment circuit, a circuit device, and an electronic device according to the present technology achieve multiple effects, it is sufficient that the pulse width adjustment circuit, the circuit device, and the electronic device according to the present technology achieve at least one effect. The effects described in this specification are merely examples and are not limiting, and other effects may also be achieved.

[0009] The description will be made in the following order: 0. Concept of the present technology 1. Pulse width adjustment circuit according to Example 1 of an embodiment of the present technology 2. Pulse width adjustment circuit according to Example 2 of an embodiment of the present technology 3. Pulse width adjustment circuit according to Example 3 of an embodiment of the present technology 4. Pulse width adjustment circuit according to Example 4 of an embodiment of the present technology 5. Pulse width adjustment circuit according to Example 5 of an embodiment of the present technology 6. Pulse width adjustment circuit according to Example 6 of an embodiment of the present technology 7. Injection method without using a logic operation circuit 8. Frequency synthesizer including a pulse width adjustment circuit according to an embodiment of the present technology 9. Modified example of the present technology

[0010] <0. Concept of the Present Technology> Conventionally, an injection-locked oscillator, as shown in FIG. 1A, has been known as an oscillator capable of reducing phase noise. In this injection-locked oscillator, as shown in FIG. 1B, the phase of the oscillator's output signal is synchronized to the phase of an injection signal (a low-jitter signal) by injection locking, thereby reducing phase noise. Furthermore, while the upper limit of the frequency band of a typical PLL (Phase Locked Loop) is 0.1 fref (fref: reference frequency), the upper limit of the frequency band of an injection-locked oscillator can be set to 0.4βfref, thereby enabling low jitter and low phase noise over a wider frequency band. Here, β is the strength of the injection locking and is also called the "locking strength." β is maximum when it is 1, and when β is maximum, i.e., 1, the oscillator's output signal is perfectly synchronized with the injection signal.

[0011] As shown in Figure 2, the phase pulled by injection is expressed as βΔT, where β is the pulling strength. ΔT varies depending on the injection timing. As injection continues, βΔT approaches zero, and the phase of the oscillator output signal and the phase of the injection signal match, achieving locking (injection lock).

[0012] 3A and 3B, it has been argued that the pulse width of the injection signal that can most effectively reduce phase noise (maximize the pull-in strength β) is 25% of the oscillation period. In Fig. 3A, PSD is an abbreviation for Power Spectral Density.

[0013] The pull-in strength β can be adjusted by adjusting the pulse width of the injection signal. In addition, the 2fosc (fosc: oscillation frequency) component of the injection signal (see Fig. 4A) is mixed with the fosc component of the oscillator (see Fig. 4B), and the larger this fosc component is, the larger β becomes, which allows for further reduction of phase noise in the IL-OSC (oscillator, see Fig. 4C).

[0014] 5A and 5B, a time adjustment circuit such as a DCDL (Digital Controlled Delay Line) has been used as a conventional pulse width adjustment circuit, but it is extremely difficult to adjust the time while tracking PVT (Process / Voltage / Temperature) fluctuations, and there is a particular concern that the circuit cannot track temperature drift. In other words, conventional pulse width adjustment circuits do not have a configuration that is effective for stably reducing phase noise.

[0015] Therefore, after extensive research, the inventors have developed a pulse width adjustment circuit according to the present technology as a pulse width adjustment circuit having a configuration that is useful for stably reducing phase noise.

[0016] Hereinafter, an embodiment of a pulse width adjustment circuit according to the present technology will be described in detail with reference to several examples.

[0017] 1. Pulse Width Adjustment Circuit According to Example 1 of an Embodiment of the Present Technology> Fig. 6 is a diagram showing a configuration of a pulse width adjustment circuit 10 according to Example 1 of an embodiment of the present technology. Fig. 7 is a diagram showing a configuration of a ring oscillator 1 into which an injection signal INJ is injected from the pulse width adjustment circuit of Fig. 6.

[0018] The pulse width adjustment circuit 10 shown in FIG. 6 is a circuit that injects an injection signal INJ into the ring oscillator 1 (oscillator circuit) shown in FIG. 7 . The ring oscillator 1 is, for example, an injection-locked two-stage differential ring oscillator. The ring oscillator 1 includes four main inverters 101M (delay elements) and four sub-inverters 101S. The sub-inverters 101S have a function of preventing DC (direct current) stabilization and enabling oscillation. Each main inverter 101M and each sub-inverter 101S is, for example, a complementary metal oxide semiconductor (CMOS) inverter. The pulse width adjustment circuit 10 and the ring oscillator 1 are driven by a power supply potential Vdd. An example of a circuit device according to the present technology is configured including the pulse width adjustment circuit 10 and the ring oscillator 1. Although the term "approximately" is used below, it means that an error of 0.5% or less is allowed in both cases.

[0019] As shown in FIG. 6, the pulse width adjustment circuit 10 has a plurality of cascaded inverters (for example, first to fourth inverters 101A, 101B, 101C, 102), and includes a delay circuit DEC that delays an input signal, a frequency control circuit 103 (control circuit) that controls at least two inverters (for example, three inverters 101A, 101B, 101C) including the first inverter 101A (one inverter) among the plurality of inverters, and a signal S IN and the signal S output from the first inverter 101A. OUT AND operation result S AND and an AND circuit 104 (output circuit) that outputs the logical operation result as an injection signal INJ. In a broad sense, an inverter is also called a "delay element."

[0020] The second inverter 101B is an inverter above the first inverter 101A. The third inverter 101C is an inverter above the second inverter 101B. The fourth inverter 102 is an inverter below the first inverter 101A. Each of the first to third inverters 101A, 101B, and 101C has approximately the same delay amount as the main inverter 101M. Here, each of the first to third inverters 101A, 101B, and 101C is a replica of the main inverter 101M. In other words, each of the first to third inverters 101A, 101B, and 101C is substantially identical to the main inverter 101M. The fourth inverter 102 is a dummy inverter that serves as a load. Each of the first to fourth inverters 101A, 101B, 101C, and 102 is, for example, a CMOS inverter. Hereinafter, each of the first to third inverters 101A, 101B, and 101C will also be referred to as a "replica inverter" as appropriate.

[0021] 6 and 7, the frequency control circuit 103 has a current source I or a variable resistor r that generates an operating current (power supply current) for the three inverters 101A, 101B, and 101C and the ring oscillator 1 to control the frequency. That is, the frequencies of the three inverters 101A, 101B, and 101C and the ring oscillator 1 are controlled by a common operating current. An analog or digital control value (OTW) is input to the frequency control circuit 103 from a higher-level control device.

[0022] The frequency control circuit 103 is, for example, electrically connected to each of the first to fourth inverters 101A, 101B, 101C, and 102.

[0023] The input terminal of the first inverter 101A is connected to one input terminal of the AND circuit 104. The output terminal of the first inverter 101A is connected to the other input terminal of the AND circuit 104. The AND circuit 104 receives the signal S IN and the signal S output from the first inverter 101A. OUT By performing an AND operation with AND The injection signal INJ is generated as follows.

[0024] The period of the pulse signal (e.g., rectangular pulse signal) that is the input signal IN input to the delay circuit DEC (more specifically, the input signal IN input to the third inverter 101C) is approximately equal to the product of the oscillation period of the ring oscillator 1 and the PLL (Phase Locked Loop) multiplication factor. More specifically, the period of the input signal In is equal to the product of the design target value of the oscillation period and the PLL multiplication factor. Therefore, the period of the signal S input to the first inverter 101A is approximately equal to the product of the design target value of the oscillation period and the PLL multiplication factor. IN and the signal S output from the first inverter 101A. OUT Each of these periods approximately coincides with the product of the oscillation period of the ring oscillator 1 and the PLL multiplication factor. The input signal IN is generated by a signal source (for example, a voltage source) not shown.

[0025] The delay amount of the main inverter 101M of the ring oscillator 1, which is a two-stage differential ring oscillator, with respect to the oscillation period of the ring oscillator 1 is 270°, and the delay amount of each of the three inverters 101A, 101B, and 101C with respect to the oscillation period of the ring oscillator 1 is also 270°.

[0026] Therefore, the signal S IN , S OUT Since the phase difference between the signal S and the signal S is 270°, the signal S input to the first inverter 101A IN (pulse signal), and the signal S output from the first inverter 101A. OUT (pulse signal) and AND operation result S AND That is, the pulse width of the output signal OUT of the AND circuit 104 is 24% to 26% (preferably 25%) of the oscillation period of the ring oscillator 1. This makes it possible to substantially maximize the pull-in strength β and generate an injection signal INJ that can substantially maximize the reduction in phase noise.

[0027] Here, the oscillation frequency of ring oscillator 1 is proportional to the operating current (the oscillation period is inversely proportional to the operating current), but even if the oscillation period of ring oscillator 1 changes due to a change in the operating current caused by a fluctuation in PVT (for example, the occurrence of temperature drift), the delay amount of the first to third inverters 101A, 101B, and 101C, which are supplied with the same operating current, also changes in accordance with the change in the oscillation period of ring oscillator 1.

[0028] Therefore, the pulse width adjustment circuit 10 can substantially maximize the pull-in strength β regardless of fluctuations in PVT, thereby substantially maximizing the reduction in phase noise.

[0029] At least two replica inverters (second and third inverters 101B and 101C) are provided in front of the first inverter 101A, so that the signal S IN and the signal S output from the first inverter 101A. OUT This makes it possible to generate an injection signal INJ with a more regular waveform, and improves the accuracy of synchronization between the injection signal INJ and the output signal of the ring oscillator 1.

[0030] Hereinafter, another example of an embodiment of the present technology will be described, focusing on differences from Example 1. <2. Pulse Width Adjustment Circuit According to Example 2 of an Embodiment of the Present Technology> Fig. 8 is a diagram showing a configuration of a pulse width adjustment circuit 20 according to Example 2 of an embodiment of the present technology.

[0031] 8, the pulse width adjustment circuit 20 can adjust the pulse width of the injection signal INJ to a pulse width of any ratio based on the oscillation period of the ring oscillator 1 (see FIG. 7) by multiplying the control value of the frequency control circuit 103 by a coefficient K. That is, here, the control value input to the frequency control circuit 103 is K (a predetermined value) times the reference value corresponding to the oscillation period of the ring oscillator 1. In this case, the pulse width of the injection signal INJ is 1 / K times the reference value (0.25) corresponding to the oscillation period of the ring oscillator 1.

[0032] For example, by setting 1 / K to 0.4 or more and 1.6 or less, the pulse width of the injection signal INJ can be set to 10% or more and 40% or less of the oscillation period of the ring oscillator 1. This range is shown in FIG. VCO In a Gaussian distribution having a peak at 0.25, this is a range in which the pulling strength β can be relatively large and in which the phase noise can be reduced.

[0033] For example, by setting 1 / K to 0.8 or more and 1.2 or less, the pulse width of the injection signal INJ can be set to 20% or more and 30% or less of the oscillation period of the ring oscillator 1. This range is shown in FIG. VCO In a Gaussian distribution having a peak at 0.25, this is a range in which a relatively large pulling strength β can be obtained, and this is a range in which phase noise can be sufficiently reduced.

[0034] For example, by setting 1 / K to 0.96 or more and 1.04 or less, the pulse width of the injection signal INJ can be set to 24% or more and 26% or less of the oscillation period of the ring oscillator 1. This range is the ratio of pulse width D / oscillation period T in FIG. VCOIn a Gaussian distribution in which the peak is at 0.25, this is a range in which a very large pulling strength β can be obtained, and this is a range in which the phase noise can be reduced sufficiently.

[0035] 3. Pulse Width Adjustment Circuit According to Third Example of an Embodiment of the Present Technology FIG. 9 is a diagram illustrating a configuration of a pulse width adjustment circuit 30 according to a third example of an embodiment of the present technology.

[0036] 9, in the pulse width adjustment circuit 30, the size of each of the first to third inverters 101A, 101B, and 101C is set to K (a predetermined value) times the reference size. In this case, the pulse width of the injection signal INJ is K times the reference value (0.25) corresponding to the oscillation period of the ring oscillator 1 (see FIG. 7).

[0037] For example, by setting K to 0.4 or more and 1.6 or less, the pulse width of the injection signal INJ can be set to 10% or more and 40% or less of the oscillation period of the ring oscillator 1. This range is the ratio of pulse width D / oscillation period T in FIG. VCO In a Gaussian distribution having a peak at 0.25, this is a range in which the pulling strength β can be relatively large and in which the phase noise can be reduced.

[0038] For example, by setting K to 0.8 or more and 1.2 or less, the pulse width of the injection signal INJ can be set to 20% or more and 30% or less of the oscillation period of the ring oscillator 1. This range is defined as the ratio of pulse width D / oscillation period T in FIG. VCO In a Gaussian distribution having a peak at 0.25, this is a range in which a relatively large pulling strength β can be obtained, and this is a range in which phase noise can be sufficiently reduced.

[0039] For example, by setting K to 0.96 or more and 1.04 or less, the pulse width of the injection signal INJ can be set to 24% or more and 26% or less of the oscillation period of the ring oscillator 1. This range is the ratio of pulse width D / oscillation period T in FIG. VCO In a Gaussian distribution in which the peak is at 0.25, this is a range in which a very large pulling strength β can be obtained, and this is a range in which the phase noise can be reduced sufficiently.

[0040] 4. Pulse Width Adjustment Circuit According to Fourth Example of an Embodiment of the Present Technology FIG. 10 is a diagram illustrating a configuration of a pulse width adjustment circuit 40 according to a fourth example of an embodiment of the present technology.

[0041] As shown in FIG. 10 , the pulse width adjustment circuit 40 has three cascaded delay elements 101′ instead of the first to third inverters 101A, 101B, and 101C, and a delay element 102′ instead of the fourth inverter 102. Each delay element 101′ is not a replica (replica inverter) of the main inverter 101M of the ring oscillator 1, but has a delay amount substantially equal to the delay amount τ of the main inverter 101M. Each delay element 101′ may have any configuration as long as it has a delay amount substantially equal to the delay amount τ. However, because the pulse width adjustment circuit 40 does not use a replica inverter for the delay element 101′, there is a risk of a larger error in the delay amount compared to the pulse width adjustment circuit 10 according to the first embodiment.

[0042] 5. Pulse Width Adjustment Circuit According to Fifth Example of an Embodiment of the Present Technology FIG. 11 is a diagram illustrating a configuration of a pulse width adjustment circuit 50 according to a fifth example of an embodiment of the present technology.

[0043] By the way, the signal S input to the first inverter 101A is delayed by the voltage drop of each of the first to third inverters 101A, 101B, and 101C that generate delays due to the current sources of the frequency control circuit 103. IN and the amplitude of the signal S output from the first inverter 101A. OUT Therefore, depending on the magnitude of the operating current generated by the current source and the magnitude of the voltage drop in each replica inverter, it may be difficult to generate the injection signal INJ.

[0044] Therefore, in the pulse width adjustment circuit 50, as shown in FIG. IN、 S OUT After applying a bias to and buffering, a NOR circuit 108 IN、 S OUT By performing a NOR operation on these, the NOR operation result S NOR (the logical operation result) is generated as an injection signal INJ.

[0045] The pulse width adjustment circuit 50 is connected between the first inverter 101A and the NOR circuit 108 as an output circuit, and adjusts the signal S IN and the signal S output from the first inverter 101 OUT The pulse width adjustment circuit 50 further includes a bias application circuit BIC that applies a bias to the pulse width adjustment circuit 50. As an example, the bias is set to Vdd / 2, which is half the power supply potential Vdd of the pulse width adjustment circuit 50.

[0046] The bias application circuit BIC receives the signal S IN a bias power supply Vbias and a bias resistor 106A for applying a bias to the signal S OUT and a bias resistor 106B for applying a bias to the

[0047] Between the input terminal of the first inverter 101A and the NOR circuit 108, a DC blocking capacitance 105A and a buffer 107A (e.g., an inverter) are inserted in this order from upstream to downstream. The output terminal of a bias resistor 106A is connected between the DC blocking capacitance 105A (e.g., a capacitor) and the buffer 107A. The input terminal of the bias resistor 106A is connected to a bias power supply Vbias. The DC blocking capacitance has the function of conducting only high-frequency components (the same applies below).

[0048] Between the output terminal of the first inverter 101A and the NOR circuit 108, a DC blocking capacitance 105B and a buffer 107B (e.g., an inverter) are inserted in this order from upstream to downstream. An output terminal of a bias resistor 106B is connected between the DC blocking capacitance 105B (e.g., a capacitor) and the buffer 107B. An input terminal of the bias resistor 106B is connected to a bias power supply Vbias.

[0049] 6. Pulse Width Adjustment Circuit According to Sixth Example of an Embodiment of the Present Technology FIG. 12 is a diagram illustrating a configuration of a pulse width adjustment circuit 60 according to a sixth example of an embodiment of the present technology.

[0050] In the pulse width adjustment circuit 60, as shown in FIG. IN and signal S OUTAfter applying a bias to and buffering, a NOR circuit 108 IN , S OUT By performing a NOR operation on these, the NOR operation result S NOR (the logical operation result) is generated as an injection signal INJ.

[0051] In the pulse width adjustment circuit 60, the bias application circuit BIC has a resistance feedback buffer between the DC cut capacitor 105A and the NOR circuit 108 and between the DC cut capacitor 105B and the NOR circuit 108, respectively.

[0052] Here, the bias application circuit BIC applies a signal S IN a parallel-connected buffer 109A (e.g., inverter) and feedback resistor 111A for biasing the signal S OUT 1B includes a parallel-connected buffer 109B (eg, an inverter) and a feedback resistor 111B for biasing the input.

[0053] 7. Injection Method Without Using a Logic Operation Circuit FIGS. 13 and 14 are citations for explaining an injection method without using a logic operation circuit.

[0054] As shown in the circuit arrangement of FIG. 13, a signal S IN , S OUT Even if the logical operation of the above is not performed, by virtually performing a logical operation (for example, an AND operation or a NOR operation) in an oscillator including an oscillation circuit, it is possible to use a signal equivalent to the logical operation result (for example, an AND operation result or a NOR operation result) as an injection signal. In this case, the output circuit of the pulse width adjustment circuit according to the present technology is present in the oscillator including the oscillation circuit, and the injection signal is injected from the output circuit to the oscillation circuit in the oscillator.

[0055] Although the circuit device of FIG. 13 is concerned about an increase in parasitic capacitance, it is considered to be effective in that the pulse width of the injection signal can be adjusted to a narrow pulse width corresponding to a higher oscillation frequency.

[0056] As in the circuit device shown in FIG. 14, it is also possible to make the output circuit of the pulse width adjustment circuit according to the present technology function equivalently as a logical operation circuit (for example, an AND circuit or a NOR circuit) within the oscillator.

[0057] 8. Frequency synthesizer including a pulse width adjustment circuit according to an embodiment of the present technology> Fig. 15 is a diagram illustrating a first configuration example of a frequency synthesizer including a pulse width adjustment circuit according to an embodiment of the present technology. Fig. 16 is a diagram illustrating a second configuration example of a frequency synthesizer (electronic device) including a pulse width adjustment circuit according to an embodiment of the present technology.

[0058] By adjusting the frequency of a VCO (Voltage Controlled Oscillator) or a DCO (Digital Controlled Oscillator) with a PLL (Phase Locked Loop) or an FLL (Frequency-Locked Loop), it is possible to realize a frequency synthesizer using injection locking by a pulse width adjustment circuit PG according to the present technology, as shown in configuration example 1 in Fig. 15 or configuration example 2 in Fig. 16. In Fig. 15 and Fig. 16, REF is a reference input signal that is input in synchronization with the PG and the PLL.

[0059] In the configuration example 2 shown in FIG. 16, the phase is matched by injection, so that no problem occurs even with frequency adjustment in FLL.

[0060] The frequency synthesizers of configuration examples 1 and 2 shown in FIGS. 15 and 16, respectively, can be used in devices and applications that require a clock (CLK), such as wired / wireless communication, ADCs (Analog to Digital Converters), and DACs (Digital to Analog Converters).

[0061] 9. Modifications of the Present Technology The present technology is not limited to the embodiment described above, and various modifications are possible.

[0062] (Modification 1) For example, as shown in FIG. 17, in a pulse width adjustment circuit M1 according to a modification 1 of the embodiment, the third inverter 101C may not be a replica of the main inverter 101M, and may be an inverter having a delay amount different from that of the main inverter 101M. However, in this case, the signal S IN , S OUT As a result, the jitter of each of the above may become large, and it may become impossible to generate the injection signal INJ with high precision.

[0063] Although a two-stage differential ring oscillator has been described as an example of a ring oscillator into which an injection signal is injected from the pulse width adjustment circuit according to each of the above embodiments, it is theoretically possible to configure other examples of circuit devices according to the present technology using a single-ended ring oscillator.

[0064] (Modification 2) As Modification 2, consider a ring oscillator 2 (see FIG. 19) and a pulse width adjustment circuit M2 (see FIG. 20) having the relationship between the control value and the frequency (see FIG. 18). As an example, the ring oscillator 2 is a single-ended ring oscillator with an odd number of stages (for example, three stages) in which three inverters 101 are cascade-connected. In the pulse width adjustment circuit M2, the target delay amount of one stage of the replica inverter is set to Tosc / 4 (Tosc is the period of the ring oscillator 2), and the delay amount of one inverter stage in the ring oscillator 2 is set to τ OSC is 2Tosc / 3, and the delay amount of one inverter stage of the pulse width adjustment circuit M2 is τ INV The pulse width adjustment circuit M2 is controlled by multiplying the control value by a coefficient K, and the frequency relationship between the control value x and the control value Kx is assumed to be linear. In this case, the delay amount for one inverter stage of the pulse width adjustment circuit M2 is τ INV =τ OSC In order to make the delay of the replica inverter the target delay, K must be set as follows: τ INV =3Tosc / 4=2Tosc / 3K, K=(2 / 3) / (3 / 4)=8 / 9=0.8888…≒0.89

[0065] In the above-described embodiments and modifications, a ring oscillator has been described as an example of an oscillation circuit into which an injection signal is injected from a pulse width adjustment circuit, but the present technology can also be applied to oscillators other than ring oscillators.

[0066] In each of the above embodiments (except for embodiment 4) and variant example 2, the input terminal and output terminal of the first inverter 101A are connected to the output circuit, but this is not limited thereto, and the input terminal and output terminal of the second inverter 101B or the third inverter 101C may be connected to the output circuit.

[0067] In each of the above embodiments (except for embodiment 4) and variant example 2, three or more inverters may be provided above the first inverter 101A, and two or more inverters may be provided below the first inverter 101A.

[0068] In each of the above-described embodiments (except for the fourth embodiment) and the second modification, one of the second and third inverters 101B and 101C may not be provided, and the fourth inverter 102 may not be provided.

[0069] The pulse width adjustment circuits of the above-described embodiments and modifications, and the circuit elements constituting the circuit devices including the pulse width adjustment circuits and oscillator circuits, may be replaced with equivalent circuits having the same functions as the circuit elements.

[0070] The oscillator into which an injection signal is injected from the pulse width adjustment circuit according to each of the above embodiments and modifications can be mounted in various electronic devices that use the oscillator as a clock oscillation source, such as imaging devices such as cameras with image sensors, image display devices such as projectors, head-up displays, and head-mounted displays, wireless or wired transmitters and receivers, processing devices such as personal computers, and low-power devices such as smartphones and smartwatches.

[0071] Parts of the configurations of the pulse width adjustment circuits according to the above-described embodiments (each example) and each modification may be combined within a range that does not contradict each other.

[0072] The present technology may also be configured as follows: (1) A pulse width adjustment circuit comprising: a delay circuit having a plurality of cascaded inverters and delaying an input signal; a control circuit controlling at least two inverters including one of the plurality of inverters; and an output circuit outputting, as an injection signal, a result of a logical operation between a signal input to the one inverter and a signal output from the one inverter, or a signal equivalent to the result of the logical operation. (2) The pulse width adjustment circuit according to (1), in which the injection signal is injected into an oscillation circuit having a delay element, and each of the at least two inverters has approximately the same delay amount as the delay element. (3) The pulse width adjustment circuit according to (2), in which the control circuit generates operating currents for the at least two inverters and the oscillation circuit. (4) The pulse width adjustment circuit according to (2) or (3), in which a period of the input signal approximately matches a product of an oscillation period of the oscillation circuit and a PLL multiplication factor. (5) The pulse width adjustment circuit according to any one of (1) to (4), wherein the pulse width of the injection signal is 10% to 40% of the oscillation period of the oscillator circuit. (6) The pulse width adjustment circuit according to any one of (1) to (5), wherein the pulse width of the injection signal is 20% to 30% of the oscillation period of the oscillator circuit. (7) The pulse width adjustment circuit according to any one of (1) to (6), wherein the pulse width of the injection signal is 24% to 26% of the oscillation period of the oscillator circuit. (8) The pulse width adjustment circuit according to any one of (1) to (7), wherein the plurality of inverters includes at least one inverter in an upper stage of the first inverter. (9) The pulse width adjustment circuit according to any one of (1) to (8), wherein the at least two inverters includes at least one inverter in an upper stage of the first inverter. (10) The pulse width adjustment circuit according to any one of (1) to (9), wherein the at least two inverters include at least two inverters in an upper stage of the one inverter. (11) The pulse width adjustment circuit according to any one of (1) to (10), wherein the plurality of inverters include at least one inverter in a lower stage of the one inverter.(12) The pulse width adjustment circuit according to any one of (1) to (11), wherein the control value input to the control circuit is K times a reference value. (13) The pulse width adjustment circuit according to any one of (1) to (12), wherein the size of each of the at least two inverters is K times a reference size. (14) The pulse width adjustment circuit according to any one of (1) to (13), further comprising a bias application circuit connected between the one inverter and the output circuit and applying a bias to the input signal and the output signal. (15) A circuit device comprising: a pulse width adjustment circuit including: a delay circuit having a plurality of cascaded inverters and delaying an input signal; a control circuit controlling at least two inverters including one inverter of the plurality of inverters; and an output circuit outputting, as an injection signal, a result of a logical operation between the input signal input to the one inverter and the signal output from the one inverter, or a signal equivalent to the result of the logical operation; and an oscillator circuit having a delay element into which the injection signal is injected. (16) The circuit device according to (15), wherein each of the at least two inverters has a delay amount substantially equal to that of the delay element. (17) The circuit device according to (15) or (16), wherein the control circuit generates operating currents for the at least two inverters and the oscillator circuit. (18) The circuit device according to any one of (15) to (17), wherein the period of the input signal substantially matches the product of the oscillation period of the oscillator circuit and a PLL multiplication factor. (19) The circuit device according to any one of (15) to (18), wherein the pulse width of the injection signal is 10% to 40% of the oscillation period of the oscillator circuit. (20) The circuit device according to any one of (15) to (19), wherein the pulse width of the injection signal is 20% to 30% of the oscillation period of the oscillator circuit. (21) The circuit device according to any one of (15) to (20), wherein the pulse width of the injection signal is 24% to 26% of the oscillation period of the oscillation circuit. (22) The circuit device according to any one of (15) to (21), wherein the control value input to the control circuit is set to K times a reference value corresponding to the oscillation period of the oscillation circuit.(23) The circuit device according to any one of (15) to (21), wherein the size of each of the at least two inverters is set to K times a reference size corresponding to the oscillation period of the oscillation circuit. (24) An electronic device comprising: a pulse width adjustment circuit including: a delay circuit having a plurality of cascade-connected inverters and delaying an input signal, a control circuit controlling at least two inverters including one inverter among the plurality of inverters, and an output circuit outputting, as an injection signal, a result of a logical operation between an input signal input to the one inverter and a signal output from the one inverter, or a signal equivalent to the result of the logical operation; and an oscillation circuit into which the injection signal is injected, wherein the oscillation circuit serves as an oscillation source of a clock.

[0073] 1, 2: Ring oscillator (oscillating circuit) 10, 20, 30, 40, 50, 60, M1, M2: Pulse width adjustment circuit 101A: First inverter (inverter, first inverter) 101B: Second inverter 101C: Third inverter 102: Fourth inverter. 101: Inverter (delay element) 101M: Main inverter (delay element) 103: Frequency control circuit (control circuit) 104: AND circuit (output circuit) 108: NOR circuit (output circuit) DEC: Delay circuit BIC: Bias application circuit IN: Input signal S IN : Signal S input to one inverter OUT : Signal S output from one inverter AND : AND operation result (logical operation result) S NOR : NOR operation result (logical operation result)

Claims

1. A pulse width adjustment circuit comprising: a delay circuit having a plurality of inverters connected in cascade and delaying an input signal; a control circuit controlling at least two inverters including one of the plurality of inverters; and an output circuit outputting, as an injection signal, a result of a logical operation between a signal input to the one inverter and a signal output from the one inverter, or a signal equivalent to the result of the logical operation.

2. The pulse width adjustment circuit according to claim 1, wherein the injection signal is injected into an oscillation circuit having a delay element, and each of the at least two inverters has a delay amount substantially equal to that of the delay element.

3. The pulse width adjustment circuit of claim 2, wherein the control circuit generates operating currents for the at least two inverters and the oscillator circuit.

4. The pulse width adjustment circuit according to claim 2, wherein the period of the input signal is approximately equal to the product of the oscillation period of the oscillator circuit and a PLL multiplication factor.

5. The pulse width adjustment circuit according to claim 2, wherein the pulse width of the injection signal is between 10% and 40% of the oscillation period of the oscillation circuit.

6. The pulse width adjustment circuit according to claim 2, wherein the pulse width of the injection signal is equal to or greater than 20% and equal to or less than 30% of the oscillation period of the oscillation circuit.

7. The pulse width adjustment circuit according to claim 2, wherein the pulse width of the injection signal is equal to or greater than 24% and equal to or less than 26% of the oscillation period of the oscillation circuit.

8. The pulse width adjustment circuit according to claim 1, wherein the plurality of inverters includes at least one inverter in an upper stage of the one inverter.

9. The pulse width adjustment circuit of claim 1, wherein the at least two inverters include at least one inverter in an upper stage of the one inverter.

10. The pulse width adjustment circuit of claim 1, wherein said at least two inverters include at least two inverters in an upper stage of said one inverter.

11. The pulse width adjustment circuit according to claim 1, wherein the plurality of inverters includes at least one inverter in a lower stage of the one inverter.

12. The pulse width adjustment circuit according to claim 1, wherein the control value input to said control circuit is K times a reference value.

13. The pulse width adjustment circuit of claim 1, wherein the size of each of said at least two inverters is K times a nominal size.

14. The pulse width adjustment circuit according to claim 1, further comprising a bias application circuit connected between said one inverter and said output circuit, for applying a bias to said input signal and said output signal.

15. A circuit device comprising: a pulse width adjustment circuit including a delay circuit having a plurality of cascaded inverters and delaying an input signal; a control circuit controlling at least two inverters including one of the plurality of inverters; and an output circuit outputting an injection signal, which is a result of a logical operation between an input signal input to the one inverter and a signal output from the one inverter, or a signal equivalent to the result of the logical operation; and an oscillation circuit having a delay element into which the injection signal is injected.

16. The circuit device according to claim 15, wherein each of the at least two inverters has a delay amount substantially equal to that of the delay element.

17. The circuit device according to claim 15, wherein the control circuit generates operating currents for the at least two inverters and the oscillator circuit.

18. The circuit device according to claim 15, wherein the period of the input signal is approximately equal to the product of the oscillation period of the oscillator circuit and a PLL multiplication factor.

19. The circuit device according to claim 15, wherein the pulse width of the injection signal is equal to or greater than 10% and equal to or less than 40% of the oscillation period of the oscillation circuit.

20. An electronic device comprising: a pulse width adjustment circuit including: a delay circuit having a plurality of cascaded inverters for delaying an input signal; a control circuit for controlling at least two inverters including one of the plurality of inverters; and an output circuit for outputting, as an injection signal, a result of a logical operation between an input signal input to the one inverter and a signal output from the one inverter or a signal equivalent to the result of the logical operation; and an oscillation circuit into which the injection signal is injected, wherein the oscillation circuit serves as an oscillation source for a clock.

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