Display device and electronic apparatus

Abstract

One of the purposes of the present invention is to improve image quality, for example.　A display device according to the present invention comprises a pixel, and a signal line and a control line connected to the pixel. The pixel includes: a first transistor that generates an output current corresponding to an input voltage; a light-emitting element that emits light according to an output current of the first transistor; a first capacitor that holds a signal voltage supplied via the signal line; a second capacitor that holds a threshold voltage of the first transistor; and a switch circuit that forms a path for writing the signal voltage into the first capacitor and a path for writing the threshold voltage into the second capacitor on the basis of a control signal supplied via the control line, and simultaneously performs a write operation of the signal voltage to the first capacitor and a write operation of the threshold voltage to the second capacitor.

Description

Display devices and electronic devices

[0001] The present technology relates to a display device and an electronic device.

[0002] There is known a display device having a light-emitting element whose light emission luminance changes according to the current value of an input current (so-called a current-driven light-emitting element). The following Patent Document 1 discloses a technology for improving image quality by correcting variations in the threshold voltage of a transistor (drive transistor) that controls the current value of an input current to a light-emitting element according to the signal voltage of a video signal.

[0003] JP 2015-034861 A

[0004] Display devices are being demanded to have even higher image quality. However, the technology disclosed in Patent Document 1 has disadvantages in terms of improving image quality due to the characteristics of the pixel circuit.

[0005] One of the objects of the present technology is to improve image quality, for example.

[0006] The present technology relates to, for example, a display device including a pixel, and a signal line and a control line connected to the pixel, wherein the pixel includes: a first transistor that generates an output current according to an input voltage, a light-emitting element that emits light according to the output current of the first transistor, a first capacitance that holds a signal voltage supplied via the signal line, a second capacitance that holds a threshold voltage of the first transistor, and a switch circuit that forms a path for writing the signal voltage to the first capacitance and a path for writing the threshold voltage to the second capacitance based on a control signal supplied via the control line, and that simultaneously performs an operation of writing the signal voltage to the first capacitance and an operation of writing the threshold voltage to the second capacitance. The present technology relates to, for example, an electronic device having the display device of the present technology.

[0007] FIG. 1 is a diagram showing an example of the configuration of a display device in a comparative example. FIG. 2 is a timing chart showing an example of the operation of the display device in the comparative example. FIG. 3 is a diagram showing a schematic configuration example of a display device according to a first embodiment of the present technology. FIG. 4 is a diagram showing an example of the configuration of a pixel circuit according to the first embodiment. FIG. 5 is a timing chart showing potential fluctuations at various points in the display device. FIG. 6A is a diagram showing the conduction state in each period when threshold voltage correction is performed, and FIG. 6B is a diagram showing the conduction state in each period when threshold voltage correction is not performed. FIG. 7 is a diagram showing an example of the configuration of a display device according to a second embodiment. FIG. 8A is a diagram showing the conduction state in each period when threshold voltage correction is performed, and FIG. 8B is a diagram showing the conduction state in each period when threshold voltage correction is not performed. FIG. 9 is a diagram showing an example of the configuration of a display device according to a third embodiment. FIG. 10 is a timing chart showing potential fluctuations at various points in the display device. FIG. 11A is a diagram showing the conduction state in each period when threshold voltage correction is performed, and FIG. 11B is a diagram showing the conduction state in each period when threshold voltage correction is not performed. FIG. 12 is a diagram illustrating an example of the configuration of a display device according to a fourth embodiment. FIG. 13 is a timing chart showing potential fluctuations at various points in the display device. FIG. 14A is a diagram illustrating a conduction state in each period when threshold voltage correction is performed, and FIG. 14B is a diagram illustrating a conduction state in each period when threshold voltage correction is not performed. FIG. 15 is a diagram illustrating an example of the configuration of a display device according to a fifth embodiment. FIG. 16 is a diagram for explaining an example of a configuration of a substrate mounting of pixel circuits. FIG. 17 is a perspective view illustrating an example of the appearance of a head-mounted display. FIG. 18 is a perspective view illustrating an example of the appearance of another head-mounted display. FIG. 19A is a front view illustrating an example of the appearance of a digital still camera. FIG. 19B is a rear view illustrating an example of the appearance of a digital still camera. FIG. 20 is a perspective view illustrating an example of the appearance of a television device. FIG. 21 is a perspective view illustrating an example of the appearance of a smartphone. FIG. 22A is a diagram illustrating an example of the interior of a vehicle viewed from the rear to the front of the vehicle. FIG. 22B is a diagram illustrating an example of the interior of a vehicle viewed from diagonally rear to diagonally front of the vehicle.

[0008] Hereinafter, embodiments of the present technology will be described with reference to the drawings. The description will be made in the following order. In this specification and the drawings, parts having substantially the same functions or configurations will be given the same reference numerals, and duplicated description will be omitted as appropriate. Furthermore, for the sake of simplicity, reference numerals may be omitted in the drawings. The following description will focus on the main parts related to the present technology, and does not exclude configurations or functions that are not shown or described. <1. Comparative Example> <2. First Embodiment> <3. Second Embodiment> <4. Third Embodiment> <5. Fourth Embodiment> <6. Fifth Embodiment> <7. Modified Examples> <8. Application Examples>

[0009] <1. Comparative Example> First, before describing an embodiment of the present technology, a comparative example to be used for comparison with the present technology will be described. FIG. 1 shows an example of the configuration of a display device in the comparative example. Note that FIG. 1 corresponds to FIG. 2 of the above-mentioned Patent Document 1 (JP 2015-034861 A). Pixels (pixel circuits) 20 shown in FIG. 1 are arranged in an array in a pixel section of the display device. The pixels 20 are connected to a write scanning unit 40 that outputs a signal WS via scanning lines 31, to a first driving scanning unit 50 that outputs a signal DS via first driving lines 32, to a second driving scanning unit 60 that outputs a signal AZ via second driving lines 33, and to a signal output unit 70 that outputs a reference voltage Vofs / signal voltage Vsig via signal lines 34.

[0010] The pixel 20 includes capacitors 26 and 27, transistors 22 to 25, and a light-emitting element 21. The transistors 22 to 25 are P-type MOSFETs. The gate of the transistor 23 is connected to a scanning line 31, the source is connected to a signal line 34, and the drain is connected to the gate of the transistor 22 and the capacitor 26. One end of the capacitor 27 is connected to a high-potential power supply Vcc (power supply voltage Vcc), and the other end is connected to the capacitor 26, the drain of the transistor 24, and the source of the transistor 22. One end of the capacitor 26 is connected to the other end of the capacitor 27, the drain of the transistor 24, and the source of the transistor 22, and the other end is connected to the drain of the transistor 23 and the gate of the transistor 22. The gate of the transistor 24 is connected to a first drive line 32, the source is connected to the power supply Vcc, and the drain is connected to the source of the transistor 22, the other end of the capacitor 27, and one end of the capacitor 26. The gate of transistor 22 is connected to the drain of transistor 23 and the other end of capacitor 26, the source is connected to the drain of transistor 24, the other end of capacitor 27, and one end of capacitor 26, and the drain is connected to the anode of light-emitting element 21 and the source of transistor 25. The gate of transistor 25 is connected to second drive line 33, the source is connected to the drain of transistor 22 and the anode of light-emitting element 21, and the drain is connected to low-potential power supply line 35 (power supply voltage Vcath). The anode of light-emitting element 21 is connected to the drain of transistor 22 and the source of transistor 25, and the cathode is connected to power supply line 35.

[0011] 2 is a timing chart showing an example of the operation of a display device in a comparative example. Note that FIG. 2 corresponds to FIG. 3 of the above-mentioned Patent Document 1 (JP 2015-034861 A). At time t0, signal DS is at a low level (low potential), and transistor 24 is in an on state (conductive state). Furthermore, signal WS is at a high level (high potential), and transistor 23 is in an off state (non-conductive state). Signal AZ switches from a high level to a low level, and transistor 25 switches from an off state to an on state.

[0012] Next, at time t1, signal WS goes low, turning transistor 23 on. Then, at time t2, signal DS goes high, turning transistor 24 off. This period from time t1 to t2 is the write period of the reference voltage Vofs. Next, at time t3, signal WS goes high, turning transistor 23 off. This period from time t2 to t3 is the threshold correction period in which the threshold voltage Vth of transistor 22 is corrected. After that, at time t4, the signal voltage Vsig of the video signal is output to the signal line 34, and at time t5, signal WS goes low, turning transistor 23 on. Then, at time t6, signal WS goes high, turning transistor 23 off. This period from time t5 to t6 is the signal write and mobility correction period. After that, at time t7, signal DS goes low, turning transistor 24 on. Next, at time t8, signal AZ goes high, turning transistor 25 off. As a result, the threshold voltage Vth of the transistor 22 is corrected, and the light emitting element 21 emits light with a luminance according to the signal voltage Vsig.

[0013] In this comparative example, as shown in part A of FIG. 2 , when the light-emitting element 21 emits light, the source potential of the transistor 22 fluctuates, causing the gate potential to fluctuate accordingly (bootstrap operation). However, because the fluctuation in the gate potential is affected by parasitic capacitance added to the gate, the threshold voltage Vth stored in the capacitance for correction may not be fully maintained, resulting in a degradation of image quality. Furthermore, as shown in part B of FIG. 2 , because the source potential of the transistor 22 fluctuates, the threshold voltage Vth is affected by the substrate bias effect, which fluctuates depending on the backgate voltage. Furthermore, as shown in part C of FIG. 2 , during signal writing from time t5 to t6, the device is affected by capacitive coupling determined by the storage capacitance (capacitor 26) and the auxiliary capacitance (capacitor 27), so only a portion of the input signal (specifically, the signal voltage corresponding to the capacitance distribution ratio) contributes to light emission. For these reasons, complex constant design (e.g., optimization of circuit element characteristics through simulation) is required to appropriately prevent a degradation of image quality.

[0014] Furthermore, in this comparative example, as shown in part D in FIG. 1 , the threshold voltage Vth and the signal voltage Vsig are held in the gate-source capacitance of the transistor 22 by capacitive coupling. In other words, the threshold voltage Vth and the signal voltage Vsig are written to a single capacitor. Because of this configuration, the threshold voltage Vth cannot be held when the signal voltage Vsig is written, and therefore the threshold voltage Vth must be corrected every horizontal period (every H). This makes it difficult to adapt to higher speeds and higher resolutions of display devices. Furthermore, because of this configuration, it is not possible to hold both the threshold voltage Vth and the signal voltage Vsig simultaneously, and as shown in part E in FIG. 2 , it is necessary to write the reference voltage Vofs, correct the threshold voltage Vth, and write the signal voltage Vsig in a chronological order. This makes it difficult to adapt to higher speeds, higher resolutions, and higher definitions of display devices due to the influence of the wiring time constant. In other words, it has been difficult to improve the image quality in a wide range of display devices, such as those with higher speeds, higher resolutions, larger sizes, and smaller sizes.

[0015] Taking these into consideration, the following embodiments and the like propose a technique that can improve image quality.

[0016] 2. First Embodiment [Schematic Configuration] Fig. 3 is a diagram showing a schematic configuration example of a display device according to a first embodiment of the present technology. The display device 1 shown in Fig. 3 is a device (electro-optical device) that displays images and the like using light-emitting elements. The light-emitting elements are current-driven light-emitting elements whose emission luminance changes according to the current value of an input current. The light-emitting elements are, for example, light-emitting diodes (LEDs). LEDs include LEDs used in micro LED displays and organic light-emitting diodes (OLEDs) used in organic electroluminescence (EL) displays. Organic EL displays include, for example, organic light-emitting diode microdisplays (OLED microdisplays). The following description will be given assuming that the display device 1 is an OLED microdisplay.

[0017] The display device 1 is, for example, a display mounted on an electronic device such as an electronic viewfinder (EVF) of a digital camera, AR glasses, or VR glasses. Note that the electronic devices to which the display device 1 can be applied are not limited to these. Specific configuration examples of electronic devices to which the display device 1 can be applied will be described later.

[0018] The display device 1 has a display panel P including a semiconductor substrate such as a silicon (Si) substrate. As shown in the figure, the display device 1 has a pixel unit 2, a first scanner 3, a second scanner 4, a third scanner 5, a fourth scanner 6, and a driver 7. The pixel unit 2, the first scanner 3, the second scanner 4, the third scanner 5, the fourth scanner 6, and the driver 7 are provided on the display panel P, for example, as shown in the figure.

[0019] Although not shown here, the pixel unit 2 has a plurality of pixels (pixel circuits) PIX arranged, for example, in a matrix of m rows and n columns (m and n are natural numbers). The pixel unit 2 is provided with pixels PIX that represent, for example, the three primary colors R (red), G (green), and B (blue), respectively, to represent a color image. Note that the number and arrangement of the pixels PIX and the color representation of the image are not limited to these, and a configuration that represents, for example, a monochrome (black and white) image may also be used. The configuration and operation of the pixel PIX will be described later.

[0020] The pixel section 2 has control lines WSL, DSL, AZSL1, and AZSL2 extending along the rows of the pixel PIX array, and a signal line (also referred to as a data line) SGL extending along the columns of the pixel PIX array. Each of the control lines WSL, DSL, AZSL1, and AZSL2 is provided for each pixel row, and the signal line SGL is provided for each pixel column. The control line WSL is connected to the output terminal of the corresponding row of the first scanner 3 and the group of pixels PIX in the corresponding row. The control line DSL is connected to the output terminal of the corresponding row of the second scanner 4 and the group of pixels PIX in the corresponding row. The control line AZSL1 is connected to the output terminal of the corresponding row of the third scanner 5 and the group of pixels PIX in the corresponding row. The control line AZSL2 is connected to the output terminal of the corresponding row of the fourth scanner 6 and the group of pixels PIX in the corresponding row. The signal line SGL is connected to the output terminal of the driver 7 in the corresponding column and to the group of pixels PIX in the corresponding column.

[0021] The first scanner 3, the second scanner 4, the third scanner 5, the fourth scanner 6, and the driver 7 are controlled by a control unit (not shown), such as a timing controller, included in the display device 1. The first scanner 3 generates a control signal WS and outputs it to a control line WSL. The second scanner 4 generates a control signal DS and outputs it to a control line DSL. The third scanner 5 generates a control signal AZ1 and outputs it to a control line AZSL1. The fourth scanner 6 generates a control signal AZ2 and outputs it to a control line AZSL2. The first scanner 3, the second scanner 4, the third scanner 5, and the fourth scanner 6 sequentially scan pixel rows of the pixel unit 2, for example, every horizontal period. The driver 7 distributes image data input from outside to each signal line SGL, converts the distributed image data into Data signals, and outputs them to the corresponding signal lines SGL of the pixel unit 2. These Data signals may be gamma-corrected. The first scanner 3, second scanner 4, third scanner 5, fourth scanner 6 and driver 7 drive the pixel section 2, whereby an image (including video) corresponding to the image data is displayed on the pixel section 2.

[0022] [Pixel Circuit Configuration] Figure 4 shows an example configuration of a pixel PIX according to this embodiment. This pixel PIX includes capacitors C11 and C12, transistors MP11 to MP17, and a light-emitting element EL. Transistors MP11 to MP17 are P-type MOSFETs. The gate of transistor MP11 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the drain of transistor MP12 and one end of capacitor C11. The gate of transistor MP12 is connected to a control line DSL, its source is connected to a high-potential power supply VCC (fixed potential VCC), and its drain is connected to the drain of transistor MP11 and one end of capacitor C11. The gate of transistor MP13 is connected to the control line WSL, its source is connected to the power supply VCC, and its drain is connected to the other end of capacitor C11 and one end of capacitor C12. One end of capacitor C11 is connected to the drains of transistors MP11 and MP12, and the other end is connected to the drain of transistor MP13 and one end of capacitor C12. One end of capacitor C12 is connected to the drain of transistor MP13 and the other end of capacitor C11, and the other end is connected to the gate of transistor MP14, the drain of transistor MP15, and the source of transistor MP16. The gate of transistor MP14 is connected to the other end of capacitor C12, the drain of transistor MP15, and the source of transistor MP16, its source is connected to power supply VCC, and its drain is connected to the sources of transistors MP15 and MP17. The gate of transistor MP15 is connected to control line AZSL1, its source is connected to the drain of transistor MP14 and the source of transistor MP17, and its drain is connected to the other end of capacitor C12, the gate of transistor MP14, and the source of transistor MP16. The gate of the transistor MP16 is connected to the control line AZSL2, the source is connected to the other end of the capacitor C12, the gate of the transistor MP14, and the drain of the transistor MP15, and the drain is connected to the initialization power supply Vini (initialization fixed potential Vini).The gate of the transistor MP17 is connected to the control line DSL, the source is connected to the drain of the transistor MP14 and the source of the transistor MP15, and the drain is connected to the anode of the light-emitting element EL. The light-emitting element EL is, for example, an organic EL light-emitting element, and has an anode connected to the drain of the transistor MP17 and a cathode connected to the low-potential power supply Vcath.

[0023] The transistors MP11 to MP17 may be transistors using low-temperature polycrystalline silicon (LTPS). Furthermore, at least one of the transistors MP11 to MP13 and MP15 to MP17 may be transistors using an oxide semiconductor. The capacitors C11 and C12 may be configured using, for example, a metal oxide semiconductor (MOS) capacitor. The capacitors C11 and C12 may also be configured using a metal insulator metal (MIM) capacitor, a metal oxide metal (MOM) capacitor, or the like. The initialization potential Vini is used to initialize the gate potential of the transistor MP14 to a predetermined potential, and is set to a value such that the gate-source voltage Vgs of the transistor MP14 is greater than the threshold voltage Vth of the transistor MP14 during operation in an initialization period (described later) (e.g., Vini<Vcath).

[0024] In this embodiment, transistor MP14 corresponds to the first transistor, transistor MP13 corresponds to the second transistor, transistor MP11 corresponds to the third transistor, and transistor MP12 corresponds to the fourth transistor. Furthermore, transistor MP15 corresponds to the fifth transistor, transistor MP17 corresponds to the sixth transistor, and transistor MP16 corresponds to the seventh transistor. Furthermore, capacitor C11 corresponds to the first capacitance, and capacitor C12 corresponds to the second capacitance. These transistors MP11 to MP17 form a switch circuit SC in pixel PIX. Based on control signals WSL, DSL, AZ1, and AZ2 supplied via control lines WSL, DSL, AZSL1, and AZSL2, the switch circuit SC forms a path for writing the signal voltage Vsig supplied from the signal line SGL to the capacitor C11 and a path for writing the threshold voltage Vth of the transistor MP14 to the capacitor C12, and simultaneously performs the operation of writing the signal voltage Vsig to the capacitor C11 and the operation of writing the threshold voltage Vth to the capacitor C12. This will be explained in detail below.

[0025] [Pixel Circuit Operation] Figures 5 and 6 are explanatory diagrams of an example of the operation of pixel PIX. Figure 5 is a timing chart showing fluctuations in the potentials of the control signals WS, DS, AZ1, and AZ2, the potential of the Data signal, and the potentials V1, V2, and V3 at predetermined locations in Figure 4. In this embodiment, the potential of the Data signal is the signal voltage Vsig of the video signal plus the power supply voltage VCC (VCC + Vsig). Furthermore, potential V1 represents the potential at one end of capacitor C11 (the write end of the Data signal), potential V2 represents the potential at the other end of capacitor C11 and one end of capacitor C12, and potential V3 represents the potential at the other end of capacitor C12, i.e., the gate potential of transistor MP14.

[0026] FIG. 6 shows the conduction state of each transistor. FIG. 6A shows the conduction state in each period when the threshold voltage Vth is corrected (corresponding to the operation example of FIG. 5 ), and FIG. 6B shows the conduction state in each period when the threshold voltage Vth is not corrected. Note that in FIGS. 6A and 6B , transistors marked as "switch-on" indicate a conductive state (active state), and transistors marked as "switch-off" indicate a non-conductive state (inactive state). Transistors MP11 to MP17 are P-channel transistors, and are in a conductive state when the potential of the corresponding gate-connected control lines WSL, DSL, AZSL1, and AZSL2 is at a low level (low potential), and in a non-conductive state when the potential is at a high level (high potential).

[0027] The bold arrows in FIGS. 6A and 6B indicate the flow of current through transistor MP14. The capacitance connected by the dashed lines in FIGS. 6A and 6B represents the parasitic capacitance added to the gate of transistor MP14. In FIGS. 6A and 6B, the changes in potentials V1 to V3 during each period are represented by symbols "a" to "f." The potentials corresponding to "a" to "f" are as shown in FIG. 5. For example, "a" means that the potential is VCC+Vsig.

[0028] First, an example of operation when correcting the threshold voltage Vth will be described with reference to FIGS. 5 and 6A. The period from time T1 to T2 shown in FIG. 5 is a light-emitting period at a certain timing. The light-emitting period is a period during which the light-emitting element EL is controlled to emit light. During the light-emitting period, the control signals WS, AZ1, and AZ2 are controlled to a high level, and the control signal DS is controlled to a low level. As a result, as shown in FIG. 6A, the transistors MP11, MP13, MP15, and MP16 are turned off (non-conductive), and the transistors MP12 and MP17 are turned on (conductive). Details of the operation during this light-emitting period will be described later.

[0029] The light-emitting period is followed by the extinction period from time T2 to time T3 shown in FIG. 5. The extinction period is a period during which the light-emitting element EL is controlled to an extinction state. During the extinction period, the control signals WS, DS, AZ1, and AZ2 are all controlled to a high level. As a result, as shown in FIG. 6A, transistors MP11 to MP13 and MP15 to MP17 are turned off. During this extinction period, transistor MP17 is controlled to an off state, so even if transistor MP14 is turned on, no light-emitting current Iel flows to the light-emitting element EL, and the light-emitting element EL is in an extinction state. Note that with transistor MP11 turned off, the potential of the DATA signal becomes VCC+Vsig of the corresponding frame.

[0030] The extinction period is followed by an overlapping period consisting of an initialization period from time T3 to T4 and a writing period from time T3 to T6, as shown in FIG. 5 . The initialization period is a period during which the gate potential of transistor MP14 is initialized (to potential Vini in this example). The operation during this initialization period is a write preparation operation that initializes the gate potential of transistor MP14 before writing the threshold voltage Vth to capacitor C12. The writing period is a period during which a video signal is written to pixel PIX, specifically, a period during which a signal voltage Vsig is written to capacitor C11. During this overlapping period of initialization and writing, the control signal DS is controlled to a high level, and the control signals WS, AZ1, and AZ2 are each controlled to a low level. As a result, as shown in FIG. 6A , transistors MP12 and MP17 are turned off, and transistors MP11, MP13, MP15, and MP16 are turned on. Therefore, the drain current of transistor MP14 flows to the initialization power supply Vini via transistors MP15 and MP16. By controlling transistor MP16 to the ON state, potential V3 becomes the initialization potential (potential Vini in this example). Furthermore, potential V1 becomes VCC+Vsig, and potential V2 becomes VCC, and the signal voltage Vsig is written to capacitor C11. Then, the gate-source voltage Vgs of transistor MP14 becomes greater than the threshold voltage Vth of transistor MP14. Therefore, during this overlapping period of initialization and writing, transistor MP14 is controlled to the ON state.

[0031] After this overlap period of initialization and writing, there is a threshold voltage (Vth) correction period and an overlap period of writing period from time T4 to time T5 shown in FIG. 5. The threshold voltage correction period is a period during which the threshold voltage Vth of transistor MP14 is corrected, in other words, a period during which the threshold voltage Vth of transistor MP14 is written to capacitor C12. During this overlap period of threshold voltage correction and writing, the control signals WS and AZ1 are controlled to a low level, and the control signals DS and AZ2 are controlled to a high level. Therefore, as shown in FIG. 6A, transistors MP11, MP13, and MP15 are turned on, and transistors MP12, MP16, and MP17 are turned off. As a result, the gate potential of transistor MP14 rises from Vini, and when the gate-source voltage Vgs of transistor MP14 reaches the threshold voltage Vth of transistor MP14, specifically, when potential V2 reaches VCC and potential V3 reaches VCC-Vth, transistor MP14 turns off and the threshold voltage Vth of transistor MP14 is held in capacitor C12. Note that potential V1 is controlled to VCC+Vsig, and potential V2 is controlled to VCC, and the signal voltage Vsig continues to be written to capacitor C11. When the writing of threshold voltage Vth to capacitor C12 is completed, the period during which the threshold voltage correction and writing are superimposed ends.

[0032] After the threshold voltage correction and write superimposition period ends, the system transitions to the write-only period (the period from time T5 to T6) shown in FIG. 5. During the write-only period, the control signal WS is controlled to a low level, and the control signals DS, AZ1, and AZ2 are controlled to a high level. Therefore, as shown in FIG. 6A, transistors MP11 and MP13 are turned on, and transistors MP12, MP15 to MP17 are turned off. This continues the writing of the signal voltage Vsig to capacitor C11. When the writing of the signal voltage Vsig to capacitor C11 ends, the write period ends. In this way, transistor MP13 is turned on when the signal voltage Vsig and threshold voltage Vth are written, so the same control signal WS as transistor MP11 can be used. Furthermore, transistor MP12 is turned on when the light-emitting element EL is to emit light, so the same control signal DS as transistor MP17 can be used. Using a common control signal reduces the number of scanners and wiring, thereby enabling the display device 1 to be more compact.

[0033] After the threshold voltage correction period and the write period end, the light-emitting period begins, from time T6 to time T7 shown in FIG. 5 . During the light-emitting period, as described above, the control signals WS, AZ1, and AZ2 are controlled to a high level, and the control signal DS is controlled to a low level. As a result, as shown in FIG. 6A , transistors MP11, MP13, MP15, and MP16 are turned off, and transistors MP12 and MP17 are turned on. Transistor MP14 generates an output current corresponding to the input voltage (gate-source voltage Igs), while capacitor C11 holds signal voltage Vsig and capacitor C12 holds threshold voltage Vth of transistor MP14. Therefore, transistor MP14 is turned on with variations in the threshold voltage Vth of transistor MP14, which occur during the manufacturing process, individually corrected, and a light-emitting current Iel corresponding to the signal voltage Vsig can be supplied to the light-emitting element EL via transistor MP14. The light-emitting element EL then emits light with a brightness corresponding to the light-emitting current Iel.

[0034] The drain-source current Ids of the transistor MP14 can be calculated by the following formula (1): where W is the gate width, L is the gate length, Cox is the gate insulating film capacitance per unit area, μ is the electron mobility, and Vth is the threshold voltage.

[0035] Here, assuming that the two storage capacitances (storage capacitances of capacitors C11 and C12) in pixel PIX are each C, the parasitic capacitance added to the gate of transistor MP14 is Cp, and further assuming that C>>Cp (Cp is sufficiently smaller than C), the gate-source voltage Vgs of transistor MP14 after correction of threshold voltage Vth and writing of signal voltage Vsig can be calculated by the following equation (2).

[0036] In this way, by arranging capacitors C11 and C12 in series between the gate and source of transistor MP14, Vgs can be simply calculated by addition. Furthermore, by providing capacitor C12 between capacitor C11 and the gate of transistor MP14, the threshold voltage Vth can be accurately added to the signal voltage Vsig. Incidentally, the potential V2 at this time can be calculated using the following equation (3), and the potential V3 can be calculated using the following equation (4).

[0037] Since the pixel PIX has a configuration in which the transistor MP13 is connected between the fixed potential VCC and the capacitors C11 and C12, a common reference potential (VCC) can be used when writing the signal voltage Vsig and the threshold voltage Vth, which makes it easy to calculate the potentials V1, V2, and V3 and simplifies the configuration of the pixel PIX.

[0038] From the above equations, the light emission current Iel can be expressed by the following equation (5).

[0039] Since the threshold voltage Vth is cancelled out in equation (5), the light emission current Iel can be calculated by the following equation (6).

[0040] Next, an example of operation when threshold voltage correction is not performed will be described with reference to FIG. 6B. In the example of operation shown in FIG. 6B, a signal voltage Vsig is written to capacitor C11 while capacitor C12 retains the threshold voltage Vth corrected in the previous frame. Unlike the case of FIG. 6A, pixel PIX does not perform the operations of the initialization period and threshold voltage correction period. In other words, it sequentially performs the three operations of the extinction period, writing period, and light emission period.

[0041] Therefore, in this case, the write period is the period during which only the write period described above is performed. That is, the control signal WS is controlled to a low level, and the control signals DS, AZ1, and AZ2 are controlled to a high level. As a result, as shown in FIG. 6B, transistors MP11 and MP13 are turned on, and transistors MP12 and MP15 to MP17 are turned off, and the signal voltage Vsig is written to capacitor C11. The operations during the light-emission period and the light-off period are the same as those in FIG. 6A, and therefore will not be described here.

[0042] In this way, in the display device 1, in frames after the threshold voltage Vth correction (operation during the initialization period and threshold voltage correction period) shown in FIG. 6A is performed, the threshold voltage Vth stored in capacitor C12 during that correction can be used. The threshold voltage Vth correction is generally performed only once (e.g., in the first frame). In subsequent frames, the threshold voltage Vth stored in capacitor C12 during that correction can be used; it does not need to be performed periodically. However, considering factors such as leakage current, it is preferable to perform the correction as needed (e.g., every few frames). The first scanner 3 to the fourth scanner 6 switch between performing and not performing this correction, for example, based on a control signal from the control unit in accordance with the initial settings. For example, in frames in which the threshold voltage Vth correction is performed, the first scanner 3 to the fourth scanner 6 generate control signals WS, DS, AZ1, and AZ2 for when the correction is performed, respectively. In frames in which the correction is not performed, the first scanner 3 to the fourth scanner 6 generate and output control signals WS, DS, AZ1, and AZ2 for when the correction is not performed, respectively. It should be noted that other methods may be used to control whether or not to perform this correction.

[0043] As described above, in the display device 1 according to the present embodiment, the source potential of the transistor MP14 included in the pixel PIX is fixed to a fixed potential VCC and does not fluctuate. Therefore, when the light-emitting element EL is caused to emit light, the gate potential of the transistor MP14 is not affected by parasitic capacitance due to bootstrap operation, and the threshold voltage Vth can be maintained in the capacitor C12, thereby achieving high image quality. Furthermore, because the source potential of the transistor MP14 is fixed to a fixed potential VCC, the threshold voltage Vth of the transistor MP14 does not fluctuate due to the substrate bias effect. Furthermore, the pixel PIX maintains the threshold voltage Vth in the capacitor C12 and the signal voltage Vsig in the capacitor C11. Because the threshold voltage Vth and the signal voltage Vsig are maintained separately in independent capacitors, they are not affected by capacitive coupling during signal writing, and all of the input signal contributes to light emission. This allows for lower input signal voltages and reduces power consumption. For these reasons, correcting the threshold voltage Vth of the transistor MP14 can further improve image quality, realize high image quality, and improve convenience. In addition, complex constant design to suppress degradation of image quality is no longer necessary.

[0044] Furthermore, in the display device 1 according to this embodiment, the pixel PIX is configured to store the threshold voltage Vth in the capacitor C12 and the signal voltage Vsig in the capacitor C11. This configuration allows the threshold voltage Vth and the signal voltage Vsig to be stored separately in independent capacitors, eliminating the need to perform a threshold voltage Vth correction operation every horizontal period. This allows the display device 1 to achieve higher speed, higher resolution, and higher definition. Furthermore, the operation of writing the signal voltage Vsig to the capacitor C11 and the operation of writing the threshold voltage Vth to the capacitor C12 (a correction operation that includes not only the operation during the threshold voltage correction period but also the operation during the initialization period) can be controlled separately, allowing the two operations to be superimposed. This allows the display device 1 to achieve higher speed and higher resolution without being affected by the wiring time constant. Specifically, since a longer write period can be provided, signal writing is possible even when the wiring connected to the pixel PIX is long and the time constant of the signal voltage Vsig is large, thereby allowing the display device 1 to be larger and faster. In particular, since the signal voltage Vth to the capacitor C11 and the threshold voltage Vth to the capacitor C12 can be simultaneously written to separate capacitances, the image quality of the display device 1 can be dramatically improved in a wide range.

[0045] Furthermore, in the display device 1 according to the present embodiment, the pixel PIX includes the transistor MP16, so that the gate potential of the transistor MP14 can be fixed to a fixed potential (potential Vini) during the initialization operation. This allows the threshold voltage Vth to be corrected from the same potential, thereby reducing variations in the threshold voltage Vth. This improves the accuracy of the threshold voltage Vth correction.

[0046] 7 shows an example of the configuration of a display device according to a second embodiment of the present technology. The display device 1 shown in Fig. 7 differs from the display device 1 of the first embodiment described above in the configuration of the pixels PIX. The other configurations are similar to those of the display device 1 of the first embodiment.

[0047] [Pixel Circuit Configuration] The pixel PIX shown in Fig. 7 differs from the pixel PIX shown in Fig. 4 in the connection of the transistor MP16. Specifically, the source of the transistor MP16 is connected to the drain of the transistor MP14, not the gate. The other configurations are the same as those shown in Fig. 4.

[0048] That is, this pixel PIX has capacitors C11 and C12, transistors MP11 to MP17, and a light-emitting element EL. The gate of transistor MP11 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the drain of transistor MP12 and one end of capacitor C11. The gate of transistor MP12 is connected to a control line DSL, its source is connected to a power supply VCC, and its drain is connected to the drain of transistor MP11 and one end of capacitor C11. The gate of transistor MP13 is connected to the control line WSL, its source is connected to the power supply VCC, and its drain is connected to the other end of capacitor C11 and one end of capacitor C12. One end of capacitor C11 is connected to the drains of transistors MP11 and MP12, respectively, and the other end is connected to the drain of transistor MP13 and one end of capacitor C12. One end of capacitor C12 is connected to the drain of transistor MP13 and the other end of capacitor C11, and the other end is connected to the gate of transistor MP14 and the drain of transistor MP15. The gate of transistor MP14 is connected to the other end of capacitor C12 and the drain of transistor MP15, its source is connected to power supply VCC, and its drain is connected to the sources of transistors MP15 to MP17. The gate of transistor MP15 is connected to control line AZSL1, its source is connected to the drain of transistor MP14 and the sources of transistors MP16 and MP17, and its drain is connected to the other end of capacitor C12 and the gate of transistor MP14. The gate of transistor MP16 is connected to control line AZSL2, its source is connected to the drain of transistor MP14 and the sources of transistors MP15 and MP17, and its drain is connected to the initialization power supply Vini. The gate of the transistor MP17 is connected to the control line DSL, the source is connected to the drain of the transistor MP14 and the sources of the transistors MP15 and MP16, and the drain is connected to the anode of the light-emitting element EL, whose anode is connected to the drain of the transistor MP17 and whose cathode is connected to the power supply Vcath.

[0049] [Operation of Pixel Circuit] Figure 8 shows the conduction state of the transistor in each period. Note that an example of operation of the pixel PIX in this embodiment is similar to that of the display device 1 in the first embodiment described above. Therefore, here, an example of operation of the pixel PIX will be briefly described using Figures 5 and 8. Figure 8A shows the conduction state in each period when the threshold voltage Vth is corrected (corresponding to the example of operation in Figure 5), and Figure 8B shows the conduction state in each period when the threshold voltage Vth is not corrected. The contents represented in each figure are as described in the first embodiment.

[0050] First, an example of operation when correcting the threshold voltage Vth will be described with reference to Fig. 5 and Fig. 8A. During the light emission period from time T1 to time T2 shown in Fig. 5, the control signals WS, AZ1, and AZ2 are controlled to a high level, and the control signal DS is controlled to a low level. As a result, as shown in Fig. 8A, transistors MP11, MP13, MP15, and MP16 are turned off, and transistors MP12 and MP17 are turned on.

[0051] 5, in the next extinction period from time T2 to time T3, the control signals WS, DS, AZ1, and AZ2 are all controlled to a high level, which turns off the transistors MP11 to MP13 and MP15 to MP17, and causes the light-emitting element EL to enter an extinction state, as shown in FIG.

[0052] During the overlap period of the next initialization period from time T3 to T4 and the write period from time T3 to T6 shown in FIG. 5, the control signal DS is controlled to a high level, and the control signals WS, AZ1, and AZ2 are each controlled to a low level. As a result, as shown in FIG. 8A, transistors MP12 and MP17 are turned off, and transistors MP11, MP13, MP15, and MP16 are turned on. Therefore, the drain current of transistor MP14 flows to power supply Vini via transistor MP16. With transistors MP15 and MP16 controlled to an on state, potential V3 becomes the initialization potential (potential Vini in this example). Potential V1 becomes VCC+Vsig, and potential V2 becomes VCC, and the signal voltage Vsig is written to capacitor C11. Then, the gate-source voltage Vgs of transistor MP14 becomes greater than the threshold voltage Vth of transistor MP14. Therefore, during the overlap period of the initialization and write periods, transistor MP14 is controlled to an on state.

[0053] During the overlap period of the threshold voltage correction and write periods from time T4 to T5 after the overlap period of the initialization and write periods shown in FIG. 5, the control signals WS and AZ1 are controlled to a low level, and the control signals DS and AZ2 are controlled to a high level. Therefore, as shown in FIG. 8A, transistors MP11, MP13, and MP15 are turned on, and transistors MP12, MP16, and MP17 are turned off. As a result, the gate potential of transistor MP14 rises from the initialization potential. When the gate-source voltage Vgs of transistor MP14 reaches the threshold voltage Vth of transistor MP14, transistor MP14 is turned off, and the threshold voltage Vth of transistor MP14 is held in capacitor C12. Note that potential V1 is controlled to VCC+Vsig, and potential V2 is controlled to VCC, and the signal voltage Vsig continues to be written to capacitor C11. Then, when writing of the threshold voltage Vth to the capacitor C12 is completed, the overlapping period of the threshold voltage correction and writing period ends.

[0054] During the write-only period from time T5 to time T6 after the overlap period of the threshold voltage correction and write periods shown in Figure 5, the control signal WS is controlled to a low level, and the control signals DS, AZ1, and AZ2 are controlled to a high level. Therefore, as shown in Figure 8A, transistors MP11 and MP13 are turned on, and transistors MP12, MP15 to MP17 are turned off, and the signal voltage Vsig continues to be written to capacitor C11. When the writing of the signal voltage Vsig to capacitor C11 is completed, the write period ends.

[0055] During the light-emitting period from time T6 to time T7 after the threshold voltage correction period and the write period shown in FIG. 5 have ended, the control signals WS, AZ1, and AZ2 are controlled to a high level, and the control signal DS is controlled to a low level. As a result, as shown in FIG. 8A, transistors MP11, MP13, MP15, and MP16 are turned off, and transistors MP12 and MP17 are turned on. The signal voltage Vsig is held in capacitor C11, and the threshold voltage Vth of transistor MP14 is held in capacitor C12. As a result, the transistor MP14 is turned on with the variation in the threshold voltage Vth of transistor MP14 corrected, and an illumination current Iel corresponding to the signal voltage Vsig is supplied to the light-emitting element EL via transistor MP14. The light-emitting element EL then emits light at a brightness corresponding to the illumination current Iel.

[0056] Next, an example of operation when the threshold voltage is not corrected will be described with reference to FIG. 8B. In the example of operation shown in FIG. 8B, the signal voltage Vsig is written to the capacitor C11 while the threshold voltage Vth corrected in the previous frame remains held in the capacitor C12. That is, as in the first embodiment, three operations, namely, the extinction period, the write period, and the light emission period, are performed sequentially. The control of whether or not to correct the threshold voltage Vth is the same as that described in the first embodiment above.

[0057] As described above, the display device 1 according to this embodiment achieves the same effects as those of the first embodiment. In other words, in the display device 1 according to this embodiment, when the light-emitting element EL emits light, the gate potential of the transistor MP14 is not affected by parasitic capacitance due to bootstrap operation, thereby achieving high image quality. Furthermore, the threshold voltage Vth of the transistor MP14 does not fluctuate due to the substrate bias effect. Furthermore, the pixel PIX is not affected by capacitive coupling during signal writing, and all input signals contribute to light emission, thereby achieving low power consumption. For these reasons, correcting the threshold voltage Vth of the transistor MP14 can further improve image quality, realize high image quality, and improve convenience. Furthermore, complex constant design to prevent degradation of image quality is no longer necessary.

[0058] Furthermore, in the display device 1 according to this embodiment, the threshold voltage Vth and the signal voltage Vsig can be separately stored in independent capacitors in the pixel PIX, eliminating the need to perform a threshold voltage Vth correction operation every horizontal period. This allows the display device 1 to achieve higher speed, higher resolution, and higher definition. Furthermore, the operation of writing the signal voltage Vsig to the capacitor C11 and the operation of correcting the threshold voltage Vth to the capacitor C12 can be superimposed. This allows the display device 1 to achieve higher speed and higher resolution without being affected by the wiring time constant, and further allows the display device 1 to be larger and faster. In particular, since the signal voltage Vth to the capacitor C11 and the threshold voltage Vth to the capacitor C12 can be simultaneously written to separate capacitors, the image quality of the display device 1 can be dramatically and widely improved.

[0059] Furthermore, in the display device 1 according to this embodiment, the pixel PIX has the transistor MP16, which reduces the variation in reaching the threshold voltage Vth and improves the correction accuracy of the threshold voltage Vth.

[0060] Here, the above-described equation (6) is also applied to this embodiment, but it is preferable that the parasitic capacitance Cp shown in equation (6) be as small as possible. In the display device 1 according to this embodiment, transistor MP16 is connected to the gate potential of transistor MP14 via transistor MP15. That is, the source of transistor MP16 is not connected to the gate of transistor MP14, but is connected to the drain of transistor MP14 and the sources of transistors MP15 and MP17. This reduces the parasitic capacitance added to the gate of transistor MP14. This allows for accurate correction of the threshold voltage Vth.

[0061] 4. Third Embodiment Fig. 9 shows a configuration example of a display device according to a third embodiment of the present technology. The display device 1 shown in Fig. 9 differs from the display device 1 of the first embodiment described above in that it does not use the fourth scanner 6, the control line AZSL2, and the transistor MP16. The other configurations are the same as those of the display device 1 of the first embodiment. Note that in this embodiment, the control signal AZ1 in the first embodiment is referred to as the control signal AZ, and the control line AZSL1 is referred to as the control line AZSL.

[0062] [Pixel Circuit Configuration] That is, this pixel PIX has capacitors C11 and C12, transistors MP11 to MP15 and MP17, and a light-emitting element EL. The gate of transistor MP11 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the drain of transistor MP12 and one end of capacitor C11. The gate of transistor MP12 is connected to a control line DSL, its source is connected to a power supply VCC, and its drain is connected to the drain of transistor MP11 and one end of capacitor C11. The gate of transistor MP13 is connected to the control line WSL, its source is connected to the power supply VCC, and its drain is connected to the other end of capacitor C11 and one end of capacitor C12. One end of capacitor C11 is connected to the drains of transistors MP11 and MP12, respectively, and the other end is connected to the drain of transistor MP13 and one end of capacitor C12. One end of capacitor C12 is connected to the drain of transistor MP13 and the other end of capacitor C11, and the other end is connected to the gate of transistor MP14 and the drain of transistor MP15. The gate of transistor MP14 is connected to the other end of capacitor C12 and the drain of transistor MP15, its source is connected to power supply VCC, and its drain is connected to the sources of transistors MP15 and MP17. The gate of transistor MP15 is connected to control line AZSL, its source is connected to the drain of transistor MP14 and the source of transistor MP17, and its drain is connected to the other end of capacitor C12 and the gate of transistor MP14. The gate of transistor MP17 is connected to control line DSL, its source is connected to the drain of transistor MP14 and the source of transistor MP15, and its drain is connected to the anode of light-emitting element EL. The anode of light-emitting element EL is connected to the drain of transistor MP17, and its cathode is connected to power supply Vcath.

[0063] [Operation of Pixel Circuit] Figures 10 and 11 are explanatory diagrams of an example of operation of pixel PIX. Figure 10 is a timing chart showing fluctuations of each potential. Figure 11A shows the conduction state in each period when the threshold voltage Vth is corrected (corresponding to the example operation of Figure 10), and Figure 11B shows the conduction state in each period when the threshold voltage Vth is not corrected. The contents shown in each figure are the same as those explained in the first embodiment.

[0064] First, an example of operation when correcting the threshold voltage Vth will be described with reference to Figures 10 and 11A. During the light emission period from time T1 to time T2 shown in Figure 10, the control signals WS and AZ are controlled to a high level, and the control signal DS is controlled to a low level. As a result, as shown in Figure 11A, transistors MP11, MP13, and MP15 are turned off, and transistors MP12 and MP17 are turned on.

[0065] During the next extinction period from time T2 to time T3 shown in Figure 10, the control signals WS, DS, and AZ are all controlled to a high level. As a result, as shown in Figure 11A, transistors MP11 to MP13, MP15, and MP17 are turned off, and the light-emitting element EL is in an extinction state. This extinction causes each of the potentials V1 to V3 to decrease. For example, the potential V1 becomes smaller than VCC.

[0066] During the next initialization period from time T3 to time T4 shown in FIG. 10, the control signal WS is controlled to a high level, and the control signals DS and AZ are controlled to a low level. As a result, as shown in FIG. 11A, transistors MP11 and MP13 are turned off, and transistors MP12, MP15, and MP17 are turned on. This causes the potentials V1 and V2 to drop further. The potential V3 drops further compared to the potentials V1 and V2 and becomes the initialization potential. Then, the gate-source voltage Vgs of transistor MP14 becomes greater than the threshold voltage Vth of transistor MP14. Therefore, during this initialization period, transistor MP14 is controlled to an on state.

[0067] After the initialization period, as shown in FIG. 10, there is a superimposed period of the threshold voltage correction period from time T4 to T5 and the write period from time T4 to T6. During this period, the control signals WS and AZ are controlled to a low level, and the control signal DS is controlled to a high level. Therefore, as shown in FIG. 11A, transistors MP11, MP13, and MP15 are turned on, and transistors MP12 and MP17 are turned off. As a result, the drain current of transistor MP14 flows through transistor MP15, and the gate potential of transistor MP14 rises. Then, when the gate-source voltage Vgs of transistor MP14 reaches the threshold voltage Vth of transistor MP14, transistor MP14 is turned off, and the threshold voltage Vth of transistor MP14 is held in capacitor C12. Note that potential V1 is controlled to VCC+Vsig, potential V2 is controlled to VCC, and the signal voltage Vsig is written to capacitor C11. Then, when writing of the threshold voltage Vth to the capacitor C12 is completed, the overlapping period of the threshold voltage correction and writing period ends.

[0068] During the write-only period from time T5 to time T6 after the overlap period of the threshold voltage correction and write periods shown in Figure 10, the control signal WS is controlled to a low level, and the control signals DS and AZ are controlled to a high level. Therefore, as shown in Figure 11A, transistors MP11 and MP13 are controlled to an on state, and transistors MP12, MP15, and MP17 are controlled to an off state, and the signal voltage Vsig continues to be written to capacitor C11. When the writing of the signal voltage Vsig to capacitor C11 is completed, the write period ends.

[0069] During the light-emitting period from time T6 to time T7 after the threshold voltage correction period and the write period have ended, as shown in FIG. 10, the control signals WS and AZ are controlled to a high level, and the control signal DS is controlled to a low level. As a result, as shown in FIG. 11A, transistors MP11, MP13, and MP15 are turned off, and transistors MP12 and MP17 are turned on. The signal voltage Vsig is held in capacitor C11, and the threshold voltage Vth of transistor MP14 is held in capacitor C12. As a result, the transistor MP14 is turned on with the variation in the threshold voltage Vth of transistor MP14 corrected, and an illumination current Iel corresponding to the signal voltage Vsig is supplied to the light-emitting element EL via transistor MP14. The light-emitting element EL then emits light at a brightness corresponding to the illumination current Iel.

[0070] Next, referring to FIG. 11B, an example of operation when threshold voltage correction is not performed will be described. In the example of operation shown in FIG. 11B, a signal voltage Vsig is written to capacitor C11 while capacitor C12 holds the threshold voltage Vth corrected in the previous frame. That is, as in the first embodiment, three operations, namely, an extinction period, a writing period, and an emission period, are performed sequentially. This writing period is a period in which operation is the same as the period in FIG. 11A in which only writing is performed. Note that the control of whether or not to perform correction is the same as that described in the first embodiment above.

[0071] As described above, the display device 1 according to this embodiment achieves the same effects as those of the first embodiment. In other words, in the display device 1 according to this embodiment, when the light-emitting element EL emits light, the gate potential of the transistor MP14 is not affected by parasitic capacitance due to bootstrap operation, thereby achieving high image quality. Furthermore, the threshold voltage Vth of the transistor MP14 does not fluctuate due to the substrate bias effect. Furthermore, the pixel PIX is not affected by capacitive coupling during signal writing, and all input signals contribute to light emission, thereby achieving low power consumption. For these reasons, correcting the threshold voltage Vth of the transistor MP14 can further improve image quality, realize high image quality, and improve convenience. Furthermore, complex constant design to prevent degradation of image quality is no longer necessary.

[0072] Furthermore, in the display device 1 according to this embodiment, the threshold voltage Vth and the signal voltage Vsig can be separately stored in independent capacitors in the pixel PIX, eliminating the need to perform a threshold voltage Vth correction operation every horizontal period. This allows the display device 1 to achieve higher speed, higher resolution, and higher definition. Furthermore, the operation of writing the signal voltage Vsig to the capacitor C11 and the operation of correcting the threshold voltage Vth to the capacitor C12 can be superimposed. This allows the display device 1 to achieve higher speed and higher resolution without being affected by the wiring time constant, and further allows the display device 1 to be larger and faster. In particular, since the signal voltage Vth to the capacitor C11 and the threshold voltage Vth to the capacitor C12 can be simultaneously written to separate capacitors, the image quality of the display device 1 can be dramatically and widely improved.

[0073] Furthermore, the display device 1 according to the present embodiment does not use the transistor MP16 used in the first embodiment. This reduces the parasitic capacitance added to the gate of the transistor MP14. This allows for accurate correction of the threshold voltage Vth.

[0074] Furthermore, in the display device 1 according to this embodiment, the transistor MP16, the control line AZSL2, and the fourth scanner 6 are not required, so the number of switches and scanners can be reduced, and the display device 1 can be made higher-definition and have a narrower frame.

[0075] 5. Fourth Embodiment Fig. 12 shows a configuration example of a display device according to a fourth embodiment of the present technology. The display device 1 shown in Fig. 12 differs from the display device 1 of the first embodiment described above in the configuration of the pixel PIX. The other configuration is the same as that of the display device 1 of the first embodiment. Specifically, this pixel PIX has a configuration in which the arrangements of the transistor MP12 and the capacitor C11 shown in Fig. 4 are swapped. The other configuration is the same as that shown in Fig. 4.

[0076] That is, this pixel PIX has capacitors C11 and C12, transistors MP11 to MP17, and a light-emitting element EL. The gate of transistor MP11 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the capacitor C11 and the source of transistor MP12. One end of capacitor C11 is connected to a power supply VCC, and the other end is connected to the drain of transistor MP11 and the source of transistor MP12. The gate of transistor MP12 is connected to a control line DSL, its source is connected to the drain of transistor MP11 and the other end of capacitor C11, and its drain is connected to the drain of transistor MP13 and one end of capacitor C12. The gate of transistor MP13 is connected to the control line WSL, its source is connected to the power supply VCC, and its drain is connected to the drain of transistor MP12 and one end of capacitor C12. One end of capacitor C12 is connected to the drains of transistors MP12 and MP13, and the other end is connected to the gate of transistor MP14, the drain of transistor MP15, and the source of transistor MP16. The gate of transistor MP14 is connected to the other end of capacitor C12, the drain of transistor MP15, and the source of transistor MP16, its source is connected to power supply VCC, and its drain is connected to the sources of transistors MP15 and MP17. The gate of transistor MP15 is connected to control line AZSL1, its source is connected to the drain of transistor MP14 and the source of transistor MP17, and its drain is connected to the other end of capacitor C12, the gate of transistor MP14, and the source of transistor MP16. The gate of transistor MP16 is connected to control line AZSL2, its source is connected to the other end of capacitor C12, the gate of transistor MP14, and the drain of transistor MP15, and its drain is connected to initialization power supply Vini. The gate of the transistor MP17 is connected to the control line DSL, the source is connected to the drain of the transistor MP14 and the source of the transistor MP15, and the drain is connected to the anode of the light-emitting element EL.The anode of the light-emitting element EL is connected to the drain of the transistor MP17, and the cathode is connected to the power supply Vcath.

[0077] [Pixel Circuit Operation] FIGS. 13 and 14 are explanatory diagrams of an example of the operation of pixel PIX. FIG. 13 is a timing chart showing the fluctuations of each potential. In this embodiment, the potential of the Data signal is signal voltage Vsig. Potential V1 represents the potential at the other end of capacitor C11 (the write end of the Data signal), potential V2 represents the potential at one end of capacitor C12, and potential V3 represents the potential at the other end of capacitor C12, i.e., the gate potential of transistor MP14. FIG. 14A shows the conduction state in each period when the threshold voltage Vth is corrected (corresponding to the operation example of FIG. 13), and FIG. 14B shows the conduction state in each period when the threshold voltage Vth is not corrected. The contents shown in each diagram are as described in the first embodiment.

[0078] First, an example of operation when correcting the threshold voltage Vth will be described with reference to Figures 13 and 14A. During the light emission period from time T1 to time T2 shown in Figure 13, the control signals WS, AZ1, and AZ2 are controlled to a high level, and the control signal DS is controlled to a low level. As a result, as shown in Figure 14A, transistors MP11, MP13, MP15, and MP16 are turned off, and transistors MP12 and MP17 are turned on.

[0079] 13, in the next extinction period from time T2 to time T3, the control signals WS, DS, AZ1, and AZ2 are all controlled to a high level, which turns off the transistors MP11 to MP13 and MP15 to MP17, and causes the light-emitting element EL to enter an extinction state, as shown in FIG.

[0080] During the overlapping period of the next initialization period from time T3 to T4 and the write period from time T3 to T6 shown in FIG. 13, the control signal DS is controlled to a high level, and the control signals WS, AZ1, and AZ2 are each controlled to a low level. As a result, as shown in FIG. 14A, transistors MP12 and MP17 are turned off, and transistors MP11, MP13, MP15, and MP16 are turned on. Therefore, the drain current of transistor MP14 flows to power supply Vini via transistors MP15 and MP16. With transistor MP16 turned on, potential V3 becomes the initialization potential (potential Vini in this example). Furthermore, potential V1 becomes VCC-Vsig, and potential V2 becomes VCC, and the signal voltage Vsig is written to capacitor C11. Then, the gate-source voltage Vgs of transistor MP14 becomes greater than the threshold voltage Vth of transistor MP14. Therefore, during the overlapping period of the initialization and writing periods, the transistor MP14 is controlled to be in the ON state.

[0081] During the overlap period of the threshold voltage correction and write periods from time T4 to T5 after the overlap period of the initialization and write periods shown in FIG. 13 , the control signals WS and AZ1 are controlled to a low level, and the control signals DS and AZ2 are controlled to a high level. Therefore, as shown in FIG. 14A , transistors MP11, MP13, and MP15 are turned on, and transistors MP12, MP16, and MP17 are turned off. This causes the gate potential of transistor MP14 to rise from the initialization potential (potential Vini). When the gate-source voltage Vgs of transistor MP14 reaches the threshold voltage Vth of transistor MP14, transistor MP14 is turned off, and the threshold voltage Vth of transistor MP14 is held in capacitor C12. Furthermore, potential V1 is controlled to VCC-Vsig, and potential V2 is controlled to VCC, and the signal voltage Vsig continues to be written to capacitor C11. Then, when writing of the threshold voltage Vth to the capacitor C12 is completed, the overlapping period of the threshold voltage correction and writing period ends.

[0082] During the write-only period from time T5 to time T6 after the overlap period of the threshold voltage correction and write periods shown in Figure 13, the control signal WS is controlled to a low level, and the control signals DS, AZ1, and AZ2 are controlled to a high level. Therefore, as shown in Figure 14A, transistors MP11 and MP13 are turned on, and transistors MP12, MP15 to MP17 are turned off, and the signal voltage Vsig continues to be written to capacitor C11. When the writing of the signal voltage Vsig to capacitor C11 is completed, the write period ends.

[0083] During the light-emitting period from time T6 to time T7 after the threshold voltage correction period and the write period shown in FIG. 13 end, the control signals WS, AZ1, and AZ2 are controlled to a high level, and the control signal DS is controlled to a low level. As a result, as shown in FIG. 14A, transistors MP11, MP13, MP15, and MP16 are turned off, and transistors MP12 and MP17 are turned on. The signal voltage Vsig is held in capacitor C11, and the threshold voltage Vth of transistor MP14 is held in capacitor C12. As a result, the transistor MP14 is turned on with the variation in the threshold voltage Vth of transistor MP14 corrected, and an illumination current Iel corresponding to the signal voltage Vsig is supplied to the light-emitting element EL via transistor MP14. The light-emitting element EL then emits light at a brightness corresponding to the illumination current Iel.

[0084] Next, referring to FIG. 14B, an example of operation when threshold voltage correction is not performed will be described. In the example of operation shown in FIG. 14B, a signal voltage Vsig is written to capacitor C11 while capacitor C12 holds the threshold voltage Vth corrected in the previous frame. That is, as in the first embodiment, three operations, namely, an extinction period, a writing period, and an emission period, are performed sequentially. This writing period is a period in which operation is the same as the period in FIG. 14A in which only writing is performed. Note that the control of whether or not to perform correction is the same as that described in the first embodiment above.

[0085] As described above, the display device 1 according to this embodiment achieves the same effects as the first embodiment. In other words, in the display device 1 according to this embodiment, the source potential of the transistor MP14 in the pixel PIX is fixed to a fixed potential VCC and does not fluctuate. Therefore, when the light-emitting element EL is caused to emit light, the gate potential of the transistor MP14 is not affected by parasitic capacitance due to bootstrap operation, and the threshold voltage Vth can be maintained in the capacitor C12, thereby achieving high image quality. Furthermore, because the source potential of the transistor MP14 is fixed to a fixed potential VCC, the threshold voltage Vth of the transistor MP14 does not fluctuate due to the substrate bias effect. Furthermore, the pixel PIX maintains the threshold voltage Vth in the capacitor C12 and the signal voltage Vsig in the capacitor C11. Because the threshold voltage Vth and the signal voltage Vsig are maintained separately in independent capacitors, they are not affected by capacitive coupling during signal writing, and all of the input signal contributes to light emission. This allows for lower input signal voltages and reduces power consumption. For these reasons, correcting the threshold voltage Vth of the transistor MP14 can further improve image quality, realize high image quality, and improve convenience. In addition, complex constant design to suppress degradation of image quality is no longer necessary.

[0086] Furthermore, in the display device 1 according to the present embodiment, the pixel PIX is configured such that the capacitor C12 holds the threshold voltage Vth and the capacitor C11 holds the signal voltage Vsig. This configuration allows the threshold voltage Vth and the signal voltage Vsig to be stored separately in independent capacitors, eliminating the need to perform a threshold voltage Vth correction operation every horizontal period. This allows the display device 1 to achieve higher speed, higher resolution, and higher definition. Furthermore, the operation of writing the signal voltage Vsig to the capacitor C11 and the operation of correcting the threshold voltage Vth to the capacitor C12 can be controlled separately, allowing the two operations to be superimposed. This allows the display device 1 to achieve higher speed and higher resolution without being affected by the wiring time constant. Specifically, since a longer write period can be provided, signal writing is possible even when the wiring connected to the pixel PIX is long and the time constant of the signal voltage Vsig is large, thereby enabling the display device 1 to be larger and faster. In particular, since the signal voltage Vth to the capacitor C11 and the threshold voltage Vth to the capacitor C12 can be simultaneously written to separate capacitances, the image quality of the display device 1 can be dramatically improved in a wide range.

[0087] Furthermore, in the display device 1 according to the present embodiment, the pixel PIX includes the transistor MP16, and therefore the gate potential of the transistor MP14 can be fixed to a fixed potential (potential Vini) during the initialization operation. This allows the correction of the threshold voltage Vth to be started from the same potential, reduces variations in reaching the threshold voltage Vth, and improves the correction accuracy of the threshold voltage Vth.

[0088] Furthermore, in the display device 1 according to the present embodiment, the switch configuration is changed by swapping the positions of the transistor MP12 and the capacitor C11, so that the input potential from the signal line SGL can be lowered to Vsig, thereby achieving low power consumption.

[0089] 6. Fifth Embodiment In the first embodiment, an example was shown in which P-channel transistors MP11 to MP17 were used, but N-channel transistors may also be used. FIG. 15 shows an example of the configuration of a display device 1 according to this embodiment. This display device 1 differs from the display device 1 according to the first embodiment in the configuration of the pixel PIX. The other configuration is similar to that of the display device 1 according to the first embodiment. Specifically, in the pixel PIX shown in FIG. 15, all transistors other than transistor MP14 are N-channel transistors. The other configuration is similar to that of the pixel PIX according to the first embodiment described above.

[0090] That is, this pixel PIX has capacitors C11 and C12, transistors MN11 to MN13, MN15 to MN17, transistor MP14, and a light-emitting element EL. Transistors MN11 to MN13, MN15 to MN17 are N-type MOSFETs, and transistor MP14 is a P-type MOSFET. The gate of transistor MN11 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the source of transistor MN12 and one end of capacitor C11. The gate of transistor MN12 is connected to a control line DSL, the drain is connected to a power supply VCC, and the source is connected to the source of transistor MN11 and one end of capacitor C11. The gate of transistor MN13 is connected to the control line WSL, the drain is connected to the power supply VCC, and the source is connected to the other end of capacitor C11 and one end of capacitor C12. One end of capacitor C11 is connected to the sources of transistors MN11 and MN12, and the other end is connected to the source of transistor MN13 and one end of capacitor C12. One end of capacitor C12 is connected to the source of transistor MN13 and the other end of capacitor C11, and the other end is connected to the gate of transistor MP14, the source of transistor MN15, and the drain of transistor MN16. The gate of transistor MP14 is connected to the other end of capacitor C12, the source of transistor MN15, and the drain of transistor MN16, the source is connected to power supply VCC, and the drain is connected to the drains of transistors MN15 and MN17. The gate of transistor MN15 is connected to control line AZSL1, the drain is connected to the drains of transistors MP14 and MN17, and the source is connected to the other end of capacitor C12, the gate of transistor MP14, and the drain of transistor MN16. The gate of the transistor MN16 is connected to the control line AZSL2, the drain is connected to the other end of the capacitor C12, the gate of the transistor MP14, and the source of the transistor MN15, and the source is connected to the initialization power supply Vini.The gate of the transistor MN17 is connected to the control line DSL, the drain is connected to the drain of the transistor MP14 and the drain of the transistor MN15, and the source is connected to the anode of the light-emitting element EL, the anode of which is connected to the source of the transistor MP17, and the cathode is connected to the power supply Vcath.

[0091] The transistors MN11 to MN13 and MN15 to MN17 may be transistors using low temperature polysilicon (LTPS), or at least one of the transistors MN11 to MN13 and MN15 to MN17 may be a transistor using an oxide semiconductor.

[0092] In this embodiment, transistor MP14 corresponds to the first transistor, transistor MN13 corresponds to the second transistor, transistor MN11 corresponds to the third transistor, and transistor MN12 corresponds to the fourth transistor. Furthermore, transistor MN15 corresponds to the fifth transistor, transistor MN17 corresponds to the sixth transistor, and transistor MN16 corresponds to the seventh transistor. Furthermore, capacitor C11 corresponds to the first capacitance, and capacitor C12 corresponds to the second capacitance. These transistors MN11 to MN13, MN15 to MN17, and transistor MP14 constitute a switch circuit SC in pixel PIX, similar to the first embodiment described above.

[0093] 16 shows an example of the substrate mounting configuration of the pixel PIX according to this embodiment. The pixel PIX uses, for example, IGZO (Indium Gallium Zinc Oxide) as an example of a metal oxide semiconductor, and adopts an IGZO / Si stacked structure. Each element is disposed on an OLED substrate 8, an IGZO substrate 9, and a Si substrate 10.

[0094] For example, in each pixel PIX included in the display device 1, the light-emitting element EL is disposed on an OLED substrate 8. Furthermore, in each pixel PIX, the transistor MP14 (drive transistor), which is a P-type MOSFET, is disposed on a Si (silicon) substrate 10, which is characterized by a high current flow rate. Furthermore, in each pixel PIX, the switching transistors MN11 to MN13 and MN15 to MN17, which are N-type MOSFETs, are disposed on an IGZO substrate 9, which is characterized by low leakage current. Furthermore, the first scanner 3, the second scanner 4, the third scanner 5, the fourth scanner 6, and the driver 7 (collectively referred to as the driver circuit) are, for example, configured using complementary metal oxide semiconductors (CMOS) and disposed on the Si substrate 10. Note that, as shown in FIG. 16 , the transistor MN17 (light-emission control transistor) disposed between the transistor MP14 and the light-emitting element EL is preferably a P-channel transistor MP17, as in the first embodiment, and disposed on the Si substrate 10. This further improves current flow, allowing the light-emitting element EL to emit light more effectively.

[0095] An example of the operation of this pixel PIX is the same as that of the pixel PIX of the first embodiment. However, because the transistors MN11 to MN13 and MN15 to MN17 are N-channel transistors, the control signals WS, DS, AZ1, and AZ2 are each conductive when high-level and non-conductive when low-level. Therefore, each control signal is generated and output accordingly.

[0096] As described above, the display device 1 according to this embodiment achieves the same effects as those of the first embodiment. In other words, in the display device 1 according to this embodiment, when the light-emitting element EL emits light, the gate potential of the transistor MP14 is not affected by parasitic capacitance due to bootstrap operation, thereby achieving high image quality. Furthermore, the threshold voltage Vth of the transistor MP14 does not fluctuate due to the substrate bias effect. Furthermore, the pixel PIX is not affected by capacitive coupling during signal writing, and all input signals contribute to light emission, thereby achieving low power consumption. For these reasons, correcting the threshold voltage Vth of the transistor MP14 can further improve image quality, realize high image quality, and improve convenience. Furthermore, complex constant design to prevent degradation of image quality is no longer necessary.

[0097] Furthermore, in the display device 1 according to this embodiment, the threshold voltage Vth and the signal voltage Vsig can be separately stored in independent capacitors in the pixel PIX, eliminating the need to perform a threshold voltage Vth correction operation every horizontal period. This allows the display device 1 to achieve higher speed, higher resolution, and higher definition. Furthermore, the operation of writing the signal voltage Vsig to the capacitor C11 and the operation of correcting the threshold voltage Vth to the capacitor C12 can be superimposed. This allows the display device 1 to achieve higher speed and higher resolution without being affected by the wiring time constant, and further allows the display device 1 to be larger and faster. In particular, since the signal voltage Vth to the capacitor C11 and the threshold voltage Vth to the capacitor C12 can be simultaneously written to separate capacitors, the image quality of the display device 1 can be dramatically and widely improved.

[0098] Furthermore, in the display device 1 according to this embodiment, the pixel PIX has the transistor MN16, which reduces the variation in reaching the threshold voltage Vth and improves the correction accuracy of the threshold voltage Vth.

[0099] Furthermore, in the display device 1 according to this embodiment, a P-channel transistor MP14 is formed on the Si substrate 10 as a drive transistor, and N-channel transistors MN11 to MN13 and MN15 to MN17 are formed on the low-leakage IGZO substrate 9 as other switch transistors. This IGZO / Si stacking allows for element distribution, contributing to higher resolution and yield of the display device 1. Forming the P-channel transistor MP17 as a light-emission control transistor on Si and the drive circuit (CMOS) on the Si substrate can be even more effective. The IGZO substrate 9 may be an oxide semiconductor substrate made of other oxides. Examples of conductive oxides that can be used include ITO (indium tin oxide) and IZO (indium zinc oxide). The stacking order and number of layers can be changed as appropriate. This combination of Si and oxide semiconductors allows for the miniaturization of the display device 1. By selectively forming the drive transistor (which may include a light-emitting control transistor and a drive circuit driver) and other switch transistors on different substrates according to their respective characteristics, it is possible to appropriately obtain effects such as improved image quality, miniaturization, enlargement, high definition, and low power consumption of the display device 1.

[0100] <7. Modifications> Although the embodiments of the present technology have been specifically described above, the content of the present technology is not limited to the above-described embodiments, and various modifications based on the technical concept of the present technology are possible. For example, the configurations, methods, processes, materials, shapes, and numerical values ​​of the above-described embodiments can be combined or substituted with each other as long as they do not deviate from the spirit of the present technology. Furthermore, one thing can be divided into two or more parts, and some parts can be omitted. Furthermore, as long as the present technology is applicable, each of the above-described configurations can be appropriately deleted, modified, or added with other configurations, or replaced with alternative configurations.

[0101] In the above-described embodiment, the display device 1 is an OLED microdisplay, but the present technology is not limited to this. For example, the present technology may be applied to a display panel such as an SXRD (Silicon X-tal Reflective Display: registered trademark) used in a projector, or a phase modulation panel using an SLM (Spatial Light Modulator) for displaying holograms. In addition, the present technology may be applied to a panel such as an LCOS (Liquid crystal on silicon, LCoS is a trademark) or an HTPS (High Temperature Poly-Silicon) panel.

[0102] Furthermore, the present technology may be an appropriate combination of the above-described embodiments. For example, the configuration of the pixel PIX in the fourth embodiment may be such that the connection of the transistor MP16 is changed as in the second embodiment, or such that the transistor MP16 is not used as in the third embodiment. Furthermore, for example, the pixel PIX in the fifth embodiment may be arranged and connected in the same manner as in the second to fourth embodiments.

[0103] Furthermore, the configuration, operation, arrangement, etc. of the drive circuit driver and the pixel PIX are not limited to those of the above-described embodiment and can be selected as appropriate as long as they do not interfere with the present technology. For example, as long as the same operational effect is achieved, the connections between the elements of the pixel PIX described above are not limited to direct connections, and they may be indirect connections, or other elements may be interposed. For example, the pixel PIX may receive a separate control signal from the scanner via a separate control line.

[0104] In the first embodiment described above, in order to miniaturize the scanner, the control signal WS controls the conduction states of the transistors MP11 and MP13, and the control signal DS controls the conduction states of the transistors MP12 and MP17, but these may be controlled by separate control signals.

[0105] Furthermore, in the above-described embodiment, an example has been given in which the write period overlaps with the entire initialization period and threshold voltage correction period, or the write period overlaps with the entire threshold voltage correction period. However, this is not limited to this; the above-described effect can be achieved by overlapping at least a portion of either the initialization period or the threshold voltage correction period with the write period. That is, the effect can be achieved by simultaneously performing the write operation of the signal line Vsig to the capacitor C11 and the write operation of the threshold voltage. "Performing these operations simultaneously" refers to simultaneous operation of the write operation of the signal line Vsig to the capacitor C11 and at least one of the initialization operation of the transistor MP14 and the write operation of the threshold voltage to the second capacitor. Furthermore, the simultaneous operation period need not be limited to the entire period of each operation, but may be simultaneous for only a portion of that period. Specifically, the operations may overlap for only a portion of that period.

[0106] 8. Application Examples Next, application examples of the display systems described in the above embodiments and modifications will be described. (Application Example 1) Fig. 17 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 on both sides of a glasses-shaped display unit 111 for wearing on the user's head. The techniques according to the above embodiments and the like can be applied to such a head-mounted display 110.

[0107] (Application Example 2) FIG. 18 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0108] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0109] (Application Example 3) Figures 19A and 19B show an example of the appearance of a digital still camera 130, with Figure 19A showing a front view and Figure 19B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 131. The grip 133 is provided on the left side of the front of the camera body 131, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0110] 20 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0111] 21 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0112] (Application Example 6) Figures 22A and 22B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 22A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 22B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0113] The vehicle in Figures 22A and 22B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 206.

[0114] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 22A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0115] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0116] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0117] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0118] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0119] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0120] The rear entertainment display 206 is attached to the back side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurements of the body temperature of the rear seat passengers by the temperature sensor 5.

[0121] The techniques according to the above-described embodiments can be applied to the center display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear entertainment display 206.

[0122] The present technology may also be configured as follows. (1) A display device including a pixel, a signal line, and a control line connected to the pixel, wherein the pixel includes: a first transistor that generates an output current according to an input voltage; a light-emitting element that emits light according to the output current of the first transistor; a first capacitance that holds a signal voltage supplied via the signal line; a second capacitance that holds a threshold voltage of the first transistor; and a switch circuit that forms a path for writing the signal voltage to the first capacitance and a path for writing the threshold voltage to the second capacitance based on a control signal supplied via the control line, and that simultaneously writes the signal voltage to the first capacitance and the threshold voltage to the second capacitance. (2) The display device according to (1), wherein the first capacitance and the second capacitance are connected in series between the gate and source of the first transistor. (3) The display device according to (2), wherein the second capacitance is provided between the first capacitance and the gate of the first transistor. (4) The display device according to (2) or (3), wherein the switch circuit has a second transistor between a fixed potential and the first capacitance and the second capacitance. (5) The display device according to (4), wherein the switch circuit has a third transistor provided between the signal line and one end of the first capacitance and a fourth transistor provided between the fixed potential and one end of the first capacitance, the second transistor is provided between the fixed potential and the other end of the first capacitance and one end of the second capacitance, and the other end of the second capacitance is connected to the gate of the first transistor. (6) The display device according to (4), wherein one end of the first capacitance is connected to the fixed potential, the switch circuit has a third transistor provided between the signal line and the other end of the first capacitance and a fourth transistor provided between the other end of the first capacitance and one end of the second capacitance, the second transistor is provided between the fixed potential and one end of the fourth transistor and the second capacitance, and the other end of the second capacitance is connected to the gate of the first transistor. (7) The display device according to (5) or (6), wherein the second transistor is controlled by a control signal common to the third transistor.(8) The display device according to any one of (1) to (7), wherein the source of the first transistor is connected to a fixed potential. (9) The display device according to any one of (1) to (8), wherein the switch circuit includes a fifth transistor provided between the gate and drain of the first transistor and a sixth transistor provided between the first transistor and the light-emitting element. (10) The display device according to any one of (1) to (9), wherein the operation of writing the threshold voltage to the second capacitor includes a write preparation operation of initializing a gate potential of the first transistor before writing the threshold voltage to the second capacitor. (11) The display device according to any one of (1) to (10), wherein the switch circuit includes a seventh transistor provided between the gate of the first transistor and an initialization potential that initializes the gate potential of the first transistor to a predetermined potential. (12) The display device according to (11), wherein the seventh transistor is connected to the gate potential of the first transistor via the fifth transistor. (13) The display device according to any one of (1) to (12), wherein the first transistor is a P-channel transistor, the switch circuit further includes an N-channel transistor, and the P-channel transistor is provided on a silicon substrate, and the N-channel transistor is provided on an oxide semiconductor substrate. (14) An electronic device including the display device according to any one of (1) to (13).

[0123] 1: Display device, 2: Pixel unit, 3: First scanner, 4: Second scanner, 5: Third scanner, 6: Fourth scanner, 7: Driver, 8: OLED substrate, 9: IGZO substrate, 10: Si substrate, WSL, DSL, AZSL, AZSL1, AZSL2: Control line, SGL: Signal line, PIX: Pixel, C11, C12: Capacitor, MP11 to MP17, MN11 to MN13, MN15 to MN17: Transistor, EL: Light-emitting element

Claims

1. A display device comprising a pixel, a signal line and a control line connected to the pixel, wherein the pixel comprises: a first transistor that generates an output current according to an input voltage; a light-emitting element that emits light according to the output current of the first transistor; a first capacitance that holds a signal voltage supplied via the signal line; a second capacitance that holds a threshold voltage of the first transistor; and a switch circuit that forms a path for writing the signal voltage to the first capacitance and a path for writing the threshold voltage to the second capacitance based on a control signal supplied via the control line, and simultaneously performs an operation of writing the signal voltage to the first capacitance and an operation of writing the threshold voltage to the second capacitance.

2. The display device according to claim 1, wherein the first capacitance and the second capacitance are connected in series between the gate and source of the first transistor.

3. The display device according to claim 2, wherein the second capacitance is provided between the first capacitance and the gate of the first transistor.

4. The display device according to claim 2, wherein the switch circuit has a second transistor between a fixed potential and the first capacitance and the second capacitance.

5. The display device according to claim 4, wherein the switch circuit has a third transistor provided between the signal line and one end of the first capacitance, and a fourth transistor provided between the fixed potential and one end of the first capacitance, the second transistor is provided between the fixed potential and the other end of the first capacitance and one end of the second capacitance, and the other end of the second capacitance is connected to the gate of the first transistor.

6. The display device of claim 4, wherein one end of the first capacitance is connected to the fixed potential, the switch circuit has a third transistor provided between the signal line and the other end of the first capacitance, and a fourth transistor provided between the other end of the first capacitance and one end of the second capacitance, the second transistor is provided between the fixed potential and one end of the fourth transistor and the second capacitance, and the other end of the second capacitance is connected to the gate of the first transistor.

7. The display device according to claim 5 or 6, wherein the second transistor is controlled by a control signal common to the third transistor.

8. The display device according to claim 1, wherein the source of the first transistor is connected to a fixed potential.

9. The display device according to claim 1, wherein the switch circuit comprises a fifth transistor provided between the gate and drain of the first transistor, and a sixth transistor provided between the first transistor and the light-emitting element.

10. The display device according to claim 1, wherein the operation of writing the threshold voltage to the second capacitance includes a write preparation operation of initializing a gate potential of the first transistor before writing the threshold voltage to the second capacitance.

11. The display device according to claim 1, wherein the switch circuit has a seventh transistor provided between the gate of the first transistor and an initialization potential that initializes the gate potential of the first transistor to a predetermined potential.

12. The display device according to claim 11, wherein the seventh transistor is connected to a gate potential of the first transistor via the fifth transistor.

13. The display device according to claim 1, wherein the first transistor is a P-channel transistor, the switch circuit further includes an N-channel transistor, the P-channel transistor is provided on a silicon substrate, and the N-channel transistor is provided on an oxide semiconductor substrate.

14. An electronic device comprising the display device according to claim 1.

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