Power conversion device

Abstract

This power conversion device comprises: a plurality of semiconductor packages constituting upper and lower arm circuits and electrically connected in parallel to each other; and a wiring board on which the plurality of semiconductor packages are mounted and which is electrically connected to each of the plurality of semiconductor packages. The plurality of semiconductor packages each include: a semiconductor element in which an electrode is formed on each surface; a first conductor that is connected to one of the electrodes of the semiconductor element and also to the high potential side of the upper and lower arm circuits; a second conductor that is connected to the other electrode of the semiconductor element and also to the low potential side of the upper and lower arm circuits; and a sealing component that seals the first conductor, the second conductor, and the semiconductor element such that a heat dissipation surface, which is a surface on the opposite side to a surface on the side where the semiconductor element is connected, is exposed in the second conductor body. The wiring board has a conductive member that is electrically connected to the heat dissipation surface of the second conductor body.

Description

Power Conversion Device

[0001] The present invention relates to a power conversion device.

[0002] Regarding measures to reduce inductance in a power conversion device, for example, Patent Document 1 listed below discloses a structure in which the high-potential side terminals and low-potential side terminals of adjacent semiconductor packages are arranged alternately to reduce inductance.

[0003] Japanese Patent Application Laid-Open No. 2023-62905

[0004] The technique described in Patent Document 1 has a problem in that it is not possible to suppress imbalances in currents flowing through a plurality of switching elements caused by differences in wiring inductance on the source side.

[0005] The power conversion device comprises: a plurality of semiconductor packages that form upper and lower arm circuits and are electrically connected in parallel to each other; and a wiring board on which the plurality of semiconductor packages are mounted and electrically connected to each of the plurality of semiconductor packages, wherein the plurality of semiconductor packages comprise a semiconductor element having electrodes formed on both sides, a first conductor connected to one electrode of the semiconductor element and the high potential side of the upper and lower arm circuit, a second conductor connected to the other electrode of the semiconductor element and the low potential side of the upper and lower arm circuit, and a sealing member that seals the first conductor, the second conductor, and the semiconductor element so that a heat dissipation surface of the second conductor, which is the surface opposite to the surface to which the semiconductor element is connected, is exposed; and the wiring board has a conductive member electrically connected to the heat dissipation surface of the second conductor.

[0006] According to the present invention, it is possible to provide a power conversion device that realizes suppression of current imbalance.

[0007] 2. A power conversion circuit diagram of FIG. 2. A plan view of the first layer of the wiring board of the semiconductor module of FIG. 2. A plan view of the second layer of the wiring board of the semiconductor module of FIG. 2. A plan view of the third layer of the wiring board of the semiconductor module of FIG. 2. A plan view of the fourth layer of the wiring board of the semiconductor module of FIG. 2. A plan view and an A-A' cross section of a semiconductor package in a semiconductor module. A plan view, a B-B' cross section, and a C-C' cross section of the semiconductor package of FIG. 8 with the sealing resin removed. A plan view and a D-D' cross section of the semiconductor package of FIG. 9 with the second conductor removed. A plan view and an E-E' cross section of the semiconductor package of FIG. 9 with the first conductor removed. First modified example of the present invention. Second modified example of the present invention.

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and some omissions and simplifications have been made as appropriate for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0009] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0010] (One embodiment and overall configuration) (FIG. 1) A semiconductor package 10, which is a semiconductor module included in a power conversion device, has a semiconductor element 2, a first conductor 21, a second conductor 22, and a bent terminal 24. In the semiconductor package 10, the semiconductor element 2, the first conductor 21, and the second conductor 22 are mold-sealed with a sealing member 11. The switching circuit of the semiconductor element 2 constituting the semiconductor package 10 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0011] Electrodes are formed on both sides of the semiconductor element 2. A first conductor 21 connected to the high-potential side of the upper and lower arm circuits configured in the semiconductor package 10 is connected to one electrode of the semiconductor element 2. A second conductor 22 connected to the low-potential side of the upper and lower arm circuits configured in the semiconductor package 10 is connected to the other electrode of the semiconductor element 2.

[0012] The second conductor 22 has a heat dissipation surface 16. The sealing member 11 seals the first conductor 21, the second conductor 22, and the semiconductor element 2 so that the heat dissipation surface 16, which is the surface of the second conductor 22 opposite to the surface to which the semiconductor element 2 is connected, is exposed from the sealing member 11. Note that, in order to ensure thermal connection with the heat dissipation fins 9 ( FIGS. 12 and 13 ), which will be described later, the semiconductor package 10 may be sealed with the sealing member 11 so that, in addition to the heat dissipation surface 16 of the second conductor 22 being exposed, a surface 21 a of the first conductor 21 opposite to the surface connected to the semiconductor element 2 is also exposed.

[0013] The wiring board 1 has a conductive member 7 formed of a material such as a copper inlay. The second conductor 22, which is a conductor on the source side of the semiconductor package 10, electrically connects the heat dissipation surface 16 to the surface of the conductive member 7 of the wiring board 1, thereby electrically connecting to the main circuit of the wiring board 1.

[0014] The bent terminals 24 have bent portions 24a that are bent in the stacking direction of the semiconductor package 10. The bent terminals 24 are electrically connected via solder 24b to side wiring patterns 7a formed on the sides of the conductive members 7 on the wiring board 1. By having the bent terminals 24 in this way, the size of the wiring board 1 in the longitudinal direction can be reduced, and stress on the solder 24b used to join the semiconductor package 10 and the wiring board 1 can be reduced, thereby improving the reliability of the power conversion device.

[0015] (FIGS. 2 to 4) The conductive member 7 has one common surface that joins the heat dissipation surfaces 16 (FIG. 1) of the second conductors 22 that are connected to the source sides of each of the semiconductor packages 10. The semiconductor packages 10 that make up the upper and lower arm circuits are electrically connected in parallel to each other. The semiconductor packages 10 are mounted on a wiring substrate 1, and the semiconductor packages 10 are each electrically connected to the wiring substrate 1. FIG. 2 illustrates, for example, positive semiconductor packages P1 to P4 and negative semiconductor packages N1 to N4, which are semiconductor packages 10, arranged on the substrate 1.

[0016] The wiring board 1 has a wiring pattern P of a positive bus bar, a wiring pattern N of a negative bus bar, and an AC wiring pattern AC. The AC wiring pattern AC is a high-potential wiring 4, and the negative bus bar wiring pattern N is a low-potential wiring 3. A drive circuit 6 is provided outside the wiring board 1. The drive circuit 6 controls the switching of the semiconductor package 10 by connecting to the gate wiring 5 on the wiring board 1.

[0017] The following describes the inductance that occurs between the wiring board 1 and the semiconductor package 10. For convenience of explanation, the inductance that occurs on the wiring pattern N side of the negative bus bar will be described, and the description of the inductance that occurs on the wiring pattern P side of the positive bus bar will be omitted.

[0018] 3, inductances Lb1, Lb2, and Lb3 are generated between terminals connected to semiconductor packages N1 to N4 on the wiring pattern N of the negative bus bar provided on the wiring board 1. Inductance L_PKG is generated at each terminal connecting the wiring pattern N of the negative bus bar to each semiconductor package 10 on the wiring board 1. Inductances La1, La2, and La3 are generated between connection surfaces (heat dissipation surfaces 16) of the semiconductor packages N1 to N4 and the conductive members 7 connected to the second conductors 22 of the semiconductor packages N1 to N4, respectively.

[0019] In this way, by placing the semiconductor package 10 on the wiring board 1, the difference in wiring inductance on the source side of the semiconductor package 10 can be further reduced compared to the conventional method of reducing inductance by alternately arranging the high-potential side terminals and low-potential side terminals of the semiconductor package 10, thereby suppressing current imbalance.

[0020] (FIGS. 4 to 7) The wiring board 1 is formed by stacking four layers of substrates, and the configurations of layers 1 to 4 are shown in FIG. 4 to 7. In each layer, the wiring patterns of the positive bus bar and the negative bus bar are different, but the positions where the conductive members 7 are provided are the same.

[0021] (FIG. 8) FIG. 8(a) is a plan view of the semiconductor package 10, and FIG. 8(b) is an A-A' cross-sectional view of FIG. 8(a). In the semiconductor package 10, a high-potential side signal terminal 12, a low-potential side signal terminal 13, a high-potential side terminal 14, and a low-potential side terminal 15 each protrude to the outside from the sealing member 11. The semiconductor element 2 is electrically connected to a first conductor 21 and a second conductor 22 via solder 2c. As shown in the A-A' cross-sectional view, the low-potential side signal terminal 13 and the high-potential side terminal 14 are bent terminals having a bent portion 24a that bends in the stacking direction of the semiconductor package 10. Although not shown, the high-potential side signal terminal 12 and the low-potential side terminal 15 are also bent terminals having a bent portion 24a.

[0022] (FIG. 9) FIG. 9(a) is a diagram of the semiconductor package 10 with the sealing member 11 removed, FIG. 9(b) is a cross-sectional view taken along line B-B' of FIG. 9(a), and FIG. 9(c) is a cross-sectional view taken along line C-C' of FIG. 9(a). The semiconductor element 2 is connected to the high-potential side signal terminal 12 and the low-potential side signal terminal 13 via bonding wires 17. The low-potential side terminal 15 is a terminal that is connected to the second conductor 22 via solder 15a. The high-potential side terminal 14 is a terminal that is connected to the first conductor 21.

[0023] (Figs. 10 and 11) Fig. 10(a) is a plan view of Fig. 9 with the second conductor 22 removed, showing the first conductor 21 as viewed from the side on which the semiconductor element 2 is mounted, and Fig. 10(b) is a cross-sectional view taken along the line D-D' in Fig. 10(a). Fig. 11(a) is a plan view of Fig. 9 with the first conductor 21 removed, showing the second conductor 22 as viewed from the side on which the semiconductor element 2 is mounted, and Fig. 11(b) is a cross-sectional view taken along the line E-E' in Fig. 11(a).

[0024] The high-potential side signal terminal 12 is connected to a high-potential side signal input section 18 of the semiconductor element 2 by a bonding wire 17. The low-potential side signal terminal 13 is connected to a low-potential side signal input section 19 of the semiconductor element 2 by a bonding wire 17.

[0025] In the semiconductor element 2, the low-potential side plane 2b is the surface that connects to the second conductor 22. In addition, in the semiconductor element 2, the high-potential side plane 2a is the surface that connects to the first conductor 21. Therefore, the connection side of the first conductor 21 is the high-potential side, and the connection side of the second conductor 22 is the low-potential side.

[0026] (First Modification) (FIG. 12) FIG. 12(a) is a cross-sectional view showing through holes 8 formed in a conductive member 7 of a wiring board 1, and FIG. 12(b) is a plan view of the wiring board 1 of FIG. 12(a). The wiring board 1 has multiple through holes 8 penetrating the wiring board 1 in the thickness direction. The conductive member 7 is connected to the through holes 8 and thermally connected to a heat dissipation fin 9 via the through holes 8. The semiconductor package 10 is thermally connected to the heat dissipation fin 9 via the conductive member 7 and the through holes 8. The heat dissipation fin 9 is also thermally connected to the surface of the first conductor 21 in the semiconductor package 10 that is not connected to the semiconductor element 2 via an insulating / heat dissipation joint 23, thereby promoting heat dissipation from the semiconductor element 2. The insulating / heat dissipation joint 23 is formed, for example, by sandwiching an insulating ceramic plate between two TIMs (thermal interface materials). This configuration reduces thermal resistance.

[0027] (Second Modification) (FIG. 13) The wiring board 1 may have a conductive member 7 made of a copper plate 25 that is provided continuously from one surface to the other surface along the thickness direction of the wiring board 1. This allows heat generated in the semiconductor element 2 to be dissipated from the connection side of the second conductor 22 that is connected to the source side of the semiconductor package 10 to the heat dissipation fins 9 via the copper plate 25, thereby reducing thermal resistance.

[0028] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0029] (1) A power conversion device includes a plurality of semiconductor packages 10 that form upper and lower arm circuits and are electrically connected in parallel to each other, and a wiring board 1 on which the plurality of semiconductor packages 10 are mounted and electrically connected to each of the plurality of semiconductor packages 10, wherein the plurality of semiconductor packages 10 each include a semiconductor element 2 having electrodes formed on both sides, a first conductor 21 connected to one electrode of the semiconductor element 2 and a high-potential side of the upper and lower arm circuit, a second conductor 22 connected to the other electrode of the semiconductor element 2 and a low-potential side of the upper and lower arm circuit, and a sealing member 11 that seals the first conductor 21, the second conductor 22, and the semiconductor element 2 so that a heat dissipation surface 16 of the second conductor 22, which is a surface opposite to the surface to which the semiconductor element 2 is connected, is exposed, and the wiring board 1 includes a conductive member 7 that is electrically connected to the heat dissipation surface 16 of the second conductor 22. By configuring in this way, a power conversion device that suppresses current imbalance can be provided.

[0030] (2) The semiconductor package 10 includes heat dissipation fins 9 that promote heat dissipation from the semiconductor element 2, the wiring board 1 includes a plurality of through holes 8 that penetrate the wiring board 1 in the thickness direction, and the conductive members 7 are connected to the through holes 8 and are thermally connected to the heat dissipation fins 9 via the through holes 8. This ensures a heat dissipation path from the source surface side, thereby reducing thermal resistance.

[0031] (3) The semiconductor packages 10 each include a bent terminal 24 that is bent in the stacking direction, and the bent terminal 24 is electrically connected to the wiring pattern 7a formed on the side of the conductive member 7 on the wiring substrate 1. This reduces stress at the joint of the solder 24b, improving the reliability of the power conversion device.

[0032] (4) The conductive member 7 is continuous from one surface to the other surface along the thickness direction of the wiring board 1. This ensures a heat dissipation path from the source surface side, thereby reducing thermal resistance.

[0033] The present invention is not limited to the above-described embodiments, and various modifications and combinations of other configurations are possible without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiments, and includes those in which some of the configurations are omitted.

[0034] REFERENCE SIGNS LIST 1 Wiring board 2 Semiconductor element 2a High potential side plane 2b Low potential side plane 2c Solder 3 Low potential wiring 4 High potential wiring 5 Gate wiring 6 Drive circuit P1 to P4 Semiconductor package (positive electrode) N1 to N4 Semiconductor package (negative electrode) 7 Conductive member 7a Side wiring pattern 8 Through hole 9 Heat dissipation fin 10 Semiconductor package 11 Sealing member 12 High potential side signal terminal 13 Low potential side signal terminal 14 High potential side terminal 15 Low potential side terminal 15a Solder 16 Heat dissipation surface 17 Bonding wire 18 High potential side signal input section 19 Low potential side signal input section 21 First conductor 21a Exposed surface 22 Second conductor 23 Insulating / heat dissipating joint section 24 Bent terminal 24a Bent section 24b Solder 25 Copper plate

Claims

1. A power conversion device comprising: a plurality of semiconductor packages which constitute upper and lower arm circuits and are electrically connected in parallel to each other; and a wiring board on which the plurality of semiconductor packages are mounted and which is electrically connected to each of the plurality of semiconductor packages, wherein the plurality of semiconductor packages comprise: a semiconductor element having electrodes formed on both sides; a first conductor connected to one electrode of the semiconductor element and a high potential side of the upper and lower arm circuits; a second conductor connected to the other electrode of the semiconductor element and a low potential side of the upper and lower arm circuits; and a sealing member which seals the first conductor, the second conductor and the semiconductor element so that a heat dissipation surface of the second conductor, which is the surface opposite to the surface to which the semiconductor element is connected, is exposed; and the wiring board has a conductive member which is electrically connected to the heat dissipation surface of the second conductor.

2. A power conversion device as claimed in claim 1, wherein the semiconductor package is provided with heat dissipation fins for promoting heat dissipation from the semiconductor element, the wiring board is provided with a plurality of through holes penetrating the wiring board in the thickness direction, and the conductive member is connected to the through holes and thermally connected to the heat dissipation fins via the through holes.

3. A power conversion device as claimed in claim 1, wherein the plurality of semiconductor packages are provided with bent terminals having a bent shape in the stacking direction, and the bent terminals are electrically connected to a wiring pattern formed on a side of the conductive member on the wiring board.

4. A power conversion device according to claim 1, wherein the conductive member is continuous from one surface to the other surface along the thickness direction of the wiring board.

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