Semiconductor substrate, method for manufacturing same, apparatus for manufacturing semiconductor substrate, and semiconductor device

Abstract

This semiconductor substrate comprises a template substrate, and a first semiconductor part that is positioned above a first seed region and a growth suppression region. The first semiconductor part includes a first wing part that is positioned above the growth suppression region. The first wing part has a first nitride semiconductor layer, an aluminum-based semiconductor layer that is positioned on the first nitride semiconductor layer, and a second nitride semiconductor layer that is positioned on the aluminum-based semiconductor layer. The upper surface of the second nitride semiconductor layer has a lower silicon concentration than the upper surface of the first nitride semiconductor layer.

Description

Semiconductor substrate and manufacturing method thereof, semiconductor substrate manufacturing apparatus, and semiconductor device

[0001] The present disclosure relates to semiconductor substrates and the like.

[0002] Patent Document 1 discloses a method (ELO method) in which a mask pattern including a mask portion and an opening is formed on a base substrate including a seed layer, and a nitride semiconductor layer is laterally grown on the mask portion using the seed layer exposed in the opening as a growth starting point.

[0003] Japanese Patent Application Publication No. 2013-251304

[0004] A semiconductor substrate in one aspect of the present disclosure comprises a template substrate including a first seed region and a growth inhibition region aligned in a first direction, and a first semiconductor portion located above the first seed region and the growth inhibition region, the first semiconductor portion including a first wing portion located above the growth inhibition region, the first wing portion having a first nitride semiconductor layer, an aluminum-based semiconductor layer containing aluminum and located on the first nitride semiconductor layer, and a second nitride semiconductor layer located on the aluminum-based semiconductor layer, and the upper surface of the second nitride semiconductor layer has a lower silicon concentration than the upper surface of the first nitride semiconductor layer.

[0005] 1 is a cross-sectional view showing a configuration of a semiconductor substrate according to an embodiment of the present disclosure; FIG. 2 is a plan view showing a configuration of a semiconductor substrate according to an embodiment of the present disclosure; FIG. 3 is an enlarged microscope image showing a magnified portion of a cross section of a semiconductor substrate according to an embodiment of the present disclosure; FIG. 4 is an enlarged view of region IV shown in FIG. 3; FIG. 5 is an enlarged microscope image showing a magnified main portion of a cross section of a semiconductor substrate according to an embodiment of the present disclosure; FIG. 6 is an enlarged cross-sectional view showing a magnified portion of a semiconductor substrate according to an embodiment of the present disclosure; FIG. 7 is a flowchart showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure; FIG. 8 is a flowchart showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure; FIG. 9 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure; FIG. 10 is a block diagram showing an apparatus for manufacturing a semiconductor substrate according to an embodiment of the present disclosure; FIG. 11 is a cross-sectional view showing an example of a configuration of a template substrate according to Example 1; FIG. 12 is a cross-sectional view showing an example of a configuration of a base substrate; FIG. 13 is a cross-sectional view showing an example of a configuration of a template substrate; FIG. 14 is a cross-sectional view showing a schematic configuration of a semiconductor substrate according to Example 1; FIG. 15 is a plan view showing a schematic configuration of a semiconductor substrate according to Example 1; FIG. 16 is a cross-sectional view showing an example of lateral growth of a first nitride semiconductor layer; FIG. 17 is a cross-sectional view showing an example of growth of an Al-based semiconductor layer and a second nitride semiconductor layer; FIG. 18 is a graph showing SIMS analysis results of the semiconductor substrate according to Example 1. FIG. 1 is a diagram in which the abundance ratio of each element determined by EDS analysis is superimposed on a microscope image of a semiconductor substrate in Example 1. FIG. 2 is a plan view showing another configuration example of a semiconductor substrate in Example 1. FIG. 3 is a cross-sectional view showing another configuration example of a semiconductor substrate in Example 1. FIG. 4 is a plan view showing another configuration example of a semiconductor substrate in Example 1. FIG. 5 is a cross-sectional view showing a method of element isolation in Example 1. FIG. 6 is a plan view showing a method of element isolation in Example 1. FIG. 7 is a plan view showing another configuration example of a semiconductor substrate in Example 1. FIG. 8 is a cross-sectional view schematically showing a configuration of a semiconductor substrate in Example 2. FIG. 9 is a cross-sectional view schematically showing a configuration of a semiconductor substrate in Example 3. FIG. 10 is a schematic view showing a configuration example of an electronic device. FIG. 11 is a schematic view showing another configuration example of an electronic device.

[0006] [Semiconductor Substrate] Fig. 1 is a cross-sectional view showing the configuration of a semiconductor substrate according to an embodiment of the present disclosure. Fig. 2 is a plan view showing the configuration of a semiconductor substrate according to an embodiment of the present disclosure. As shown in Figs. 1 and 2, a semiconductor substrate 10 includes a template substrate TS including a first seed region S1 and a growth inhibition region DA aligned in a first direction (X direction), and a first semiconductor portion 8A located above the first seed region S1 and the growth inhibition region DA. The first semiconductor portion 8A includes a first wing portion F1 located above the growth inhibition region DA. The first wing portion F1 includes a first nitride semiconductor layer NS1, an aluminum-based semiconductor layer (hereinafter referred to as an Al-based semiconductor layer) ALS containing aluminum and located on the first nitride semiconductor layer NS1, and a second nitride semiconductor layer NS2 located on the Al-based semiconductor layer ALS. An upper surface N2T of the second nitride semiconductor layer NS2 has a lower silicon concentration than an upper surface N1T of the first nitride semiconductor layer NS1. Furthermore, in the first wing portion F1, the upper surface roughness of the aluminum-based semiconductor layer ALS may be smaller than the upper surface roughness of the first nitride semiconductor layer NS1.

[0007] In FIG. 1 , the upper surface N1T of the first nitride semiconductor layer NS1 is highlighted with dark gray hatching for ease of illustration. The upper surface roughness and silicon concentration of the first nitride semiconductor layer NS1 may be determined in the upper portion of the first nitride semiconductor layer NS1 (e.g., the portion above the reference point where the depth from the upper surface is half the thickness of the portion where the thickness of the first nitride semiconductor layer NS1 is minimum). The Al-based semiconductor layer ALS can also be expressed as an Al-containing semiconductor layer (or compound semiconductor layer). The Al-based semiconductor layer ALS may contain, for example, aluminum nitride (AlN) or a GaN-based semiconductor containing aluminum. The Al-based semiconductor layer ALS may contain, for example, aluminum gallium nitride (AlGaN). The Al-based semiconductor layer ALS will be described in detail below.

[0008] The semiconductor substrate 10 can improve the surface quality of the first wing portion F1. For example, the first wing portion F1 may have a highly flat surface and a low impurity concentration. The improved surface quality of the first wing portion F1 allows a high-quality functional layer to be formed above the first wing portion F1. The semiconductor substrate 10 achieves the following effects even if surface defects (surface roughness, impurity condensation, etc.) occur in the first nitride semiconductor layer NS1 by increasing the aspect ratio (ratio of width to thickness) of the first nitride semiconductor layer NS1. That is, the Al-based semiconductor layer ALS containing highly reactive aluminum functions as a planarizing film, allowing a thin second nitride semiconductor layer NS2 with high surface quality to be formed on the Al-based semiconductor layer ALS. This allows a high-quality first wing portion F1 with a high aspect ratio (flatness). The impurity may be an element (e.g., Si element) derived from at least one of the template substrate TS and the crystal growth apparatus (e.g., MOCVD apparatus). The upper surface N2T of the second nitride semiconductor layer NS2 may have a lower impurity (e.g., silicon) concentration than the upper surface N1T of the first nitride semiconductor layer NS1. The upper surface roughness and silicon concentration of the second nitride semiconductor layer NS2 may be determined in the upper portion of the second nitride semiconductor layer NS2 (e.g., the portion above the reference point where the depth from the upper surface is half the thickness of the portion where the second nitride semiconductor layer NS2 has the smallest thickness). The first semiconductor portion 8A includes a first base portion B1 located above the first seed region S1. Details of each portion of the first semiconductor portion 8A will be described later.

[0009] In the semiconductor substrate 10 of this embodiment, the template substrate TS may include a base substrate BS, and a mask pattern 6 may be formed on the base substrate BS. The base substrate BS may have a main substrate 1 and an underlayer 4 located above the main substrate 1. The mask pattern 6 may include a mask portion 5 that functions as a growth inhibition region DA, and a first opening K1 that corresponds to the first seed region S1. Specifically, the surface of the mask portion 5 may be the growth inhibition region DA. The template substrate TS may also be referred to as a growth substrate.

[0010] The first semiconductor portion 8A includes a nitride semiconductor. The first nitride semiconductor layer NS1, the Al-based semiconductor layer ALS, and the second nitride semiconductor layer NS2 each include a nitride semiconductor. A nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), for example. Specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0011] The first semiconductor portion 8A may be doped (e.g., n-type including donors) or non-doped. A semiconductor substrate means a substrate including a semiconductor, and the main substrate 1 of the template substrate TS may or may not include a semiconductor (e.g., silicon, silicon carbide). An example of a main substrate 1 that does not include a semiconductor is a sapphire substrate. The main substrate 1 and the underlayer 4 may be collectively referred to as a base substrate BS. The base substrate BS is a substrate that serves as a support base (base) for various upper layers.

[0012] The underlayer 4 may have a single-layer structure or a multilayer structure. The underlayer 4 may have a multilayer structure including a periodic structure. The underlayer 4 may include, for example, a seed portion (seed layer) that serves as a growth starting point for the nitride semiconductor, and a buffer portion (buffer layer) located between the main substrate 1 and the seed portion.

[0013] The first nitride semiconductor layer NS1 in the first semiconductor portion 8A can be formed on the template substrate TS by an epitaxial lateral overgrowth (ELO) method. In the ELO method, for example, a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor is used as the main substrate 1, an inorganic compound film is used as the mask portion 5, and the first seed region S1 exposed in the first opening K1 can be used as the starting point for crystal growth. This allows an initial growth layer 8s to be formed on the first seed region S1, and then the first nitride semiconductor layer NS1 can be laterally grown from the initial growth layer 8s onto the mask portion 5. The initial growth layer 8s can also be referred to as a seed crystal portion.

[0014] Of the first semiconductor portion 8A, the first base portion B1 located above the first opening K1 becomes a dislocation inheritance portion with a large number of threading dislocations, and the first wing portion F1 located above the mask portion 5 can be made into a low-defect portion with a lower threading dislocation density than the dislocation inheritance portion.

[0015] The template substrate TS may have a second seed region S2 adjacent to the first seed region S1 in the first direction (X direction) with a growth inhibition region DA interposed therebetween. The mask pattern 6 may include a second opening K2 corresponding to the second seed region S2. The template substrate TS may have a shape in which the first seed region S1 and the growth inhibition region DA aligned in the first direction (X direction) each have a longitudinal direction that is a second direction (Y direction) perpendicular to the first direction. The template substrate TS may have a shape in which the first seed region S1, the growth inhibition region DA, and the second seed region S2 aligned in the first direction each have a longitudinal direction that is the second direction.

[0016] The template substrate TS has a second semiconductor portion 8C located above the second seed region S2 and the growth inhibition region DA, and the second semiconductor portion 8C includes a second base portion B2 located above the second seed region S2 and a second wing portion F2 located above the growth inhibition region DA, and the first wing portion F1 and the second wing portion F2 may be adjacent to each other via a gap G.

[0017] In one embodiment, the growth of the first nitride semiconductor layer NS1 may be stopped before the first nitride semiconductor layer NS1 growing laterally on the mask portion 5 from the initial growth layer 8s grown starting from the first seed region S1 and the first nitride semiconductor layer NS1 growing laterally on the mask portion 5 from the initial growth layer 8s grown starting from the second seed region S2 meet each other. As described above for the first semiconductor portion 8A, in the second semiconductor portion 8C, the second base portion B2 located above the second seed region S2 becomes a dislocation inherited portion, and the second wing portion F2 located above the growth inhibition region DA becomes a low-defect portion.

[0018] Hereinafter, the first semiconductor portion 8A and the second semiconductor portion 8C may be collectively referred to as semiconductor portion 8, the first base portion B1 and the second base portion B2 as base portion B, and the first wing portion F1 and the second wing portion F2 as wing portion F. In addition, the first opening K1 and the second opening K2 of the mask pattern 6 may be collectively referred to as opening K, and the first seed region S1 and the second seed region S2 as seed region S. The semiconductor portion 8 may be a semiconductor layer 8, and the mask portion 5 may be a mask layer 5.

[0019] In the following description, the direction from the main substrate 1 to the semiconductor portion 8 will be referred to as "upward," and viewing an object with a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective views) will be referred to as "planar view." The seed region S and the growth inhibition region DA may be aligned in a first direction (the direction perpendicular to the thickness direction of the substrate, the X direction) in a planar view. The seed region S (e.g., the surface of the underlayer 4) and the growth inhibition region DA (e.g., the surface of the mask portion 5) may have different positions (heights) in the thickness direction of the semiconductor substrate 10 (the up-down direction, the Z direction), or may be the same or approximately the same.

[0020] The first direction (X direction) may be the a-axis direction (<11-20> direction) of the semiconductor portion 8 (nitride semiconductor crystal such as GaN). The second direction (Y direction) orthogonal to the first direction may be the m-axis direction (<1-100> direction) of the semiconductor portion 8. The thickness direction of the semiconductor substrate 10 may be the c-axis direction (<0001> direction) of the semiconductor portion 8.

[0021] The semiconductor substrate 10 in this embodiment includes an initial growth layer 8s grown from a seed region S and a first nitride semiconductor layer NS1 grown from the initial growth layer 8s. The first nitride semiconductor layer NS1 may be a layer grown laterally with vertical growth being highly suppressed. In this case, lateral crystal growth may proceed faster than vertical crystal growth. The wing portion F of the semiconductor substrate 10 includes an Al-based semiconductor layer ALS formed on the first nitride semiconductor layer NS1 and a second nitride semiconductor layer NS2 formed on the Al-based semiconductor layer ALS. This improves the surface quality of the wing portion F. Furthermore, the thickness of the semiconductor portion 8 can be reduced. The second nitride semiconductor layer NS2 has the surface quality required for growing, for example, a device layer. The findings of the present disclosure are briefly described below.

[0022] The surface quality of a nitride semiconductor layer (ELO layer) formed by the ELO method affects the growth and performance of semiconductor layers grown (e.g., epitaxially) on the ELO layer. Generally, ELO layers are formed under growth conditions that allow for both lateral and vertical growth to some extent. In this case, the surface quality of the ELO layer can be improved along with the vertical growth. For convenience of explanation, these growth conditions are referred to as "(conventional) simultaneous vertical and horizontal growth conditions." The vertical direction refers to the thickness direction of the ELO layer.

[0023] The ELO layer formed under conventional simultaneous vertical and horizontal growth conditions has a relatively large thickness. Therefore, for example, defects (such as slip defects) may occur in the ELO layer due to a large difference in stress (internal stress) between the ELO layer and the growth substrate. To reduce the thickness of the ELO layer, if the growth conditions in the ELO method are changed from simultaneous vertical and horizontal growth conditions to suppress vertical growth, a relatively thin ELO layer can be formed. On the other hand, hillocks (protrusions) may occur on the surface of the ELO layer, making it difficult to form a device layer on the surface of the ELO layer. Therefore, the possibility of hillock occurrence is usually reduced by using simultaneous vertical and horizontal growth conditions as the growth conditions in the ELO method.

[0024] Under the circumstances described above, the present inventors have come to the following discovery: They attempted to drastically change the growth conditions of the ELO layer so as to further suppress vertical growth (bring vertical growth closer to zero). As a result, contrary to the expectation that crystal growth itself would cease (both vertical and horizontal growth would cease), they discovered that there exist conditions (highly flat growth conditions) under which the ELO layer grows laterally while vertical growth is highly suppressed.

[0025] According to the high-flatness growth conditions of the present disclosure, the first nitride semiconductor layer NS1 can be grown substantially only in the lateral direction while reducing hillocks on the surface of the first nitride semiconductor layer NS1 formed by the ELO method. The first nitride semiconductor layer NS1 formed by the ELO method under the high-flatness growth conditions may have a ratio of vertical growth to lateral growth of less than 0.2, less than 0.1, or less than 0.05, for example.

[0026] The thickness direction of the first nitride semiconductor layer NS1 may be the c-axis direction of the nitride semiconductor. Under the highly flat growth conditions of the present disclosure, for example, it is considered that on the top surface N1T of the first nitride semiconductor layer NS1, a reaction in which the attached raw materials (particles derived from them) evaporate before being incorporated into the first nitride semiconductor layer NS1 is dominant. On the other hand, on the lateral growth end faces (for example, the a-plane and r-plane of the nitride semiconductor, etc.), it is considered that a crystal growth reaction occurs due to the attached raw materials (particles derived from them). Note that, for example, there is a method of improving the lateral growth rate of the ELO layer by using dimethylhydrazine as a nitrogen source (group V raw material), but under the highly flat growth conditions of the present disclosure, it is considered that a general raw material other than dimethylhydrazine (for example, NH ３ gas) can be used.

[0027] Next, in order to form a device layer (functional layer) above the first nitride semiconductor layer NS1 formed to be thin and wide under the highly flat growth conditions of the present disclosure, an attempt was made to grow a semiconductor layer (e.g., GaN) on the first nitride semiconductor layer NS1. As a result, preferential growth of the semiconductor layer occurred on the surface of the edge portion (portion far from the initial growth layer 8s) of the first nitride semiconductor layer NS1, resulting in a phenomenon in which the semiconductor layer was not formed uniformly on the first nitride semiconductor layer NS1. After careful investigation into this phenomenon, it was discovered that a relatively high concentration of silicon was non-uniformly present on the surface (top surface N1T) of the first nitride semiconductor layer NS1 formed under the highly flat growth conditions of the present disclosure, and that fine surface roughness occurred on a microscale.

[0028] Here, the semiconductor substrate 10 may include, for example, a silicon-based mask that functions as a growth inhibition region DA. In other words, the mask portion 5 may be a silicon-based mask. A silicon-based mask is a mask that contains silicon, and may also be expressed as a silicon-containing mask. The silicon-based mask may be any mask that contains silicon and is used in the ELO method. The silicon-based mask may have, for example, the largest silicon content (number of moles) among elements other than electronegative elements in its constituent components (elements that donate electrons to electronegative elements in chemical bonds). Specific examples of silicon-based masks will be described later.

[0029] The silicon concentration on the upper surface N1T of the first nitride semiconductor layer NS1 is thought to originate from the mask portion 5 or furnace components of the film formation apparatus (e.g., MOCVD apparatus). Furthermore, various analyses suggest that a microstructure with oblique facets is formed on the upper surface N1T of the first nitride semiconductor layer NS1. The phenomenon of silicon concentration on the upper surface N1T of the first nitride semiconductor layer NS1 and the formation of the microstructure may effectively contribute to the high suppression of vertical growth of the first nitride semiconductor layer NS1 under the highly flat growth conditions of the present disclosure. On the other hand, it can be said that the first nitride semiconductor layer NS1 is in a state where it is difficult to grow another nitride semiconductor (e.g., GaN) on the upper surface N1T as it is.

[0030] Therefore, the semiconductor substrate 10 according to an embodiment of the present disclosure includes an Al-based semiconductor layer ALS (e.g., AlGaN) located on the surface of the first nitride semiconductor layer NS1. The Al-based semiconductor layer ALS is easily grown uniformly even on the upper surface N1T of the first nitride semiconductor layer NS1 having the surface state described above due to the action of aluminum. The Al-based semiconductor layer ALS may cover the side surfaces of the first nitride semiconductor layer NS1.

[0031] The semiconductor substrate 10 further includes a second nitride semiconductor layer NS2 located on the surface of the Al-based semiconductor layer ALS. By using the Al-based semiconductor layer ALS as an intermediate layer, the second nitride semiconductor layer NS2 can be formed while reducing the possibility of hillocks or the like occurring on the surface. As a result, the surface quality of the second nitride semiconductor layer NS2 can be improved. The second nitride semiconductor layer NS2 may have the surface quality required for forming a functional layer 9 (described below) having a function corresponding to the device structure. The functional layer 9 includes, for example, an active layer. Furthermore, in the semiconductor substrate 10, the surface quality of the second nitride semiconductor layer NS2 can be improved while the thickness of the first nitride semiconductor layer NS1 is relatively thin. Therefore, the thickness of the wing portion F can be adjusted, and wing portions F with high surface quality can be formed. For example, the semiconductor substrate 10 may have wing portions F with uniform surface quality.

[0032] Fig. 3 is a microscope image showing an enlarged view of a portion of a cross section of a semiconductor substrate according to an embodiment of the present disclosure. Fig. 4 is an enlarged view of region IV shown in Fig. 3. Fig. 5 is a microscope image showing an enlarged view of a main portion of a cross section of a semiconductor substrate according to an embodiment of the present disclosure. Figs. 3 to 5 show a cross section of a portion of the first wing portion F1 in the first semiconductor portion 8A. Fig. 3 also shows a state in which a functional layer 9 is formed above the second nitride semiconductor layer NS2.

[0033] 3 to 5, the interface between the first nitride semiconductor layer NS1 and the Al-based semiconductor layer ALS is not flat but has an uneven shape. The interface between the first nitride semiconductor layer NS1 and the Al-based semiconductor layer ALS corresponds to the surface (top surface N1T) of the first nitride semiconductor layer NS1 formed under the highly flat growth conditions of the present disclosure, and it can be seen that the top surface N1T of the first nitride semiconductor layer NS1 has a fine uneven structure.

[0034] The surface layer (portion of the top surface N1T) of the first nitride semiconductor layer NS1 may have, for example, a plurality of recesses RP (also referred to as top surface roughness) having a depth D1 of 20 nm to 80 nm. The roughness of the top surface N1T of the first nitride semiconductor layer NS1 (also referred to as the top surface roughness of the first nitride semiconductor layer NS1) may be 20 nm to 80 nm. The average value of the roughness of the top surface N1T of the first nitride semiconductor layer NS1 may be 45 nm to 55 nm. During the process of forming the first nitride semiconductor layer NS1 under the highly flat growth conditions of the present disclosure, for example, the top surface N1T may be formed with a fine uneven structure by etching a flat surface or by vertical stacking occurring so as to form a pyramidal shape with oblique facets.

[0035] The silicon concentration in each portion of the semiconductor portion 8 can be measured (analyzed) in the depth direction using, for example, TOF-SIMS (time-of-flight secondary ion mass spectrometry). The upper surface N1T of the first nitride semiconductor layer NS1 has a significantly higher silicon concentration than the surface of an ELO layer formed under conventional simultaneous vertical and horizontal growth conditions. The semiconductor substrate 10 may have a non-uniform silicon concentration distribution in the first direction (X direction) on the upper surface N1T of the first nitride semiconductor layer NS1. Here, a certain period from the start of deposition of the first nitride semiconductor layer NS1 under the highly flat growth conditions of the present disclosure is referred to as the initial growth period, and a certain period until the end of deposition is referred to as the final growth period. The first nitride semiconductor layer NS1 may have a relatively high silicon concentration in a portion of the upper surface N1T corresponding to the initial growth period (near the initial growth layer 8s), and a relatively low silicon concentration in a portion of the upper surface N1T corresponding to the final growth period (an end portion far from the initial growth layer 8s). This suggests that the deposition time required to grow the wide first nitride semiconductor layer NS1 under the highly flat growth conditions of the present disclosure affects the non-uniformity of the silicon concentration distribution on the surface (top surface N1T) of the first nitride semiconductor layer NS1.

[0036] The silicon concentration distribution in the upper surface N1T of the first nitride semiconductor layer NS1 may be, for example, as follows: That is, in the first direction, for example, the ratio of the silicon concentration on the end side (corresponding to an edge region JA described later) of the upper surface N1T of the first nitride semiconductor layer NS1 to the silicon concentration on the surface of a fine-growth portion SGP (see FIG. 6 ) described later located above the seed region S may be 0.60 to 0.85, or may be 0.70 to 0.75. For example, when the fine-growth portion SGP is not present, the ratio of the silicon concentration on the end side of the upper surface N1T of the first nitride semiconductor layer NS1 to the silicon concentration on the surface (upper surface 8sT described later) of the initial growth layer 8s may be 0.60 to 0.85, or may be 0.70 to 0.75. In the first semiconductor portion 8A, the silicon concentration of the first base portion B1 located above the first seed region S1 may be 1, and the silicon concentration of the tip surface of the first nitride semiconductor layer NS1 may be 0.60 to 0.85, or 0.70 to 0.75. Furthermore, in the first direction, for example, the ratio of the silicon concentration of the portion of the surface of the first nitride semiconductor layer NS1 near the initial growth layer 8s (corresponding to the connection region CA described below) to the silicon concentration of the end side (corresponding to the edge region JA described below) may be 0.60 to 0.85, or 0.70 to 0.75. The silicon concentration of the surface of the end portion of the first nitride semiconductor layer NS1 on the first base portion B1 side may be 1, and the silicon concentration of the tip surface of the first nitride semiconductor layer NS1 may be 0.6 to 0.85, or 0.7 to 0.75. The tip portion of the first nitride semiconductor layer NS1 is a side surface portion of the first nitride semiconductor layer NS1 in the first direction (X direction).

[0037] On the other hand, the second nitride semiconductor layer NS2 may have a relatively low silicon concentration at its surface. This is because the area of ​​the exposed portion of the mask portion 5 is small during deposition of the second nitride semiconductor layer NS2, and the top surface N2T of the second nitride semiconductor layer NS2 is formed by vertical growth. The vertical growth may be, for example, epitaxial growth. In the semiconductor substrate 10 of this embodiment, the silicon concentration of the top surface N2T of the second nitride semiconductor layer NS2 may be lower than the silicon concentration of the top surface N1T of the first nitride semiconductor layer NS1. In the semiconductor substrate 10 of this embodiment, the silicon concentration of the top surface N1T of the first nitride semiconductor layer NS1 may be five times or more the silicon concentration of the top surface N2T of the second nitride semiconductor layer NS2. The level of the silicon concentration of the top surface N1T may vary depending on various conditions. Therefore, although it is difficult to set a specific numerical range, the silicon concentration of the upper surface N1T may be, for example, 5 to 2000 times, or 5 to 1000 times, the silicon concentration of the upper surface N2T. The silicon concentrations of the upper surfaces N1T and N2T can be calculated by, for example, dividing the wing portion F into five equal parts in the X-axis direction, measuring (analyzing) the silicon concentration in the depth direction at four points between two end points using SIMS or the like, and calculating the average value of the four points. For the upper surface N2T, the silicon concentration may be calculated using, for example, the peak value of the signal intensity near the surface (for example, a region at a depth of about 1 nm or less) in a measurement profile obtained by SIMS or the like.

[0038] The top surface N1T has a higher silicon concentration than the inside of the first nitride semiconductor layer NS1 (the portion laterally grown from the initial growth layer 8s). The top surface N1T may have a silicon-enriched layer formed in the form of a film on the surface of the fine unevenness structure. The state of silicon unevenly concentrated on the top surface N1T may be a state in which silicon is incorporated into the nitride semiconductor crystal of the first nitride semiconductor layer NS1. The silicon-enriched layer may be formed of nitride semiconductor crystal containing a relatively high concentration of silicon. The silicon-enriched layer may be located on the top surface N1T so as to cover the entire surface of the fine unevenness structure, or may have fine pores.

[0039] The Al-based semiconductor layer ALS includes a lower layer (first layer) FL that fills in the rough upper surface (fine uneven structure, multiple recesses) of the first nitride semiconductor layer NS1, and an upper layer (second layer) SL that is flatter than the lower layer FL, and the lower layer FL may have a lower aluminum concentration than the upper layer SL. The aluminum concentrations of the lower layer FL and the upper layer SL here may refer to the aluminum concentrations in the main portions of the lower layer FL and the upper layer SL, excluding the boundary portion (dark gray portion shown in FIG. 5 ) described below. Filling in the rough upper surface refers to a state in which the lower layer FL is located inside the depression of the recess RP that forms the rough upper surface.

[0040] 3 to 5 , the Al-based semiconductor layer ALS may include a first boundary portion BP1 located at the boundary between the lower layer FL and the upper layer SL, and a second boundary portion BP2 located at the boundary between the upper layer SL and the second nitride semiconductor layer NS2. The upper layer SL may include a main portion MP located between the first boundary portion BP1 and the second boundary portion BP2 in the height (thickness) direction. The main portion MP may have a thickness greater than that of the first boundary portion BP1 and may have a thickness greater than that of the second boundary portion BP2.

[0041] The Al-based semiconductor layer ALS may be, for example, a layer containing AlGaN (AlGaN layer) or a layer containing AlN (AlN layer). In the example shown in FIG. 5 , the Al-based semiconductor layer ALS is an AlGaN layer, and when the aluminum concentration of each portion of the Al-based semiconductor layer ALS is analyzed using, for example, EDS (Energy Dispersive X-ray Spectroscopy), the following can be said. That is, each portion of the Al-based semiconductor layer ALS may satisfy at least one of the following relationships regarding the aluminum concentration: The first boundary portion BP1 may have a higher aluminum concentration than the lower layer FL. The first boundary portion BP1 may have a higher aluminum concentration than the main portion MP. The first boundary portion BP1 may have a higher aluminum concentration than the second boundary portion BP2. Furthermore, the second boundary portion BP2 may have a higher aluminum concentration than the main portion MP. The upper surface LST of the Al-based semiconductor layer ALS may have a higher aluminum concentration than the main portion MP. The upper surface LST may have a higher aluminum concentration than the second boundary portion BP2.

[0042] The lower layer FL fills in the fine unevenness on the upper surface N1T of the first nitride semiconductor layer NS1, allowing the upper layer SL to form a flat upper surface LST. The following model, for example, can be considered as a process for forming such an Al-based semiconductor layer ALS. That is, it is considered that Al is more easily incorporated into the semiconductor crystal at the stage where a flat surface is formed on the lower layer FL and the upper layer SL grows on the lower layer FL than at the stage where the lower layer FL grows on the upper surface N1T having a fine unevenness. Specifically, at the beginning of the process for forming the Al-based semiconductor layer ALS, a growth starting point on the upper surface N1T is formed by the action of Al. During the subsequent growth process of the lower layer FL, Al is relatively difficult to incorporate, and once the surface becomes flat (reaching the first boundary portion BP1), the upper layer SL grows so as to contain Al close to the composition of the raw materials. The second boundary portion BP2 may be generated, for example, during the process for forming the second nitride semiconductor layer NS2 (due to the influence of heat, etc.). Since the surface (upper surface LST) of the Al-based semiconductor layer ALS is flat, it becomes easier to form the second nitride semiconductor layer NS2 on the Al-based semiconductor layer ALS, and the surface quality of the upper surface N2T of the second nitride semiconductor layer NS2 can be improved. However, the present invention is not limited to the above model (mechanism).

[0043] The roughness (top surface roughness) of the top surface LST of the aluminum-based semiconductor layer ALS may be smaller than the top surface roughness of the first nitride semiconductor layer NS1, which makes it easier to improve the surface quality of the top surface N2T of the second nitride semiconductor layer NS2. The roughness (top surface roughness) of the top surface LST of the aluminum-based semiconductor layer ALS may be less than 20 nm, less than 5 nm, or less than 1 nm.

[0044] The top surface roughnesses of the first nitride semiconductor layer NS1, the second nitride semiconductor layer NS2, and the aluminum-based semiconductor layer ALS can be determined, for example, by AFM (atomic force microscope) measurement or visually confirmed from SEM or TEM images. The top surface roughness of the second nitride semiconductor layer NS2 may be, for example, the maximum height roughness Rz that can be measured by AFM. When the top surface roughness of the first nitride semiconductor layer NS1 is visually confirmed from a TEM image, the average value of the depths D1 of multiple recesses RP (e.g., any 10 recesses in the TEM image) may be used as the top surface roughness. Here, if no recesses are observed on the top surface LST of the aluminum-based semiconductor layer ALS, or if the average value of the depths of the observed recesses is smaller than the top surface roughness of the top surface NST of the first nitride semiconductor layer NS1, the roughness (top surface roughness) of the top surface LST of the aluminum-based semiconductor layer ALS can be determined to be smaller than the top surface roughness of the first nitride semiconductor layer NS1. The roughness of the top surface of the second nitride semiconductor layer NS2 may be, for example, less than 5 nm, or less than 1 nm, or may be such that only atomic-level steps (around 1 nm) are observed and there is essentially no roughness.

[0045] 6 is an enlarged cross-sectional view showing a portion of a semiconductor substrate according to an embodiment of the present disclosure, in which a portion of a top surface N1T of a first nitride semiconductor layer NS1 is shown thickly hatched in dark gray for convenience of illustration.

[0046] As shown in FIG. 6 (also see FIG. 1 ), the first semiconductor portion 8A includes a first base portion B1 located above the first seed region S1. The top surface N1T of the first nitride semiconductor layer NS1 includes a connection region CA connected to the first base portion B1 and an edge region JA spaced from the first base portion B1 in the first direction (X direction). The silicon concentration in the connection region CA may be higher than the silicon concentration in the edge region JA. Furthermore, the top surface roughness of the connection region CA may be greater than the top surface roughness of the edge region JA. The first semiconductor portion 8A may include a slight growth portion SGP in the first base portion B1, which is a portion that has grown slightly from the top surface 8sT of the initial growth layer 8s. The first nitride semiconductor layer NS1 is a portion that has grown substantially only laterally from the side surface 8sS of the initial growth layer 8s above the growth inhibition region DA under the high-flatness growth conditions of the present disclosure. The first nitride semiconductor layer NS1 is in contact with a side surface 8sS of the initial growth layer 8s. The first nitride semiconductor layer NS1 also has an edge E1 located above the mask portion 5 (growth inhibition region DA). The edge region JA is a region in the top surface N1T near the edge E1. For example, in the cross-sectional view shown in FIG. 6 , the edge region JA may be a region corresponding to a portion including the edge E1 when the top surface N1T is divided into five equal parts in the a-axis direction (X direction).

[0047] The top surface N1T may have an intermediate region MA located between the connection region CA and the edge region JA. In the first semiconductor portion 8A, the silicon concentration in the intermediate region MA may be lower than that in the connection region CA and higher than that in the edge region JA. In the first semiconductor portion 8A, the top surface roughness in the intermediate region MA may be greater than that in the connection region CA and smaller than that in the edge region JA.

[0048] In the semiconductor substrate 10 according to an embodiment of the present disclosure, for example, the ratio of the length W1 in the first direction (X direction) to the thickness D10 of the first nitride semiconductor layer NS1 may be 5.0 or greater. The ratio of the length W1 to the thickness D10 may be 6.0 or greater, or may be 7.0 or greater. The thickness D10 of the first nitride semiconductor layer NS1 may be the distance in the thickness direction between the lowest point of the edge E1 of the first nitride semiconductor layer NS1 and the top surface N1T (edge ​​region JA). The thickness D10 may be the same as or approximately the same as the height of the portion of the initial growth layer 8s protruding from the mask portion 5. The height of the portion of the initial growth layer 8s protruding from the mask portion 5 may be the distance between the surface of the mask portion 5 and the top surface 8sT of the initial growth layer 8s.

[0049] In the thickness direction (Z direction) of the semiconductor substrate 10, the first nitride semiconductor layer NS1 and the second nitride semiconductor layer NS2 may each be thicker than the Al-based semiconductor layer ALS. The thickness D10 of the first nitride semiconductor layer NS1 may be, for example, 300 nm or more, or 500 nm or more. There is no particular limitation on the upper limit of the thickness D10 of the first nitride semiconductor layer NS1, and the thickness D10 may be, for example, 5000 nm or less, 3000 nm or less, or 2000 nm or less. The thickness D2 of the second nitride semiconductor layer NS2 may be, for example, 10 μm or less, or 50 nm or more and 5 μm or less. The thickness D3 of the Al-based semiconductor layer ALS may be, for example, 60 nm or more, or 200 nm or more. If the thickness D3 of the Al-based semiconductor layer ALS is too small, the flatness of the upper surface LST of the Al-based semiconductor layer ALS may be insufficient. The upper limit of the thickness D3 of the Al-based semiconductor layer ALS is not particularly limited, but the thickness D3 may be, for example, 1000 nm or less, 800 nm or less, or 600 nm or less.

[0050] The thickness D11 of the micro-growth portion SGP may be, for example, 1 nm or more, and may be about 1 to 100 nm. The thickness D11 may be, for example, 3000 nm or less.

[0051] In the example shown in FIG. 1 and elsewhere, the top surface N1T of the first nitride semiconductor layer NS1 has a flat shape (a shape with the same or approximately the same height position in the width direction), but this is not limited thereto. In the first nitride semiconductor layer NS1, the position of the top surface N1T may be elevated in the macroscopic shape as the layer grows substantially laterally under the highly flat growth conditions of the present disclosure. For example, in the first nitride semiconductor layer NS1, the middle region MA and the edge region JA may be located above the connection region CA, and the edge region JA may be located above the middle region MA (not shown). Even if the top surface N1T is inclined or curved, forming the Al-based semiconductor layer ALS and the second nitride semiconductor layer NS2 above the first nitride semiconductor layer NS1 makes it easier to flatten the top surface N2T of the second nitride semiconductor layer NS2. By forming the lower layer FL and the upper layer SL of the Al-based semiconductor layer ALS on the curved upper surface N1T, the upper surface LST of the Al-based semiconductor layer ALS can be made flatter than the upper surface N1T. Therefore, the upper surface N2T of the second nitride semiconductor layer NS2 may have a flat shape.

[0052] The Al-based semiconductor layer ALS may contain, for example, 1.5 atomic % or more of aluminum. The aluminum content in the Al-based semiconductor layer ALS is a value expressed as a percentage of the ratio of the atomic weight of aluminum to the total atomic weight of Group III atoms (elements) in the Al-based semiconductor layer ALS, as analyzed using, for example, EDS. A high aluminum content in the Al-based semiconductor layer ALS can facilitate growth of the Al-based semiconductor layer ALS on the upper surface N1T of the first nitride semiconductor layer NS1. The Al-based semiconductor layer ALS may contain more than 1.5 atomic % of aluminum, or may contain 2.0 atomic % or more of aluminum.

[0053] Aluminum-containing nitride semiconductors have low requirements for surface quality that allows growth due to the effect of aluminum. Therefore, the semiconductor substrate 10 may have an edge E1 of the first nitride semiconductor layer NS1 covered with an Al-based semiconductor layer ALS. The semiconductor substrate 10 may also have a by-product BPP in contact with the growth inhibition region DA (here, the surface of the mask portion 5). The by-product BPP may be formed as a by-product during the growth of the Al-based semiconductor layer ALS. The by-product BPP is located on the surface of the mask portion 5 where the first nitride semiconductor layer NS1 is not formed, and includes an aluminum-containing nitride semiconductor. The by-product BPP may include AlGaN or AlN. The by-product BPP may have lower crystallinity than the Al-based semiconductor layer ALS, for example, it may be amorphous. The by-product BPP may also be referred to as a third semiconductor portion.

[0054] The by-product portion BPP can function as a lid for the mask portion 5, and can suppress unintentional Si doping (migration of raw materials from the mask portion 5) into the second nitride semiconductor layer NS2 formed on the Al-based semiconductor layer ALS and into the semiconductor crystal formed above the second nitride semiconductor layer NS2.

[0055] The second nitride semiconductor layer NS2 may also be formed on the surface of the Al-based semiconductor layer ALS covering the edge E1 of the first nitride semiconductor layer NS1, and may have an edge E2 located above the mask portion 5 (growth inhibition region DA). The second nitride semiconductor layer NS2 may not contain aluminum, or may contain aluminum, and may have a lower aluminum content than the Al-based semiconductor layer ALS. The second nitride semiconductor layer NS2 may contain aluminum diffused from the Al-based semiconductor layer ALS due to its connection to the Al-based semiconductor layer ALS. In the second nitride semiconductor layer NS2, the aluminum concentration may be lower closer to the top surface N2T than in a portion closer to the top surface LST of the Al-based semiconductor layer ALS.

[0056] In the semiconductor substrate 10, the threading dislocation density of the upper surface N2T of the first wing portion F1 may be 1 / 5 or less of the threading dislocation density of the first base portion B1. The threading dislocation density of the first wing portion F1 may be, for example, 1 / 10 or less of that of the first base portion B1, which is a dislocation inheritance portion. The threading dislocation density of the first wing portion F1, which is a low defect portion, may be, for example, 5×10 ６ [pcs / cm ２ Threading dislocations are dislocations (defects) that extend in the c-axis direction (<0001> direction) in the semiconductor portion 8. The threading dislocation density can be determined, for example, by subjecting the surface of each portion in the semiconductor portion 8 to CL (Cathode Luminescence) measurement and counting the number of black dots in the CL measurement image.

[0057] Furthermore, for the semiconductor substrate 10, it is also possible to distinguish between regions formed by lateral growth (lateral growth regions) and regions formed by vertical growth (vertical growth regions) based on the CL measurement image. In the CL measurement image, the lateral growth regions and the vertical growth regions may have different brightness levels, allowing their boundaries to be visually recognized. It was confirmed that the first nitride semiconductor layer NS1 formed under the highly flat growth conditions of the present disclosure is a lateral growth region, and that at least the portion of the second nitride semiconductor layer NS2 that overlaps with the first nitride semiconductor layer NS1 in a planar view, except for the portion near the edge E2, is a vertical growth region. The portion of the second nitride semiconductor layer NS2 near the edge E2, in other words, the portion grown from the Al-based semiconductor layer ALS covering the edge E1 of the first nitride semiconductor layer NS1, may be a lateral growth region.

[0058] In the semiconductor substrate 10 of one embodiment, the template substrate TS includes a silicon wafer, a silicon carbide wafer, or a sapphire wafer, and the first nitride semiconductor layer NS1 and the second nitride semiconductor layer NS2 may be layers containing GaN (GaN layers). The mask portion 5 may include a silicon-based mask, and may be, for example, a silicon oxide film or a silicon nitride film. Examples of materials for the mask portion 5 include silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxide (SiO ２), silicon oxynitride (SiON), etc. The mask portion 5 may be a single layer film made of these materials, or may be a multilayer film (laminated film) made of a combination of these materials.

[0059] 1 and 6 , the wing portion F and the mask portion 5 are in close contact with each other, but this is not limiting. In one embodiment, the semiconductor substrate 10 may have a gap between the mask portion 5 (growth inhibition region DA) and the first wing portion F1. The gap may be formed, for example, by a phenomenon in which at least a portion of the wing portion F spontaneously peels off from the mask portion 5 when the temperature is lowered from the growth temperature (during temperature drop) during the formation of the semiconductor portion 8. Alternatively, the gap can be formed by positioning the first seed region S1 higher than the growth inhibition region DA (see the examples described later).

[0060] As described above, the semiconductor substrate 10 according to an embodiment of the present disclosure includes a first semiconductor portion 8A including a first wing portion F1. The first wing portion F1 includes a wide and relatively thin first nitride semiconductor layer NS1 formed under the high-flatness growth conditions of the present disclosure, a thin Al-based semiconductor layer ALS located on the first nitride semiconductor layer NS1, and a thin second nitride semiconductor layer NS2 located on the Al-based semiconductor layer ALS. This allows the surface quality of the second nitride semiconductor layer NS2 to be improved even when the total thickness of the first semiconductor portion 8A is reduced. Therefore, a first wing portion F1 with high surface quality and a relatively thin thickness (adjustable thickness) can be realized. In the semiconductor substrate 10, for example, when the width WF of the first wing portion F1 is approximately 25 μm, the total thickness Dt of the semiconductor portion 8 can be 4 μm or less, and can also be 3 μm or less. Theoretically, the total thickness Dt can be 1 μm or less. The lower limit of the total thickness Dt can be, for example, 0.5 μm. In the semiconductor substrate 10, the ratio of the width WF of the first wing portion F1 to the width WB of the base B may be 5 or more and 100 or less. In the first wing portion F1 of the semiconductor substrate 10, the ratio of the width WF to the total thickness Dt (aspect ratio) may be 20 or more and 300 or less.

[0061] Furthermore, when a silicon-based mask is used for the mask portion 5, the semiconductor substrate 10 has the second nitride semiconductor layer NS2 in which the silicon concentration is significantly reduced compared to a semiconductor layer formed under conventional vertical and horizontal simultaneous growth conditions. This is also of great practical significance in that it makes it relatively easy to control the silicon concentration of the second nitride semiconductor layer NS2 incorporated into a part of a semiconductor device (for example, it makes it easy to adjust the concentration by changing the feed composition of the raw materials).

[0062] [Manufacturing of Semiconductor Substrate] Fig. 7 is a flowchart illustrating an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. Fig. 8 is a flowchart illustrating an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. Fig. 9 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. Fig. 10 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure.

[0063] 7 to 10 , a method for manufacturing a semiconductor substrate 10 according to an embodiment of the present disclosure includes the steps of: preparing a template substrate TS (S10) including a first seed region S1 and a growth inhibition region DA aligned in a first direction (X direction); growing an initial growth layer 8s on the first seed region S1 (S20); growing a first nitride semiconductor layer NS1 having a rough top surface from a side surface 8sS of the initial growth layer 8s above the growth inhibition region DA (S30); and growing an Al-based semiconductor layer ALS so as to fill the rough top surface of the first nitride semiconductor layer NS1 (S40). After performing S20, S30 can be performed by changing the growth conditions. For example, by changing the raw material ratio and increasing the deposition temperature, the highly flat growth conditions of the present disclosure can be achieved.

[0064] In the method for manufacturing the semiconductor substrate 10, in step S30, the first nitride semiconductor layer NS1 may be grown so that the thickness of the portion located on the initial growth layer 8s (the fine growth portion SGP) is ⅕ or less of the thickness of the portion contacting the side surface of the initial growth layer 8s. In step S30, the growth may be stopped before the first nitride semiconductor layer NS1 grown from the initial growth layer 8s on the first seed region S1 and the first nitride semiconductor layer NS1 grown from the initial growth layer 8s on the second seed region S2 meet each other, thereby forming a first gap Gf. In step S40, if the first gap Gf is present, a by-product portion BPP may be formed on the surface of the mask portion 5 that is not covered by the first nitride semiconductor layer NS1, in conjunction with the formation of the Al-based semiconductor layer ALS. The Al-based semiconductor layer ALS and the by-product portion BPP may be connected (continuous) to each other. In the method for manufacturing the semiconductor substrate 10 according to the embodiment of the present disclosure, the second gap Gs is provided above the by-product portion BPP.

[0065] The semiconductor substrate removed from the film forming apparatus after the above S40 (the semiconductor substrate in the state after the above S40) also falls within the category of the semiconductor substrate 10 in one embodiment of the present disclosure.

[0066] In the manufacturing method of the semiconductor substrate 10 according to an embodiment of the present disclosure, after step S40, a step (S50) of forming a second nitride semiconductor layer NS2 on the Al-based semiconductor layer ALS is further performed. The silicon concentration of the upper surface N1T of the first nitride semiconductor layer NS1 may be five times or more the silicon concentration of the upper surface N2T of the second nitride semiconductor layer NS2. The semiconductor substrate 10 may have a gap (third gap) G between the first semiconductor portion 8A and the second semiconductor portion 8C. The width of the gap G may be 10 μm or less, 4 μm or less, or 3 μm or less. By having the gap G, the semiconductor substrate 10 can reduce internal stress in the semiconductor portion 8. This can reduce cracks and defects (dislocations) that occur in the semiconductor portion 8. This effect is particularly effective when the main substrate 1 is a heterogeneous substrate.

[0067] FIG. 11 is a block diagram illustrating a semiconductor substrate manufacturing apparatus according to an embodiment of the present disclosure. As shown in FIG. 11 , the semiconductor substrate manufacturing apparatus 30 includes an apparatus M10 that performs step S10 of FIG. 7 , an apparatus M20 that performs step S20 of FIG. 7 , an apparatus M30 that performs step S30 of FIG. 7 , an apparatus M40 that performs step S40 of FIG. 7 , and an apparatus M50 that performs step S50 of FIG. 8 , as well as a control device MC that controls the apparatuses M10, M20, M30, M40, and M50. The apparatus M10 may include a sputtering apparatus. If a template substrate TS is prepared in advance, the manufacturing apparatus 30 may not include the apparatus M10. The apparatuses M20, M30, M40, and M50 may include, for example, metal-organic chemical vapor deposition (MOCVD) apparatuses. The apparatus M20, the apparatus M30, the apparatus M40, and the apparatus M50 may be a single apparatus, and the above steps S20, S30, S40, and S50 may be performed by a single apparatus. The manufacturing apparatus 30 does not need to include the apparatus M50.

[0068] [Semiconductor Device] The semiconductor portion 8 in the semiconductor substrate 10 has wing portions F, which are low-defect portions. A semiconductor device can be formed using the wing portions F. Specific examples of semiconductor devices include light emitters (LED chips, semiconductor laser chips, etc.), light-emitting elements in which light emitters are submounted, and light-emitting modules in which light-emitting elements are packaged. The semiconductor device is not limited to light-emitting semiconductor devices, and may be, for example, a light-receiving element (photodiode) or a transistor (including a power transistor or a high-electron mobility transistor).

[0069] In the semiconductor substrate 10 according to an embodiment of the present disclosure, the first nitride semiconductor layers NS1 grown in opposite directions to each other in the above step S30 may be joined together. However, when the first nitride semiconductor layers NS1 are formed to be thin, joining the first nitride semiconductor layers NS1 may relatively increase the possibility of cracks or the like occurring.

[0070] Furthermore, in one embodiment of the present disclosure, the semiconductor substrate 10 has a plurality of island-shaped portions grown from each of a plurality of seed regions S, and by making the first gap Gf between adjacent island-shaped portions relatively small, in the above S50, the second nitride semiconductor layer NS2 may be positioned over the plurality of island-shaped portions, and in this case, the gap G may not be present.

[0071] In the semiconductor substrate 10 according to an embodiment of the present disclosure, in the template substrate TS, the growth inhibition region DA may be a modified region of the underlayer 4 or the main substrate 1, and the first seed region S1 (seed region S) may be an unmodified region of the underlayer 4 or the main substrate 1. The surface of the underlayer 4 or the main substrate 1 can be modified by, for example, performing plasma treatment on the underlayer 4 or the main substrate 1.

[0072] In the plasma treatment, for example, argon plasma is irradiated onto a predetermined region of the base layer 4 or the main substrate 1 to modify the surface of the irradiated region and form a growth inhibition region DA. By introducing not only argon gas but also oxygen gas, nitrogen gas, hydrogen gas, or the like into the chamber, the plasma treatment can use oxygen plasma, nitrogen plasma, hydrogen plasma, or a mixture of these plasmas in addition to argon plasma. As a result, the growth inhibition region DA may contain argon, oxygen, nitrogen, or the like as impurities.

[0073] First Embodiment In the following, first, the template substrate TS before the semiconductor portion 8 is formed will be described, and then the semiconductor substrate 10 will be described.

[0074] (Template Substrate) Fig. 12 is a cross-sectional view schematically illustrating the configuration of the template substrate in Example 1. As shown in Fig. 12, in Example 1, the template substrate TS has a base substrate BS including a main substrate 1 and an underlayer 4, and a mask pattern 6 may be formed on the base substrate BS.

[0075] 13 is a cross-sectional view showing an example of the configuration of a base substrate. The base substrate BS may include a main substrate 1 and an underlayer 4 on the main substrate 1. The base substrate BS may also have a metal layer (Al layer) between the main substrate 1 and the underlayer 4. The Al layer and an AlN layer serving as the underlayer 4 may be formed successively by sputtering. The base substrate BS may be formed of a free-standing single-crystal substrate (e.g., a wafer cut from a bulk crystal) of GaN, SiC, or the like, in which case a mask pattern 6 may be disposed on the single-crystal substrate.

[0076] The main substrate 1 may be a silicon substrate, a silicon carbide substrate (4H—SiC, 6H—SiC substrate), a sapphire substrate, a nitride substrate (GaN, AlN substrate, etc.), a ScMgAlO substrate, or the like. The surface orientation of the main substrate 1 may be, for example, the (111) surface of a silicon substrate, or the 6H—SiC (0001) or 4H—SiC (0001) surface of a SiC substrate. The main substrate 1 may also be 3C-SiC. These are merely examples, and the main substrate 1 may have a material and surface orientation that satisfy the following two conditions; the specific material and surface orientation of the main substrate 1 are not necessarily limited. That is, the main substrate 1 may be, first, capable of manufacturing a template substrate TS by forming a seed region S and a growth inhibition region DA above a base substrate BS including the main substrate 1. The main substrate 1 may be, second, capable of growing a semiconductor portion 8 using the template substrate TS. By using an inexpensive substrate as the main substrate 1, the manufacturing costs of the template substrate TS and the semiconductor substrate 10 can be effectively reduced.

[0077] The underlayer 4 may be a GaN-based semiconductor containing aluminum, aluminum nitride (AlN), silicon carbide (SiC), AlScN, graphene, or the like. An AlN layer, an example of the underlayer 4, can be formed to a thickness of approximately 10 nm to 5 μm using, for example, an MOCVD apparatus. The underlayer 4 may also be a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, Al, or the like formed at a low temperature (500°C or less). When a silicon substrate is used as the main substrate 1, it is desirable that the underlayer 4 in contact with the silicon substrate be substantially free of gallium to suppress meltback. "Substantially free of a certain element" means that the element is not intentionally added, and the element may be present as an unintentional impurity. The underlayer 4 may also be formed by a sputtering method. Deposition using a sputtering apparatus (e.g., pulse sputter deposition (PSD) or pulse laser deposition (PLD)) can improve the efficiency of the manufacturing process. The underlayer 4 may have at least one of the effects of increasing the crystallinity of the initial growth layer 8 s and the effect of alleviating internal stress of the initial growth layer 8 s. The underlayer 4 may have a single-layer structure, a multilayer structure, or a multilayer structure including a periodic structure.

[0078] The mask pattern 6 in the template substrate TS is formed on the base substrate BS using a material that suppresses vertical growth (growth in the c-axis direction) of the nitride semiconductor. The template substrate TS may have a first seed region S1 that overlaps with the first opening K1 in a planar view and a second seed region S2 that overlaps with the second opening K2. The mask portion 5 may be, for example, a single-layer film including one of a silicon oxide film (SiOx), a silicon nitride film (SiNx), and a silicon oxynitride film (SiON), or a stacked film including at least two of these.

[0079] The mask portion 5 may be any material capable of forming the first nitride semiconductor layer NS1 from the initial growth layer 8s, and is not necessarily limited to a silicon-based mask. Examples of materials for the mask portion 5 include diamond-like carbon, titanium nitride, molybdenum nitride, tungsten nitride, tantalum carbide, and high-melting-point metals (molybdenum, tungsten, platinum, etc.). The mask portion 5 may be a single-layer film made of one of these materials, or a stacked film containing at least two of these materials. In the semiconductor substrate 10 according to an embodiment of the present disclosure, the upper surface N2T of the second nitride semiconductor layer NS2 may have a lower concentration of impurity components derived from the mask portion 5 than the upper surface N1T of the first nitride semiconductor layer NS1.

[0080] The thickness of the mask portion 5 may be, for example, 0.1 nm to 5 μm, and may be, for example, 10 nm to 1 μm. The width Wm (size in the X direction) of the mask portion 5 may be, for example, 10 μm or more, and may be, for example, 20 μm to 500 μm.

[0081] The openings K (exposed portions of the seed regions S) in the mask pattern 6 serve as growth starting points for the initial growth layer 8s. The openings K may have a longitudinal shape with the first direction (X direction) as the width direction and the second direction (Y direction) as the longitudinal direction. The mask pattern 6 may have a plurality of openings K arranged in the first direction (X direction). The openings K may have a tapered shape (a shape in which the width narrows downward). The width Wk (size in the first direction) of the openings K may be, for example, approximately 0.1 μm to 20 μm. The width Wk of the openings K may be smaller than the width Wm of the mask portion 5. The ratio of the thickness of the mask portion 5 to the width Wk of the openings K may be 3.0 or less. The smaller the width Wk of the openings K, the fewer the number of threading dislocations propagating from the openings K to the semiconductor portion 8. Furthermore, the wing portions F (low-defect portions) may be enlarged.

[0082] FIG. 14 is a cross-sectional view showing an example of the configuration of a template substrate. As shown in FIG. 14 , the template substrate TS may have a configuration in which an underlayer 4 (e.g., AlN) and a mask pattern 6 are formed in this order on a main substrate 1 (e.g., a silicon substrate). Alternatively, the template substrate TS may have a configuration in which a multi-layer underlayer 4 (including a buffer portion 2 and a seed portion 3) and a mask pattern 6 are formed in this order on the main substrate 1. The underlayer 4 may be formed locally (e.g., in a stripe pattern) so as to overlap with the opening K of the mask pattern 6 in a planar view. The template substrate TS may also have a configuration in which the mask pattern 6 is formed on the main substrate 1 (e.g., a SiC bulk crystal substrate or a GaN bulk crystal substrate). The template substrate TS is not limited to an example in which the mask pattern 6 is formed on a base substrate BS. A growth inhibition region DA and a seed region S may be formed on the base substrate BS. For example, the growth inhibition region DA may be a surface-modified region of the main substrate 1 or the underlayer 4, and the seed region S may be the surface of the underlayer 4. The seed region S may be located above the growth inhibition region DA.

[0083] The seed portion 3 is a growth starting point for the initial growth layer 8s and can function as a seed region S. The seed portion 3 can be made of a GaN-based semiconductor, aluminum nitride (AlN), silicon carbide (SiC), AlScN, graphene, or the like. The seed portion 3 may be made of a material containing at least Al and N. The material of the seed portion 3 may be a nitride semiconductor containing aluminum. The silicon carbide used for the seed portion 3 may be hexagonal 6H—SiC or 4H—SiC. The seed portion 3 may be made of a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, an AlGaInN layer, or the like formed at a low temperature (500°C or less). The thickness of the seed portion 3 may be approximately 10 nm to 500 nm.

[0084] For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed portion 3, a buffer portion 2 including at least one of an AlN layer and a SiC (silicon carbide) layer may be provided to reduce the possibility of the two (main substrate and seed portion) fusing together. The buffer portion 2 improves the crystallinity and flatness of the seed portion 3. The thickness of the buffer portion 2 may be, for example, approximately 10 nm to 500 nm. The silicon carbide used for the buffer portion 2 may be hexagonal (6H—SiC, 4H—SiC) or cubic (4C—SiC). At least one of the buffer portion 2 (e.g., aluminum nitride) and the seed portion 3 (e.g., GaN-based semiconductor) may also be formed using a sputtering apparatus.

[0085] The underlayer 4 may include a strain relaxation layer. Examples of the strain relaxation layer include an AlGaN superlattice structure and a graded structure in which the Al composition of AlGaN changes stepwise. The strain relaxation layer can relieve stress in the longitudinal direction of the semiconductor portion 8. At least one of the buffer portion 2 and the seed portion 3 may include a strain relaxation layer.

[0086] When a main substrate 1 that does not fuse with the seed portion 3 is used, it is possible to configure the structure without providing the buffer portion 2. Also, when a seed portion 3 that is less reactive with the main substrate 1 is used, it is possible to configure the structure without providing the buffer portion 2.

[0087] As an example of the template substrate TS, a silicon substrate is used as the main substrate 1, an AlN layer (about 30 nm to 300 nm, for example, 150 nm) is used as the buffer portion 2 of the underlayer 4, a GaN-based graded layer is used as the seed portion 3 of the underlayer 4, and a silicon nitride film (SiN) can be used as the mask portion 5. The GaN-based graded layer can be, for example, an Al ０．６ Ga ０．４ It may include an N layer (eg, 300 nm) and a second GaN layer (eg, 1 to 2 μm).

[0088] (Semiconductor Substrate) FIG. 15 is a cross-sectional view schematically illustrating the configuration of a semiconductor substrate in Example 1. FIG. 16 is a plan view schematically illustrating the configuration of a semiconductor substrate in Example 1. As shown in FIGS. 15 and 16 , the semiconductor substrate 10 in Example 1 includes a first semiconductor portion 8A and a second semiconductor portion 8C above a template substrate TS having a base substrate BS and a mask pattern 6. A gap G may be formed between an edge E2 of a first wing portion F1 in the first semiconductor portion 8A and an edge E3 of a second wing portion F2 in the second semiconductor portion 8C. The edges E2 and E3 may each be inclined. The width of the gap G may be the shortest distance between the edges E2 and E3, and may be, for example, 10 μm or less, 5 μm or less, 3 μm or less, or 2 μm or less.

[0089] In the manufacturing process of the semiconductor substrate 10, a by-product portion BPP may be formed as the Al-based semiconductor layer ALS is formed. In the semiconductor substrate 10, the mask portion 5 or the by-product portion BPP may be exposed at the gap G. The Al-based semiconductor layer ALS and the by-product portion BPP may or may not be connected to each other. For example, the Al-based semiconductor layer ALS may not cover the entire surface of the edge E1 of the first nitride semiconductor layer NS1, and the by-product portion BPP may be formed in a part of the mask portion 5 where the first nitride semiconductor layer NS1 is not formed. Furthermore, a part of the by-product portion BPP may be covered by the second nitride semiconductor layer NS2.

[0090] The Al-based semiconductor layer ALS and the by-product portion BPP may contain aluminum gallium nitride. In the aluminum gallium nitride, the composition ratio of Al to Ga and Al may be, for example, 0.010 or more, 0.015 or more, or 0.020 or more. In the aluminum gallium nitride, the composition ratio of Al to Ga and Al may be, for example, 0.20 or less. The aluminum gallium nitride may have a graded structure in which the Al composition changes stepwise in the thickness direction. The Al-based semiconductor layer ALS may be mainly composed of aluminum gallium nitride. The by-product portion BPP may have a smaller thickness than the Al-based semiconductor layer ALS. The surface roughness of the by-product portion BPP may be greater than the surface roughness of the Al-based semiconductor layer ALS.

[0091] Fig. 17 is a cross-sectional view showing an example of lateral growth of the first nitride semiconductor layer NS1. Fig. 18 is a cross-sectional view showing an example of growth of the Al-based semiconductor layer ALS and the second nitride semiconductor layer NS2. Figs. 17 and 18 show an example in which the mask pattern 6 has a rectangular opening K in cross section.

[0092] 17, first, an initial growth layer 8s is grown vertically, starting from a seed region S located overlapping the opening K. By controlling the growth conditions in the ELO method, it is possible to control the growth of the nitride semiconductor to either the c-axis direction or the a-axis direction (X direction).

[0093] As mentioned above, lateral growth in the ELO method generally uses growth conditions that allow for some vertical growth as well as lateral growth (simultaneous vertical and horizontal growth conditions). Examples of such conventional simultaneous vertical and horizontal growth conditions include a growth temperature of 1000 to 1200°C, a V / III ratio of 500 to 20,000, and a growth pressure of 50 kPa.

[0094] In the example shown in Figure 17, after the initial growth layer 8s is formed, the growth conditions are significantly changed. Specifically, in the stage of forming the initial growth layer 8s, for example, the growth temperature can be about 1030°C and the V / III can be about 2000. The growth of the initial growth layer 8s can be stopped when the opening K is filled with the initial growth layer 8s and the upper surface 8sT is higher than the growth inhibition region DA. The protrusion height Ds of the initial growth layer 8s (the distance between the upper surface 8sT and the growth inhibition region DA in the height direction) can be, for example, about 0.5 μm to 2 μm.

[0095] After the initial growth layer 8s is formed, the growth conditions are switched to high-flat growth conditions. For example, the growth temperature is increased and the supply rate of raw materials (such as gallium source raw materials and nitrogen source raw materials) is reduced. This allows the first nitride semiconductor layer NS1 to grow substantially only laterally, starting from the initial growth layer 8s. Under the high-flat growth conditions of the present disclosure, the supply rate of raw materials is reduced, so the lateral growth rate may be relatively lower than that under conventional simultaneous vertical and horizontal growth conditions. During the growth of the first nitride semiconductor layer NS1, silicon concentration occurs on the top surface N1T, forming a fine structure. On the top surface N1T, the connection region CA may have a higher silicon concentration than the edge region JA. The growth of the first nitride semiconductor layer NS1 may be stopped before the first nitride semiconductor layer NS1 grown from the initial growth layer 8s on the first seed region S1 and the first nitride semiconductor layer NS1 grown from the initial growth layer 8s on the second seed region S2 meet each other. This forms a first gap Gf. After two first nitride semiconductor layers NS1 grown so as to approach each other are joined, the joined portion can be removed by etching or the like to form the first gap Gf.

[0096] The width of the first nitride semiconductor layer NS1 is defined as W1, and the thickness of the first nitride semiconductor layer NS1 is defined as D10. The thickness D10 may be greater than the protrusion height Ds of the initial growth layer 8s. The first nitride semiconductor layer NS1 may undergo slight vertical growth under the highly flat growth conditions of the present disclosure. The top surface N1T may be inclined or curved. The edge region JA (the portion near the edge E1) of the top surface N1T may be higher than the connection region CA (the portion near the initial growth layer 8s). The ratio (W1 / D10) of the width W1 (size in the X direction) to the thickness D10 of the first nitride semiconductor layer NS1 may be, for example, 2.0 or greater. W1 / D10 may be 2.0 or greater, 4.0 or greater, 5.0 or greater, 7.0 or greater, or 10.0 or greater. By setting W1 / D10 to 2.0 or more, the internal stress of the first nitride semiconductor layer NS1 can be easily reduced. As a result, warpage of the semiconductor substrate 10 can be reduced. The width W1 of the first nitride semiconductor layer NS1 may be, for example, 7.0 μm or more, 10.0 μm or more, 20.0 μm or more, or 40.0 μm or more. The thickness D10 may be 10.0 μm or less, 5.0 μm or less, or 2.0 μm or less.

[0097] Next, as shown in FIG. 18 , an Al-based semiconductor layer ALS is grown to fill the roughness of the upper surface of the first nitride semiconductor layer NS1. By successively forming the first nitride semiconductor layer NS1 and the Al-based semiconductor layer ALS, the Al-based semiconductor layer ALS can be formed with the upper surface N1T in a relatively active state. For example, the growth temperature is lowered from the high-flatness growth conditions of the present disclosure, and the source supply conditions are changed. Specifically, for example, an aluminum source source is supplied while maintaining the supply of a gallium source source and a nitrogen source source. The source supply amounts may be appropriately adjusted according to the composition of the Al-based semiconductor layer ALS, thereby forming an Al-based semiconductor layer ALS including a lower layer FL and an upper layer SL (see FIGS. 4 and 5 ). The Al-based semiconductor layer ALS may be formed to cover the edge E1 of the first nitride semiconductor layer NS1. The Al-based semiconductor layer ALS does not need to have a multi-layer structure like the lower layer FL and upper layer SL in the portion covering the edge E1. This is because the edge E1 does not have a fine structure like the top surface N1T. Depending on the size of the first gap Gf, the Al-based semiconductor layer ALS may cover a part of the edge E1, or the Al-based semiconductor layer ALS may not be in contact with the edge E1.

[0098] 18 , as the Al-based semiconductor layer ALS is formed, a by-product portion BPP is formed in the second gap Gs, and the by-product portion BPP does not have to be connected to the Al-based semiconductor layer ALS. The by-product portion BPP does not have to be formed in the second gap Gs. The by-product portion BPP can be formed by adsorption and deposition of (atoms or molecules derived from) raw materials that have reached the growth inhibition region DA (the surface of the mask portion 5).

[0099] Next, as shown in FIG. 18 , a second nitride semiconductor layer NS2 is formed on the Al-based semiconductor layer ALS. By continuously forming the Al-based semiconductor layer ALS and the second nitride semiconductor layer NS2, the second nitride semiconductor layer NS2 can be formed with the top surface LST in a relatively active state. For example, the supply of the aluminum source material is stopped while the supply of the gallium source material and the nitrogen source material is maintained. The growth temperature can also be changed appropriately. This allows the second nitride semiconductor layer NS2 to be formed. In the example shown in FIG. 18 , the edge E2 of the second nitride semiconductor layer NS2 has an inclined surface (facet). The edge E2 may be a crystal plane, such as the (11-22) plane or the (11-2β) plane (β is an integer) of the nitride semiconductor crystal. The edge E2 of the second nitride semiconductor layer NS2 does not have to be an inclined surface. In this case, it may be a plane (e.g., the (11-20) plane) along the c-axis of the nitride semiconductor crystal. During the growth of the second nitride semiconductor layer NS2, raw materials may further be deposited in the by-product portion BPP.

[0100] In Example 1, the width Wm of the mask portion 5 was 50 μm, the width Wk of the opening K was 5 μm, the lateral width of the semiconductor portion 8 was 53 μm, the width WF of the wing portion F (size in the X direction) was 24 μm, the thickness D10 of the first nitride semiconductor layer NS1 was 2 μm, the thickness D3 of the Al-based semiconductor layer ALS was 150 nm, and the thickness D2 of the second nitride semiconductor layer NS2 was 0.5 μm (see FIGS. 6 and 12 for reference symbols). The aspect ratio of the semiconductor portion 8 was 53 μm / 2.65 μm=20, and the aspect ratio of the wing portion F was 24 μm / 2.65 μm=9.06, which were very high aspect ratios, and the total thickness of the semiconductor portion 8 was approximately 4 μm or less, which was an extremely high level of thinning.

[0101] FIG. 19 shows the results of SIMS analysis of the impurity concentrations contained in the template substrate TS, the first nitride semiconductor layer NS1, the Al-based semiconductor layer ALS, and the second nitride semiconductor layer NS2. The SIMS analysis was performed using a CAMECA IMS-6f, with the following analysis conditions: a primary ion species of Cs+, a primary acceleration voltage of 15.0 kV, and a detection area of ​​8 μmφ. In FIG. 19, the vertical axis on the left represents the concentrations of H (hydrogen), C (carbon), O (oxygen), and Si (silicon), respectively, and the vertical axis on the right represents the secondary ion intensity of Ga (gallium) and Al (aluminum). The horizontal axis represents the depth from the reference point. In FIG. 19, H is represented by a solid line, C by a dashed line, O by a dotted line, Si by a thick line, Ga by a two-dot chain line, and Al by a thick one-dot chain line. In Figure 19, the locations corresponding to the interfaces between the template substrate TS, the first nitride semiconductor layer NS1, the Al-based semiconductor layer ALS, and the second nitride semiconductor layer NS2 are indicated by vertical dashed lines. Figure 19 shows that the silicon concentration at the top surface N1T of the first nitride semiconductor layer NS1 (the interface between the first nitride semiconductor layer NS1 and the Al-based semiconductor layer ALS) is relatively higher than the silicon concentration at the top surface N2T of the second nitride semiconductor layer NS2 (the left end of the figure). In Figure 19, the concentrations are detected as high in the region corresponding to the top surface N2T of the second nitride semiconductor layer NS2 (the left end of the figure) due to the influence of the atmosphere in the chamber where the surface is exposed, and the values ​​at a depth of 0 to 15 nm can be ignored. In reality, there is no significant difference in silicon concentration between the interior of the second nitride semiconductor layer NS2 and the top surface N2T.

[0102] FIG. 20 shows the results of overlaying the TEM image of the first nitride semiconductor layer NS1 shown in FIG. 5 with the abundance ratios of each element (silicon, aluminum, etc.) obtained by EDS. The TEM analysis was performed using a JEOL JEM-ARM200F, with the analysis conditions being an acceleration voltage of 200 kV. The EDS analysis was performed using a JEOL JED-2300T, with the analysis conditions being an acceleration voltage of 200 kV, a probe current of approximately 80 pA, a time constant of approximately T4, and a dwell time of 20 s. In FIG. 20, the vertical axis on the left indicates the abundance ratios (%) of N (nitrogen), Ga (gallium), and Al (aluminum) at the location of the thick right-pointing arrow shown in the center of the figure. The vertical axis on the right indicates the abundance ratio (%) of Si (silicon) at the location of the thick right-pointing arrow shown in the center of the figure. The horizontal axis indicates the distance from the reference point. As shown in Figure 20, the silicon concentration of the top surface N1T of the first nitride semiconductor layer NS1 is approximately 0.5%, while the other portions are less than approximately 0.1%. This indicates that the top surface N1T of the first nitride semiconductor layer NS1 has a higher silicon concentration than the other portions. Also, in Figure 20, the aluminum abundance ratio is approximately 8% at the first boundary portion BP1, approximately 6% at the second boundary portion BP2, approximately 2% at the lower layer FL, approximately 4% at the main portion MP, and approximately 7% at the top surface LST. Here, "approximately" means that the value includes an error of ±10%.

[0103] 17 and 18 , the opening K may have a tapered shape (a shape whose width narrows toward the base substrate BS). The initial growth layer 8s may rise onto the upper surface of the mask portion 5, and the width W2 of the upper surface 8sT may be larger than the width Wk of the opening K. The width W2 of the upper surface 8sT may correspond to the width WB (see FIG. 6 ) of the first base portion B1 of the first semiconductor portion 8A in the semiconductor substrate 10.

[0104] In the example shown in Figures 17 and 18, the back surface N1B of the first nitride semiconductor layer NS1 is in contact with the mask portion 5, but this is not limited to this, and the semiconductor substrate 10 may have a gap between the back surface N1B and the mask portion 5.

[0105] 21 is a plan view showing another example of the configuration of the semiconductor substrate 10 in Example 1. In FIG. 21, each component is hatched in the plan view for clarity. As shown in FIG. 21, the first wing portion F1 may be separated into multiple parts PA arranged in a second direction (Y direction) perpendicular to the first direction (X direction). For example, multiple trenches TR extending in the X direction may be formed.

[0106] FIG. 22 is a cross-sectional view showing another example of the configuration of the semiconductor substrate 10 in Example 1. FIG. 23 is a plan view showing another example of the configuration of the semiconductor substrate in Example 1. In FIG. 23, each component is hatched in the plan view for clarity. As shown in FIGS. 22 and 23, the semiconductor substrate 10 may be located on a first semiconductor portion 8A and include a functional layer (device layer) 9 including an active layer. In the example shown in FIGS. 22 and 23, the functional layer 9 is formed on the semiconductor portion 8.

[0107] The functional layer 9 may be a single layer or a laminate. The functional layer 9 may include a p-type layer, an n-type layer, or an electron blocking layer. The active layer may have a quantum well structure. The functional layer 9 may have at least one of the following functions: a function as a component of a semiconductor device; a protection function against external forces; a protection function against static electricity; a protection function for preventing the intrusion of foreign substances such as water and oxygen; a protection function against etchants, etc.; an optical function; and a sensing function. The functional layer 9 may also be formed on the side surfaces (end faces) of the first semiconductor portion 8A and the second semiconductor portion 8C.

[0108] The second nitride semiconductor layer NS2 and the functional layer 9 may be made of GaN-based semiconductors and may be formed continuously in an MOCVD apparatus. During the formation of the functional layer 9, the thickness of the functional layer 9 is thin and the width of the gap G is narrow, so that the deposition of raw materials on the by-product portion BPP is not a problem. Furthermore, as will be described later, the semiconductor portion 8 and the functional layer 9 can be separated from the template substrate TS.

[0109] An anode EA and a cathode EC may be provided on the functional layer 9. The anode EA may be in contact with a p-type layer in the functional layer 9, and the cathode EC may be in contact with an n-type layer in the functional layer 9. In a plan view, at least a portion of the anode EA may be positioned to overlap with the first wing portion F1, or the entire anode EA may be positioned to overlap with the first wing portion F1. The first semiconductor portion 8A may include a third wing portion F3 positioned on the opposite side of the first wing portion F1 in the X direction from the first wing portion F1, with the first base portion B1 interposed therebetween. The third wing portion F3 has, like the first wing portion F1, a first nitride semiconductor layer NS1, an Al-based semiconductor layer ALS, and a second nitride semiconductor layer NS2. The cathode EC may be in contact with an upper surface N2T of the second nitride semiconductor layer NS2 in the third wing portion F3.

[0110] A device structure including the semiconductor portion 8 and the functional layer 9 is referred to as a laminated body LB. The semiconductor substrate 10 has a plurality of bar-shaped laminated bodies LB. For the functional layer 9 formed on the semiconductor portion 8, by forming at least the active region (e.g., light-emitting region) above the wing portion F, a very high-quality element can be fabricated.

[0111] Fig. 24 is a cross-sectional view showing a method for element isolation in Example 1. Fig. 25 is a plan view showing a method for element isolation in Example 1. As shown in Figs. 24 and 25 , the semiconductor substrate 10 may have a plurality of element bodies 20 separated by a plurality of trenches TR on a base substrate BS. The element bodies 20 may include wing portions F, a functional layer 9, an anode EA, and a cathode EC.

[0112] The semiconductor substrate 10 may have a plurality of element bodies 20 formed therein by forming a plurality of trenches TR in the laminate LB by etching. Alternatively, the semiconductor substrate 10 may be divided into a plurality of parts PA (see FIG. 21 ) by forming a plurality of trenches TR in the semiconductor portion 8, and then the functional layer 9, anode EA, and cathode EC may be formed on the parts PA. Alternatively, the semiconductor substrate 10 may have a plurality of element bodies 20 formed therein by cleaving the laminate LB.

[0113] The mask portion 5 may be removed by etching using hydrofluoric acid, buffered hydrofluoric acid (BHF), or the like. In this case, the element body 20 can be easily separated from the base substrate BS. The semiconductor substrate 10 may have a gap between the back surface N1B of the thin first nitride semiconductor layer NS1 and the surface of the mask portion 5, and the mask portion 5 need not be removed. For example, the element body 20 may be bonded to the support substrate SK via bonding layers H1 and H2. The bond between the seed region S and the semiconductor portion 8 (initial growth layer 8s) is then broken, thereby peeling the element body 20 from the base substrate BS. The support substrate SK may have a conductive pad in contact with the bonding layer H1 and a conductive pad in contact with the bonding layer H2. The bonding layers H1 and H2 may be formed of a solder material.

[0114] The element body (semiconductor device) 20 includes a first nitride semiconductor layer NS1, an Al-based semiconductor layer ALS containing aluminum and located on the first nitride semiconductor layer NS1, a second nitride semiconductor layer NS2 located on the Al-based semiconductor layer ALS, and a functional layer 9 located on the second nitride semiconductor layer NS2, wherein an upper surface N2T of the second nitride semiconductor layer NS2 has a lower concentration of silicon as an impurity than an upper surface N1T of the first nitride semiconductor layer NS1. In the element body 20, the upper surface roughness of the aluminum-based semiconductor layer ALS may be smaller than that of the first nitride semiconductor layer NS1. Specific examples of the element body 20 include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, and transistors (including power transistors and high electron mobility transistors).

[0115] 26 is a plan view showing another example of the configuration of the semiconductor substrate 10 in Example 1. As shown in Fig. 26, the semiconductor substrate 10 may have the anode EA and the cathode EC formed above the same wing portion F (e.g., the first wing portion F1). A trench TR (not shown) may be formed in a portion of the stacked body LB located above the seed region S.

[0116] 27 is a cross-sectional view schematically illustrating the configuration of a semiconductor substrate 10 in Example 2. In Fig. 27, the black dots illustrated at the positions indicated by the lead lines of the reference symbols J1 and J2 represent spaces (gaps) between the wing portions F and the template substrate TS.

[0117] 27 , in the semiconductor substrate 10 of Example 2, the template substrate TS may have a ridge portion R on its upper surface, and a first seed region S1 may be located on the upper surface of the ridge portion R. A first gap J1 (gap J) may be present between the first semiconductor portion 8A and the mask portion 5. The first gap J1 can also be considered to be a space sandwiched between the growth inhibition region DA and the first wing portion F1. The first wing portion F1 is spaced apart from the mask portion 5, which functions as the growth inhibition region DA. The first seed region S1 (the surface thereof) is located above the growth inhibition region DA, and the first semiconductor portion 8A has a first base portion B1 located on the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth inhibition region DA via the first gap J1.

[0118] In the template substrate TS, the base layer 4 may not overlap the mask portion 5 in a plan view, and the base layer 4 may be included in the ridge portion R. The upper surface (first seed region S1) of the ridge portion R may be formed by the base layer 4, and the side surface of the ridge portion R may be covered by the mask portion 5. In the template substrate TS, a part of the mask portion 5 may be included in the side surface of the ridge portion R. The base layer 4 may not be exposed on the side surface of the ridge portion R. The side surface of the ridge portion R may not be in contact with the first wing portion F1 (first nitride semiconductor layer NS1). The entire side surface of the ridge portion R may face the first gap J1. This reduces the contact area between the ridge portion R and the first wing portion F1, and as a result, the defect density of the first wing portion F1 can be reduced.

[0119] The first semiconductor portion 8A can be formed by growing an initial growth layer 8s starting from the base layer 4 exposed in the ridge portion R, then growing a first nitride semiconductor layer NS1 under the highly flat growth conditions of the present disclosure, and then growing an Al-based semiconductor layer ALS and a second nitride semiconductor layer NS2.

[0120] In the semiconductor substrate 10, a second gap J2 (gap J) may be present between the second semiconductor portion 8C and the mask portion 5, and the second gap J2 may have the same configuration as the first gap J1. The template substrate TS of the example shown in FIG. 27 can be formed by etching the main substrate 1 and the underlayer 4 using a resist, forming the mask portion 5, and lifting off the resist. The main substrate 1 may include a convex portion Q on its main surface, and at least a part of the convex portion Q may be included in the ridge portion R. In the semiconductor substrate 10, the side surface of the ridge portion R (mask portion 5) may be in contact with the first wing portion F1 (first nitride semiconductor layer NS1).

[0121] Example 3 Figure 28 is a cross-sectional view schematically illustrating the configuration of a semiconductor substrate 10 in Example 3. As shown in Figure 28, in the semiconductor substrate 10 in Example 3, the template substrate TS has a modified region of the underlayer 4 that serves as a growth inhibition region DA. The method of modifying the surface of the underlayer 4 to form the growth inhibition region DA is not particularly limited. For example, the underlayer 4 may be subjected to a plasma treatment, an annealing treatment, or an impurity ion implantation treatment. The underlayer 4 may be a seed portion 3.

[0122] 28 , after forming convex portions 4Q on the surface of the base layer 4, growth inhibition regions DA are formed in portions of the base layer 4 other than the protruding surfaces (high-position surfaces) of the convex portions 4Q. The surfaces of the convex portions 4Q in the ridge portion R may serve as first seed regions S1. The first semiconductor portion 8A can be formed by growing an initial growth layer 8s starting from the base layer 4 exposed in the ridge portion R, then growing a first nitride semiconductor layer NS1 under the highly flat growth conditions of the present disclosure, and then growing an Al-based semiconductor layer ALS and a second nitride semiconductor layer NS2.

[0123] [Other Configuration Examples] FIG. 29 is a schematic diagram showing one configuration example of an electronic device. The electronic device 55 of FIG. 29 includes a semiconductor device 25 including a semiconductor portion 8, a drive substrate 23 on which the semiconductor device 25 is mounted, and a control circuit 27 that controls the drive substrate 23. FIG. 30 is a schematic diagram showing another configuration example of an electronic device. The element region (element portion) PA does not need to be peeled off from the template substrate TS. The electronic device 55 of FIG. 30 includes a semiconductor substrate 10 including the template substrate TS and the element region PA, a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 27 that controls the drive substrate 23. In this case, the main substrate 1 included in the template substrate TS may be a light-transmitting substrate (e.g., a sapphire substrate). Examples of the electronic device 55 include a light-emitting device, a display device, a laser emission device (including a Fabry-Perot type and a surface-emitting type), a measurement device, a lighting device, a communication device, an information processing device, and a power control device.

[0124] [Additional Notes] The invention according to the present disclosure has been described above based on the drawings and examples. However, the invention according to the present disclosure is not limited to the above-described embodiments and examples. In other words, the invention according to the present disclosure can be modified in various ways within the scope of the present disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments and examples are also included in the technical scope of the invention according to the present disclosure. In other words, it should be noted that a person skilled in the art can easily make various modifications or corrections based on the present disclosure. It should also be noted that these modifications or corrections are included in the scope of the present disclosure.

[0125] [Summary] A semiconductor substrate in aspect 1 of the present disclosure comprises a template substrate including a first seed region and a growth-inhibition region aligned in a first direction, and a first semiconductor portion located above the first seed region and the growth-inhibition region, the first semiconductor portion including a first wing portion located above the growth-inhibition region, the first wing portion having a first nitride semiconductor layer, an aluminum-based semiconductor layer containing aluminum and located on the first nitride semiconductor layer, and a second nitride semiconductor layer located on the aluminum-based semiconductor layer, and the upper surface of the second nitride semiconductor layer has a lower silicon concentration than the upper surface of the first nitride semiconductor layer.

[0126] In a semiconductor substrate according to a second aspect of the present disclosure, in the first aspect, the aluminum-based semiconductor layer has a smaller top surface roughness than the first nitride semiconductor layer.

[0127] In a third aspect of the present disclosure, the semiconductor substrate is the first or second aspect, wherein the silicon concentration in the upper surface of the first nitride semiconductor layer is at least five times the silicon concentration in the upper surface of the second nitride semiconductor layer.

[0128] In a fourth aspect of the present disclosure, in the semiconductor substrate of any one of the first to third aspects, the silicon concentration distribution in the first direction is non-uniform on the top surface of the first nitride semiconductor layer.

[0129] The semiconductor substrate in aspect 5 of the present disclosure is, in any one of aspects 1 to 4, the first semiconductor portion includes a first base portion located above the first seed region, and the upper surface of the first nitride semiconductor layer includes a connection region connected to the first base portion and an edge region spaced apart from the first base portion in the first direction, and the silicon concentration in the connection region is higher than the silicon concentration in the edge region.

[0130] The semiconductor substrate in aspect 6 of the present disclosure is, in any one of aspects 1 to 5, wherein the first semiconductor portion includes a first base portion located above the first seed region, and the upper surface of the first nitride semiconductor layer includes a connection region connected to the first base portion and an edge region spaced apart from the first base portion in the first direction, and the upper surface roughness of the connection region is greater than the upper surface roughness of the edge region.

[0131] A semiconductor substrate according to Aspect 7 of the present disclosure is any one of Aspects 1 to 6, wherein the first nitride semiconductor layer has a ratio of the length in the first direction to the thickness of 5.0 or more.

[0132] In an eighth aspect of the present disclosure, in the semiconductor substrate of any one of the first to seventh aspects, the aluminum-based semiconductor layer covers a side surface of the first nitride semiconductor layer.

[0133] A semiconductor substrate according to a ninth aspect of the present disclosure is the semiconductor substrate according to any one of the first to eighth aspects, which includes a silicon-based mask that functions as the growth suppression region.

[0134] A semiconductor substrate according to a tenth aspect of the present disclosure is any one of the first to ninth aspects, wherein the surface layer of the first nitride semiconductor layer has a plurality of recesses having a depth of 20 to 80 nm.

[0135] In an eleventh aspect of the present disclosure, the semiconductor substrate is any one of the first to tenth aspects, wherein the first and second nitride semiconductor layers are thicker than the aluminum-based semiconductor layer.

[0136] In a twelfth aspect of the present disclosure, in the semiconductor substrate of any one of the first to eleventh aspects, the threading dislocation density of the upper surface of the first wing portion is equal to or less than 1 / 5 of the threading dislocation density of the first base portion.

[0137] A semiconductor substrate according to Aspect 13 of the present disclosure is any one of Aspects 1 to 12, wherein the aluminum-based semiconductor layer contains 1.5 atomic % or more of aluminum.

[0138] In a semiconductor substrate according to aspect 14 of the present disclosure, in the semiconductor substrate according to aspect 10, the aluminum-based semiconductor layer includes a lower layer at least a portion of which is located inside the depression of the recess of the first nitride semiconductor layer, and an upper layer that is flatter than the lower layer, and the lower layer has a lower aluminum concentration than the upper layer.

[0139] A semiconductor substrate according to a fifteenth aspect of the present disclosure is any one of the first to fourteenth aspects, wherein the aluminum-based semiconductor layer is a layer containing AlGaN or AlN.

[0140] A semiconductor substrate in aspect 16 of the present disclosure is any one of aspects 1 to 15, wherein the template substrate includes a silicon wafer, a silicon carbide wafer, or a sapphire wafer, and the first and second nitride semiconductor layers are layers containing GaN.

[0141] The semiconductor substrate according to Aspect 17 of the present disclosure is the semiconductor substrate according to any one of Aspects 1 to 16, further comprising a functional layer including an active layer above the first wing portion.

[0142] The semiconductor substrate in aspect 18 of the present disclosure is any one of aspects 1 to 17, wherein the template substrate comprises a second seed region and a second semiconductor portion located above the second seed region and the growth inhibition region, the second semiconductor portion includes a second base portion located above the second seed region and a second wing portion located above the growth inhibition region, and the first wing portion and the second wing portion are adjacent to each other with a gap between them.

[0143] A semiconductor substrate according to Aspect 19 of the present disclosure is any one of Aspects 1 to 18, wherein a gap is located between the growth inhibition region and the first wing portion.

[0144] A method for manufacturing a semiconductor substrate in aspect 20 of the present disclosure includes the steps of preparing a template substrate including a first seed region and a growth inhibition region aligned in a first direction, growing an initial growth layer on the first seed region, growing a first nitride semiconductor layer having a rough top surface from a side surface of the initial growth layer above the growth inhibition region, and growing an aluminum-based semiconductor layer so as to fill in the rough top surface of the first nitride semiconductor layer.

[0145] A twenty-first aspect of the present disclosure relates to the method for manufacturing a semiconductor substrate according to the twenty-first aspect, and further includes the step of forming a second nitride semiconductor layer on the aluminum-based semiconductor layer.

[0146] In the method for manufacturing a semiconductor substrate in aspect 22 of the present disclosure, in aspect 20 or 21, the first nitride semiconductor layer is grown so that the thickness of the portion located on the initial growth layer is 1 / 5 or less of the thickness of the portion contacting the side surface of the initial growth layer.

[0147] A method for manufacturing a semiconductor substrate in aspect 23 of the present disclosure is any one of aspects 20 to 22, wherein the silicon concentration in the upper surface of the first nitride semiconductor layer is five times or more the silicon concentration in the upper surface of the second nitride semiconductor layer.

[0148] The semiconductor substrate manufacturing apparatus according to Aspect 24 of the present disclosure performs each step according to any one of Aspects 20 to 23.

[0149] A semiconductor device in aspect 25 of the present disclosure has a first nitride semiconductor layer, an aluminum-based semiconductor layer containing aluminum and located on the first nitride semiconductor layer, a second nitride semiconductor layer located on the aluminum-based semiconductor layer, and a functional layer located on the second nitride semiconductor layer, and the upper surface of the second nitride semiconductor layer has a lower silicon concentration than the upper surface of the first nitride semiconductor layer.

[0150] REFERENCE SIGNS LIST 1 Main substrate 4 Underlayer 5 Mask portion 6 Mask pattern 8 Semiconductor portion 8A First semiconductor portion 8C Second semiconductor portion 8s Initial growth layer 9 Functional layer 10 Semiconductor substrate 25 Semiconductor device 30 Semiconductor substrate manufacturing apparatus ALS Al-based semiconductor layer BPP By-product portion BS Base substrate B1 First base portion B2 Second base portion CA Connection region DA Growth inhibition region F1 First wing portion F2 Second wing portion JA Edge region J1 First gap J2 Second gap K1 First opening K2 Second opening N1T Upper surface N2T Upper surface NS1 First nitride semiconductor layer NS2 Second nitride semiconductor layer SGP Fine growth portion S Seed region S1 First seed region S2 Second seed region TS Template substrate

Claims

1. A semiconductor substrate comprising: a template substrate including a first seed region and a growth inhibition region aligned in a first direction; and a first semiconductor portion located above the first seed region and the growth inhibition region, wherein the first semiconductor portion includes a first wing portion located above the growth inhibition region, the first wing portion having a first nitride semiconductor layer, an aluminum-based semiconductor layer containing aluminum and located on the first nitride semiconductor layer, and a second nitride semiconductor layer located on the aluminum-based semiconductor layer, wherein an upper surface of the second nitride semiconductor layer has a lower concentration of silicon than an upper surface of the first nitride semiconductor layer.

2. The semiconductor substrate according to claim 1, wherein the upper surface roughness of said aluminum-based semiconductor layer is smaller than the upper surface roughness of said first nitride semiconductor layer.

3. The semiconductor substrate according to claim 1 or 2, wherein the silicon concentration in the upper surface of said first nitride semiconductor layer is at least five times the silicon concentration in the upper surface of said second nitride semiconductor layer.

4. The semiconductor substrate according to claim 1, wherein the silicon concentration distribution in the first direction on the upper surface of the first nitride semiconductor layer is non-uniform.

5. A semiconductor substrate as described in any one of claims 1 to 4, wherein the first semiconductor portion includes a first base portion located above the first seed region, an upper surface of the first nitride semiconductor layer includes a connection region connected to the first base portion and an edge region spaced apart from the first base portion in the first direction, and a silicon concentration of the connection region is higher than a silicon concentration of the edge region.

6. A semiconductor substrate according to any one of claims 1 to 4, wherein the first semiconductor portion includes a first base portion located above the first seed region, an upper surface of the first nitride semiconductor layer includes a connection region connected to the first base portion and an edge region spaced apart from the first base portion in the first direction, and a top surface roughness of the connection region is greater than a top surface roughness of the edge region.

7. A semiconductor substrate according to any one of claims 1 to 6, wherein the first nitride semiconductor layer has a ratio of the length in the first direction to the thickness of 5.0 or more.

8. The semiconductor substrate according to any one of claims 1 to 7, wherein the aluminum-based semiconductor layer covers a side surface of the first nitride semiconductor layer.

9. The semiconductor substrate according to claim 1, further comprising a silicon-based mask that functions as said growth inhibition region.

10. The semiconductor substrate according to any one of claims 1 to 9, wherein the surface layer of the first nitride semiconductor layer has a plurality of recesses having a depth of 20 to 80 nm.

11. The semiconductor substrate according to any one of claims 1 to 10, wherein the first and second nitride semiconductor layers are thicker than the aluminum-based semiconductor layer.

12. The semiconductor substrate according to claim 5 or 6, wherein the threading dislocation density in the upper surface of said first wing portion is not more than 1 / 5 of the threading dislocation density in said first base portion.

13. The semiconductor substrate according to any one of claims 1 to 12, wherein the aluminum-based semiconductor layer contains 1.5 atomic % or more of aluminum.

14. The semiconductor substrate according to claim 10, wherein the aluminum-based semiconductor layer includes a lower layer at least a portion of which is located inside the depression of the recess of the first nitride semiconductor layer, and an upper layer which is flatter than the lower layer, and the lower layer has a lower aluminum concentration than the upper layer.

15. The semiconductor substrate according to any one of claims 1 to 14, wherein the aluminum-based semiconductor layer is a layer containing AlGaN or AlN.

16. The semiconductor substrate according to any one of claims 1 to 15, wherein the template substrate comprises a silicon wafer, a silicon carbide wafer or a sapphire wafer, and the first and second nitride semiconductor layers are layers containing GaN.

17. The semiconductor substrate according to any one of claims 1 to 16, further comprising a functional layer including an active layer above the first wing portion.

18. A semiconductor substrate as described in any one of claims 1 to 17, wherein the template substrate comprises a second seed region and a second semiconductor portion located above the second seed region and the growth inhibition region, the second semiconductor portion includes a second base portion located above the second seed region and a second wing portion located above the growth inhibition region, and the first wing portion and the second wing portion are adjacent to each other with a gap between them.

19. The semiconductor substrate of claim 1, wherein a gap is located between the growth inhibition region and the first wing portion.

20. A method for manufacturing a semiconductor substrate, comprising: preparing a template substrate including a first seed region and a growth inhibition region aligned in a first direction; growing an initial growth layer on the first seed region; growing a first nitride semiconductor layer having a rough top surface from a side surface of the initial growth layer above the growth inhibition region; and growing an aluminum-based semiconductor layer so as to fill in the rough top surface of the first nitride semiconductor layer.

21. The method for producing a semiconductor substrate according to claim 20, further comprising the step of forming a second nitride semiconductor layer on said aluminum-based semiconductor layer.

22. A method for manufacturing a semiconductor substrate as described in claim 20 or 21, wherein the first nitride semiconductor layer is grown so that the thickness of the portion located on the initial growth layer is 1 / 5 or less of the thickness of the portion in contact with a side surface of the initial growth layer.

23. The method for producing a semiconductor substrate according to claim 21, wherein the silicon concentration in the upper surface of the first nitride semiconductor layer is at least five times the silicon concentration in the upper surface of the second nitride semiconductor layer.

24. A semiconductor substrate manufacturing apparatus which performs each of the steps recited in claim 20.

25. A semiconductor device comprising: a first nitride semiconductor layer; an aluminum-based semiconductor layer containing aluminum and located on the first nitride semiconductor layer; a second nitride semiconductor layer located on the aluminum-based semiconductor layer; and a functional layer located on the second nitride semiconductor layer, wherein an upper surface of the second nitride semiconductor layer has a lower concentration of silicon than an upper surface of the first nitride semiconductor layer.

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