Circuit board and semiconductor package comprising same

Abstract

A circuit board, according to one embodiment, comprises: an insulating layer having a plurality of inorganic fillers embedded therein; a wiring layer disposed on the insulating layer; and a protection layer disposed on the wiring layer, wherein the wiring layer is provided with a plurality of protrusions projected toward the insulating layer, and the protrusions do not make contact with the plurality of inorganic fillers and overlap at least one of the plurality of inorganic fillers along the horizontal direction.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package board including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to accommodate multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the substrate. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are increasing the number of semiconductor elements and / or the size of each semiconductor element in line with the trend toward high integration, but the concept is expanding to semiconductor chiplets in which the functional parts of semiconductor elements are divided due to limitations of the reticle, etc.

[0005] Accordingly, intercommunication between semiconductor devices and / or semiconductor chiplets is becoming more important, and accordingly, there is a trend toward placing an interposer between the substrate of a semiconductor package and the semiconductor devices.

[0006] An interposer can function as a redistribution layer that gradually increases the width or depth of a circuit pattern from a semiconductor device toward a semiconductor package to facilitate communication between semiconductor devices and / or semiconductor chiplets, or to interconnect a semiconductor device and a semiconductor package substrate, thereby facilitating electrical signals between a semiconductor device and a semiconductor package substrate having a circuit pattern that is relatively large compared to the circuit pattern of the semiconductor device.

[0007] Meanwhile, as the pitch of semiconductor device terminals becomes smaller, the line width, thickness, and spacing of the wiring layer provided on the package substrate and / or interposer may also become smaller. When the line width, thickness, and spacing of the wiring layer become smaller, the adhesion between the wiring layer and the insulating layer may deteriorate. Therefore, the surface of the insulating layer can be provided with a surface roughness value above a certain level, thereby improving the adhesion between the insulating layer and the wiring layer.

[0008] At this time, in the conventional technology, desmear is performed on the surface of the insulating layer using a dry method using plasma or a wet method using chemicals, thereby giving the surface of the insulating layer a surface roughness value above a certain level.

[0009] However, according to the prior art, the surface of the insulating layer is not provided with a uniform surface roughness value overall, and thus, there is a problem of reduced adhesion between the insulating layer and the wiring layer. That is, the insulating layer includes an inorganic filler, and the surface of the insulating layer is provided with a surface roughness value with a large deviation due to the inorganic filler.

[0010] For example, when performing a desmear process, the resin of the insulating layer may be removed, but the inorganic filler including SiO2 or TiO2 is not removed. Therefore, the inorganic filler is exposed on the surface of the insulating layer after the desmear process. Furthermore, at least a portion of the inorganic filler exposed to the outside of the insulating layer is removed by peeling off from the insulating layer.

[0011] Accordingly, the surface of the insulating layer includes a first region formed of resin shaved off by the desmear process, a second region formed of exposed inorganic filler, and a third region where the inorganic filler has fallen off. At this time, different surface roughness values ​​may be provided to the first to third regions of the insulating layer, and thus, there may be a problem that the dispersion of the adhesion between the insulating layer and the wiring layer increases due to the unevenness of the surface roughness values. This problem causes a problem that the reliability of the adhesion between the insulating layer and the wiring layer is reduced. Furthermore, the wiring layer disposed on the second region of the insulating layer may come into contact with the inorganic filler of the insulating layer, and thereby the electrical characteristics of the wiring layer may be deteriorated. For example, the permittivity of the inorganic filler may be higher than the permittivity of the resin of the insulating layer, and there is a problem that the transmission loss of a signal transmitted through the wiring layer increases due to the high permittivity of the inorganic filler. In addition, the adhesion between the inorganic filler and the wiring layer may be weaker than the adhesion between the inorganic filler and the resin of the insulating layer, so there is a problem of reduced reliability of the adhesion between the wiring layer and the insulating layer.

[0012] Therefore, a new method is required to provide a uniform surface roughness value to the surface of the insulating layer.

[0013] The embodiment provides a circuit board having a uniform roughness value applied to the surface of an insulating layer and a semiconductor package including the same.

[0014] In addition, the embodiment provides a circuit board having improved adhesion between an insulating layer and a wiring layer and a semiconductor package including the same.

[0015] In addition, the embodiment provides a circuit board having a wiring layer having electrical characteristics disclosed therein and a semiconductor package including the same.

[0016] In addition, the embodiment provides a circuit board having a minimized height deviation of wiring layers provided on the same layer and a semiconductor package including the same.

[0017] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0018] A circuit board according to an embodiment comprises an insulating layer having a plurality of inorganic fillers embedded therein; a wiring layer disposed on the insulating layer; and a protective layer disposed on the wiring layer, wherein the wiring layer has a plurality of protrusions protruding toward the insulating layer, the protrusions not in contact with the plurality of inorganic fillers and overlapping at least one of the plurality of inorganic fillers in a horizontal direction.

[0019] Additionally, the protective layer has a plurality of protrusions protruding toward the insulating layer.

[0020] Additionally, the protrusion of the protective layer does not contact the plurality of inorganic fillers and overlaps at least one of the plurality of inorganic fillers in the horizontal direction.

[0021] Additionally, at least one of the protrusions of the wiring layer and the protrusions of the protective layer is in direct contact with the insulating layer.

[0022] Additionally, the protrusion of the protective layer overlaps the protrusion of the wiring layer in a horizontal direction.

[0023] Additionally, the thickness of at least one of the plurality of protrusions of the wiring layer is different from the thickness of at least one other protrusion.

[0024] In addition, a concave portion corresponding to a protrusion of the wiring layer is provided on the upper surface of the insulating layer, and a plurality of protrusions are provided on the lower surface of the insulating layer.

[0025] Additionally, the circuit board further includes a connecting member embedded within the insulating layer, the connecting member overlapping at least one of the plurality of protrusions along a vertical direction.

[0026] Additionally, the curvature of the protrusion is different from the curvature of the inorganic filler.

[0027] Additionally, the circuit board further includes a via electrode penetrating at least a portion of the insulating layer along a vertical direction and connected to the wiring layer, and at least one of the plurality of inorganic fillers is in contact with a side surface of the via electrode.

[0028] Meanwhile, a circuit board according to an embodiment includes a first insulating layer having a plurality of inorganic fillers embedded therein; and a second insulating layer disposed on the first insulating layer, wherein a lower surface of the second insulating layer is provided with a plurality of protrusions protruding toward the first insulating layer, and the protrusions do not contact the plurality of inorganic fillers and overlap at least one of the plurality of inorganic fillers in a horizontal direction.

[0029] In addition, the wiring layer is further included between the first insulating layer and the second insulating layer, and a plurality of protrusions protruding toward the first insulating layer are provided on the lower surface of the wiring layer, and the protrusions of the wiring layer do not contact the plurality of inorganic fillers and overlap at least one of the plurality of inorganic fillers in a horizontal direction.

[0030] Additionally, the protrusions of the second insulating layer and the protrusions of the wiring layer are in direct contact with the upper surface of the first insulating layer.

[0031] Additionally, the protrusion of the second insulating layer overlaps the protrusion of the wiring layer in a horizontal direction.

[0032] Additionally, the circuit board further includes a connecting member embedded within the first insulating layer, the connecting member overlapping at least one of the plurality of protrusions along a vertical direction.

[0033] Meanwhile, a semiconductor package according to an embodiment includes an insulating layer having a plurality of inorganic fillers embedded therein; a wiring layer disposed on the insulating layer; a protective layer disposed on the wiring layer; and a semiconductor element disposed on the protective layer, wherein the wiring layer has a plurality of protrusions protruding toward the insulating layer, the protrusions being in direct contact with the insulating layer, not in contact with the plurality of inorganic fillers, and overlapping at least one of the plurality of inorganic fillers along a horizontal direction.

[0034] Additionally, the protective layer has a plurality of protrusions protruding toward the insulating layer, and the protrusions of the protective layer are in direct contact with the insulating layer, do not contact the plurality of inorganic fillers, and overlap with at least one of the plurality of inorganic fillers along a horizontal direction.

[0035] Additionally, the protrusion of the protective layer overlaps the protrusion of the wiring layer in a horizontal direction.

[0036] In addition, a concave portion corresponding to a protrusion of the wiring layer is provided on the upper surface of the insulating layer, and a plurality of protrusions are provided on the lower surface of the insulating layer.

[0037] Additionally, the semiconductor package further includes a connecting member embedded within the insulating layer, the connecting member overlapping at least one of the plurality of protrusions along a vertical direction.

[0038] The embodiments can improve the physical reliability and / or electrical reliability of a circuit board and a semiconductor package including the same.

[0039] Specifically, the embodiment includes an insulating layer. The insulating layer includes a resin and an inorganic filler embedded within the resin. At this time, a plurality of recesses are provided on the upper surface of the insulating layer. In addition, each of the plurality of recesses provided on the upper surface of the insulating layer may have a curvature different from the curvature of the inorganic filler. For example, the inorganic filler embedded within the insulating layer is not exposed through the recesses provided on the upper surface of the insulating layer.

[0040] Accordingly, the embodiment can provide a plurality of concave portions on the upper surface of the insulating layer while preventing the inorganic filler embedded within the insulating layer from being exposed to the outside of the insulating layer. Accordingly, the embodiment can resolve physical reliability issues and / or electrical reliability issues that arise when the inorganic filler of the insulating layer is exposed to the outside during a process of imparting a certain level of surface roughness to the upper surface of the insulating layer.

[0041] Specifically, when the inorganic filler is exposed to the outside of the insulating layer, there is a problem of reduced adhesion between the insulating layer and the wiring layer. That is, the adhesion between the inorganic filler of the insulating layer and the wiring layer is lower than the adhesion between the resin of the insulating layer and the wiring layer. Accordingly, the adhesion between the insulating layer and the wiring layer may be reduced in the area where the inorganic filler is exposed, which may result in the wiring layer being peeled off from the insulating layer.

[0042] In contrast, the embodiment can transfer a concave portion to the upper surface of the insulating layer corresponding to the protrusions provided in the metal layer rather than a desmear process, thereby providing a concave portion having a uniform depth on the upper surface of the insulating layer. Accordingly, the embodiment can prevent the inorganic filler from being exposed to the outside of the insulating layer. Through this, the embodiment can ensure that the wiring layer disposed on the same layer has a uniform thickness, and further improve the adhesion between the insulating layer and the wiring layer.

[0043] In addition, the insulating layer of the prior art using the desmear process has a space where the exposed inorganic filler is removed. At this time, the space where the inorganic filler is removed may have a greater vertical depth than other parts. Therefore, when a chemical copper plating process is performed to form a wiring layer in the space where the inorganic filler is removed, voids may be formed because the chemical copper plating is not performed in at least a portion of the space where the inorganic filler is removed. In addition, stress acting on the insulating layer may be concentrated in the space where the reinforcing member is removed, which may deteriorate the physical reliability and / or electrical reliability of the semiconductor package.

[0044] In contrast, the embodiment can eliminate voids by forming a uniform concave portion on the surface of the insulating layer, thereby further improving the physical reliability and electrical reliability of the semiconductor package. Furthermore, when stress is applied to the insulating layer, the embodiment can prevent the stress from being concentrated in a specific region of the insulating layer by forming a uniform concave portion on the upper surface of the insulating layer, and further, can evenly distribute the stress overall, thereby improving the physical reliability and electrical reliability of the semiconductor package.

[0045] In addition, the embodiment can prevent the inorganic filler embedded in the insulating layer from falling off in the process of providing a concave portion on the surface of the insulating layer, and can prevent the change in the dielectric constant of the insulating layer that may be caused by the falling off of the inorganic filler, thereby further improving the electrical characteristics of the circuit board and semiconductor package.

[0046] In addition, the embodiment includes a wiring layer disposed on an insulating layer, and the wiring layer may have a protrusion protruding toward the insulating layer. The protrusion may correspond to a concave portion provided in the insulating layer. At this time, the protrusion of the wiring layer may horizontally overlap with at least one of a plurality of inorganic fillers embedded in the insulating layer. Through this, the embodiment can improve the rigidity of the circuit board, and by using the inorganic filler overlapped in the horizontal direction as described above, the degree of thermal deformation occurring at the interface between the insulating layer and the wiring layer according to the heat cycle can be minimized, thereby further improving the mechanical reliability.

[0047] In addition, the embodiment includes a protective layer disposed on an insulating layer, and the protective layer may have a protrusion protruding toward the insulating layer. The protrusion of the protective layer may correspond to a concave portion provided in the insulating layer. At this time, the protrusion of the protective layer may horizontally overlap with at least one of a plurality of inorganic fillers embedded in the insulating layer. Through this, the embodiment can improve the rigidity of the circuit board, and by using the inorganic filler overlapping in the horizontal direction described above, the degree of thermal deformation occurring at the interface between the insulating layer and the protective layer according to the heat cycle can be minimized, thereby further improving the mechanical reliability. Furthermore, the embodiment can prevent the stress according to the heat cycle from being transmitted to the bump layer penetrating the protective layer, thereby preventing the occurrence of cracks in the bump layer due to the above-described stress. Therefore, the embodiment can stably mount a semiconductor device on the bump layer, and thereby enable the semiconductor package to operate stably.

[0048] Figure 1 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0049] FIG. 2 is a drawing showing one embodiment of an insulating layer of the circuit board of FIG. 1.

[0050] Figure 3 is an optical microscope photograph for comparing the surface roughness values ​​of the insulating layers of the examples and comparative examples.

[0051] Fig. 4 is a drawing showing another embodiment of the insulating layer of the circuit board of Fig. 1.

[0052] Fig. 5 is an enlarged cross-sectional view of the first region (A) of the semiconductor package of Fig. 1.

[0053] Fig. 6 is an enlarged cross-sectional view of the second region (B) of the semiconductor package of Fig. 1.

[0054] Fig. 7 is a drawing showing a semiconductor package according to the second embodiment.

[0055] Figure 8 is a drawing showing a semiconductor package according to the third embodiment.

[0056] Figures 9 to 15 are drawings showing the manufacturing method of the semiconductor package illustrated in Figure 1 in process order.

[0057] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0058] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0059] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0060] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0061] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0062] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0063] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0064] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0065]

[0066] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0067]

[0068] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0069] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion for electrically connecting the semiconductor element and the circuit board, a resin portion for filling the space between the semiconductor element and the circuit board, and a molding portion for entirely enclosing the semiconductor element.

[0070] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0071] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0072]

[0073] FIG. 1 is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 2 is a view showing an embodiment of an insulating layer of a circuit board of FIG. 1, FIG. 3 is an optical microscope photograph for comparing surface roughness values ​​of insulating layers of an embodiment and a comparative example, FIG. 4 is a view showing another embodiment of an insulating layer of the circuit board of FIG. 1, FIG. 5 is an enlarged cross-sectional view of a first region (A) of the semiconductor package of FIG. 1, and FIG. 6 is an enlarged cross-sectional view of a second region (B) of the semiconductor package of FIG. 1.

[0074] Referring to FIG. 1, a semiconductor package (1000) may include a circuit board (100), a connecting member (200) embedded in the circuit board (100), a semiconductor element (320, 330) disposed on the circuit board (100), and a connecting portion (310) disposed between the circuit board (100) and the semiconductor element (320, 330).

[0075] Hereinafter, for easy explanation of the semiconductor package of the embodiment, terms referring to each component constituting the semiconductor package are described, and a detailed description of each component referred to will be provided later.

[0076] The circuit board (100) may include an insulating layer (110), a wiring layer (120), a via electrode (130), a bump layer (140), and a protective layer (150, 160).

[0077] The insulating layer (110) may have a structure in which a plurality of layers are laminated along the vertical direction. The insulating layer (110) may include a core layer (111), an upper build-up insulating layer (112) disposed on one surface of the core layer (111), and a lower build-up insulating layer (113) disposed on the other surface of the core layer (111). Here, the meaning of being disposed on one surface and the other surface should not be understood only as a configuration in direct contact with the one surface and the other surface, but should also be understood as having another configuration between the one surface and the upper build-up insulating layer (112), and between the other surface and the lower build-up insulating layer (113).

[0078] The core layer (111) is composed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing material such as glass fiber, and has the function of improving the rigidity of the circuit board (100).

[0079] As the number of terminals of semiconductor devices (320, 330) arranged on a recent circuit board (100) increases, wiring becomes more complex, and accordingly, the thickness of the upper build-up insulating layer (112) and the lower build-up insulating layer (113) is increasing. Accordingly, the core layer (111) may have a thickness of 120 μm to 1200 μm in order to improve the overall rigidity of the circuit board (100) and prevent excessive signal loss. A via hole penetrating one surface and the other surface may be formed in the core layer (111). The via hole of the core layer (111) may be formed using a mechanical drilling process or a CO2 laser, etc. When a via hole of the core layer (111) is formed using a mechanical drill, the slope of the inner wall of the via hole may be perpendicular to one surface and / or the other surface of the core layer (111), and when a via hole of the core layer (111) is formed using a CO2 laser, the inner wall of the via hole may have a plurality of concave portions and / or convex portions that are alternately stacked along the vertical direction. Here, the concave portion may mean a concave region that is concave in a direction away from the horizontal center of the via hole provided in the core layer (111), and the convex portion may mean a region that protrudes and / or is convex toward the horizontal center of the via hole provided in the core layer (111). In addition, the concave portions and the convex portions may be alternately provided on the inner wall forming the via hole of the core layer (111) along the vertical direction. Here, being alternately provided may mean that the convex portion is provided between a plurality of concave portions, and that the concave portion is provided between a plurality of convex portions. In the case of via holes formed using a mechanical drilling process, the path for transmitting electrical signals is shortened, which may be advantageous for electrical characteristics, but the process cost may increase. In addition, in the case of forming concave and convex portions on the inner wall of the via hole using a CO2 laser, the thickness of the core via electrode (131) provided on the inner wall of the via hole can be thickened in a subsequent process, which has the advantage of lowering the impedance and lowering the process cost.Accordingly, the processing method of the via hole provided in the core layer (111) can be freely and selectively used depending on the application field of the semiconductor package.

[0080] A core via electrode (131) may be arranged within the via hole of the core layer (111). The core via electrode (131) functions to electrically connect the wiring layer (120) and / or the via electrode (130) provided in the upper build-up insulating layer (112) with the wiring layer (120) and / or the via electrode (130) provided in the lower build-up insulating layer (113). Therefore, it is preferable that the core via electrode (131) densely fill the via hole for the function of resistance or heat dissipation. However, when the thickness of the core layer (111) becomes thick as described above, it may become difficult for the core via electrode (131) to densely fill the via hole. For example, when attempting to fill the via hole provided in the thick core layer (111) as described above according to the plating process, a void may occur within the core via electrode (131). Voids expand due to heat generated during the operation of a semiconductor package, which becomes a factor that reduces the mechanical reliability of a circuit board. Therefore, a core via electrode (131) having a predetermined thickness is arranged on the inner wall of the via hole of the core layer (111). The thickness of the core via electrode (131) refers to the thickness in the horizontal direction perpendicular to the stacking of the core layer (111), the upper build-up insulating layer (112), and the lower build-up insulating layer (113), not the thickness in the vertical direction. The thickness of the core via electrode (131) may be arranged to have a thickness of 5 μm to 20 μm to prevent a voltage drop that occurs as the thickness of the core layer (111) increases and to prevent the occurrence of voids. It is difficult to densely fill the inner side of the core via electrode (131) with metal through a process such as plating, resulting in the formation of an empty space. The empty space may cause a problem in that the upper build-up insulation layer (112) and / or the lower build-up insulation layer (113) are not evenly placed on the upper and / or lower surfaces of the core layer (111).

[0081] Accordingly, the insulating member (110A) can be placed on the inner side of the core via electrode (131), thereby ensuring the flatness of the core layer (111). For example, the insulating member (110A) can be placed in the via hole of the core layer (111), and the core via electrode (131) can surround the side of the insulating member (110A) and be placed between the inner wall of the via hole and the outer surface of the insulating member (110A).

[0082] The upper surface of the insulating member (110A) may be on the same plane as the upper surface of the core layer (111), or may be arranged closer to the upper build-up insulating layer (112) in the vertical direction than the upper surface of the core layer (111). The lower surface of the insulating member (110A) may be on the same plane as the lower surface of the core layer (111), or may be arranged closer to the lower build-up insulating layer (113) in the vertical direction than the lower surface of the core layer (111). This can be freely designed to solve the flatness when laminating the upper build-up insulating layer (112) and the lower build-up insulating layer (113), or to secure the flatness of the first wiring layer (121) and / or the fourth wiring layer (124) to be described later.

[0083] One surface of the core layer (111) includes an upper build-up insulating layer (112), a plurality of wiring layers (121, 122, 123), a plurality of via electrodes (132, 133), and a first protective layer (150).

[0084] The upper build-up insulating layer (112) may include a first insulating layer disposed on an upper surface of the core layer (111) and a second insulating layer disposed on an upper surface of the first insulating layer. In addition, a plurality of wiring layers (121, 122, 123) disposed on one surface of the core layer (111) may include a first wiring layer (121) that is closest to the core layer (111) in a vertical direction, a second wiring layer (122) that is positioned farther from the core layer (111) in a vertical direction than the first wiring layer (121), and a third wiring layer (123) that is positioned farther from the core layer (111) in a vertical direction than the second wiring layer (122). The first to third wiring layers (121, 122, 123) may function to electrically connect to semiconductor elements (320, 330) disposed on a circuit board (100). Each of the first to third wiring layers (121, 122, 123) can be freely designed considering impedance.

[0085] Additionally, via electrodes (132, 133) may be arranged to connect the first to third wiring layers (121, 122, 123), respectively. For example, the first via electrode (132) is arranged between the first wiring layer (121) and the second wiring layer (122), and the second via electrode (133) is arranged between the second wiring layer (122) and the third wiring layer (123), thereby electrically connecting the first to third wiring layers (121, 122, 123).

[0086] The first and second via electrodes (132, 133) can be formed simultaneously in the process of arranging the first to third wiring layers (121, 122, 123). For example, in the process of arranging the second wiring layer (122) on the first wiring layer (121), a through hole can be formed in the first insulating layer of the upper build-up insulating layer (112) to expose a portion of the first wiring layer (121), and through this, the second wiring layer (122) can be formed together with the first via electrode (132) filling the through hole of the first insulating layer. Accordingly, the first via electrode (132) can be distinguished as a protruding electrode of the second wiring layer (122). Likewise, each of the first and second via electrodes (132, 133) may be separated by a protruding electrode of the second and third wiring layers (122, 123) and may be connected to another wiring layer disposed below each wiring layer.

[0087] The first wiring layer (121) may be in contact with one surface of the core layer (111). In this case, a part of the first wiring layer (121) may be arranged to cover the above-described insulating member (110A). The part of the first wiring layer (121) that covers the insulating member (110A) may be thinner than the remaining parts that do not vertically overlap the insulating member (110A). Here, the thickness of the first wiring layer (121) refers to the thickness in the vertical direction. When designing the first wiring layer (121), the insulating member (110A) may be covered or not covered depending on the degree of freedom of wiring, and thus the freedom of wiring connection may be increased. When the first wiring layer (121) does not cover the insulating member (110A), the insulating member (110A) may be in direct contact with the first insulating layer (104). When the first wiring layer (121) and the first insulating layer of the upper build-up insulating layer (112) are in contact with each other, the bonding strength may be better and heat dissipation may be advantageous compared to when the insulating member (110A) and the first insulating layer (104) are in direct contact. However, in order to reduce the process cost, the first wiring layer (121) may be arranged so as not to cover the insulating member (110A). Furthermore, depending on the design of the first via electrode (132), the first wiring layer (121) may or may not cover the insulating member (110A). For example, when the first via electrode (132) is arranged to overlap the first wiring layer (121) in the vertical direction, the first wiring layer (121) may be provided to cover the insulating member (110A) in order to secure electrical connectivity and / or mechanical coupling between the first wiring layer (121) and the first via electrode (132). Additionally, when the first via electrode (132) that vertically overlaps the first wiring layer (121) is not arranged, the first wiring layer (121) may be provided without covering the insulating member (110A).

[0088] The upper build-up insulating layer (112) may include a first insulating layer that is closest to the core layer (111) in a direction perpendicular to the core layer (111), and a second insulating layer that is positioned further from the core layer (111) in a direction perpendicular to the first insulating layer. In this case, the upper build-up insulating layer (112) is illustrated as including the first and second insulating layers, but is not limited thereto. For example, the upper build-up insulating layer (112) may include three or more insulating layers, thereby enabling more smooth electrical connection between the semiconductor element and the semiconductor package substrate.

[0089] The first and second insulating layers of the upper build-up insulating layer (112) are arranged to vertically insulate between the first to third wiring layers (121, 122, 123) described above. For example, a thermosetting insulating material containing an inorganic filler in a resin may be used for the first and second insulating layers of the upper build-up insulating layer (112), and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.

[0090] The first protective layer (150) can protect the third wiring layer (123) from external moisture or contaminants. In addition, when semiconductor elements are arranged on the circuit board (100) using a material such as solder, the first protective layer (150) functions to prevent short circuits between solders due to its low wettability with the solder. The first protective layer (150) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0091] The other surface of the core layer (111) includes a lower build-up insulating layer (113), a plurality of wiring layers (124, 125, 126), a plurality of via electrodes (134, 135), and a second protective layer (160).

[0092] A plurality of wiring layers (124, 125, 126) arranged on the other surface of the core layer (111) may include a fourth wiring layer (124) that is most adjacent to the core layer (111) in a vertical direction, a fifth wiring layer (125) arranged under the fourth wiring layer (124), and a sixth wiring layer (126) arranged under the fifth wiring layer (125). The fourth to sixth wiring layers (124, 125, 126) may electrically connect a main board (not shown) of an electronic device and semiconductor elements (320, 330) arranged on a circuit board (100). Each of the fourth to sixth wiring layers (124, 125, 126) may be freely designed in consideration of impedance.

[0093] Additionally, via electrodes (134, 135) may be arranged to connect the fourth to sixth wiring layers (124, 125, 126), respectively. The third via electrode (134) is arranged between the fourth wiring layer (124) and the fifth wiring layer (125), and the fourth via electrode (135) is arranged between the fifth wiring layer (125) and the sixth wiring layer (126), thereby electrically connecting the fourth to sixth wiring layers (124, 125, 126).

[0094] As described above with respect to the first and second via electrodes (132, 133) arranged on one surface of the core layer (111), the arrangement of the third and fourth via electrodes (134, 135) can also be performed simultaneously in the process of arranging the fourth to sixth wiring layers (124, 125, 126). Therefore, as described above, the third via electrode (132) can be distinguished as a protruding electrode of the fifth wiring layer (125). However, since the fourth to sixth wiring layers (124, 125, 126) are laminated in a different direction from the first to third wiring layers (121, 122, 123), the inclination direction of the first and second via electrodes (132, 133) can have a direction opposite to the inclination direction of the third and fourth via electrodes (134, 135). For example, the first and second via electrodes (132, 133) may have slopes that become narrower toward the core layer (111), and the third and fourth via electrodes (134, 135) may also have slopes that become narrower toward the core layer (111). For example, the slopes of the first and second via electrodes (132, 133) may be symmetrical with respect to the slopes of the third and fourth via electrodes (134, 135) with respect to the core layer (111).

[0095] The fourth wiring layer (124) may be in contact with the other surface of the core layer (111). In this case, a part of the fourth wiring layer (124) may be arranged to cover the above-described insulating member (110A). The part of the fourth wiring layer (124) that covers the insulating member (110A) may be thinner than the remaining parts that do not vertically overlap the insulating member (110A). Here, the thickness of the fourth wiring layer (124) refers to the thickness in the vertical direction. When designing the fourth wiring layer (124), the insulating member (110A) may or may not be covered depending on the degree of freedom of the wiring, and thus the freedom of wiring connection may be increased. When the fourth wiring layer (124) does not cover the insulating member (110A), the insulating member (110A) may be in direct contact with the third insulating layer of the lower build-up insulating layer (113). Compared to the case where the insulating member (110A) and the third insulating layer of the lower build-up insulating layer (113) are in direct contact, when the fourth wiring layer (124) and the third insulating layer are in contact, the bonding strength may be better and heat dissipation may be advantageous. However, in order to reduce the process cost, the fourth wiring layer (124) may be arranged so as not to cover the insulating member (110A). Furthermore, depending on the design of the third via electrode (134), the fourth wiring layer (124) may or may not cover the insulating member (110A). For example, when the third via electrode (134) is arranged to vertically overlap the fourth wiring layer (124), the fourth wiring layer (124) may be provided to cover the insulating member (110A) in order to secure electrical connectivity and / or mechanical coupling between the fourth wiring layer (124) and the third via electrode (134). Additionally, when the third via electrode (134) that vertically overlaps the fourth wiring layer (124) is not arranged, the fourth wiring layer (124) may be provided without covering the insulating member (110A).

[0096] The lower build-up insulating layer (113) is provided with a plurality of layers, and may include, for example, a third insulating layer that is closest to the core layer (111) in the vertical direction, and a fourth insulating layer disposed below the third insulating layer. The third and fourth insulating layers of the lower build-up insulating layer (113) are disposed to vertically insulate the fourth to sixth wiring layers (124, 125, 126) described above. In addition, for example, a thermosetting insulating material containing an inorganic filler in a resin may be used for the third and fourth insulating layers of the lower build-up insulating layer (113), and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.

[0097] The second protective layer (160) can protect the sixth wiring layer (126) from external moisture or contaminants. In addition, when semiconductor elements are arranged on the circuit board (100) using a material such as solder, the second protective layer (160) functions to prevent short circuits between solders due to its low wettability with the solder. The second protective layer (160) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0098] The bump layer (140) penetrates the first protective layer (150) and is electrically connected to the wiring layer (120). For example, the first protective layer (150) may have a through hole that overlaps the third wiring layer (123) in a vertical direction, and the bump layer (140) may be disposed within the through hole of the first protective layer (150) and be electrically connected to the third wiring layer (123).

[0099] The bump layer (140) may refer to an electrode on which a bonding member such as solder is placed for bonding with a semiconductor element, and may include a through-hole (141) placed in a through-hole of a first protective layer (150) and a bonding member (142) placed on the through-hole (141) and protruding onto the first protective layer (150). Recently, as the functions provided by semiconductor elements increase and the performance of semiconductor elements improves, the number of I / O terminals provided to semiconductor elements is also increasing. Accordingly, as the width and / or pitch of the I / O terminals provided to semiconductor elements become smaller, an electrical short circuit may occur in which a plurality of bonding members come into contact with each other in a process of connecting the I / O terminals of the semiconductor element through a bonding member such as solder. Accordingly, as the density of terminals of semiconductor devices increases, in order to reduce the amount of bonding materials such as solder, a micro-bonding process such as applying a connection portion (310) to the upper surface of the bonding portion (142) of the bump layer (140) protruding above the first protective layer (150) and performing thermal compression bonding (hereinafter referred to as 'TC bonding') may be performed. In addition, when the micro-bonding process is performed, in order to improve the alignment between the terminal of the semiconductor device and the bump layer (140), the bump layer (140) may be provided with a bonding portion (142) protruding above the first protective layer (150) as described above. In addition, when bonding the circuit board (100) and the semiconductor device using the thermal compression bonding method, a crack may occur in the penetration portion (141) of the bump layer (140) due to the load generated thereby. Accordingly, cracks can be prevented by placing a material having a higher elastic modulus than the elastic modulus of the third wiring layer (123) in the penetration portion (141) of the bump layer (140) adjacent to the third wiring layer (123). This material may be nickel (Ni), but a copper layer having a low grain density can be placed by electroless plating.At this time, the penetration portion (141) of the bump layer (140) can be arranged in various ways. For example, a process may be performed in which the first protective layer (150) is exposed and developed to form an opening in the first protective layer (150), and then the penetration portion (141) and the bonding portion (142) of the bump layer (140) are arranged in the opening. In addition, a process may be performed in which a penetration hole of the first protective layer (150) is formed using a laser, and then the penetration portion (141) and the bonding portion (142) of the bump layer (140) are arranged in the opening. In addition, by using DFR (Dry Film resist), DFR is first placed in the area where the penetration portion (141) is to be placed, and then the first protective layer (150) is placed so that the DFR is covered, and then a part of the first protective layer (150) is etched with a chemical solution to expose the DFR, and then the DFR is peeled off to form an opening in the first protective layer (150), and then the penetration portion (141) and bonding portion (142) of the bump layer (140) can be placed. Therefore, the penetration portion (141) of the bump layer (140) can have various shapes depending on the process method. For example, when the opening of the first protective layer (150) is formed through an exposure process, the side surface of the through-hole (141) of the bump layer (140) may have a structure in which the width gradually narrows toward the third wiring layer (123). When the opening of the first protective layer (150) is formed through a laser process, the side surface of the through-hole (141) may have a vertical side surface and a curved side surface adjacent to the third wiring layer (123). When the opening of the first protective layer (150) is formed using DFR, the side surface of the through-hole (141) may only have a vertical side surface. As described above, when the semiconductor element is bonded to the circuit board (100) through thermocompression bonding, a load may be applied to the through-hole (141). In this case, in the case of the through-hole (141) using DFR, the stress may be applied uniformly, so that the manufacturing yield may be increased.

[0100] The circuit board (100) may further include at least one connecting member (200). Recently, as the number of signals that semiconductor devices must process increases, the size of semiconductor devices is trending toward larger areas. However, this larger area of ​​semiconductor devices is causing problems in lowering the yield of semiconductor devices. Therefore, there is a trend to divide the pattern size or functional part of semiconductor devices, place chiplets on the circuit board (100), and embed connecting members (200) that have the function of electrically connecting them within the circuit board (100). However, the connecting members (200) are not limited thereto, and may also connect semiconductor devices with other functions, such as memory. In addition, the connecting members (200) may be disposed on the core layer (111) of the circuit board. For example, the core layer (111) may have a cavity, and the connecting members (200) may be disposed within the cavity of the core layer (111). At this time, the first insulating layer of the upper build-up insulating layer (112) and the third insulating layer of the lower build-up insulating layer (113) may surround the side surface of the connecting member (200) and fill the cavity of the core layer (111). However, the embodiment is not limited thereto, and the connecting member (200) may be embedded in the upper build-up insulating layer (112) rather than the core layer (111). For example, when the connecting member (200) is embedded in the upper build-up insulating layer (112), the signal transmission distance with the semiconductor element can be reduced, which is advantageous in preventing signal loss. That is, the connecting member (200) electrically connects between a plurality of semiconductor elements arranged on the circuit board (100), and thus, reducing the signal transmission distance while being adjacent to the plurality of semiconductor elements can be advantageous in reducing signal transmission loss. At this time, when the connecting member (200) is placed on the upper build-up insulating layer (112), at least one of the first and second insulating layers of the upper build-up insulating layer (112) may have a cavity.In the past, a cavity was provided in only one specific insulating layer and the connecting member (200) was embedded. However, this may cause a problem in that the flatness of the uppermost insulating layer deteriorates. In addition, if the thickness of the connecting member (200) is thicker than the thickness of a specific insulating layer of the upper build-up insulating layer (112), the problem of deteriorating flatness may become more serious. Therefore, it is necessary to improve the flatness by reducing the difference between the thickness of the connecting member (200) and the depth of the cavity. Accordingly, cavities may be provided in at least two insulating layers, and the connecting member (200) may be embedded in cavities provided in at least two insulating layers.

[0101] The connecting member (200) may be formed of a material similar to a semiconductor element, such as silicon, or may be formed of an organic material such as a photosensitive resin or a thermosetting resin. Chiplet units separated according to functionality and / or pitch, or a plurality of semiconductor elements having different functions, such as a CPU and GPU, or a GPU and HBM, may be mounted on a circuit board, and the connecting member (200) may be embedded in the circuit board and may function to horizontally electrically connect the plurality of semiconductor elements.

[0102] Semiconductor elements (320, 330) may be arranged on the circuit board (100). The semiconductor elements (320, 330) may include a first semiconductor element (320) and a second semiconductor element (330), but are not limited thereto. For example, three or more semiconductor elements may be arranged on the circuit board (100), or one semiconductor element may be arranged.

[0103] The semiconductor package includes a connection portion (310) disposed between a semiconductor element (320, 330) and a circuit board (100). The connection portion (310) electrically connects a terminal (325, 335) of the semiconductor element (320, 330) and a bump layer (140) of the circuit board (100). The connection portion (310) uses at least one bonding method among wire bonding, solder bonding, and direct metal-to-metal bonding, and electrically connects the bump layer (140) of the circuit board (100) and the terminal (325, 335) of the semiconductor element (320, 330).

[0104] The wire bonding method refers to electrically connecting the bump layer (140) of the circuit board (100) and the terminals (325, 335) of the semiconductor elements (320, 330) using a conductive wire such as gold (Au). The solder bonding method electrically connects the bump layer (140) of the circuit board (100) and the terminals (325, 335) of the semiconductor elements (320, 330) using a material including at least one of Sn, Ag, and Cu. The direct metal bonding method refers to applying heat and pressure between the bump layer (140) of the circuit board (100) and the terminals (325, 335) of the semiconductor elements (320, 330) to recrystallize them without using solder, wires, conductive adhesives, etc., thereby directly bonding the electrode portion of the board (100) and the terminals (325, 335) of the semiconductor elements (320, 330). In this case, the connection portion (310) may refer to a metal layer provided between the bump layer (140) of the circuit board (100) and the terminal (325, 335) of the semiconductor element (320, 330) by recrystallization.

[0105] The structure of the circuit board (100) described above is only one embodiment for explaining the present invention, and the technical idea of ​​the present invention is not limited to the laminated structure of the present embodiment.

[0106] The circuit board (100) requires adhesion between the insulating layer (110) and the wiring layer (120) to enable stable electrical connection with the semiconductor elements (320, 330) and to ensure stable transmission of electrical signals between the main board of the electronic device and the semiconductor elements (320, 330). If the adhesion between the insulating layer (110) and the wiring layer (120) is reduced, the wiring layer (120) may be peeled off from the insulating layer (110), which may result in deterioration of the mechanical reliability and / or electrical reliability of the circuit board (100) and the semiconductor package (1000).

[0107] In a conventional circuit board, in order to secure adhesion between the insulating layer (110) and the wiring layer (120), at least one surface of the insulating layer (110) is subjected to a desmear treatment, thereby providing a certain level of roughness to the surface of the insulating layer (110). However, when the surface of the insulating layer (110) is subjected to a desmear treatment, uniform roughness may not be provided to the surface of the insulating layer (110) due to the inorganic filler provided in the insulating layer (110).

[0108] In the circuit board of the embodiment, a metal layer (not shown) to which uniform roughness is applied is laminated on an insulating layer (110), and thereby the roughness applied to the metal layer can be transferred to the surface of the insulating layer (110). Through this, the surface of the insulating layer (110) can be provided with a uniform surface roughness corresponding to the roughness applied to the surface of the metal layer, and thereby the adhesion between the insulating layer (110) and the wiring layer (120) can be improved.

[0109] Referring to FIG. 2, a concave portion (110C) may be provided on at least one surface of the insulating layer (110). The concave portion (110C) may be provided on one surface of the insulating layer (110) and may be provided concavely in a vertical direction from one surface of the insulating layer (110) toward the other surface of the insulating layer (110). The concave portions (110C) may be provided in multiple numbers on at least one surface of the insulating layer (110) and may be spaced apart from and / or connected in a horizontal direction. Here, the insulating layer (110) having the concave portion (110C) may refer to the upper build-up insulating layer (112) and / or the lower build-up insulating layer (113) described above.

[0110] The concave portion (110C) may be provided on one side and the other side of the insulating layer (110), but is not limited thereto. The concave portion (110C) may be provided on one side of the insulating layer (110) based on the lamination direction of the insulating layer (110).

[0111] For example, the upper build-up insulation layer (112) may be laminated along a vertical direction from the other surface of the core layer (111) toward one surface of the core layer (111). Therefore, the concave portion (110C) in the upper build-up insulation layer (112) may be provided on the upper surface of the upper build-up insulation layer (112). For example, the lower build-up insulation layer (113) may be laminated along a vertical direction from one surface of the core layer (111) toward the other surface of the core layer (111). Therefore, the concave portion (110C) in the lower build-up insulation layer (113) may be provided on the lower surface of the lower build-up insulation layer (113).

[0112] In addition, the insulating layer (110) may have a structure in which a plurality of layers are laminated along the vertical direction, and depending on the laminated structure, at least one surface of the insulating layer (110) may be provided with a protrusion (to be described later) corresponding to the concave portion (110C). For example, the upper build-up insulating layer (112) may have a first insulating layer and a second insulating layer. At this time, a concave portion (110C) may be provided on the upper surface of the first insulating layer, and a protrusion (120P, see FIG. 5) corresponding to the concave portion (110C) provided on the upper surface of the first insulating layer (110) may be provided on the lower surface of the second insulating layer. That is, the second insulating layer of the upper build-up insulating layer (112) can be laminated in a state in which a concave portion (110C) is provided in the first insulating layer of the upper build-up insulating layer (112), and through this, the second insulating layer can fill the concave portion (110C) provided in the first insulating layer and can have a protrusion (120P) corresponding to the concave portion (110C).

[0113] Each of the plurality of concave portions (110C) provided in the insulating layer (110) may have a uniform curvature. Here, having a uniform curvature may mean that the difference in the width in the horizontal direction and / or the depth in the vertical direction of each concave portion (110C) is 1 μm or less, or 0.8 μm or less, or 0.5 μm or less.

[0114] In the embodiment, since the plurality of concave portions (110C) have a uniform curvature, it is possible to form a wiring layer (120) having a uniform thickness on the insulating layer (110). Accordingly, the height deviation between the wiring layers (120) can be minimized, and the semiconductor elements (320, 330) can be stably installed on the wiring layer (120), thereby enabling the semiconductor package to operate stably. Furthermore, in the embodiment, since the insulating layer (110) has concave portions (110C) having a uniform curvature, the adhesion between the insulating layer (110) and the wiring layer (120) can be improved. For example, when the plurality of concave portions (110C) do not have a uniform curvature, a problem may occur in which plating of the wiring layer (120) is not smoothly performed in an area having a relatively large curvature or large depth. For example, when plating a wiring layer (120) on an insulating layer (110), plating may not be performed smoothly in areas having a relatively large curvature or depth, so that the area may not be completely filled with a metal material, and voids may be formed between the insulating layer (110) and the wiring layer (120). The voids may reduce the adhesion between the insulating layer (110) and the wiring layer (120), which may cause the wiring layer (120) to peel off from the insulating layer (110). In addition, cracks (or popcorn defects) may occur in the area where the voids are formed due to stress caused by a heat cycle. In contrast, the embodiment can completely remove voids by providing a concave portion (110C) having a uniform curvature on the surface of the insulating layer (110), and can further improve the adhesion between the wiring layer (120) and the insulating layer (110).

[0115] That is, a plurality of concave portions (110C) having a uniform width and / or depth may be provided on one surface of the insulating layer (110) of the embodiment. At this time, the concave portions (110C) may provide a certain level of surface roughness to one surface of the insulating layer (110). Through this, a uniform surface roughness may be provided to one surface of the insulating layer (110). Therefore, the embodiment can further improve the adhesion between the wiring layer (120) and the insulating layer (110), solve the problem of cracks occurring at the interface between the insulating layer (110) and the wiring layer (120) due to stress caused by a heat cycle, and form a wiring layer (120) having a uniform thickness on the insulating layer (110) through improvement of the plating process.

[0116] In addition, the curvature of the concave portion (110C) provided on the surface of the insulating layer (110) may be different from the curvature of the inorganic filler (110F) embedded in the insulating layer (110). Here, the different curvature may mean that the shape of the concave portion (110C) and the shape of the inorganic filler (110F) are different, but is not limited thereto. For example, the different curvature may mean that the inorganic filler (110F) embedded in the insulating layer (110) is not exposed to the outside of the insulating layer (110) through the concave portion (110C) of the insulating layer (110). In addition, the different curvature may mean that the inorganic filler (110F) embedded in the insulating layer (110) is not detached from the insulating layer (110) during the process of forming the concave portion (110C) on the surface of the insulating layer (110).

[0117] In the embodiment, a concave portion (110C) is provided on the surface of the insulating layer (110) while preventing the inorganic filler (110F) embedded in the insulating layer (110) from being exposed and / or falling off to the outside of the insulating layer (110). Through this, the embodiment can solve physical reliability problems and / or electrical reliability problems that occur when the inorganic filler (110F) of the insulating layer (110) is exposed and / or falling off to the surface of the insulating layer (110) in a process of providing a certain level of surface roughness to the surface of the insulating layer (110).

[0118] In addition, at least one of the inorganic fillers (110F) embedded in the insulating layer (110) may overlap a concave portion (110C) provided on the surface of the insulating layer (110) in a horizontal direction. For example, at least one inorganic filler (110F) may be arranged between a plurality of concave portions (110C) provided on the surface of the insulating layer (110). At this time, the inorganic filler (110F) overlapped with the concave portion (110C) in a horizontal direction may function as a reinforcing portion that reduces the degree of thermal deformation due to thermal expansion and / or thermal shrinkage caused by the heat cycle of the insulating layer (110), may prevent the stress described above from being transmitted to the wiring layer (120) provided on the insulating layer (110), and may further function to improve the adhesion between the insulating layer (110) and the wiring layer (120).

[0119] In addition, the concave portion (110C) provided in the insulating layer (110) may overlap with the connecting member (200) in the vertical direction. Accordingly, the protrusion (120P) of the wiring layer (120) corresponding to the concave portion (110C) of the insulating layer (110) may overlap with the connecting member (200) in the vertical direction. Through this, the embodiment can prevent stress according to the heat cycle from being transmitted to the connecting member (200), secure the rigidity of the circuit board, and thereby enable the connecting member (200) to be stably placed within the circuit board and operate stably.

[0120] Referring to (a) of Fig. 3, in the conventional technology, a concave portion corresponding to a certain level of surface roughness is provided on the surface of the insulating layer (10) through a desmear process.

[0121] At this time, in the conventional technology, a desmear process of etching and removing with a chemical agent is performed to provide a concave portion on the surface of the insulating layer (10). According to the conventional technology described above, in the process of desmearing the insulating layer (10), the inorganic filler (10F) embedded in the insulating layer (10) may be exposed to the outside of the insulating layer (10). At this time, when the inorganic filler (10F) is exposed to the outside of the insulating layer (10), there is a problem that the adhesion between the insulating layer (10) and the wiring layer is reduced. That is, the adhesion between the inorganic filler (10F) of the insulating layer (10) and the wiring layer is lower than the adhesion between the resin of the insulating layer (10) and the wiring layer. Accordingly, the adhesion between the insulating layer (10) and the wiring layer in the area where the inorganic filler (10F) is exposed may be reduced, and this may cause a problem in which the wiring layer is peeled off from the insulating layer. Additionally, as the wiring layer and the inorganic filler (10F) come into contact, loss of electrical signals and / or power applied to the semiconductor element (320, 330) and / or the connecting member (200) may occur.

[0122] In addition, a plurality of concave portions are provided on the surface of the insulating layer (10) of the prior art. At this time, the plurality of concave portions provided on the surface of the insulating layer (10) of the prior art include a first concave portion (10C1), which is a region where the resin of the insulating layer (10) is removed in the desmear process, and a second concave portion (10C2), which corresponds to a space where the inorganic filler (10F) is removed. At this time, the first concave portion (10C1) and the second concave portion (10C2) may have different depths in the vertical direction. For example, the depth of the second concave portion (10C2) in the vertical direction may be greater than the depth of the first concave portion (10C1) in the vertical direction. Therefore, when a chemical copper plating layer, which is a seed layer of a wiring layer, is formed on the surface of the insulating layer (10), chemical copper plating may not be performed on at least a portion of the second concave portion (10C2), which may result in voids. Additionally, stress due to the heat cycle may be concentrated in the second concave portion (10C2) having a relatively large depth, which may deteriorate the physical reliability and / or electrical reliability of the semiconductor package.

[0123] In addition, an inorganic filler may be embedded in the insulating layer (10) to ensure that the insulating layer (10) has a certain level of dielectric constant. However, in the process of desmearing the insulating layer (10), the inorganic filler embedded in the insulating layer (10) may be removed, and depending on the dielectric constant of the removed inorganic filler, the dielectric constant of the insulating layer (10) may change, and the dielectric properties of the insulating layer (110) may change, which may cause the dielectric properties of the circuit board to change.

[0124] In contrast, referring to (b) of FIG. 3, an embodiment may be provided with a protrusion having a uniform thickness on the surface of a metal layer, and the above-described metal layer may be laminated on the surface of an insulating layer (110), thereby transferring a concave portion (110C) to the surface of the insulating layer (110) corresponding to the protrusion.

[0125] Accordingly, the embodiment forms a concave portion (110C) using a metal layer having protrusions, so that the inorganic filler (110F) embedded in the insulating layer (110) may not be exposed to the surface of the insulating layer (110). For example, when the metal layer having protrusions is placed on the surface of the insulating layer (110) and pressurized, the inorganic filler (110F) positioned adjacent to the upper surface of the insulating layer (110) may move downward due to the pressurization of the metal layer, and thus may not be exposed to the surface of the insulating layer (110). Accordingly, the embodiment not only prevents the inorganic filler (110F) from being exposed, but also may form a plurality of concave portions (110C) having a more uniform curvature or a more uniform depth than the conventional technology on the upper surface (110T) of the insulating layer (110).

[0126] Accordingly, when stress due to a heat cycle is applied to the insulating layer (110), the embodiment can prevent stress from being concentrated in a specific area of ​​the insulating layer (110) by providing a plurality of concave portions (110C) with uniform curvature on the upper surface of the insulating layer (110), and further, can evenly distribute the stress overall, thereby improving the physical reliability and electrical reliability of the semiconductor package.

[0127] In addition, the embodiment can provide a dense region of the inorganic filler (110F) arranged adjacent to the surface of the insulating layer (110) so that the inorganic filler (110F) can move inwardly of the insulating layer (110) by the pressure of the metal layer, thereby providing a dense region of the inorganic filler (110F) adjacent to the concave portion (110C). The dense region of the inorganic filler (110F) can mean that the gap between a plurality of inorganic fillers (110F) is smaller than that between other regions. Through this, the embodiment can solve the problem of the semiconductor package being greatly warped in a specific direction by providing a region where the inorganic filler (110F) is densely packed adjacent to the surface of the insulating layer (110). For example, the embodiment can firmly hold the insulating layer (110) in the region where the inorganic filler (110F) is densely packed, thereby preventing the semiconductor package from being greatly warped in a specific direction.

[0128] In addition, the embodiment can prevent the inorganic filler (110F) embedded in the insulating layer (110) from falling off from the insulating layer (110) in the process of providing a concave portion (110C) on the surface of the insulating layer (110). Therefore, the embodiment can prevent the dielectric constant of the insulating layer (110) from changing due to the falling off of the inorganic filler (110F), thereby improving the dielectric properties of the circuit board.

[0129] Referring to the embodiment of FIG. 4, recesses having different depths may be provided on the surface of the insulating layer (110). For example, a first recess (110C) having a first depth in the vertical direction may be provided on the surface of the insulating layer (110). The first recess (110C) corresponds to the recess described with reference to FIGS. 2 and 3, and thus, a detailed description thereof will be omitted. A second recess (110E) having a second depth in the vertical direction that is different from the first depth of the first recess (110C) may be provided on the surface of the insulating layer (110). The second recess (110E) may refer to a region that is provided by etching the surface of the insulating layer (110) together with the metal layer in a process of removing the metal layer laminated on the surface of the insulating layer (110) by etching. At this time, when only the first concave portion (110C) is provided on the surface of the insulating layer (110), the portion of the surface of the insulating layer (110) where the first concave portion (110C) is not provided may be flat and a height difference with the first concave portion (110C) may occur. Therefore, the embodiment may provide the second concave portion (110E) between a plurality of first concave portions (110C) on the surface of the insulating layer (110), thereby minimizing the height difference on the surface of the insulating layer (110). Therefore, the embodiment may provide a uniform chemical copper plating layer on the surface of the insulating layer (110), prevent the plating current from being concentrated and distributed in an area with a relatively high height in the plating process of the wiring layer (120), and enable the wiring layer (120) to be formed with a uniform thickness. For example, the second concave portion (110E) may be provided between a plurality of first concave portions (110C) to serve as a bridge for dispersing plating current in a plating process for forming a wiring layer (120), thereby further improving the adhesion between the insulating layer (110) and the wiring layer (120) while minimizing the thickness deviation of the wiring layer (120).

[0130] In addition, as described above, a wiring layer (120) may be provided on the surface of the insulating layer (110), and further, the insulating layer (110) may have a structure in which a plurality of layers are laminated along the vertical direction. Accordingly, a concave portion and / or a protruding portion may be provided at the interface between the plurality of insulating layers and / or at the interface between the insulating layer and the wiring layer.

[0131] Referring to the embodiment of FIG. 5, the insulating layer (110) may have a structure in which multiple layers are stacked along a vertical direction. Hereinafter, the recesses and / or protrusions provided at the interface between the multiple insulating layers and the recesses and / or protrusions provided at the interface between the insulating layer and the wiring layer will be described based on the upper build-up insulating layer (112) of FIG. 1.

[0132] The circuit board may include a first insulating layer (510) and a second insulating layer (520) disposed on the first insulating layer (510). In addition, a wiring layer (530) may be provided between the first insulating layer (510) and the second insulating layer (520), a first via electrode (540) may be provided penetrating at least a portion of the first insulating layer (510), and a second via electrode (550) may be provided penetrating at least a portion of the second insulating layer (520).

[0133] A concave portion (510C) may be provided on the upper surface of the first insulating layer (510). The concave portion (510C) may be provided to provide a certain level of roughness to the upper surface of the first insulating layer (510), and may be provided to improve the adhesion between the first insulating layer (510) and the second insulating layer (520) and the adhesion between the first insulating layer (510) and the wiring layer (530).

[0134] The upper surface of the first insulating layer (510) may have a first upper surface in contact with the second insulating layer (520) and a second upper surface in contact with the wiring layer (530). In addition, each of the first and second upper surfaces of the first insulating layer (510) may have a concave portion (510C).

[0135] In addition, the concave portion (510C) provided on the first upper surface of the first insulating layer (510) can be filled with the second insulating layer (520), and the concave portion (510C) provided on the second upper surface of the first insulating layer (510) can be filled with the wiring layer (530).

[0136] For example, a protrusion (520P) may be provided on the lower surface of the second insulating layer (520) to fill a concave portion (510C) provided on the first upper surface of the first insulating layer (510). The protrusion (520P) provided on the lower surface of the second insulating layer (520) may have a curvature and / or thickness corresponding to the curvature and / or depth of the concave portion (510C) provided on the first upper surface of the first insulating layer (510).

[0137] The protrusion (520P) provided on the lower surface of the second insulating layer (520) may be in direct contact with the upper surface of the first insulating layer (510), may not be in contact with the inorganic filler (510F) embedded in the first insulating layer (510), and may overlap with at least one inorganic filler (510F1) of the inorganic fillers (510F) embedded in the first insulating layer (510) along the horizontal direction. Through this, the embodiment can improve the adhesion between the first insulating layer (510) and the second insulating layer (520), and can minimize the degree of thermal deformation at the interface between the first insulating layer (510) and the second insulating layer (520) according to the heat cycle by improving the rigidity, thereby further improving the mechanical reliability.

[0138] Additionally, a protrusion (530P) may be provided on the lower surface of the wiring layer (530) to fill a concave portion (510C) provided on the second upper surface of the first insulating layer (510). The protrusion (530P) provided on the lower surface of the wiring layer (530) may have a curvature and / or thickness corresponding to the curvature and / or depth of the concave portion (510C) provided on the second upper surface of the first insulating layer (510).

[0139] The protrusion (530P) provided on the lower surface of the wiring layer (530) may be in direct contact with the upper surface of the first insulating layer (510), may not be in contact with the inorganic filler (510F) embedded in the first insulating layer (510), and further may overlap with at least one inorganic filler (510F1) of the inorganic fillers (510F) embedded in the first insulating layer (510) along the horizontal direction. Therefore, the embodiment can further improve the adhesion between the first insulating layer (510) and the wiring layer (530), and can improve the rigidity to minimize the degree of thermal deformation at the interface between the first insulating layer (510) and the wiring layer (530) according to the heat cycle, thereby further improving the mechanical reliability.

[0140] In addition, the first via electrode (540) penetrating the first insulating layer (510) can be formed by filling the interior of a via hole penetrating at least a portion of the first insulating layer (510) with a conductive material. At this time, in the process of forming the via hole in the first insulating layer (510), at least one of the inorganic fillers (510F) embedded in the first insulating layer (510) can be exposed through the via hole. Therefore, the first via electrode (540) can have a first side surface (540S1) that contacts the inorganic filler (510F). Furthermore, in the process of forming a via hole in the first insulating layer (510), at least one of the inorganic fillers (510F) embedded in the first insulating layer (510) may be removed from the first insulating layer (510), and accordingly, the first via electrode (540) may include a second side surface (540S2) that is convex toward the outer surface of the first insulating layer (510) while filling the space where the inorganic filler (510F) is removed. At this time, the second side surface (540S2) of the first via electrode (540) may function as an anchor to firmly fix the first via electrode (540) to the first insulating layer (510) while improving the adhesion between the first insulating layer (510) and the first via electrode (540). Through this, the embodiment can further improve the adhesion between the first insulating layer (510) and the first via electrode (540), thereby further improving the physical reliability and / or electrical reliability of the semiconductor package.

[0141] Additionally, the concave portion provided in the insulating layer may be filled with a protective layer, and accordingly, a protrusion corresponding to the concave portion provided on the surface of the insulating layer may be provided on the lower surface of the protective layer.

[0142] Referring to FIG. 6, the circuit board may include an insulating layer (610), a wiring layer (620), a via electrode (630), a protective layer (650), and a bump layer (640). The insulating layer (610) may represent an insulating layer provided on the outermost side (e.g., the top side) among the insulating layers provided in the multiple layers described in the previous embodiment.

[0143] A plurality of concave portions (610C) may be provided on the surface of the insulating layer (610). That is, the concave portions (610C) may be provided on the upper surface of the insulating layer (610) and may be concave toward the lower surface of the insulating layer (610). The concave portions (610C) may be provided to provide a certain level of roughness to the upper surface of the insulating layer (610), and may be provided to improve the adhesion between the insulating layer (610) and the protective layer (650), and the adhesion between the insulating layer (610) and the wiring layer (620).

[0144] The upper surface of the insulating layer (610) may have a first upper surface in contact with the protective layer (650) and a second upper surface in contact with the wiring layer (620). In addition, each of the first and second upper surfaces of the insulating layer (610) may have a concave portion (610C).

[0145] In addition, the concave portion (610C) provided on the first upper surface of the insulating layer (610) can be filled with a protective layer (650), and the concave portion (610C) provided on the second upper surface of the insulating layer (610) can be filled with a wiring layer (620).

[0146] For example, the lower surface of the protective layer (650) may be provided with a protrusion (650P) that fills the concave portion (610C) provided on the first upper surface of the insulating layer (610). The protrusion (650P) provided on the lower surface of the protective layer (650) may have a curvature and / or thickness corresponding to the curvature and / or depth of the concave portion (610C) provided on the first upper surface of the insulating layer (610).

[0147] The protrusion (650P) provided on the lower surface of the protective layer (650) may be in direct contact with the upper surface of the insulating layer (610), may not be in contact with the inorganic filler (610F) embedded in the insulating layer (610), and may overlap with at least one of the inorganic fillers (510F) embedded in the insulating layer (610) along the horizontal direction. Through this, the embodiment can improve the adhesion between the insulating layer (610) and the protective layer (650), improve the rigidity, and minimize the degree of thermal deformation at the interface between the insulating layer (610) and the protective layer (650) according to the heat cycle, thereby further improving the mechanical reliability.

[0148] In addition, a protrusion (620P) that fills a concave portion (610C) provided on the second upper surface of the insulating layer (610) may be provided on the lower surface of the wiring layer (620). Since this has already been described in the previous embodiment, a detailed description thereof will be omitted.

[0149]

[0150] Fig. 7 is a drawing showing a semiconductor package according to the second embodiment.

[0151] Referring to FIG. 7, the semiconductor package (2000) of the second embodiment may have a structure in which the connecting member (200) is omitted compared to the semiconductor package (1000) of the first embodiment.

[0152] The circuit board (2100) of the semiconductor package of the second embodiment may include an insulating layer (2110), a wiring layer (2120), a via electrode (2130), a bump layer (240), a first protective layer (2150), and a second protective layer (2150). In addition, depending on the stacking direction of the plurality of layers of the insulating layer (2110), a concave portion and / or a protrusion may be provided on the upper surface and / or the lower surface, and the wiring layer (2120) and the protective layers (2140, 2150) may be provided with protrusions corresponding to the concave portions.

[0153] In addition, the concave portion and / or protrusion provided in the insulating layer (2110) of the second embodiment, the protrusion provided in the wiring layer (2120), and the protrusion provided in the protective layer (2140, 2150) are substantially the same as those of the semiconductor package of the first embodiment, and a description thereof is omitted.

[0154] Additionally, the semiconductor package includes a connection portion (2310) and a semiconductor element (2320) arranged on a bump layer (2140) of a circuit board (2100). For example, the circuit board (2100) of the semiconductor package of the second embodiment may be a 2D substrate, through which at least one semiconductor element (2320) may be arranged on the circuit board (2100) without including a connection member (200) embedded within the circuit board (2100).

[0155]

[0156] Figure 8 is a drawing showing a semiconductor package according to the third embodiment.

[0157] Referring to FIG. 8, the semiconductor package of the third embodiment may have a different structure of the circuit board (3100) compared to the semiconductor package of the first embodiment.

[0158] The circuit board (3100) of the semiconductor package of the third embodiment may include an insulating layer (3110), a wiring layer (3120), a via electrode (3130), a bump layer (3140), a first protective layer (3150), and a second protective layer (3160). In addition, a recess and / or a protrusion may be provided on the surface of the insulating layer (3100), and accordingly, the protective layers (3150, 3160) and the wiring layer (3120) may be provided with protrusions. The features of the recess and the protrusion provided on the surface of the insulating layer (3110) of the third embodiment and the protrusions provided on the protective layers (3150, 3160) and the wiring layer (3120) are substantially the same as those of the semiconductor package of the first embodiment, and a description thereof will be omitted. However, unlike the insulating layer of the first embodiment, the insulating layer (3110) of the circuit board (3100) of the third embodiment has a structure in which it is laminated in only one direction based on the insulating layer positioned at the top, and accordingly, a concave portion can be provided on the lower surface of each insulating layer laminated along the vertical direction.

[0159] Additionally, the semiconductor package includes a connection portion (3310) and a semiconductor element (3320) disposed on a bump layer (3140) of a substrate (3100). Additionally, the semiconductor package includes a connection member (3200) embedded in an insulating layer (3110) of the substrate (3100). Additionally, the semiconductor package further includes a second connection portion (3230) embedded in the insulating layer (3110) and electrically connecting a pad portion (3210) of the connection member (3200) and a wiring layer (3120).

[0160] For example, the substrate of the first embodiment of FIG. 1 may be a core substrate, and the substrate of FIG. 8 may be a core-less substrate. In addition, each of the uppermost and lowermost wiring layers provided in the circuit substrate of the first embodiment of FIG. 1 may be provided so as to protrude above and below the insulating layer (110). In contrast, either of the uppermost and lowermost wiring layers provided in the circuit substrate of the third embodiment of FIG. 8 may have a structure in which it is embedded within the insulating layer (3110). For example, the substrate (3100) may have an ETS (Embedded Trace Substrate) structure.

[0161] The embodiments can improve the physical reliability and / or electrical reliability of a circuit board and a semiconductor package including the same.

[0162] Specifically, the embodiment includes an insulating layer. The insulating layer includes a resin and an inorganic filler embedded within the resin. At this time, a plurality of recesses are provided on the upper surface of the insulating layer. In addition, each of the plurality of recesses provided on the upper surface of the insulating layer may have a curvature different from the curvature of the inorganic filler. For example, the inorganic filler embedded within the insulating layer is not exposed through the recesses provided on the upper surface of the insulating layer.

[0163] Accordingly, the embodiment can provide a plurality of concave portions on the upper surface of the insulating layer while preventing the inorganic filler embedded within the insulating layer from being exposed to the outside of the insulating layer. Accordingly, the embodiment can resolve physical reliability issues and / or electrical reliability issues that arise when the inorganic filler of the insulating layer is exposed to the outside during a process of imparting a certain level of surface roughness to the upper surface of the insulating layer.

[0164] Specifically, when the inorganic filler is exposed to the outside of the insulating layer, there is a problem of reduced adhesion between the insulating layer and the wiring layer. That is, the adhesion between the inorganic filler of the insulating layer and the wiring layer is lower than the adhesion between the resin of the insulating layer and the wiring layer. Accordingly, the adhesion between the insulating layer and the wiring layer may be reduced in the area where the inorganic filler is exposed, which may result in the wiring layer being peeled off from the insulating layer.

[0165] In contrast, the embodiment can transfer a concave portion to the upper surface of the insulating layer corresponding to the protrusions provided in the metal layer rather than a desmear process, thereby providing a concave portion having a uniform depth on the upper surface of the insulating layer. Accordingly, the embodiment can prevent the inorganic filler from being exposed to the outside of the insulating layer. Through this, the embodiment can ensure that the wiring layer disposed on the same layer has a uniform thickness, and further improve the adhesion between the insulating layer and the wiring layer.

[0166] In addition, the insulating layer of the prior art using the desmear process has a space where the exposed inorganic filler is removed. At this time, the space where the inorganic filler is removed may have a greater vertical depth than other parts. Therefore, when a chemical copper plating process is performed to form a wiring layer in the space where the inorganic filler is removed, voids may be formed because the chemical copper plating is not performed in at least a portion of the space where the inorganic filler is removed. In addition, stress acting on the insulating layer may be concentrated in the space where the reinforcing member is removed, which may deteriorate the physical reliability and / or electrical reliability of the semiconductor package.

[0167] In contrast, the embodiment can eliminate voids by forming a uniform concave portion on the surface of the insulating layer, thereby further improving the physical reliability and electrical reliability of the semiconductor package. Furthermore, when stress is applied to the insulating layer, the embodiment can prevent the stress from being concentrated in a specific region of the insulating layer by forming a uniform concave portion on the upper surface of the insulating layer, and further, can evenly distribute the stress overall, thereby improving the physical reliability and electrical reliability of the semiconductor package.

[0168] In addition, the embodiment can prevent the inorganic filler embedded in the insulating layer from falling off in the process of providing a concave portion on the surface of the insulating layer, and can prevent the change in the dielectric constant of the insulating layer that may be caused by the falling off of the inorganic filler, thereby further improving the electrical characteristics of the circuit board and semiconductor package.

[0169] In addition, the embodiment includes a wiring layer disposed on an insulating layer, and the wiring layer may have a protrusion protruding toward the insulating layer. The protrusion may correspond to a concave portion provided in the insulating layer. At this time, the protrusion of the wiring layer may horizontally overlap with at least one of a plurality of inorganic fillers embedded in the insulating layer. Through this, the embodiment can improve the rigidity of the circuit board, and by using the inorganic filler overlapped in the horizontal direction as described above, the degree of thermal deformation occurring at the interface between the insulating layer and the wiring layer according to the heat cycle can be minimized, thereby further improving the mechanical reliability.

[0170] In addition, the embodiment includes a protective layer disposed on an insulating layer, and the protective layer may have a protrusion protruding toward the insulating layer. The protrusion of the protective layer may correspond to a concave portion provided in the insulating layer. At this time, the protrusion of the protective layer may horizontally overlap with at least one of a plurality of inorganic fillers embedded in the insulating layer. Through this, the embodiment can improve the rigidity of the circuit board, and by using the inorganic filler overlapping in the horizontal direction described above, the degree of thermal deformation occurring at the interface between the insulating layer and the protective layer according to the heat cycle can be minimized, thereby further improving the mechanical reliability. Furthermore, the embodiment can prevent the stress according to the heat cycle from being transmitted to the bump layer penetrating the protective layer, thereby preventing the occurrence of cracks in the bump layer due to the above-described stress. Therefore, the embodiment can stably mount a semiconductor device on the bump layer, and thereby enable the semiconductor package to operate stably.

[0171]

[0172] Figures 9 to 15 are drawings showing the manufacturing method of the semiconductor package illustrated in Figure 1 in process order.

[0173] Referring to FIG. 9, the embodiment may include a process of preparing a core layer, a process of forming a cavity in the core layer, a process of placing a connecting member in the cavity of the core layer, and a process of laminating a portion of an upper build-up insulating layer and a portion of a lower build-up insulating layer that embed the connecting member on the upper and lower portions of the core layer.

[0174] Next, referring to FIG. 10, a process of placing a metal layer on an insulating layer (110) is performed. For example, the embodiment places a first metal layer (700) including a protrusion (710) on the insulating layer (110). In addition, the embodiment includes a second metal layer (720) including a protrusion (730) under the insulating layer (110).

[0175] Next, referring to FIG. 11, the embodiment proceeds with a process of attaching the first metal layer (700) and the second metal layer (720) to the insulating layer (110) by pressing them.

[0176] Next, referring to FIG. 12, the embodiment performs a process of removing the first metal layer (700) and the second metal layer (720) by etching. Accordingly, the insulating layer (110) is provided with a concave portion (110C) corresponding to the protrusions (710, 730) of the first metal layer (700) and the second metal layer (720).

[0177] Next, referring to FIG. 13, the embodiment proceeds with a process of forming a wiring layer (120).

[0178] Next, referring to FIG. 14, the embodiment performs a process of forming a first protective layer (150) on an insulating layer (110). In addition, the embodiment performs a process of forming a second protective layer (160) under the insulating layer (110). In addition, the embodiment performs a process of forming a bump layer (140) penetrating the first protective layer (150).

[0179] Next, referring to FIG. 15, the embodiment proceeds with a process of placing a connection portion (310) on a bump layer (140). Thereafter, the embodiment proceeds with a process of mounting a semiconductor element (320, 330) on the connection portion (310).

[0180]

[0181] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0182] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0183] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0184] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. An insulating layer with multiple inorganic fillers embedded therein; A wiring layer disposed on the above insulating layer; and Including a protective layer disposed on the above wiring layer, The above wiring layer has a plurality of protrusions protruding toward the insulating layer, The above protrusion does not contact the plurality of inorganic fillers and overlaps at least one of the plurality of inorganic fillers along the horizontal direction. Circuit board.

2. In paragraph 1, The above protective layer has a plurality of protrusions protruding toward the insulating layer. Circuit board.

3. In paragraph 2, The protrusion of the protective layer does not contact the plurality of inorganic fillers and overlaps at least one of the plurality of inorganic fillers along the horizontal direction. Circuit board.

4. In paragraph 3, At least one of the protrusions of the wiring layer and the protrusions of the protective layer is in direct contact with the insulating layer. Circuit board.

5. In paragraph 2, The protrusion of the above protective layer overlaps the protrusion of the above wiring layer in a horizontal direction. Circuit board.

6. In paragraph 1, The thickness of at least one of the plurality of protrusions of the above wiring layer is different from the thickness of at least one other protrusion. Circuit board.

7. In paragraph 1, The upper surface of the insulating layer is provided with a concave portion corresponding to the protrusion of the wiring layer, The lower surface of the above insulating layer is provided with a plurality of protrusions. Circuit board.

8. In paragraph 1, Further comprising a connecting member embedded within the insulating layer; The above connecting member overlaps at least one of the plurality of protrusions along a vertical direction, Circuit board.

9. In paragraph 1, The curvature of the above protrusion is different from the curvature of the above inorganic filler. Circuit board.

10. In paragraph 1, Further comprising a via electrode penetrating at least a portion of the insulating layer along the vertical direction and connected to the wiring layer; At least one of the plurality of inorganic fillers is in contact with a side surface of the via electrode; Circuit board.

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