Systems and methods of three-dimensional integrated circuit stacking for high-performance computing applications

Abstract

Systems for co-locating memory and logic integrated circuits (ICs) to form three-dimensional integrated circuits (3DICs) are disclosed. A logic IC is bonded to a memory module such as a DRAM module through one or more hybrid bonds, one or more micro-bumps, or a combination of both hybrid bonds and micro-bumps. One or both of the logic IC and memory module includes a redistribution layer (RDL) to reroute a plurality of traces from a first pattern exposed on a first side of the RDL to a second pattern on a second side of the RDL.

Description

SYSTEMS AND METHODS OF THREE-DIMENSIONAL INTEGRATED CIRCUIT STACKING FOR HIGH-PERFORMANCE COMPUTING APPLICATIONSCROSS-REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims the priority benefit, under 35 U.S.C. 119(e), of U.S. Provisional Patent Application No. 63 / 605,198, filed December 1, 2023 and entitled “3D DRAM Stacking on Al Accelerators,” U.S. Provisional Patent Application No. 63 / 605,344, filed December 1, 2023 and entitled “Stacked Semiconductor Structure with Direct Electrical Connections,” and U.S. Provisional Patent Application No. 63 / 606,314, filed December 5, 2023 and entitled “Computing Systems with 3-Dimensional Stacking Architecture,” each of which are incorporated herein by reference in their entirety for all purposes.BACKGROUND

[0002] As feature sizes and transistor sizes have decreased for computing hardware such as integrated circuits (ICs) including chips and semiconductor dies, the amount of heat generated by a single chip, such as a microprocessor, has increased. Computing hardware that has traditionally been air cooled has evolved to levels of power consumption requiring more heat dissipation than can be provided by air alone. In some cases, immersion cooling of ICs in a tank containing a coolant liquid is employed to maintain ICs at appropriate operating temperatures.

[0003] One type of immersion cooling is two-phase immersion cooling, in which heat from a semiconductor die is high enough to boil the coolant liquid. The boiling creates a coolantliquid vapor in the tank, which is condensed by cooling coils back to liquid form. Heat from the semiconductor dies can then be sunk into the liquid-to-gas and gas-to-liquid phase transitions of the coolant liquid with the result that the semiconductor dies are kept at an acceptable temperature.

[0004] This improved heat removal capability has led to new computing hardware architectures to increase computational density. However, this increased computational density has shifted computational and data transfer bottlenecks from the realm of IC processing power to the realm of memory latency and bandwidth. Traditional memory architectures have failed to keep pacewith increased computational density and power efficiency requirements, and a new solution is needed.SUMMARY

[0005] State of the art computing systems require greater computing power and associated hardware systems and circuits than ever before. Examples include systems for carrying out artificial intelligence (Al), large language models (LLM) and other computationally intensive applications. Such systems and applications are limited or challenged by available integrated circuit and data storage hardware architectures. Current computing technologies are not suited to meet the future needs for such intensive computing applications including as to compute density, data storage and access, speed, bandwidth, power consumption and heat removal to name a few.

[0006] The foregoing limitations affect existing technologies that attempt to increase the number of processor units or dies side by side or laterally on a common substrate, consuming an unacceptably large form factor and packaging footprint. Examples of such designs include side by side two dimensional multichip modules (MDM), 2.5 dimensional integrated fan-out designs and other chip-on-wafer-on-silicon variants. Such designs introduce substrate or interposer layer limitations. So-called advanced process node designs are costly and will or have reached physical and semiconductor limits and cannot be relied on to achieve greater results than currently available technologies.

[0007] The addition of more circuit components to computing systems to obtain greater computational output has thus not been able to resolve the above challenges and limitations. Attempts to increase the capacity of such systems by additively placing more circuits onto shared or distributed substrates has resulted in unacceptable area and volume on chip and wafer problems, excess power consumption and heat dissipation problems and other issues as far as noise control and unwanted parasitic capacitances as well. Improved systems and computing hardware circuit designs are needed to address high demand applications such as Al systems.

[0008] The high bandwidth and low latency requirements of these computationally intensive processes has driven integrated circuit (IC) designers to improve information transmission efficiency wherever possible. One way to improve the performance of high-computational- intensity processes is to co-locate the logic circuitry used to perform computations with the memory on which the computed data is stored. An exemplary co-located logic and memoryarchitecture may include a memory module bonded directly on top of a logic IC. This disclosure is directed in various aspects to stacked IC and / or memory designs, which address the need to substantially increase the computational capacity of a given die or wafer while avoiding the unwanted side-effects of additive components described above.

[0009] In some aspects, the present technology is directed to a system for computing in the context of advanced artificial intelligence (Al), machine language and other computationally intensive applications, generally, high performance computing applications. Moreover, the present technology is directed in some aspects to high performance applications while sustaining achievable hardware footprints on a semiconductor platform and without exceeding power and / or thermal design limitations.

[0010] In further aspects, the present technology is directed to three-dimensional integrated circuits (3DICs) by stacking (or otherwise bonding) DRAM memory modules with computational logic ICs such as Al accelerator units. The connection between stack elements may be established using hybrid bonding or micro-bump bonding, in some instances including redistribution layers. The 3DIC format and related bonding improves energy consumption and data transfer efficiency. The improved heat dissipation capability provided by two-phase immersion cooling helps enable the 3DIC format and leads to improvements in computational speed, reduced energy consumption, lower data transfer latencies, and higher bandwidths.

[0011] In further aspects, sensors and transceivers may be connected electrically to a system- on-a-chip (SoC) using a substrate or printed circuit board (PCB). Examples of techniques for such electrical connections include surface-mounted technology and pluggable connections. These electrical connections cause several problems including slow data transport speeds, high power consumption, and large form factors. The slow data transport speeds limit engine data speeds to approximately 800 GHz, which increases latency, for example, of moving data between memory storage and the SoC. This architecture also may also result in increased power consumption.

[0012] To address the latency issues, slow data transport speeds, and high power consumption associated with conventional semiconductor structures and electrical connections, novel semiconductor structures and electrical connections are provided. The novel semiconductor structure includes an SoC, a memory module, and an optical engine. The optical engine is directly electrically connected to the SoC or to the memory module. The SoC is directly electrically connected to the memory module. The direct electrical connections are formedusing electrical connection points without using an intermediate structure such as an interposer. The direct electrical connections are made through any layers and elements disposed on the front and / or back sides of the SoC, the memory module, and / or the optical engine, such as conductive leads, insulator layers, and / or redistribution layers.

[0013] By placing the SoC in close physical proximity to memory module and to the optical engine, latency is significantly reduced, data transport speeds are significantly increased (e.g., to over 1.6 THz), and power consumption is significantly reduced compared to conventional semiconductor structures. The SoC can include Al accelerators and / or can form a portion of an Al training server or an Al inference server. The semiconductor structure can also be deployed in a data center.

[0014] In some aspects, the techniques described herein relate to a system for co-locating memory and computational logic, the system including: a memory module including a memory face side and a memory back side; a logic integrated circuit (IC) configured to perform computations, the logic IC including a logic IC face side and a logic IC back side; and a first plurality of connections that communicatively couples the logic IC to the memory module; wherein the memory module is mechanically coupled to the logic IC through the first plurality of connections.

[0015] In some aspects, the techniques described herein relate to a system, wherein the memory face side is communicatively and mechanically coupled to the logic IC face side.

[0016] In some aspects, the techniques described herein relate to a system, wherein the memory face side is communicatively and mechanically coupled to the logic IC back side.

[0017] In some aspects, the techniques described herein relate to a system, wherein the memory back side is communicatively and mechanically coupled to the logic IC face side.

[0018] In some aspects, the techniques described herein relate to a system, further including: one or more high-bandwidth memory (HBM) modules; an interposer communicatively coupled to the one or more HBM modules; and a second plurality of connections that communicatively couples the one or more HBM modules, the logic IC, and the interposer.

[0019] In some aspects, the techniques described herein relate to a system, wherein the first plurality of connections includes at least one of hybrid bonds or micro-bumps.

[0020] In some aspects, the techniques described herein relate to a system, wherein the first connections and the second connections includes at least one of hybrid bonds or micro-bumps.

[0021] In some aspects, the techniques described herein relate to a system, wherein: the logic IC face side includes a logic IC redistribution layer (RDL), the logic IC RDL including: a first side exposing a plurality of logic IC traces in a first pattern matching the logic IC face side; and a second side exposing the plurality of logic IC traces in a second pattern matching a plurality of memory traces exposed on the memory module; and the logic IC RDL is communicatively and mechanically coupled to the memory face side.

[0022] In some aspects, the techniques described herein relate to a system, wherein: the memory module face side includes a memory redistribution layer (RDL), the memory RDL including: a first side exposing a plurality of memory module traces in a first pattern matching the memory module face side; and a second side exposing the plurality of memory module traces in a second pattern matching a plurality of logic IC traces exposed on the logic IC; and the memory RDL is communicatively and mechanically coupled to the logic IC face side.

[0023] In some aspects, the techniques described herein relate to a system for co-locating memory and computational logic, the system including: a memory module including a memory face side, a memory back side, and a memory redistribution layer (RDL) disposed on the memory face side; and a logic integrated circuit (IC) configured to perform computations, the logic IC including a logic IC face side, a logic IC back side, and a logic IC RDL disposed on the logic IC face side; wherein the memory module is communicatively and mechanically coupled to the logic IC through a plurality of connections between the memory RDL and the logic IC RDL.

[0024] In some aspects, the techniques described herein relate to a system, wherein: the memory RDL reroutes a plurality of memory traces from a first pattern at the memory face side to a second pattern matching a plurality of logic IC traces exposed by the logic IC RDL; and the logic IC RDL reroutes the plurality of logic IC traces from the second pattern to a third pattern matching the plurality of logic IC traces exposed by the logic IC face side.

[0025] In some aspects, the techniques described herein relate to a system 10 or 11, wherein the plurality of connections includes a plurality of hybrid bonds.

[0026] In some aspects, the techniques described herein relate to a system 10 or 11, wherein the plurality of connections includes a plurality of micro-bumps.

[0027] In some aspects, the techniques described herein relate to a system 10 or 11, wherein the plurality of connections includes a combination of one or more hybrid bonds and one or more micro-bumps.

[0028] In some aspects, the techniques described herein relate to a semiconductor structure including: a system-on-a-chip (SoC) having a front side and a back side; a memory module having a front side and a back side, the back side of the memory module being directly electrically connected to the front side of the SoC; and an optical engine having a front side and a back side, the back side of the optical engine being directly electrically connected to the front side of the memory module.

[0029] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a first set of micro bumps that directly electrically connect the back side of the memory module to the front side of the SoC; and a second set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0030] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a first set of hybrid bonds that directly electrically connect the back side of the memory module to the front side of the SoC; and a second set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0031] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a set of micro bumps that directly electrically connect the back side of the memory module to the front side of the SoC; and a set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0032] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a set of hybrid bonds that directly electrically connect the back side of the memory module to the front side of the SoC; and a set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0033] In some aspects, the techniques described herein relate to a semiconductor structure, wherein the optical engine includes an electrical integrated circuit (EIC) and a photonic integrated circuit (PIC).

[0034] In some aspects, the techniques described herein relate to a semiconductor structure, wherein the EIC and the PIC are disposed on a common chip.

[0035] In some aspects, the techniques described herein relate to a semiconductor structure, wherein the EIC and the PIC are disposed on separate chips.

[0036] In some aspects, the techniques described herein relate to a semiconductor structure, further including a redistribution layer on the back side of the memory module, the front side of the SoC, the back side of the optical engine, or the front side of the memory module.

[0037] In some aspects, the techniques described herein relate to a semiconductor structure, further including a plurality of redistribution layers, each redistribution layer on the back side of the memory module, the front side of the SoC, the back side of the optical engine, or the front side of the memory module.

[0038] In some aspects, the techniques described herein relate to a semiconductor structure, wherein the memory module includes random access memory (RAM) integrated circuits.

[0039] In some aspects, the techniques described herein relate to a semiconductor structure, wherein at least a portion of the RAM integrated circuits are dynamic RAM (DRAM) integrated circuits.

[0040] In some aspects, the techniques described herein relate to a semiconductor structure including: a memory module having a front side and a back side; a system-on-a-chip (SoC) having a front side and a back side, the back side of the SoC being directly electrically connected to the front side of the memory module; and an optical engine having a front side and a back side, the back side of the optical engine being directly electrically connected to the front side of the SoC.

[0041] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a first set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the SoC.

[0042] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a first set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the SoC.

[0043] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the SoC.

[0044] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the SoC.

[0045] In some aspects, the techniques described herein relate to a semiconductor structure 27- 31 wherein the optical engine includes an electrical integrated circuit (EIC) and a photonic integrated circuit (PIC).

[0046] In some aspects, the techniques described herein relate to a semiconductor structure wherein the EIC and the PIC are disposed on a common chip.

[0047] In some aspects, the techniques described herein relate to a semiconductor structure wherein the EIC and the PIC are disposed on separate chips.

[0048] In some aspects, the techniques described herein relate to a semiconductor structure further including a redistribution layer on the back side of the SoC, the front side of the memory module, the back side of the optical engine, or the front side of the SoC.

[0049] In some aspects, the techniques described herein relate to a semiconductor structure further including a plurality of redistribution layers, each redistribution layer on the back side of the SoC, the front side of the memory module, the back side of the optical engine, or the front side of the SoC.

[0050] In some aspects, the techniques described herein relate to a semiconductor structure wherein the memory module includes random access memory (RAM) integrated circuits.

[0051] In some aspects, the techniques described herein relate to a semiconductor structure, wherein at least a portion of the RAM integrated circuits are dynamic RAM (DRAM) integrated circuits.

[0052] In some aspects, the techniques described herein relate to a semiconductor structure including: a memory module having a front side and a back side; a system-on-a-chip (SoC) having a front side and a back side, the back side of the SoC being directly electrically connected to the front side of the memory module; and an optical engine having a front side and a back side, the back side of the optical engine being directly electrically connected to the front side of the memory module.

[0053] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a first set of micro bumps that directly electrically connect the back side ofthe SoC to the front side of the memory module; and a second set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0054] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a first set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0055] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0056] In some aspects, the techniques described herein relate to a semiconductor structure, further including: a set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0057] In some aspects, the techniques described herein relate to a semiconductor structure 39- 43 wherein the optical engine includes an electrical integrated circuit (EIC) and a photonic integrated circuit (PIC).

[0058] In some aspects, the techniques described herein relate to a semiconductor structure wherein the EIC and the PIC are disposed on a common chip.

[0059] In some aspects, the techniques described herein relate to a semiconductor structure wherein the EIC and the PIC are disposed on separate chips.

[0060] In some aspects, the techniques described herein relate to a semiconductor structure further including a redistribution layer on the back side of the SoC, the front side of the memory module, or the back side of the optical engine.

[0061] In some aspects, the techniques described herein relate to a semiconductor structure further including a plurality of redistribution layers, each redistribution layer on the back side of the SoC, the front side of the memory module, or the back side of the optical engine.

[0062] All combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are part of the inventive subject matter disclosed herein.The terminology used herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and / or structurally similar elements).

[0064] FIG. 1 illustrates energy efficiency vs. distance for multiple logic IC and memory module arrangements.

[0065] FIG. 2A illustrates computational system architectures including a single logic IC and a single memory module bonded together to form a 3DIC stack.

[0066] FIG. 2B illustrates a plurality of memory modules in a stack bonded to a logic IC through one or more hybrid bonds or one or more micro-bump bonds.

[0067] FIG. 3A illustrates systems having a logic IC communicatively and mechanically coupled to a single memory module through a direct bond.

[0068] FIG. 3B illustrates systems having a logic IC communicatively and mechanically coupled to a plurality of memory modules through a direct bond between the logic IC and at least one of the plurality of memory modules.

[0069] FIG. 4A depicts a logic IC and memory module in accordance with the present technology.

[0070] FIG. 4B illustrates four bonding orientations for a logic IC and a memory module using one or more hybrid bonds.

[0071] FIG. 4C illustrates four bonding orientations for a logic IC and a memory module using one or more micro-bumps.

[0072] FIG. 4D illustrates a logic IC and memory module bonded by one or more hybrid bonds between redistribution layers.

[0073] FIG. 5 illustrates a flowchart of a method in accordance with the present technology.

[0074] FIG. 6 illustrates a three-dimensional integrated circuit (3DIC) in accordance with the present technology.

[0075] FIG. 7 illustrates a circuit diagram of a 3DIC stack including a memory module and logic IC.

[0076] FIG. 8 illustrates an exemplary 3DIC using bump bonding between stacked dies.

[0077] FIG. 9 illustrates an exemplary 3DIC using hybrid bonding between stacked dies.

[0078] FIG. 10 illustrates an exemplary 3DIC stacked system.

[0079] FIG. 11 illustrates an additional exemplary 3DIC stacked system.

[0080] FIG. 12 illustrates an additional exemplary 3DIC stacked system.

[0081] FIG. 13 illustrates a method for making a 3DIC system.

[0082] FIG. 14 is a cross section of a semiconductor structure according to an embodiment.

[0083] FIG. 15 is a cross section of a semiconductor structure according to another embodiment.

[0084] FIG. 16 is a cross section of a semiconductor structure according to another embodiment.

[0085] FIG. 17 is a cross section of a semiconductor structure according to another embodiment.

[0086] FIG. 18 is a cross section of a semiconductor structure according to another embodiment.

[0087] FIG. 19 is a cross section of a semiconductor structure according to another embodiment.

[0088] FIG. 20 is a cross section of a semiconductor structure according to another embodiment.

[0089] FIG. 21 is a cross section of a semiconductor structure according to another embodiment.

[0090] FIG. 22 depicts aspects of an immersion cooling system for dissipating heat from one or more heat-generating components such as semiconductor die packages via immersion cooling.DETAILED DESCRIPTION

[0091] FIG. 1 illustrates energy efficiency vs. memory architecture for memory access operations. In a Von Neumann arrangement, a logic IC may be communicatively coupled to a memory module through one or more wires, traces or similar connections. The logic IC and memory module in such a connection may be positioned such that they are not mechanically coupled directly to one another. This arrangement may use on the order of 10-20 picojoules of energy per computed bit. In a near-memory architecture (also referred to as 2.5-dimensional or 3 -dimensional) the memory module may be co-located with a logic IC (such that the corresponding structures abut) or the memory module may be bonded directly to the logic IC forming a 3DIC stack. Bonding a memory module directly to a logic IC may be significantly more energy efficient (an order of magnitude or more) than a Von Neumann arrangement. For example, a 3DIC stack may use on the order of 1-5 picojoules of energy per computed bit.

[0092] FIGS. 2A-B illustrate system architectures for stacking memory modules. FIG. 2A illustrates a first computational system architectures 1200a-l and 1200a-2 including a single logic integrated circuit (IC) and a single memory module bonded together to form a 3DIC stack. A system architecture as illustrated in FIG. 2A may include a logic IC such as a central processing unit (CPU), graphics processing unit (GPU), artificial intelligence (Al) accelerator, field-programmable gate array (FPGA), programmable logic controller (PLC), applicationspecific integrated circuit (ASIC), a digital signal processing (DSP) die, or any suitable logic IC.

[0093] A memory module may be attached to the logic IC, for example in a stacked arrangement with a face of the logic IC bonded to a face of the memory module. A memory module may include a dynamic random access memory (DRAM) module, a static random access memory (SRAM) module, a flash memory module, a solid-state drive (SSD), a nonvolatile random access memory (NVRAM) module, a read-only memory (ROM) module (such as a floating-gate ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), one-time programmable ROM (OTPROM), or the like), or any suitable type of memory module.

[0094] A memory module may be attached to a logic IC using a bond. FIG. 2A illustrates two exemplary systems having different bonds between a memory module and a logic IC: hybridbonds (also referred to as a direct bond interconnect [DBI]) in system 1200a-l and micro-bump bonds in system 1200a-2.

[0095] A hybrid bond combines a bond between two dielectric interfaces (one on each of two dies to be bonded) such as SiCN, SiO, or SiCh and two metallic interfaces (one on each of two dies to be bonded) such as copper, aluminum, or gold. The metallic interfaces may additionally be part of or mechanically coupled to respective traces or leads for transmitting signals. The dielectric interfaces are bonded first, while a gap (referred to as a dishing gap) remains between the metal interfaces. The dies (and interfaces) are then annealed, causing the metal interfaces to reflow and / or bond to one another, creating both a mechanical bond and an electrical / communicative connection between the metal interfaces. A hybrid bond may have the advantages of sub-10-pm bonding pitch, higher bandwidth, lower latency, and improves performance without power and signal penalties.

[0096] A micro-bump is a bond between pads, traces, leads, etc., using a small and targeted amount of solder that may have dimensions on the order of 25 pm. Micro-bumps may enable pitches as small as 40-50 pm; however, smaller pitch spacing becomes difficult due to imprecision in micro-bump placement and resulting cross-contamination between adjacent micro-bumps.

[0097] The logic IC may be mechanically and / or communicatively coupled with a substrate through one or more controlled collapse of chip connection (C4) bumps. The substrate may be a production substrate such as a printed circuit board (PCB) designed to communicatively couple the logic IC to additional circuitry, for example additional circuitry within a server or on a motherboard to which the substrate is attached.

[0098] FIG. 2B illustrates a modification of system 1200a-l and 1200a-2 to include a plurality of memory modules in a stack, which are bonded to a logic IC through one or more hybrid bonds in system 1200b-l or one or more micro-bump bonds in system 1200b-2. The memory modules may be mechanically and / or communicatively coupled to one another using the same bonds connecting the bottom-most memory module to the logic IC (in other words using one or more hybrid bonds between memory modules in system 1200b-l or one or more microbumps between memory modules in system 1200b-2). In an embodiment, the plurality of memory modules may be mechanically and / or communicatively coupled to one another using both micro-bumps and hybrid bonds. Likewise, the bottom-most memory module may bemechanically and / or communicatively coupled to the logic IC using a combination of one or more micro-bumps and one or more hybrid bonds.

[0099] As in systems 1200a-l and 1200a-l, each of the logic ICs of systems 1200b-l and 1200b-2 may be mechanically and / or communicatively coupled with a substrate through one or more controlled collapse of chip connection (C4) bumps. The substrate may be a production substrate such as a printed circuit board (PCB) designed to communicatively couple the logic IC to additional circuitry, for example additional circuitry within a server or on a motherboard to which the substrate is attached.

[0100] Each of the C4 bump, hybrid bond, and / or micro-bump connections may provide a communicative coupling between one or more memory modules of systems 1200a-l through 1200b-2 and one or more additional elements external to systems 1200a-l through 1200b-2. For example, one or more memory modules may be communicatively coupled to one or more CPUs, GPUs, additional memory modules, FPGAs, PLCs, Al accelerators, head nodes, network interface cards (NICs), optical networks, sensors, power supplies, or any suitable external elements.

[0101] FIGS. 3 A and 3B illustrate a system for high-performance computing having memory modules bonded to a logic IC as well as connected high-bandwidth memory. Each of systems 1300a-l through 1300b-2 may include a logic IC, one or more memory modules, and a substrate, each analogous to or having a similar (or same) design as the respective elements of FIGS. 2A and 2B. Each of systems 1300a-l through 1300b-2 may additionally include one or more high-bandwidth memory (HBM) modules, which are communicatively coupled to at least the logic IC through an interposer. HBM may be organized in stacks as depicted in FIGS. 3A and 3B. Each HBM module in an HBM stack may be communicatively coupled to neighboring HBM modules using one or more through silicon vias (TSVs) connected by micro-bumps. HBM modules may be designed for high data transfer rates in excess of tens or hundreds of gigabytes per second.

[0102] An interposer may provide communicative coupling between a logic IC, one or more HBM modules, one or more memory modules, and a substrate via one or more traces, leads, pins, pads, wires, or any suitable communications path. An interposer may be mechanically and / or communicatively coupled to a substrate through one or more C4 bumps, which may provide an indirect connection from the substrate to one or more other elements of systems1300a-l through 1300b-2 including one or more memory modules, the logic IC, and / or one or more HBM modules.

[0103] FIG. 3A illustrates systems 1300a-l and 1300a-2 having a logic IC communicatively and mechanically coupled to a single memory module through a direct bond. System 1300a-l illustrates a single memory module bonded to a logic IC through a hybrid bond, which may be analogous to the memory module, logic IC, and hybrid bond of system 1200a-l.

[0104] System 1300a-2 illustrates a single memory module bonded to a logic IC through a micro-bump bond, which may be analogous to the memory module, logic IC, and micro-bump bond of system 1200a-2.

[0105] FIG. 3B illustrates systems 1300b-l and 1300b-2 having a logic IC communicatively and mechanically coupled to a plurality of memory modules through a direct bond between the logic IC and at least one of the plurality of memory modules. System 1300b- 1 may include a plurality of memory modules bonded to a logic IC through one or more hybrid bonds. The plurality of memory modules, logic IC, and hybrid bonds of system 1300b- 1 may be analogous to the memory modules, logic IC, and hybrid bonds of system 1200b-l. Each memory module of the plurality of memory modules may be connected to one or more neighboring memory modules through one or more hybrid bonds.

[0106] System 1300b-2 may include a plurality of memory modules bonded to a logic IC through one or more micro-bumps. The plurality of memory modules, logic IC, and microbumps of system 1300b-2 may be analogous to the memory modules, logic IC, and microbumps of system 1200b-2. Each memory module of the plurality of memory modules may be connected to one or more neighboring memory modules through one or more micro-bumps.

[0107] Each element of systems 1300a-l through 1300b-2 including logic IC, one or more memory modules, HBM, and interposer may be communicatively coupled to one or more additional elements external to any of systems 1300a-l through 1300b-2. For example, one or more memory modules may be communicatively coupled to one or more CPUs, GPUs, additional memory modules, FPGAs, PLCs, Al accelerators, head nodes, network interface cards (NICs), optical networks, sensors, power supplies, or any suitable external elements.

[0108] FIGS. 4A-4D illustrate several different system architectures that may be used for bonding a memory module to a logic IC in accordance with the present technology.

[0109] FIG. 4A depicts a logic IC and memory module in accordance with the present technology. Each of the logic IC and memory module may have a “face” side and a “back”side as illustrated by 1400-la and 1400-2a respectively. Each side may expose one or more connections such as leads, pads, traces, wires, or similar communications paths for conveying signals to and from the logic IC or memory module. The connections exposed by each side may be different than the other side. In an embodiment, a face side or a back side may expose no connections. In an embodiment, a face side and / or a back side may be bonded to a redistribution layer (RDL) as illustrated by 1400-3a for the logic IC and 1400-4a for the memory module. A redistribution layer may rearrange, reroute, or otherwise re-shape an exposure of any leads, traces, pads, or other connections exposed on a face layer or a back layer of a circuit element. The leads, traces, pads, or other connections may be exposed in a different arrangement, pattern, pitch, or orientation on an exposed surface of the RDL. This rearranged exposure of leads may enable a connection of two 3DIC elements without requiring a redesign of either of the underlying elements.

[0110] FIG. 4B illustrates four bonding orientations for a logic IC and a memory module using one or more hybrid bonds. A first orientation 1400-lb, illustrated in the top left of FIG. 4B, may be a face-to-face (F2F) bonding orientation in which a face side of a logic IC is bonded directly to a face side of a memory module by one or more hybrid bonds. A first element may be “above” or “on top” of a second element if the first element would rest on the second element due to gravity in the absence of a bond attaching the two elements. In an embodiment, a memory module may be placed on top of a logic IC with a F2F bonding orientation. A bottom element in such an orientation may be disposed on or otherwise attached to an interposer, a substrate, or a similar element. The interposer, substrate, or similar element may be further attached to an additional structure such as a server, a server rack, or a motherboard, a printed circuit board (PCB), or other structure.

[0111] A second orientation 1400-2b, illustrated in the bottom left of FIG. 4B, may be a face- to-back (F2B) orientation with a memory module on top of a logic IC. In this F2B orientation, the back side of the memory module may be bonded to the face side of the logic IC by one or more hybrid bonds. FIG. 4B illustrates two additional orientations with a logic IC on top of a memory module. The top right illustration of FIG. 4B shows orientation 1400-3b in which a logic IC is disposed on top of a memory module in an F2F orientation bonded by one or more hybrid bonds. The bottom right illustration of FIG. 4B shows orientation 1400-4b in which a logic IC is disposed on top of a memory module in an F2B orientation with the back side of the logic IC bonded to the face side of the memory module by one or more hybrid bonds.

[0112] FIG. 4C illustrates four bonding orientations 1400-lc, 1400-2c, 1400-3c, and 1400-4c analogous to the bonding orientations 1400-lb, 1400-2b, 1400-3b, and 1400-4b depicted in FIG. 4B with the difference that the hybrid bonds of FIG. 4B are replaced by the micro-bumps of FIG. 4C.

[0113] FIG. 4D illustrates four bonding configurations 1400-ld, 1400-2d, 1400-3d, and 1400- 4d analogous to the bonding orientations 1400-lb, 1400-2b, 1400-3b, and 1400-4b depicted in FIG. 4B and 1400-lc, 1400-2c, 1400-3 c, and 1400-4c depicted in FIG. 4C with the difference that each of the bonded layers are RDLs. These RDLs may allow two 3DIC elements with different lead exposure patterns to be bonded and communicatively coupled without redesigning the underlying elements. FIG. 4D illustrates a logic IC and memory module bonded by one or more hybrid bonds. In an embodiment, the one or more hybrid bonds may be replaced by one or more micro-bumps in accordance with the present technology.

[0114] FIG. 5 illustrates a flowchart for a method 1500 in accordance with the present technology. Method 1500 includes blocks 1510-1530.

[0115] Block 1510 includes fabricating a logic integrated circuit (IC) die comprising first exposed leads in a first pattern.

[0116] Block 1520 includes fabricating a memory module comprising second exposed leads in a second pattern.

[0117] Block 1530 includes mechanically securing the logic IC die to the memory module through one or more bonds that further communicatively couple at least a portion of the first exposed leads to at least a portion of the second exposed leads. Mechanically securing the logic IC die to the memory module may include bonding at least some of the first exposed leads to at least some of the second exposed leads through the one or more bonds. The one or more bonds may include one or more of a bump bond, a micro-bump bond, a hybrid bond, a solder bond, or a controlled collapse chip connection (C4) bond. Mechanically securing the logic IC die to the memory module may include disposing a redistribution layer (RDL) between the logic IC and the memory module. The logic IC die may be mechanically secured to a first side of the RDL and the memory module may be mechanically secured to a second side of the RDL. The first side of the RDL may include leads matching the first pattern and the second side of the RDL comprises leads matching the second pattern. The RDL may include one or more through- substrate- vias (TSVs) communicatively coupling the first side of the RDL to the second side of the RDL.

[0118] Method 1500 may further include thinning at least one of the logic IC die or the memory module. The thinning may be performed before block 1530 or prior to block 1530.

[0119] FIG. 6 illustrates a three-dimensional integrated circuit 1610 in accordance with the present technology. 3-D integrated circuit (3DIC) 1610 may include logic IC 1612 and memory module 1614, where memory module 1614 may be bonded or otherwise attached to logic IC 1612. Integrated circuit 1610 may be mounted or otherwise disposed on laminate substrate 1630, which may be a PCB or other substrate. Integrated circuit 1610 may be communicatively coupled with one or more external components through traces, circuitry, or similar connections through laminate substrate 1630.

[0120] Logic IC 1612 may include circuitry configured to receive input from one or more TSEs and determine at least a temperature and / or a thermal flux within a material that the one or more TSEs are contacting. Logic IC 1612 may include one or more TSEs and / or may be communicatively coupled to one or more TSEs disposed externally to logic IC 1612. For example, logic IC 1612 may be communicatively coupled to one or more TSEs disposed within a memory module such as memory module 1614. Logic IC 1612 may be configured to control the operation of circuitry within logic IC 1612. Additionally or alternatively, logic IC 1612 may be configured to be controlled by one or more external control elements such as a processor, CPU head node, PLC, control plane, or the like.

[0121] Logic IC 1612 may be communicatively coupled with memory module 1614 and laminate substrate 1630. Logic IC 1612 may be fixedly attached to memory module 1614 and / or laminate substrate 1630 through a solder, a braise, an epoxy, a mechanical attachment mechanism such as a clip, screw, bolt, or similar mechanism, and the like. Integrated circuit 1610 may be part of a server, for example a GPU server. In an embodiment, logic IC 1612 may generate waste heat as a result of normal operation. A portion of this waste heat may flow into memory module 1614 and be subsequently emitted by convection, conduction, or radiation from memory module 1614 to a surrounding environment.

[0122] Memory module 1614 may include one or more TSEs configured to output signals indicating a temperature or heat flux at the location of the TSE. Memory module 1614 may include logic circuitry configured to determine a temperature or heat flux from one or more TSE outputs or may only include the one or more TSEs. The one or more TSEs may be communicatively coupled to logic circuitry disposed externally to memory module 1614 (e.g., in logic IC 1612 or another processor) configured to determine a temperature of memorymodule 1614 based on the output from the one or more TSEs disposed within memory module 1614. Memory module 1614 may include one or more memory modules 1716a-b, each memory module 1716a-b communicatively coupled to one or more low-dropout regulators (LDOs) configured to provide energy efficient access to the respective memory module.

[0123] Co-location of memory module 1614 with logic IC 1612 may expose memory module 1614 to more heat than it is designed for. This heat may increase a temperature of memory module 1614 or junction between components of integrated circuit 1610 above a safe operating limit, which may damage or destroy the memory module. To prevent this, logic IC 1612 may read outputs from one or more temperature sensors or TSEs disposed within memory module 1614 and control a power consumption (and therefore waste heat) of logic IC 1612. For example, if logic IC 1612 receives an output from a TSE disposed within memory module 1614 indicating that a temperature of memory module 1614 is above a threshold (for example, above 125° C), logic IC 1612 or other controller may reduce a power drawn (and exhausted as waste heat) by logic IC 1612. Additionally or alternatively, logic IC 1612 may manage a DRAM voltage in response to a temperature of memory module 1614; for example, logic IC 1612 may lower a voltage in response to determining that a temperature of memory module 1614 is higher than a threshold temperature.

[0124] FIG. 7 illustrates a circuit diagram of a 3DIC stack including a memory module and logic IC. 3DIC stack 1710 may include logic IC 1712 and memory module 1714, which may be respectively analogous to logic IC 1612 and memory module 1614 in FIG. 6. Memory module 1714 may include thermal sensing elements 1724a-b (TSEs 1724a-b). TSEs 1724a-b may include a temperature diode, a Vt threshold current mirror, a thermistor, a thermocouple, or any suitable temperature sensor. A Vt threshold current mirror may include one or more bidirectional N / P metal-oxide semiconductor field effect transistor (MOSFET) circuits including a current source. The threshold voltage for turn on current within the current mirror will change with temperature, allowing the voltage to be used as an indicator of temperature. Additionally or alternatively, TSEs 1724a-b may transmit a delta voltage from a band gap circuit.

[0125] TSEs 1724a-b may be communicatively coupled with thermal monitoring circuitry 1740 disposed within logic IC 1712. Logic IC 1712 may additionally include TSEs 1722a-b to provide additional resolution of temperature sensors. TSEs 1724a-b may operate by generating a voltage proportional to temperature, which may then be read by thermal monitoring circuitry 1740 and converted into a temperature. Thermal monitoring circuitry1740 may include one or more temperature sensor circuits 1742a-d, one or more analog-to- digital converters 1744a-d, and control logic 1746.

[0126] Control logic 1746 may include circuitry configured to multiplex individual sensor signals, store sensor values, provide output signals including signals indicating a temperature of memory module 1714 and / or a temperature of logic IC 1712, and provide serial output to allow system engineers to provide feedback control for temperature management. Control logic 1746 may include one or more registers for storing data and making the data accessible through control logic output 1748 and / or control logic input 1747. For example, a user may send a signal using control logic input 1747 causing control logic 1746 to transmit one or more data elements stored on the one or more registers of control logic 1746 using control logic output 1748. Control logic 1746 may utilize control logic output 1748 to output one or more temperatures of memory module 1714, one or more temperatures of logic IC 1712, one or more voltages from TSEs 1722a-b and / or 1724a-b, or any suitable output.

[0127] Control logic 1746 may control an operational parameter of logic IC 1712 and / or memory module 1714. For example, control logic 1746 may control a frequency, voltage, current, power, data transfer rate, computational speed, processing speed, clock speed, or any suitable operational parameter of logic IC 1712 and / or memory module 1714. Control logic 1746 may raise or lower an operational parameter of logic IC 1712 and / or memory module 1714 in response to a temperature of logic IC 1712 and / or memory module 1714. For example, control logic 1746 may lower a frequency, voltage, current, power, data transfer rate, computational speed, processing speed, clock speed, or any suitable operational parameter of logic IC 1712 and / or memory module 1714 in response to determining that a temperature of logic IC 1712 and / or memory module 1714 exceeds a threshold.

[0128] TSEs 1722a-b and 1724a-b may be communicatively coupled to temperature sensor circuits 1742. Temperature sensor circuits 1742 may include circuitry or similar logic configured to receive a voltage, current, or other signal from any of TSEs 1722a-b and / or TSEs 1724a-b and transmit the voltage, current, or other signal to one or more of analog-to-digital converters 1744a-d (ADCs 1744a-d). One or more of ADCs 1744a-d may convert a voltage, current, or other signal from TSE 1722a-b and / or 1724a-b to a number representing a temperature at the location of the respective TSE. ADCs 1744a-d may convert analog voltage readings to digital temperature values with a suitable number of bits of resolution.

[0129] In an embodiment, TSEs may be disposed within memory module 1714 only, logic IC 1712 only, or both memory module 1714 and logic IC 1712. Thermal monitoring circuitry 1740 may be disposed within logic IC 1712 only, memory module 1714 only, or both logic IC 1712 and memory module 1714. Temperature sensor circuits 1742a-d may substantially continuously receive signals from TSEs 1722a-b and / or 1724a-b.

[0130] FIG. 8 depicts an exemplary configuration of components of a system comprising a 3DIC 1810 according to the present disclosure. Considering a base or substrate (not illustrated) as a horizontal plane (along “X”) for the sake of illustration, a plurality of components such as silicon (Si) computing dies 1820, 1822, 1824 are configured vertically (along “Z”) in a 3- dimensional stacked arrangement. The stacked logic circuits may comprise a 3DIC stack of a plurality Al computing dies, which may be identical or substantially identical to one another so as to result in a scaled computing structure with a greater computing capacity on a smaller footprint and in a spatially compact and higher compute density form factor compared to traditional side-by-side designs. In an example, the silicon dies 1820, 1822, 1824 each comprise an identical or substantially identical Al computing die.

[0131] In the above example, the silicon dies 1820, 1822, 1824 are coupled at respective interfaces therebetween using bump bonding points 1830. Bump bonding points 1830 may include one or more micro-bumps, controlled collapse chip connection (C4) bumps, solder bumps, or any suitable bumps.

[0132] In this and other embodiments, a 3DIC stack can comprise a plurality of stacked layers, devices, dies, including processing, data storage and other dies in a stacked product. Specifically, two or more such stacked layers bonded to one another at respective die bonds are envisioned. More specifically, stacks comprising two, three, four or more (almost arbitrary) numbers of stacked dies, circuits and / or memory devices can be formed as suits a given application.

[0133] FIG. 9 depicts another exemplary configuration of components of a system comprising a 3DIC 1910 according to the present disclosure. As before, a plurality of components such as silicon (Si) computing dies 1920, 1922, 1924 are generally disposed in respective parallel planes (along “X”) such that one or more edges of Si computing dies 1920, 1922, and 1924 are disposed substantially parallel to one another and configured vertically (along “Z”) in a 3- dimensional stacked arrangement. As stated, the stacked logic circuits may comprise a 3DIC stack of a plurality Al computing dies, which may be identical or substantially identical to oneanother. In an example, the silicon dies 1920, 1922, 1924 each comprise an identical or substantially identical Al computing die.

[0134] The stacked dies 1820, 1822, 1824, 1920, 1922, 1924 are intended to represent a general arrangement of a plurality of such stacked dies and may comprise examples with two, three, four or more such stacked dies configured and arranged as described and illustrated in the exemplary drawing which is not intended to be limited with respect to the number of the plurality of stacked dies nor as to the scale of the components illustrated for the sake of explanation. Those skilled in the art will appreciate how to multiply and generalize the illustrated examples to include such multi-die 3DIC stacks without loss of generality.

[0135] In the above example, the silicon dies 1920, 1922, 1924 are coupled at respective interfaces therebetween using hybrid bonding (HB) 1930. Further examples of bonding between semiconductor dies, including additional arrangements of 3DIC stacks, dies, and related bonding methods (including further examples of hybrid bonded and / or micro-bump bonded 3DIC stack arrangements having one or more logic ICs bonded to one or more memory modules) can be found in U.S. Provisional Patent Application No. 63 / 605,198, filed December 1, 2023, and titled “3D DRAM Stacking on Al Accelerators,” the entirety of which is incorporated herein by reference.

[0136] FIG. 10 depicts an exemplary architecture for high performance computing systems such as an Al computing system having the foregoing stacked arrangement of computing units such as Al integrated circuits and / or memory storage units such as DRAM units.

[0137] The figure illustrates a 3DIC system 2010 of a plurality of Al computing processor units 2012 arranged vertically upon one another and coupled as described above, with respect to a horizontal substrate 2014, which may be an organic substrate or another type of substrate as best suits a given application. Connection points or bumps 2016 may be applied as shown in the exemplary embodiment, but other configurations are possible as would be required in said given application. The 3DIC assembly may be housed within a heat spreading housing or packaging 2018 as necessary to address the potential temperature management needs of the system as discussed herein.

[0138] FIG. 11 depicts a 3DIC system 2110 comprising a plurality of vertically stacked circuits such as Al computing circuits 2112 and memory units 2114, e.g., DRAM. The present examples illustrate that the components described can be stacked vertically with respect to a substrate 2116 as well as laterally across the substrate to form a high-density computingassembly or system in three dimensions (stacked and side-by-side). The example shown demonstrates a plurality of dies stacked both vertically and laterally with respect to a common system substrate 2116, and more specifically showing a plurality of Al computing circuits 2112 bonded to one another in said vertical (stacked) fashion as well as having a memory module (DRAM) 2114 disposed thereon. Those skilled in the art will understand that the shown examples throughout this disclosure can be generalized to other stacks of computing and / or memory modules in almost arbitrary configurations and combinations to achieve the purpose of a given application. Therefore, the present concept is not limited to the exemplary illustrations given by way of explanation.

[0139] While the illustration is a cross section in the vertical and plane of the figure, it is to be understood that further circuits in the dimension perpendicular to the plane of the figure (in and out of the page) are also comprehended by the disclosure, i.e., in true three-dimensional fashion.

[0140] FIG. 12 illustrates a 3DIC stacked system 2210 having a housing 2218 which may include heat distribution and management structures and a plurality of stacked dies including Al computing dies 2212 and memory modules 2214 such as DRAM memory. The architecture comprises a chip on wafer on substrate (CoWoS) structure 2215 in this example. The architecture also or in the alternative comprises a silicon substrate and / or redistribution layer (RDL) 2217.

[0141] In some aspects, an embodiment such as 3DIC 2210 may comprise a logic die 2220 providing or residing in or embodying a physical layer (PHY) as understood to provide functionality for the memory modules 2214. Again, the illustrated non-limiting example shows the use of vertically stacked as well as laterally disposed dies on common substrate 2216, which in turn may be bump bonded at 2222 to other parts of an overall Al or high performance computing system or computing environment.

[0142] FIG. 13 illustrates an exemplary process, method, steps or acts 2310 in fabricating and making a computing hardware system such as those described in this disclosure. In this example, an Al accelerator chip is fabricated at 2311, for example using copper and silicon oxide (Cu and SiOx) or any other suitable architecture. At 2312 a memory module, e.g., DRAM die or chip is fabricated, which may also comprise Cu and / or SiOx architecture. The exposed Cu leads on the logic IC may match the exposed Cu leads on the memory module (e.g., a first pattern of first exposed leads on the logic IC may match a second pattern of second exposedleads on the memory module when mirrored) and may communicatively and / or mechanically couple the logic IC with the memory module by one or more hybrid bonds. The bonding orientation may be an F2F orientation with the logic IC on top of the memory module and bonded using one or more hybrid bonds, analogous to the orientation and bonding methodology depicted in the top right illustration of FIG. 4B. The Al computing and / or the DRAM components here may be likewise obtained from or sourced for use in the following system. Two or more of such dies are bonded at 2313, for example using a hybrid bond (HB) or other bonding method or means. While FIG. 13 depicts an F2F orientation with a logic IC on top, any suitable combination of bonds and orientations are possible in accordance with the present technology including F2B, micro-bumps, memory module on top, and the like.

[0143] If desired, the Al accelerator or other components may be built up or reduced (thinned down) at 2314. This may be accomplished using any suitable wafer or die thinning technique, including wafer grinding, mechanical polishing, chemical etching (including wet etching, plasma etching, and dry chemical etching), and the like. This thinning process may reduce the complexity of accessing circuitry inside the logic IC by reducing the amount of material between the back side of the logic IC and the circuitry disposed within the logic IC. Open power contacts and metal redistribution may be applied or fabricated at 2315. For example, one or more channels are etched into the remaining back side silicon layer, exposing the internal circuitry of the logic IC. The channels are filled in with metal, creating one or more TSVs. The TSVs may be created using sputter coating, electroplating, or any suitable deposition process. Once the one or more TSVs have been created, one or more bumps may be disposed on the one or more TSVs. These may be standard solder bumps, micro-bumps, C4 bumps, or any suitable bump.

[0144] The system may also be provided with electrical contact bumps at 2316 for coupling to other components of an overall computing environment or system.

[0145] A plurality of stacked units or systems like those described herein (1910, 2010, 2110, 2210) may be coupled electrically, electronically, mechanically and / or logically to form a high performance and spatially compact computing machine or environment. Those also in turn may be coupled to one another locally in a common housing, platform, or may be distributed as needed to deliver the required computing functions desired.

[0146] In an aspect, a 3DIC stack comprises a first stack configured and arranged vertically relative to a horizontal substrate, and wherein said die bond runs substantially along aninterface between said first and second dies, and wherein said die bond runs substantially parallel to said substrate. Using the present examples and illustrations, and not by way of limitation as the illustrations and examples are merely for conveying the invention, we can consider a relative configuration whereby the interface or die bonds are depicted as being horizontal and the 3DIC stacking taking place in vertically sandwiched layers above and / or below such an interface for the sake of convention. Those skilled in the art will understand of course that the reference to something being “horizontal” or “vertical” is a relative term and the actual fabrication or use of such devices can be equally accomplished in any other relative orientation and frame of reference.

[0147] Such 3DIC stacks and systems formed thereby can comprise more than one 3DIC stack configured and arranged in a larger or compound computing environment, machine, or structure. For example, a second stack can be disposed laterally beside a first stack on a common substrate thereby forming a computing volume comprising a plurality of dies in both a vertically stacked as well as a laterally disposed configuration.

[0148] While the examples herein generally illustrate and describe the 3DIC arrangements as comprising vertically stacked dies disposed above and below one another in a vertical dimension and / or laterally beside one another, it is understood that this is merely for the sake of illustration and discussion. Those skilled in the art will understand that these illustrations can be turned upside down or sideways or in any other physical orientation, therefore the use of terms such as vertical, above, beside and horizontal are herein merely descriptive and are relative terms that do not limit the actual construction and arrangement of systems based on this disclosure.

[0001] FIG. 14 is a cross section of a semiconductor structure 2400 according to an embodiment. The semiconductor structure 2400 includes an SoC 2460, a memory module 2410, and an optical engine 2420. The SoC 2460 includes a face or front side (in general, front side) 2401 and a back side 2402. The memory module 2410 includes a face or front side (in general, front side) 2411 and a back side 2412. The optical engine 2420 includes a face or front side (in general, front side) 2421 and a back side 2422. The front sides 2401, 2411, 2421 are represented with a first hash pattern, and the back sides 2402, 2412, 2422 are represented with a second hash pattern.

[0002] The front side 2401 of the SoC 2460 may be directly electrically connected to the back side 2412 of the memory module 2410. The electrical connection between the front side 2401of the SoC 2460 and the back side 2412 of the memory module 2410 includes or consists of micro bumps 2430 (e.g., a first set of micro bumps). Other electrical connections, such as hybrid bonds, solder bumps, controlled collapse chip connection (C4) bumps, and / or wire bonds, can be used in other embodiments.[0003| The front side 2411 of the memory module 2410 may be directly electrically connected to the back side 2422 of the optical engine 2420. The electrical connection between the front side 2411 of the memory module 2410 and the back side 2422 of the optical engine 2420 may include or consist of micro bumps 2430 (e.g., a second set of micro bumps). Other electrical connections, such as hybrid bonds, solder bumps, controlled collapse chip connection (C4) bumps, and / or wire bonds, can be used in other embodiments.[0004| The front side 2401 of the SoC 2460 and / or the back side 2412 of the memory module 2410 can include respective first and second redistribution layers 2441, 2442. The first and second redistribution layers 2441, 2442 are optional layers that include conductive wiring to align the electrical connections at the front side 2401 of the SoC 2460 to the respective electrical connections at the back side 2412 of the memory module 2410. Additionally or alternatively, the front side 2411 of the memory module 2410 and / or the back side 2422 of the optical engine 2420 can include respective third and fourth redistribution layers 2443, 2444. The third and fourth redistribution layers 2441, 2442 are optional layers that include conductive wiring to align the electrical connections at the front side 2411 of the memory module 2410 to the respective electrical connections at the back side 2422 of the optical engine 2420. In some embodiments, the back side 2402 of the SoC 2460 can include a redistribution layer for example to align the electrical connections at the back side 2402 of the SoC 2460 to another device and / or to a printed circuit board (PCB).[0005| Any and all combinations of the first, second, third, and / or fourth redistribution layers 2441-2444 are possible. Each redistribution layer can be included or excluded independently of the other redistribution layers.

[0006] The SoC 2460 can include one or more central processing units (CPUs), graphics processing units (GPU), auxiliary processing units (XPU), application-specific integrated circuits (ASICs), communications circuits (e.g., a cellular network radio modem, a Bluetooth radio modem, and / or a Wi-Fi radio modem), field-programmable gate arrays (FPGAs), readonly memory (ROM) integrated circuits, random-access memory (RAM) integrated circuits,digital signal processors (DSPs), switches, input / output (I / O) devices and / or interfaces, secondary storage interfaces, and / or other components.

[0007] The memory module 2410 can include or consist of RAM integrated circuits, such as dynamic RAM (DRAM), static RAM (SRAM), flash memory, and / or high-bandwidth memory. In an embodiment, the memory module 2410 includes or consists of a DRAM memory module. In another embodiment, the memory module 2410 includes or consists of an SRAM memory module. In another embodiment, the memory module 2410 includes or consists of a flash memory module. The memory module 2410 can include multiple memory modules and / or multiple memory integrated circuits. Additionally or alternatively, additional memory modules can be electrically connected to the SoC 2460 and to the optical engine 2420 in the same manner as memory module 2410. Each memory module can be the same or different than memory module 2410. A memory module may include a dynamic random access memory (DRAM) module, a static random access memory (SRAM) module, a flash memory module, a solid-state drive (SSD), a non-volatile random access memory (NVRAM) module, a read-only memory (ROM) module (such as a floating-gate ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), one-time programmable ROM (OTPROM), or the like), or any suitable type of memory module.

[0008] The optical engine 2420 includes an electrical integrated circuit (EIC) 2424, a photonic integrated circuit (PIC) 2426, and / or other components. The EIC 2424 and PIC 2426 can be disposed on separate chips or substrates. Alternatives, the EIC 2424 and PIC 2426 can be disposed on the same chip or substrate. The PIC 2426 is configured to transmit and receive optical signals to / from one or more optical fibers 2450 that can be optically coupled to the front side 2421 of the optical engine 2420. For example, the optical fiber(s) can be optically coupled to the PIC 2426. The EIC 2424 is configured to convert the received optical signals to electrical signals and to convert outgoing electrical signals to optical signals. In some embodiments, additional optical engines can be electrically connected to the front side 2411 of the memory module 2410 in the same manner as optical engine 2420. An example of an optical engine is disclosed in Provisional Application No. 63 / 123,476, titled “Compute Express Link Switch With Integrated Optical Engine,” filed on October 31, 2023, which is hereby incorporated by reference in its entirety.

[0009] The optical engine may be configured to convert electrical signals to optical signals and vice versa. Representations of the converted electrical signals and / or their digital equivalentscan be stored in the memory module 2410 and / or in memory integrated circuits in the SoC 2460. In addition, representations of the optical signals to be transmitted and / or their digital equivalents can be stored in the memory module 2410 and / or in memory integrated circuits in the SoC 2460. The SoC 2460 can process the converted electrical signals and / or their digital equivalents.[00101 In some embodiments, other electrical components can be electrically connected to the front side 2401 of the SoC 2460 and / or to the front side 2411 of the memory module 2410 in the same or similar manner as the memory module 2410 and the optical engine 2420, respectively. In addition or in the alternative, additional SoCs can be electrically coupled to the memory module 2410 in the same manner as SoC 2460.[00111 The semiconductor structure 2400 can be represented as a 3 -layer structure in which the SoC 2460 is on the first layer, the memory module 2410 is on the second layer, and the optical engine 2420 is on the third layer.10012 ] Directly electrically connected means that the electrical connections are made without using an intermediate structure such as an interposer. For example, a direct electrical connection is made through any layers and elements disposed on the front and / or back sides of the SoC 2460, the memory module 2410, and / or the optical engine 2420, such as conductive leads and / or redistribution layers.

[0013] FIG. 15 is a cross section of a semiconductor structure 2500 according to another embodiment. Semiconductor structure 2500 may be the same as semiconductor structure 2400 except that in semiconductor structure 2500 the SoC 2460 is between the optical engine 2420 and the memory module 2410. Thus, in semiconductor structure 2500 the front side 2401 of the SoC 2460 is directly electrically connected to the back side 2422 of the optical engine 2420. The electrical connection between the front side 2401 of the SoC 2460 and the back side 2422 of the optical engine 2420 includes or consists of micro bumps 2430 (e.g., a first set of micro bumps). Other electrical connections, such as hybrid bonds can be used in other embodiments.

[0014] The front side 2411 of the memory module 2410 may be directly electrically connected to the back side 2402 of the SoC 2460. The electrical connection between the front side 2411 of the memory module 2410 and the back side 2402 of the SoC 2460 may include or consist of micro bumps 2430 (e.g., a second set of micro bumps). Other electrical connections, such as hybrid bonds, solder bumps, controlled collapse chip connection (C4) bumps, and / or wire bonds, can be used in other embodiments. Additional memory modules and / or additionaloptical engines can be electrically connected to respective sides of the SoC 2460 in the same or similar manner as the memory module 2410 and the optical engine 2420, respectively. In some embodiments, other electrical components can be electrically coupled to either or both sides of the SoC 2460 in the same or similar manner as the memory module 2410 and the optical engine 2420, respectively. In addition or in the alternative, additional SoCs can be electrically coupled to the memory module 2410 in the same manner as SoC 2460.[00.15] The back side 2412 of the memory module 2410 does not include the optional second redistribution layer 2442 in semiconductor structure 2500. Instead, the back side 2402 of the SoC 2460 includes an optional redistribution layer 2442 that includes conductive wiring to align the electrical connections at the back side 2402 of the SoC 2460 to the respective electrical connections at the front side 2411 of the memory module 2410. Any and all combinations of the redistribution layers 2441, 2443, 2444, 2442 are possible. Each redistribution layer can be included or excluded independently of the other redistribution layers. In some embodiments, the back side 2412 of the memory module 2410 can include a redistribution layer for example to align the electrical connections at the back side 2412 of the memory module 2410 to another device and / or to a PCB.[00.16] FIG. 16 is a cross section of a semiconductor structure 2600 according to another embodiment. Semiconductor structure 2600 may be analogous to or the same as semiconductor structure 2500 except that in semiconductor structure 2600 the optical engine 2420 and the SoC 2460 are electrically connected to the memory module 2410. Thus, in semiconductor structure 2600 the front side 2411 of the memory module 2410 is directly electrically connected to the back side 2422 of the optical engine 2420 and to the back side 2402 of the SoC 2460. The electrical connection between the front side 2401 of the SoC 2460 and the back side 2422 of the optical engine 2420 and the back side 2402 of the SoC 2460 includes or consists of micro bumps 2430 (e.g., first and second set of micro bumps). Other electrical connections, such as hybrid bonds can be used in other embodiments.[00.17] Additional memory modules and / or additional SoCs can be electrically connected to front side 2411 of the memory module 2410 in the same or similar manner as the memory module 2410 and the SoC 2460, respectively. Additionally or alternatively, the back side 2422 of the optical engine 2420 can be electrically connected to the front side of two or more memory modules, including but not limited to the front side 2411 of memory module 2410. Additionally or alternatively, the back side 2402 of the SoC 2460 can be electrically connected to the front side of two or more memory modules, including but not limited.

[0018] The front side 2401 of the SoC 2460 does not include the optional first redistribution layer 2441 as in semiconductor structures 2400, 2500. The back side 2402 of the SoC 2460 includes the optional redistribution layer 2442 as in semiconductor structure 2500. Any and all combinations of the redistribution layers 2443, 2444, 2442 are possible. Each redistribution layer can be included or excluded independently of the other redistribution layers. In some embodiments, the front side 2401 of the SoC 2460 and / or the back side 2412 of the memory module 2410 can include a respective redistribution layer for example to align the electrical connections at the front side 2401 of the SoC 2460 and / or at the back side 2412 of the memory module 2410 to another respective device and / or to a PCB.(0019] The semiconductor structure 2600 can be represented as a 2-layer structure in which the memory module 2410 is on the first layer and the SoC 2460 and the optical engine 2420 are on the second layer.

[0020] FIG. 17 is a cross section of a semiconductor structure 2700 according to another embodiment. Semiconductor structure 2700 may be analogous to or the same as semiconductor structure 2400 except that in semiconductor structure 2700 the optical engine 2420 and the memory module 2410 are electrically connected to the SoC 2460. Thus, in semiconductor structure 2700 the front side 2401 of the SoC 2460 is directly electrically connected to the back side 2422 of the optical engine 2420 and to the back side 2412 of the memory module 2410. The electrical connection between the front side 2401 of the SoC 2460 and the back side 2422 of the optical engine 2420 and the back side 2412 of the memory module 2410 includes or consists of micro bumps 2430 (e.g., a first set of micro bumps). Other electrical connections, such as hybrid bonds can be used in other embodiments.

[0021] The front side 2411 of the memory module 2410 does not include the optional third redistribution layer 2443 as in semiconductor structures 2400, 2500, 2600. Any and all combinations of the redistribution layers 2441, 2442, 2444 are possible. Each redistribution layer can be included or excluded independently of the other redistribution layers. In some embodiments, the back side 2402 of the SoC 2460 and / or the front side 2411 of the memory module 2410 can include a respective redistribution layer for example to align the electrical connections at the back side 2402 of the SoC 2460 and / or at the front side 2411 of the memory module 2410 to another respective device and / or to a PCB.

[0022] In some embodiments, the back side 2402 of the SoC 2460 can include a redistribution layer for example to align the electrical connections at the back side 2402 of the SoC 2460 to another device and / or to a PCB.

[0023] The semiconductor structure 2700 can be represented as a 2-layer structure in which the SoC 2460 is on the first layer and the memory module 2410 and the optical engine 2420 are on the second layer.

[0024] FIG. 18 is a cross section of a semiconductor structure 2800 according to another embodiment. Semiconductor structure 2800 may be analogous to or the same as semiconductor structure 2400 except that in semiconductor structure 2800 the electrical connections are formed by hybrid bonds 500 instead of micro bumps.

[0025] It is noted that hybrid bonds can be used to form the electrical connections between first and second of the components in semiconductor structure 2800 and micro bumps can be used to form the electrical connections between second and third of the components in semiconductor structure 2800. For example, hybrid bonds can be used to form the electrical connections between the optical engine 2420 and the memory module 2410 and micro bumps can be used to form the electrical connections between the memory module 2410 and the SoC 2460. In another example, micro bumps can be used to form the electrical connections between the optical engine 2420 and the memory module 2410 and hybrid bonds can be used to form the electrical connections between the memory module 2410 and the SoC 2460.

[0026] FIG. 19 is a cross section of a semiconductor structure 2900 according to another embodiment. Semiconductor structure 2900 may be analogous to or the same as semiconductor structure 2500 except that in semiconductor structure 2900 the electrical connections are formed by hybrid bonds 500 instead of micro bumps.

[0027] It is noted that hybrid bonds can be used to form the electrical connections between first and second of the components in semiconductor structure 2900 and micro bumps can be used to form the electrical connections between second and third of the components in semiconductor structure 2900. For example, hybrid bonds can be used to form the electrical connections between the optical engine 2420 and the SoC 2460 and micro bumps can be used to form the electrical connections between the SoC 2460 and the memory module 2410. In another example, micro bumps can be used to form the electrical connections between the optical engine 2420 and the SoC 2460 and hybrid bonds can be used to form the electrical connections between the SoC 2460 and the memory module 2410.[0028J FIG. 20 is a cross section of a semiconductor structure 3000 according to another embodiment. Semiconductor structure 3000 may be analogous to or the same as semiconductor structure 2600 except that in semiconductor structure 3000 the electrical connections are formed by hybrid bonds 500 instead of micro bumps.

[0029] It is noted that hybrid bonds can be used to form the electrical connections between first and second of the components in semiconductor structure 3000 and micro bumps can be used to form the electrical connections between second and third of the components in semiconductor structure 3000. For example, hybrid bonds can be used to form the electrical connections between the optical engine 2420 and the memory module 2410 and micro bumps can be used to form the electrical connections between the SoC 2460 and the memory module 2410. In another example, micro bumps can be used to form the electrical connections between the optical engine 2420 and the memory module 2410 and hybrid bonds can be used to form the electrical connections between the SoC 2460 and the memory module 2410.

[0030] FIG. 21 is a cross section of a semiconductor structure 3100 according to another embodiment. Semiconductor structure 3100 may be analogous to or the same as semiconductor structure 2700 except that in semiconductor structure 3100 the electrical connections are formed by hybrid bonds 500 instead of micro bumps.

[0149] It is noted that hybrid bonds can be used to form the electrical connections between first and second of the components in semiconductor structure 3100 and micro bumps can be used to form the electrical connections between second and third of the components in semiconductor structure 3100. For example, hybrid bonds can be used to form the electrical connections between the optical engine 2420 and the SoC 2460 and micro bumps can be used to form the electrical connections between the memory module 2410 and the SoC 2460. In another example, micro bumps can be used to form the electrical connections between the optical engine 2420 and the SoC 2460 and hybrid bonds can be used to form the electrical connections between the memory module 2410 and the SoC 2460.

[0150] Immersion cooling systems may provide particular advantage to 3DIC stacks due to the lower surface area to volume ratio of a 3DIC stack compared to the individual components of the 3DIC stack (e.g., a bonded logic IC and memory module will have a lower surface area to volume ratio than the combined surface area to volume ratio of the physically separated logic IC and memory module) as well as the additional heat generated by state of the art logic ICs. This lower surface area to volume ratio means waste heat generated by the 3DIC stack may notbe as efficiently dissipated and may require better cooling performance than air cooling can provide. Two-phase immersion cooling in particular can provide this additional heat removal required by 3DIC stacks.

[0151] FIG. 22 depicts aspects of an immersion cooling system 3200 for dissipating heat from one or more heat-generating components such as semiconductor die packages 3205 via immersion cooling. Each package 3205 can include one or more semiconductor dies that produce heat when the system is in operation. The immersion cooling system 3200 in the illustrated example of FIG. 22 is a two-phase immersion cooling system, though the invention may also be implemented in a single-phase immersion cooling system.

[0152] One or more semiconductor die packages 3205 may be 3DIC stacks in accordance with the present technology. For example, one or more semiconductor die packages 3205 may include a logic IC and at least one memory module bonded to the logic IC using a hybrid bond or micro-bump bond.

[0153] Immersion cooling system 3200 includes a container such as tank 3220 filled, at least in part, with immersion cooling liquid 3264. The immersion cooling system 3200 can further include at least one chiller 3280 that flows a heat-transfer fluid through at least one condenser tube 3270 that is disposed in the tank 3220 and headspace 3208. Condenser tubes 3270 and chiller 3280 may be part of a heat exchanger. The packages 3205 can be mounted on one or more printed circuit boards (PCBs) 3257 that are immersed, at least in part, in the immersion cooling liquid 3264. Immersion-cooling system 3200 may further include a filter 3275 disposed adjacent to the tank 3220.

[0154] Filter 3275 may include a filtration media, a housing, and a pump configured to force immersion cooling liquid 3264 through filter 3275 to remove contaminants, particulates, or other impurities that may be added to immersion cooling liquid 3264 during use. Filter 3275 may be housed outside of tank 3220 while being in fluidic communication with immersion cooling liquid 3264 in tank 3220. Alternatively, filter 3275 may be submerged within immersion cooling liquid 3264 inside of tank 3220.

[0155] Immersion cooling liquid 3264 may be a hydrocarbon, a fluoroketone, an oil, or a similar dielectric liquid that will act as an insulator while simultaneously transferring heat from package 3205 more efficiently than air. Examples of immersion cooling liquid 3264 are Novec™ 649, Novec™ 7000, and Novec™ 7100 produced by 3M™. An exemplary immersion cooling liquid 3264 used in accordance with embodiments of the present invention may have a dielectric constant baseline value of about 1.8-2 at a frequency of about 1 kHz.

[0156] In an embodiment of the invention, immersion cooling liquid 3264 may be considered unacceptably contaminated if the dielectric constant and / or dielectric loss tangent of immersion cooling fluid being used in an immersion cooling system 3200 differs by a threshold amount as compared to unused or pure immersion cooling liquid 3264. For example, immersion cooling liquid 3264 may be considered unacceptably contaminated or degraded if the dielectric constant and / or dielectric loss tangent differs by a threshold of 10% or more as compared to unused or pure immersion cooling liquid 3264. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be 20%, 15%, 5%, 3%, 1%, or any suitable threshold.

[0157] Contamination of the immersion cooling liquid 3264 and resulting changes to dielectric constant and / or dielectric loss tangent may alter or negatively impact operation of components within immersion cooling liquid 3264 including semiconductor die(s) 3250. An altered dielectric constant and / or dielectric loss tangent may result in undesirable cross-talk between components on a PCB, additional noise or reduction in signal strength transmitted along exposed wires of a PCB or semiconductor die(s) 3250 submerged in immersion fluid, and / or signal dissipation through the immersion cooling liquid 3264. Signal loss may be severe enough that two elements may be effectively represented as being separated by an open circuit despite being physically connected. In an embodiment, a dielectric constant and / or dielectric loss tangent variation threshold may be selected based on an observed or inferred effect on one or more submerged semiconductor die(s) 3250. For example, an increase in PCIe bit error rate above an error rate baseline may be correlated with an increase in dielectric constant and / or dielectric loss tangent above a dielectric constant and / or dielectric loss tangent baseline. Accordingly, operation of semiconductor die(s) 3250 may be throttled or suspended when a dielectric constant and / or dielectric loss tangent of immersion cooling liquid 3264 exceeds a predetermined threshold.

[0158] Changes to dielectric constant and / or dielectric loss tangent may be caused by contaminants within immersion cooling liquid 3264. In some cases, changes to dielectric constant and / or dielectric loss tangent may be reversed by filtering the contaminants from immersion cooling liquid 3264. In some embodiments, upon detecting an increase in dielectric constant and / or dielectric loss tangent of immersion cooling liquid 3264, controller 3202 may instruct filter 3275 to increase filtration throughput or notify a user that an immersion cooling liquid 3264 filtration media may need to be replaced. If a dielectric constant and / or dielectric loss tangent exceeds a predetermined threshold, controller 3202 may throttle or shut down oneor more semiconductor die(s) 3250, generate a notification that immersion cooling liquid 3264 should be replaced, trigger an alarm, etc.

[0159] Further examples of sensors and methods for immersion cooling contamination monitoring may include probes for monitoring immersion cooling liquid parameters such as dielectric constant and dielectric loss tangent, and processors configured to identify trends in sensor data, model immersion cooling system behavior as a function of contamination, and alter operations of immersion cooling systems based on detected levels and / or states of contamination may be found in U.S. Provisional Patent Application 63 / 516,748, filed July 31, 2023 and entitled “Di-Electric Monitoring of Immersion Fluid During Cooling Operation,” the entirety of which is incorporated herein by reference.

[0160] The illustrated example of FIG. 22 is not intended to be to scale. The immersion cooling system 3200 may house and provide immersion cooling liquid 3264 to tens, hundreds, or even thousands of packages 3205. In some cases, the immersion cooling system 3200 can be small (e.g., the size of a floor unit air conditioner, approximately 1 meter high, 0.5 meter width, 0.5 meter depth or length). In some implementations, the immersion cooling system can be large (e.g., the size of a van or larger, approximately 2.5 meters high, 2.5 meters width, 4 meters depth or length).

[0161] The immersion cooling system 3200 can also include a controller 3202 (e.g., a microcontroller, programmable logic controller (PLC), microprocessor, field-programmable gate array, logic circuitry, memory, or some combination thereof) to manage system operation. Controller 3202 can perform various system functions such as monitoring temperatures of system components, cooling fluid level, tank access, chiller operation etc. The controller 3202 can further issue commands to control system operation such as executing a start-up sequence, executing a shut-down sequence, assigning workloads among the packages, changing cooling fluid level, changing the temperature of the heat-transfer fluid circulated by the chiller 3280, etc. In some implementations, controller 3202 can include (or itself be) a baseboard management controller (BMC) 3204. That is, the BMC 3204 may monitor and control all aspects of system operation for the immersion cooling system 3200 in addition to monitoring and controlling workloads of the semiconductor dies 3250 in the packages 3205 cooled by the system. The immersion cooling system 3200 can also include a network interface controller (NIC 3203) to allow the system to communicate over a network, such as a local area network or wide area network. The immersion cooling system 3200 can further include a fluid sensorarray 3290 having a plurality of fluid sensors 3210. Fluid sensors 3210 may include one or more leak detection sensors at least partially submerged in immersion cooling liquid 3264.

[0162] The semiconductor die(s) 3250 and can be mounted on and attached to a printed circuit board (PCB) 3255 (sometimes referred to as a substrate) in device package 3205. The package 3205 can be made commercially available as an off-the-shelf (OTS) product. The package 3205 can be used for single-phase or two-phase immersion cooling of at least one semiconductor die 3250, such as a microprocessor (e.g., a central processing unit (CPU) and / or graphics processing unit (GPU)), voltage regulator (VR), high bandwidth memory (HBM), a digital signal processing (DSP) die, an artificial intelligence (Al) accelerator, an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), and / or other densely patterned semiconductor die.

[0163] In the two-phase immersion cooling system 3200 of FIG. 22, heat flows from the semiconductor die 3250 where it is generated into the heat spreader 3252. The heat spreader 3252 is in thermal contact with an immersion cooling liquid 3264 that can flow over and extract heat from the heat spreader 3252. The amount of heat delivered by the heat spreader 3252 to the immersion cooling liquid 3264 is enough to boil the immersion cooling liquid 3264 that contacts the heat spreader 3252 (creating bubbles 3265 and potentially creating froth 3267 when bubbles 3265 reach the surface of immersion cooling liquid 3264). The vapor 3266 from the boiled immersion cooling liquid 3264 can be cooled and condensed back to liquid droplets 3268, for example, by the condenser tube 3270. The heat-transfer fluid, such as chilled water, from the chiller 3280 can be circulated through the condenser tube 3270 to lower the temperature of the condenser tube 3270 below the condensation point in the headspace 3208 of the tank 3220. As a result, vapor 3266 condenses on exterior surfaces of the condenser tube 3270 and liquid droplets 3268 from the condensed vapor can drip and / or flow back to the immersion cooling liquid 3264. There may be a plurality of condenser tubes 3270 in tank 3220 to condense the vapor 3266 into droplets. Some or all of the condenser tubes 3270 may or may not be located directly over the PCBs 3257. Instead, the condenser tube(s) 3270 can be located near one or more walls of the tank 3220, such that the condenser tube(s) 3270 are not directly over the PCBs 3257 on which the packages 3205 are mounted.

[0164] To improve thermal performance in two-phase immersion cooling system 3200, the heat spreader 3252 can include a boiling enhancement coating (BEC) on at least one surface. The BEC can be formed from copper or a copper alloy and can be porous, for example, though BECs can take various forms. In some cases, the BEC is a micro porous copper coating havinga thickness from approximately or exactly 50 microns to 500 microns thick (which may be produced by electroplating and / or etching). In some implementations, the BEC comprises a mesh copper layer bonded (e.g., via resistance heating) to at least an outer surface of the heat spreader 3252. In some cases, the BEC is applied as particulates to at least one smooth surface of the heat spreader 3252 and then subsequently sintered to adhere to one another and to the heat spreader 3252. The BEC provides an improved surface area to contact the immersion cooling liquid 3264 and can increase the heat transfer coefficient from the heat spreader 3252 to the immersion cooling liquid 3264 by up to a factor of 15 versus a smooth surface on the heat spreader 3252. Accordingly, BECs can increase thermal conductivity to, and accelerate the boiling of, the immersion cooling liquid 3264.

[0165] Further implementations of boiling enhancement coatings and enclosures are possible. Additional arrangements, applications, and methods of use of boiling enhancement coatings and enclosures, including with semiconductor dies and 3DIC stacks, are described in the below U.S. Patent Applications.

[0166] U.S. Patent Application No. 18 / 327,615, filed June 1, 2023 and entitled "Boiler Enhancement Coatings with Active Boiling Management,” discloses heat spreader and boiling enhancement enclosure architectures thermally and / or mechanically coupled to one or more semiconductor dies or logic ICs that may be used for passive and / or active management of immersion cooling fluid boiling, including through the use of valves to control pressure of boiling immersion cooling fluid within a boiling enhancement chamber, particularly in paragraphs

[0018] -

[0039] and FIGS. 3-5B. The entirety of U.S. Patent Application No. 18 / 327,615 is incorporated herein by reference.

[0167] U.S. Provisional Patent Application No. 63 / 500,167, filed May 4, 2023 and entitled “Direct to Chip Heat Spreader and Boiler Enhancement Coatings for Microelectronics,” discloses heat spreader and BECs thermally and / or mechanically coupled to one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0015] -

[0033] and FIGS. 2A-4. BEC form factors may include graphite heat spreader architectures, vapor chambers, heat pipes, copper plates, fins, and the like. BEC form factors may be thermally and / or mechanically coupled to the one or more semiconductor dies, logic ICs, and / or 3DIC stacks through a thermally conductive epoxy, and may have varying dimensions relative to a surface to which the semiconductor dies and / or logic ICs are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 500,167 is incorporated herein by reference.

[0168] U.S. Patent Application No. 18 / 460,091, filed September 1, 2023 and entitled “Direct to Chip Application of Boiling Enhancement Coating,” discloses BECs and methods for applying BECs to semiconductor dies, logic ICs, and / or 3DIC stacks in accordance with the present technology. In particular, paragraphs

[0024] -

[0046] and FIGS. 2A-5 disclose embodiments of BEC layers, adhesives, solders, sintering, laser ablation, meshes, and other BECs and BEC application methods. The entirety of U.S. Patent Application No. 18 / 460,091 is incorporated herein by reference.

[0169] U.S. Provisional Patent Application No. 63 / 506,945, filed June 8, 2023 and entitled “Vapor- Shedding Structures for Boiler Plates in Two-Phase Immersion Cooling Systems,” discloses structures that may be thermally and / or mechanically coupled to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks to enable the shedding of immersion cooling vapors generated from the boiling of immersion cooling fluid during operation of the computing hardware. In particular, paragraphs

[0021] -

[0039] and FIGS. 3A-5 disclose vapor-shedding structures including varying porosities, constituent materials, and geometries relative to the computing hardware on which they are mounted. The entirety of U.S. Provisional Patent Application No. 63 / 506,945 is incorporated herein by reference.

[0170] U.S. Provisional Application No. 63 / 513,828, filed July 14, 2023 and entitled “Grinding Apparatuses and Methods for Mechanically Modifying Surfaces of Processors to Promote Boiling of a Coolant Liquid,” discloses methods for creating boiling enhancement modifications to surfaces such as the surfaces of computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks, particularly in paragraphs

[0036] -

[0095] and FIGS. 2A-8. For example, grooves, patterns, gouges, trenches, or other structures may be added to a surface or lid of a processor, semiconductor die, logic IC, 3DIC stack component, and / or BEC to encourage nucleation sites for bubbles of immersion cooling vapor to form during a cooling process, thus decreasing the thermal resistance between the processor, semiconductor die, logic IC, and / or 3DIC stack component and the surrounding immersion cooling fluid. The entirety of U.S. Provisional Application No. 63 / 513,828 is incorporated herein by reference.

[0171] U.S. Provisional Patent Application No. 63 / 513,829, filed July 14, 2023 and entitled “Electrical Connector Having a Heater to Facilitate Boiling of a Coolant Liquid to Improve Signal Integrity in Immersion Cooling Environment,” discloses heaters for promoting boiling of immersion cooling fluid near electrical connectors such as connections between components of a 3DIC stack and enable improved impedances at those connectors, particularly inparagraphs

[0019] -

[0052] and FIGS. 1A-3B. The entirety of U.S. Provisional Patent Application No. 63 / 513,829 is incorporated herein by reference.

[0172] U.S. Provisional Patent Application No. 63 / 603,242, filed November 28, 2023 and entitled “Woven Boiler Enhancement Coatings,” provides additional examples of BECs including woven BECs with variable weave patterns, densities, attachment mechanisms, and materials (including copper and tungsten) that may be attached to computing hardware such as one or more semiconductor dies, logic ICs, and / or 3DIC stacks in order to promote more efficient heat transfer and immersion cooling vapor nucleation, particularly in paragraphs [003 l]-

[0055] and FIGS. 3-7. The entirety of U.S. Provisional Patent Application No. 63 / 603,242 is incorporated herein by reference.

[0173] Clause 1. A system for co-locating memory and computational logic, the system comprising: a memory module comprising a memory face side and a memory back side; a logic integrated circuit (IC) configured to perform computations, the logic IC comprising a logic IC face side and a logic IC back side; and a first plurality of connections that communicatively couples the logic IC to the memory module; wherein the memory module is mechanically coupled to the logic IC through the first plurality of connections.

[0174] Clause 2. The system of clause 1, wherein the memory face side is communicatively and mechanically coupled to the logic IC face side.

[0175] Clause 3. The system of clause 1, wherein the memory face side is communicatively and mechanically coupled to the logic IC back side.

[0176] Clause 4. The system of clause 1, wherein the memory back side is communicatively and mechanically coupled to the logic IC face side.

[0177] Clause 5. The system of clause 1, further comprising: one or more high-bandwidth memory (HBM) modules; an interposer communicatively coupled to the one or more HBM modules; and a second plurality of connections that communicatively couples the one or more HBM modules, the logic IC, and the interposer.

[0178] Clause 6. The system of any one of clauses 1-4, wherein the first plurality of connections comprises at least one of hybrid bonds or micro-bumps.

[0179] Clause 7. The system of clause 5, wherein the first connections and the second connections comprises at least one of hybrid bonds or micro-bumps.

[0180] Clause 8. The system of clause 1, wherein: the logic IC face side comprises a logic IC redistribution layer (RDL), the logic IC RDL comprising: a first side exposing a plurality of logic IC traces in a first pattern matching the logic IC face side; and a second side exposing the plurality of logic IC traces in a second pattern matching a plurality of memory traces exposed on the memory module; and the logic IC RDL is communicatively and mechanically coupled to the memory face side.

[0181] Clause 9. The system of clause 1, wherein: the memory module face side comprises a memory redistribution layer (RDL), the memory RDL comprising: a first side exposing a plurality of memory module traces in a first pattern matching the memory module face side; and a second side exposing the plurality of memory module traces in a second pattern matching a plurality of logic IC traces exposed on the logic IC; and the memory RDL is communicatively and mechanically coupled to the logic IC face side.

[0182] Clause 10. A system for co-locating memory and computational logic, the system comprising: a memory module comprising a memory face side, a memory back side, and a memory redistribution layer (RDL) disposed on the memory face side; and a logic integrated circuit (IC) configured to perform computations, the logic IC comprising a logic IC face side, a logic IC back side, and a logic IC RDL disposed on the logic IC face side; wherein the memory module is communicatively and mechanically coupled to the logic IC through a plurality of connections between the memory RDL and the logic IC RDL.

[0183] Clause 11. The system of clause 10, wherein: the memory RDL reroutes a plurality of memory traces from a first pattern at the memory face side to a second pattern matching a plurality of logic IC traces exposed by the logic IC RDL; and the logic IC RDL reroutes the plurality of logic IC traces from the second pattern to a third pattern matching the plurality of logic IC traces exposed by the logic IC face side.

[0184] Clause 12. The system of either of clauses 10 or 11, wherein the plurality of connections comprises a plurality of hybrid bonds.

[0185] Clause 13. The system of either of clauses 10 or 11, wherein the plurality of connections comprises a plurality of micro-bumps.

[0186] Clause 14. The system of either of clauses 10 or 11, wherein the plurality of connections comprises a combination of one or more hybrid bonds and one or more microbumps.

[0187] Clause 15. A semiconductor structure comprising: a system-on-a-chip (SoC) having a front side and a back side; a memory module having a front side and a back side, the back side of the memory module being directly electrically connected to the front side of the SoC; and an optical engine having a front side and a back side, the back side of the optical engine being directly electrically connected to the front side of the memory module.

[0188] Clause 16. The semiconductor structure of clause 15, further comprising: a first set of micro bumps that directly electrically connect the back side of the memory module to the front side of the SoC; and a second set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0189] Clause 17. The semiconductor structure of clause 15, further comprising: a first set of hybrid bonds that directly electrically connect the back side of the memory module to the front side of the SoC; and a second set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0190] Clause 18. The semiconductor structure of clause 15, further comprising: a set of micro bumps that directly electrically connect the back side of the memory module to the front side of the SoC; and a set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0191] Clause 19. The semiconductor structure of clause 15, further comprising: a set of hybrid bonds that directly electrically connect the back side of the memory module to the front side of the SoC; and a set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0192] Clause 20. The semiconductor structure of any of clauses 15-19 wherein the optical engine includes an electrical integrated circuit (EIC) and a photonic integrated circuit (PIC).

[0193] Clause 21. The semiconductor structure of clause 20 wherein the EIC and the PIC are disposed on a common chip.

[0194] Clause 22. The semiconductor structure of clause 20 wherein the EIC and the PIC are disposed on separate chips.

[0195] Clause 23. The semiconductor structure of any of clauses 15-22 further comprising a redistribution layer on the back side of the memory module, the front side of the SoC, the back side of the optical engine, or the front side of the memory module.

[0196] Clause 24. The semiconductor structure of any of clauses 15-22 further comprising a plurality of redistribution layers, each redistribution layer on the back side of the memory module, the front side of the SoC, the back side of the optical engine, or the front side of the memory module.

[0197] Clause 25. The semiconductor structure of any of clauses 15-24 wherein the memory module comprises random access memory (RAM) integrated circuits.

[0198] Clause 26. The semiconductor structure of clause 25, wherein at least a portion of the RAM integrated circuits are dynamic RAM (DRAM) integrated circuits.

[0199] Clause 27. A semiconductor structure comprising: a memory module having a front side and a back side; a system-on-a-chip (SoC) having a front side and a back side, the back side of the SoC being directly electrically connected to the front side of the memory module; and an optical engine having a front side and a back side, the back side of the optical engine being directly electrically connected to the front side of the SoC.

[0200] Clause 28. The semiconductor structure of clause 27, further comprising: a first set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the SoC.

[0201] Clause 29. The semiconductor structure of clause 27, further comprising: a first set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the SoC.

[0202] Clause 30. The semiconductor structure of clause 27, further comprising: a set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the SoC.

[0203] Clause 31. The semiconductor structure of clause 27, further comprising: a set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the SoC.

[0204] Clause 32. The semiconductor structure of any clauses 27-31 wherein the optical engine includes an electrical integrated circuit (EIC) and a photonic integrated circuit (PIC).

[0205] Clause 33. The semiconductor structure of clause 32 wherein the EIC and the PIC are disposed on a common chip.

[0206] Clause 34. The semiconductor structure of clause 32 wherein the EIC and the PIC are disposed on separate chips.

[0207] Clause 35. The semiconductor structure of any of clauses 27-34 further comprising a redistribution layer on the back side of the SoC, the front side of the memory module, the back side of the optical engine, or the front side of the SoC.

[0208] Clause 36. The semiconductor structure of any of clauses 27-34 further comprising a plurality of redistribution layers, each redistribution layer on the back side of the SoC, the front side of the memory module, the back side of the optical engine, or the front side of the SoC.

[0209] Clause 37. The semiconductor structure of any of clauses 27-36 wherein the memory module comprises random access memory (RAM) integrated circuits.

[0210] Clause 38. The semiconductor structure of clause 37, wherein at least a portion of the RAM integrated circuits are dynamic RAM (DRAM) integrated circuits.

[0211] Clause 39. A semiconductor structure comprising: a memory module having a front side and a back side; a system-on-a-chip (SoC) having a front side and a back side, the back side of the SoC being directly electrically connected to the front side of the memory module; and an optical engine having a front side and a back side, the back side of the optical engine being directly electrically connected to the front side of the memory module.

[0212] Clause 40. The semiconductor structure of clause 39, further comprising: a first set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0213] Clause 41. The semiconductor structure of clause 39, further comprising: a first set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0214] Clause 42. The semiconductor structure of clause 39, further comprising: a set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0215] Clause 43. The semiconductor structure of clause 39, further comprising: a set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

[0216] Clause 44. The semiconductor structure of any clauses 39-43 wherein the optical engine includes an electrical integrated circuit (EIC) and a photonic integrated circuit (PIC).

[0217] Clause 45. The semiconductor structure of clause 44 wherein the EIC and the PIC are disposed on a common chip.

[0218] Clause 46. The semiconductor structure of clause 44 wherein the EIC and the PIC are disposed on separate chips.

[0219] Clause 47. The semiconductor structure of any of clauses 39-46 further comprising a redistribution layer on the back side of the SoC, the front side of the memory module, or the back side of the optical engine.

[0220] Clause 48. The semiconductor structure of any of clauses 39-46 further comprising a plurality of redistribution layers, each redistribution layer on the back side of the SoC, the front side of the memory module, or the back side of the optical engine.Conclusion

[0221] While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the inventive teachings is / are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition,any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

[0222] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0223] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0224] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0225] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0226] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) whenpreceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.”“Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0227] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0228] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

CLAIMS1. A system for co-locating memory and computational logic, the system comprising: a memory module comprising a memory face side and a memory back side; a logic integrated circuit (IC) configured to perform computations, the logic IC comprising a logic IC face side and a logic IC back side; and a first plurality of connections that communicatively couples the logic IC to the memory module; wherein the memory module is mechanically coupled to the logic IC through the first plurality of connections.

2. The system of claim 1, wherein the memory face side is communicatively and mechanically coupled to the logic IC face side.

3. The system of claim 1, wherein the memory face side is communicatively and mechanically coupled to the logic IC back side.

4. The system of claim 1, wherein the memory back side is communicatively and mechanically coupled to the logic IC face side.

5. The system of claim 1, further comprising: one or more high-bandwidth memory (HBM) modules; an interposer communicatively coupled to the one or more HBM modules; and a second plurality of connections that communicatively couples the one or more HBM modules, the logic IC, and the interposer.

6. The system of any one of claims 1-4, wherein the first plurality of connections comprises at least one of hybrid bonds or micro-bumps.

7. The system of claim 5, wherein the first connections and the second connections comprises at least one of hybrid bonds or micro-bumps.

8. The system of claim 1, wherein: the logic IC face side comprises a logic IC redistribution layer (RDL), the logic IC RDL comprising:a first side exposing a plurality of logic IC traces in a first pattern matching the logic IC face side; and a second side exposing the plurality of logic IC traces in a second pattern matching a plurality of memory traces exposed on the memory module; and the logic IC RDL is communicatively and mechanically coupled to the memory face side.

9. The system of claim 1, wherein: the memory module face side comprises a memory redistribution layer (RDL), the memory RDL comprising: a first side exposing a plurality of memory module traces in a first pattern matching the memory module face side; and a second side exposing the plurality of memory module traces in a second pattern matching a plurality of logic IC traces exposed on the logic IC; and the memory RDL is communicatively and mechanically coupled to the logic IC face side.

10. A system for co-locating memory and computational logic, the system comprising: a memory module comprising a memory face side, a memory back side, and a memory redistribution layer (RDL) disposed on the memory face side; and a logic integrated circuit (IC) configured to perform computations, the logic IC comprising a logic IC face side, a logic IC back side, and a logic IC RDL disposed on the logic IC face side; wherein the memory module is communicatively and mechanically coupled to the logic IC through a plurality of connections between the memory RDL and the logic IC RDL.

11. The system of claim 10, wherein: the memory RDL reroutes a plurality of memory traces from a first pattern at the memory face side to a second pattern matching a plurality of logic IC traces exposed by the logic IC RDL; and the logic IC RDL reroutes the plurality of logic IC traces from the second pattern to a third pattern matching the plurality of logic IC traces exposed by the logic IC face side.

12. The system of either of claims 10 or 11, wherein the plurality of connections comprises a plurality of hybrid bonds.

13. The system of either of claims 10 or 11, wherein the plurality of connections comprises a plurality of micro-bumps.

14. The system of either of claims 10 or 11, wherein the plurality of connections comprises a combination of one or more hybrid bonds and one or more micro-bumps.

15. A semiconductor structure comprising: a system-on-a-chip (SoC) having a front side and a back side; a memory module having a front side and a back side, the back side of the memory module being directly electrically connected to the front side of the SoC; and an optical engine having a front side and a back side, the back side of the optical engine being directly electrically connected to the front side of the memory module.

16. The semiconductor structure of claim 15, further comprising: a first set of micro bumps that directly electrically connect the back side of the memory module to the front side of the SoC; and a second set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

17. The semiconductor structure of claim 15, further comprising: a first set of hybrid bonds that directly electrically connect the back side of the memory module to the front side of the SoC; and a second set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

18. The semiconductor structure of claim 15, further comprising: a set of micro bumps that directly electrically connect the back side of the memory module to the front side of the SoC; and a set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

19. The semiconductor structure of claim 15, further comprising: a set of hybrid bonds that directly electrically connect the back side of the memory module to the front side of the SoC; and a set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

20. The semiconductor structure of any of claims 15-19, wherein the optical engine includes an electrical integrated circuit (EIC) and a photonic integrated circuit (PIC).

21. The semiconductor structure of claim 20, wherein the EIC and the PIC are disposed on a common chip.

22. The semiconductor structure of claim 20, wherein the EIC and the PIC are disposed on separate chips.

23. The semiconductor structure of any of claims 15-22, further comprising a redistribution layer on the back side of the memory module, the front side of the SoC, the back side of the optical engine, or the front side of the memory module.

24. The semiconductor structure of any of claims 15-22, further comprising a plurality of redistribution layers, each redistribution layer on the back side of the memory module, the front side of the SoC, the back side of the optical engine, or the front side of the memory module.

25. The semiconductor structure of any of claims 15-24, wherein the memory module comprises random access memory (RAM) integrated circuits.

26. The semiconductor structure of claim 25, wherein at least a portion of the RAM integrated circuits are dynamic RAM (DRAM) integrated circuits.

27. A semiconductor structure comprising: a memory module having a front side and a back side; a system-on-a-chip (SoC) having a front side and a back side, the back side of the SoC being directly electrically connected to the front side of the memory module; andan optical engine having a front side and a back side, the back side of the optical engine being directly electrically connected to the front side of the SoC.

28. The semiconductor structure of claim 27, further comprising: a first set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the SoC.

29. The semiconductor structure of claim 27, further comprising: a first set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the SoC.

30. The semiconductor structure of claim 27, further comprising: a set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the SoC.

31. The semiconductor structure of claim 27, further comprising: a set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the SoC.

32. The semiconductor structure of any claims 27-31, wherein the optical engine includes an electrical integrated circuit (EIC) and a photonic integrated circuit (PIC).

33. The semiconductor structure of claim 32, wherein the EIC and the PIC are disposed on a common chip.

34. The semiconductor structure of claim 32, wherein the EIC and the PIC are disposed onseparate chips.

35. The semiconductor structure of any of claims 27-34, further comprising a redistribution layer on the back side of the SoC, the front side of the memory module, the back side of the optical engine, or the front side of the SoC.

36. The semiconductor structure of any of claims 27-34, further comprising a plurality of redistribution layers, each redistribution layer on the back side of the SoC, the front side of the memory module, the back side of the optical engine, or the front side of the SoC.

37. The semiconductor structure of any of claims 27-36, wherein the memory module comprises random access memory (RAM) integrated circuits.

38. The semiconductor structure of claim 37, wherein at least a portion of the RAM integrated circuits are dynamic RAM (DRAM) integrated circuits.

39. A semiconductor structure comprising: a memory module having a front side and a back side; a system-on-a-chip (SoC) having a front side and a back side, the back side of the SoC being directly electrically connected to the front side of the memory module; and an optical engine having a front side and a back side, the back side of the optical engine being directly electrically connected to the front side of the memory module.

40. The semiconductor structure of claim 39, further comprising: a first set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

41. The semiconductor structure of claim 39, further comprising: a first set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a second set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

42. The semiconductor structure of claim 39, further comprising: a set of micro bumps that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of hybrid bonds that directly electrically connect the back side of the optical engine to the front side of the memory module.

43. The semiconductor structure of claim 39, further comprising: a set of hybrid bonds that directly electrically connect the back side of the SoC to the front side of the memory module; and a set of micro bumps that directly electrically connect the back side of the optical engine to the front side of the memory module.

44. The semiconductor structure of any claims 39-43, wherein the optical engine includes an electrical integrated circuit (EIC) and a photonic integrated circuit (PIC).

45. The semiconductor structure of claim 44, wherein the EIC and the PIC are disposed on a common chip.

46. The semiconductor structure of claim 44, wherein the EIC and the PIC are disposed on separate chips.

47. The semiconductor structure of any of claims 39-46, further comprising a redistribution layer on the back side of the SoC, the front side of the memory module, or the back side of the optical engine.

48. The semiconductor structure of any of claims 39-46, further comprising a plurality of redistribution layers, each redistribution layer on the back side of the SoC, the front side of the memory module, or the back side of the optical engine.

49. A method for fabricating a three-dimensional integrated circuit (3DIC), the method comprising: fabricating a logic integrated circuit (IC) die comprising first exposed leads in a first pattern;fabricating a memory module comprising second exposed leads in a second pattern; and mechanically securing the logic IC die to the memory module through one or more bonds that further communicatively couple at least a portion of the first exposed leads to at least a portion of the second exposed leads.

50. The method of claim 49, wherein fabricating the 3DIC further comprises: thinning at least one of the logic IC die or the memory module.

51. The method of claim 50, wherein the thinning is performed prior to mechanically securing the logic IC die to the memory module.

52. The method of claim 50, wherein the thinning is performed after mechanically securing the logic IC die to the memory module.

53. The method of claim 49, wherein mechanically securing the logic IC die to the memory module comprises bonding at least some of the first exposed leads to at least some of the second exposed leads through the one or more bonds.

54. The method of claim 53, wherein the one or more bonds comprise one or more of a bump bond, a micro-bump bond, a hybrid bond, a solder bond, or a controlled collapse chip connection (C4) bond.

55. The method of claim 49, wherein: mechanically securing the logic IC die to the memory module comprises disposing a redistribution layer (RDL) between the logic IC and the memory module; the logic IC die is mechanically secured to a first side of the RDL and the memory module is mechanically secured to a second side of the RDL; the first side of the RDL comprises a first plurality of leads matching the first pattern; and the second side of the RDL comprises a second plurality of leads matching the second pattern.

56. The method of claim 55, wherein the RDL comprises one or more through-substratevias (TS Vs) communicatively coupling the first side of the RDL to the second side of the RDL.

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