Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a base substrate (101), a reflective layer (305), and a light-emitting composite layer (307). The reflective layer (305) has a plurality of first vias, and the light-emitting composite layer (307) comprises a first light-emitting device (301). The display substrate further comprises a first conductive structure (111), and the first light-emitting device (301) is at least partially in surface contact with the first conductive structure (111). At least part of the first conductive structure (111) is located within the first vias. The first conductive structure (111) comprises at least two sections. The orthographic projection, on the plane on which the display substrate is located, of the section close to the light-emitting composite layer (307) is located within the orthographic projection, on the plane on which the display substrate is located, of a section which is adjacent to said section and is away from the light-emitting composite layer (307), and the area of the orthographic projection of the section close to the light-emitting composite layer (307) on the plane on which the display substrate is located is smaller than the area of the orthographic projection of the section which is adjacent to said section and is away from the light-emitting composite layer (307) on the plane on which the display substrate is located.

Description

Display substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Micro Organic Light-Emitting Diode (Micro-OLED) is a micro display that has been developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED can not only realize active addressing of pixels, but also realize the preparation of pixel driving circuits and other structures on silicon-based substrates, which is conducive to reducing the system volume and achieving lightweight. Silicon-based OLED is prepared using the mature complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) integrated circuit process. It has the advantages of small size, high resolution (Pixels Per Inch, PPI), high refresh rate, etc., and is widely used in the field of virtual reality (VR) or augmented reality (AR) near-eye display.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, embodiments of the present disclosure provide a display substrate. The display substrate includes a base substrate and a light-emitting structure layer located on one side of the base substrate. The light-emitting structure layer includes a reflective layer and a light-emitting composite layer stacked sequentially in a direction away from the base substrate. The reflective layer has a plurality of first via holes. The light-emitting composite layer includes a first light-emitting device, a second light-emitting device, and a third light-emitting device arranged sequentially.

[0006] The light-emitting structure layer also includes a first conductive structure, and the first conductive structure is located between the light-emitting composite layer and the base substrate, and the first light-emitting device is in contact with at least a portion of the surface of the first conductive structure away from the base substrate; at least a portion of the first conductive structure is located within the first via hole; along the thickness direction of the display substrate, the first conductive structure includes at least two segments, the orthographic projection of the segment close to the light-emitting composite layer on the plane where the display substrate is located is located within the orthographic projection of the segment adjacent to the segment and away from the light-emitting composite layer on the plane where the display substrate is located, and the area of ​​the orthographic projection of the segment close to the light-emitting composite layer on the plane where the display substrate is located is smaller than the area of ​​the orthographic projection of the segment adjacent to the segment and away from the light-emitting composite layer on the plane where the display substrate is located.

[0007] In an exemplary embodiment, a plurality of sub-pixels are included, the plurality of sub-pixels including at least a first sub-pixel, a second sub-pixel, and a third sub-pixel; the first sub-pixel includes the first light-emitting device and is configured to emit light of a first color; the second sub-pixel includes the second light-emitting device and is configured to emit light of a second color; the third sub-pixel includes a third light-emitting device and is configured to emit light of a third color, and the first color, the second color, and the third color are all one of three primary colors;

[0008] The light-emitting structure layer further includes a microcavity adjustment layer, which is located between the reflective layer and the light-emitting composite layer; the microcavity adjustment layer is configured so that the first sub-pixel, the second sub-pixel, and the third sub-pixel have different microcavity lengths.

[0009] In an exemplary embodiment, the microcavity adjustment layer includes a first adjustment portion, a second adjustment portion, and a third adjustment portion arranged in sequence; the first adjustment portion is configured so that the first sub-pixel has a first microcavity length H1 and a first thickness h1; the second adjustment portion is configured so that the second sub-pixel has a second microcavity length H2 and a second thickness h2; the third adjustment portion is configured so that the third sub-pixel has a third microcavity length H3 and a third thickness h3;

[0010] Among them, H1>H2>H3, and h1>h2>h3.

[0011] In an exemplary embodiment, the thickness of the third adjustment portion ranges from 200 angstroms to 600 angstroms.

[0012] In an exemplary embodiment, the thickness of the first adjustment portion is in a range of 1300 angstroms to 1700 angstroms, and the thickness of the second adjustment portion is in a range of 1200 angstroms to 1600 angstroms.

[0013] In an exemplary embodiment, the microcavity adjustment layer has a plurality of second via holes, and the plurality of second via holes are arranged in a one-to-one correspondence with the plurality of first via holes and are connected;

[0014] The first conductive structure includes two sections, namely a first section and a second section. The second section is closer to the light-emitting composite layer than the first section. The first section is located within the first via hole, and the second section is located within the second via hole.

[0015] In an exemplary embodiment, the orthographic projection of the first segment on the plane where the display substrate is located has a first outer edge, and the orthographic projection of the second segment on the plane where the display substrate is located has a second outer edge;

[0016] The first outer edge surrounds the second outer edge, and there is a gap between the first outer edge and the second outer edge, and the range of the gap is greater than or equal to 0.04 micrometers and less than or equal to 0.1 micrometers.

[0017] In an exemplary embodiment, an orthographic projection of the second segment on the plane where the display substrate is located coincides with an orthographic projection of the second via hole on the plane where the display substrate is located.

[0018] In an exemplary embodiment, the surface of the first segment away from the base substrate is flush with the surface of the reflective layer away from the base substrate; or, the surface of the first segment away from the base substrate is closer to the base substrate than the surface of the reflective layer away from the base substrate.

[0019] In an exemplary embodiment, the microcavity adjustment layer includes a first adjustment portion, a second adjustment portion, and a third adjustment portion arranged in sequence, and the thicknesses of the first adjustment portion, the second adjustment portion, and the third adjustment portion are different;

[0020] The second adjustment portion has a plurality of second via holes, and the plurality of second via holes are arranged in a one-to-one correspondence with and connected to the plurality of first via holes; the light-emitting structure layer also includes a second conductive structure, and the second conductive structure is located between the light-emitting composite layer and the base substrate, and the second light-emitting device is in contact with at least a portion of the surface of the second conductive structure away from the base substrate; at least a portion of the second conductive structure is located within the first via hole.

[0021] In an exemplary embodiment, the first light-emitting device includes a first electrode, a first organic light-emitting layer, and a second electrode that are stacked, and the first electrode is closer to the base substrate than the second electrode; wherein at least a portion of the first electrode is located on a side of the microcavity adjustment layer away from the base substrate.

[0022] In an exemplary embodiment, the microcavity adjustment layer has a plurality of second via holes, and the plurality of second via holes are arranged in a one-to-one correspondence with and connected to the plurality of first via holes; the first electrode includes a first portion and a second portion that are connected; the first portion is located on a side of the microcavity adjustment layer away from the base substrate, and the second portion is located within the second via hole.

[0023] In an exemplary embodiment, along the aperture direction of the second via hole, the thickness of the second portion is greater than or equal to 30% of the thickness of the first portion and less than or equal to the thickness of the first portion.

[0024] In an exemplary embodiment, a dimension of the second portion along a thickness direction of the display substrate does not exceed 50% of a depth of the second via hole.

[0025] In an exemplary embodiment, the first electrode further includes a third portion, the third portion is located on a side of the microcavity adjustment layer away from the base substrate, and the third portion and the first portion are respectively located on two opposite sides of the second portion.

[0026] In an exemplary embodiment, a size range of an orthographic projection of the third portion on the plane where the display substrate is located along the aperture direction of the second via hole is greater than or equal to 0.04 micrometers and less than or equal to 0.1 micrometers.

[0027] In an exemplary embodiment, the light-emitting structure layer further includes an isolation layer, which is located within the first via hole and is arranged around the first conductive structure; the edge of the third portion on the side close to the second light-emitting device of the orthographic projection of the plane where the display substrate is located is located within the range of the orthographic projection of the isolation layer on the plane where the display substrate is located.

[0028] In an exemplary embodiment, the second light-emitting device includes a third electrode, a second organic light-emitting layer, and a fourth electrode that are stacked, and the third electrode is closer to the base substrate than the fourth electrode;

[0029] There is a gap between the orthographic projection of the third portion on the plane where the display substrate is located and the orthographic projection of the third electrode on the plane where the display substrate is located, and the gap ranges from greater than or equal to 0.2 micrometers to less than or equal to 0.5 micrometers.

[0030] In an exemplary embodiment, the interval is greater than a difference between a diameter of the first via hole and a diameter of the second via hole.

[0031] In an exemplary embodiment, the orthographic projection of the third part on the plane where the display substrate is located is located within the orthographic projection of the first adjustment part on the plane where the display substrate is located, and the orthographic projection of the third electrode on the plane where the display substrate is located is located within the orthographic projection of the second adjustment part on the plane where the display substrate is located.

[0032] In an exemplary embodiment, the light emitting structure layer further includes an isolation layer, wherein the isolation layer is located within the first via hole and surrounds the first conductive structure.

[0033] In an exemplary embodiment, a surface of the isolation layer away from the base substrate is flush with a surface of the reflective layer away from the base substrate.

[0034] In an exemplary embodiment, the ring width of the isolation layer is greater than or equal to 0.2 micrometers and less than or equal to 0.3 micrometers.

[0035] In an exemplary embodiment, the third thickness is greater than the maximum ring width of the isolation layer.

[0036] In another aspect, an embodiment of the present disclosure provides a display device comprising the display substrate described in any one of the above embodiments.

[0037] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0038] Summary of the Figures

[0039] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0040] FIG1 is a test graph showing the relationship between the refractive index and wavelength of two materials;

[0041] FIG2 is a test curve diagram of the relationship between the extinction coefficient and wavelength of two materials;

[0042] FIG3 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0043] FIG4 is a schematic diagram of a planar structure of a display device according to an embodiment of the present disclosure;

[0044] FIG5 is a schematic diagram of a partial cross-sectional structure of a display device according to an embodiment of the present disclosure;

[0045] FIG6A is a schematic diagram of a partial cross-sectional structure of a display substrate according to an embodiment of the present disclosure;

[0046] FIG6B is a partial enlarged schematic diagram of the area marked A in FIG6A ;

[0047] FIG6C is a partial enlarged cross-sectional view of a display substrate according to another embodiment of the present disclosure;

[0048] FIG7 is a second schematic diagram of a partial cross-sectional structure of a display substrate according to an embodiment of the present disclosure;

[0049] 8A to 8N are schematic diagrams of a process for preparing a display substrate according to an embodiment of the present disclosure.

[0050] Reference numerals: 101 - base substrate, 102 - driving circuit layer, 201 - circuit structure layer, 202 - connection layer, 202 - 1 - first connection electrode, 202 - 2 - second connection electrode, 202 - 3 - third connection electrode; 103-light-emitting structure layer, 301-first light-emitting device, 301-1-first electrode, 301a-first portion, 301b-second portion, 301c-third portion, 301-2-second electrode, 301-3-first organic light-emitting layer, 302-second light-emitting device, 302-3-third electrode, 302-4-fourth electrode, 302-5-second organic light-emitting layer, 303-third light-emitting device, 303-5-fifth electrode, 303-6-sixth electrode, 303-7-third organic light-emitting layer, 304-insulating layer, 305-reflective layer, 305-1-first reflective electrode, 305-2-second reflective electrode, 305-3-third reflective electrode; 306-microcavity adjustment layer, 306-1-first adjustment portion, 306-2-second adjustment portion, 306-3-third adjustment portion, 307-light-emitting composite layer, 308-pixel definition layer, 308a-partitioning portion, 308-1-first sublayer, 308-2-second sublayer, 308-3-third sublayer, 309-isolation layer; 111-first conductive structure, 111-1-first segment, 111-2-second segment, 112-second conductive structure, 113-third conductive structure; 104-first encapsulation layer, 105-color filter structure layer, 106-second encapsulation layer, 107-cover layer, 10-photoresist pattern, 11-first conductive film, 12-second conductive film, 13-third conductive film, 14-metal routing layer, 15-second insulating film, 21-first adjustment layer, 22-second adjustment layer, 23-1-initial pattern of the third adjustment layer, 23-third adjustment layer.

[0051] Details

[0052] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0053] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0054] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.

[0055] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0056] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0057] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0058] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0059] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged.

[0060] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0061] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0062] In the present disclosure, “about” and “approximately” refer to values ​​that are not strictly defined and allow for process and measurement errors.

[0063] The triangles, rectangles, trapezoids, pentagons or hexagons in the present disclosure are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0064] The top-emitting microcavity OLED display device mainly realizes the full-color display effect through the micro-resonant cavity effect. The micro-resonant cavity effect refers to the optical interference effect that occurs inside the OLED device. To realize the micro-resonant cavity effect, it is necessary to make a semi-transparent and semi-reflective half-mirror at the light output of the device. When the photons are emitted from the light-emitting layer, they will interfere with each other between the emitting anode and the half-mirror, resulting in light interference. Only certain wavelengths of light will be enhanced, and some light will be weakened, so the half-width of the light wave will also be narrowed. The microcavity structure is generally divided into a weak microcavity structure and a strong microcavity structure. In the weak microcavity structure, the cavity lengths of different sub-pixels are equal, so the weak microcavity structure cannot maximize the use of the micro-resonant cavity effect to improve the light efficiency. In the strong microcavity structure, the cavity lengths of different sub-pixels are not equal. The use of the micro-resonant cavity effect can improve the light efficiency by about 3 times. There are two main ways to realize the strong microcavity structure. One is to thicken the electrode and the other is to set an adjustment layer. The material of the electrode is usually indium tin oxide (ITO), and the material of the adjustment layer is usually silicon oxide (SiO x As shown in Figure 1 and Figure 2, the curve marked ① represents the test curve of indium tin oxide (ITO), and the curve marked ② represents the test curve of silicon oxide (SiO x ) test curve, the refractive index and extinction coefficient of indium tin oxide (ITO) are higher than those of silicon oxide (SiO x ) has a large refractive index and extinction coefficient, so the use of thickened electrodes has a greater impact on the microcavity sensitive device (B Stack), which will cause a certain proportion of blue light loss and affect the maximum white light brightness.

[0065] An embodiment of the present disclosure provides a display substrate, comprising a base substrate and a light-emitting structure layer located on one side of the base substrate, wherein the light-emitting structure layer comprises a reflective layer and a light-emitting composite layer stacked in sequence in a direction away from the base substrate, the reflective layer having a plurality of first via holes, and the light-emitting composite layer comprising a first light-emitting device, a second light-emitting device, and a third light-emitting device arranged in sequence;

[0066] The light-emitting structure layer also includes a first conductive structure, and the first conductive structure is located between the light-emitting composite layer and the base substrate, and the first light-emitting device is in contact with at least a portion of the surface of the first conductive structure away from the base substrate; at least a portion of the first conductive structure is located within the first via hole; along the thickness direction of the display substrate, the first conductive structure includes at least two segments, the orthographic projection of the segment close to the light-emitting composite layer on the plane where the display substrate is located is located within the orthographic projection of the segment adjacent to the segment and away from the light-emitting composite layer on the plane where the display substrate is located, and the area of ​​the orthographic projection of the segment close to the light-emitting composite layer on the plane where the display substrate is located is smaller than the area of ​​the orthographic projection of the segment adjacent to the segment and away from the light-emitting composite layer on the plane where the display substrate is located.

[0067] The display substrate provided by the embodiment of the present disclosure, by designing the first conductive structure with a variable cross-section, is advantageously used to increase the spacing between the section of the first conductive structure close to the light-emitting composite layer and the anode of the second light-emitting device, thereby avoiding electrical crosstalk between the first light-emitting device and the second light-emitting device, and improving the reliability of the electrical connection of the display substrate.

[0068] FIG3 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in FIG3 , the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The display unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. The sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and to the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the data driver's specifications to the data driver, and may provide clock signals, scan start signals, and other signals suitable for the scan driver's specifications to the scan driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be supplied to the data signal lines D1, D2, D3, ..., and Dn. For example, the data driver may sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel column basis, where n may be a natural number. The scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and other signals from the timing controller. For example, the scan driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured as a shift register and may generate scan signals by sequentially transmitting the scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m may be a natural number. In example embodiments, a pixel array may be provided on a display substrate.

[0069] FIG4 is a schematic diagram of a planar structure of a display device according to an embodiment of the present disclosure. As shown in FIG4 , the display device may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a plurality of sub-pixels. The plurality of sub-pixels may include at least a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is respectively connected to a scan signal line and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting device. The light-emitting device in the sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0070] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel that emits red (R) light, the second sub-pixel P2 may be a green sub-pixel that emits green (G) light, and the third sub-pixel P3 may be a blue sub-pixel that emits blue (B) light. In the embodiments of the present disclosure, red may also be referred to as the first color, green may also be referred to as the second color, and blue may also be referred to as the third color. In an exemplary embodiment, the shape of the sub-pixels may be any one of a triangle, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, etc., and multiple sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a square, or a diamond shape, etc., which is not limited in the present disclosure.

[0071] Figure 5 is a schematic diagram of the partial cross-sectional structure of a display device according to an embodiment of the present disclosure, illustrating a structure that uses white light + color filter to achieve full-color display. As shown in Figure 5, taking only one pixel unit as an example, the display device may include a display substrate and a first encapsulation layer 104, a color filter structure layer 105, a second encapsulation layer 106, and a cover layer 107 sequentially arranged on one side of the display substrate. The display substrate may include a base substrate 101, a driving circuit layer 102 arranged on the base substrate 101, and a light-emitting structure layer 103 arranged on the side of the driving circuit layer 102 away from the base substrate 101. In some possible implementations, the display device may also include other film layers, which are not limited in this disclosure.

[0072] In an exemplary embodiment, the base substrate 101 may be a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be prepared on the base substrate 101 by a silicon semiconductor process (e.g., a CMOS process). The driving circuit layer 102 may include a plurality of circuit units. The circuit units may include at least a pixel driving circuit. The pixel driving circuit is connected to a scanning signal line and a data signal line, respectively. The pixel driving circuit may include a plurality of transistors and a storage capacitor. The transistor may include a gate electrode, a first electrode, and a second electrode. The gate electrode, the first electrode, and the second electrode may be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), respectively, and may be connected to other electrical structures (e.g., traces, etc.) through the connection electrodes.

[0073] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting devices, and the light-emitting device may include at least a first electrode, an organic light-emitting layer, and a second electrode. The first electrode may be connected to the second electrode of the transistor through a connecting electrode, the organic light-emitting layer is connected to the first electrode, the second electrode is connected to the organic light-emitting layer, and the second electrode may be connected to a second power line. The organic light-emitting layer emits light under the drive of the first electrode and the second electrode. For example, the first electrode may be the anode of the light-emitting device, and the second electrode may be the cathode of the light-emitting device. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML for short), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In some possible implementations, for a light-emitting device that emits white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0074] In one exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can be made of thin film encapsulation (TFE) to prevent external moisture from entering the light-emitting structure layer. The cover layer 107 can be made of glass or a flexible plastic such as colorless polyimide.

[0075] In an exemplary embodiment, the color film structure layer 105 may include a black matrix (BM) and a color filter (CF). The color filters are respectively arranged in the red sub-pixel, the green sub-pixel and the blue sub-pixel to filter the white light emitted by the light-emitting device into red (R) light, green (G) light and blue (B) light. The black matrix can be located between adjacent color filters.

[0076] Figure 6A is a schematic diagram of a partial cross-sectional structure of a display substrate according to an embodiment of the present disclosure. As shown in Figure 6A, only one pixel unit is illustrated as an example. The display substrate may include a base substrate 101, a driving circuit layer 102 disposed on the base substrate 101, and a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the base substrate 101. The light-emitting structure layer 103 may include a plurality of light-emitting devices, and the plurality of light-emitting devices may include at least a first light-emitting device 301, a second light-emitting device 302, and a third light-emitting device 303. In the embodiment of the present disclosure, the first light-emitting device 301, the second light-emitting device 302, and the third light-emitting device 303 are all configured to emit white light.

[0077] As shown in FIG6A , the driving circuit layer 102 may include a circuit structure layer 201 and a connection layer 202. The circuit structure layer 201 may include multiple pixel driving circuits, each of which may include multiple transistors and storage capacitors. The transistors may include a gate electrode, a first electrode, and a second electrode. The connection layer 202 may include multiple connection electrodes, each of which may include at least a first connection electrode 202-1, a second connection electrode 202-2, and a third connection electrode 202-3. The first connection electrode 202-1 is configured to connect the first light-emitting device 301 and the pixel driving circuit electrically connected thereto. The second connection electrode 202-2 is configured to connect the second light-emitting device 302 and the pixel driving circuit electrically connected thereto. The third connection electrode 202-3 is configured to connect the third light-emitting device 303 and the pixel driving circuit electrically connected thereto.

[0078] In an exemplary embodiment, the material of the connection layer 202 can be a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, it can be an alloy material of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or molybdenum-nickel-titanium alloy (MoNiTi). The connection layer 202 can have a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi.

[0079] In an exemplary embodiment, as shown in FIG6A , the light-emitting structure layer 103 may further include an insulating layer 304, a reflective layer 305 located on a side of the insulating layer 304 away from the base substrate 101, and a microcavity adjustment layer 306 located on a side of the reflective layer 305 away from the base substrate 101, and a plurality of light-emitting devices are located on a side of the microcavity adjustment layer 306 away from the base substrate 101.

[0080] As shown in FIG6A , the reflective layer 305 may have a plurality of first via holes K1. The first via holes K1 extend through the reflective layer 305 and the insulating layer 304 along the thickness direction of the display substrate, exposing a portion of the surface of the connection electrode on the side away from the base substrate 101. The first via holes K1 are configured to connect the light-emitting device to the connection electrode via the via holes. For example, the first via holes K1 may be rectangular, circular, or hexagonal.

[0081] As shown in FIG6A , the microcavity adjustment layer 306 may have a plurality of second vias K2, and the second vias K2 extend through the microcavity adjustment layer 306 along the thickness direction of the display substrate. The plurality of second vias K2 are arranged in a one-to-one correspondence with the plurality of first vias K1, and one second via K2 is connected to one first via K1. The orthographic projection of the second via K2 on the plane where the display substrate is located is within the orthographic projection of the first via K1 on the plane where the display substrate is located, and the orthographic projection area of ​​the second via K2 on the plane where the display substrate is located is smaller than the orthographic projection area of ​​the first via K1 on the plane where the display substrate is located. For example, the second via K2 may be a rectangular hole, a circular hole, or a hexagonal hole, etc.

[0082] In one exemplary embodiment, as shown in FIG6A , the reflective layer 305 may include a plurality of reflective electrodes, which may include at least a first reflective electrode 305-1, a second reflective electrode 305-2, and a third reflective electrode 305-3. The first reflective electrode 305-1 is configured to cause light emitted by the first light-emitting device 301 to generate a micro-resonant cavity effect, the second reflective electrode 305-2 is configured to cause light emitted by the second light-emitting device 302 to generate a micro-resonant cavity effect, and the third reflective electrode 305-3 is configured to cause light emitted by the third light-emitting device 303 to generate a micro-resonant cavity effect.

[0083] In an exemplary embodiment, the reflective layer 305 may be made of a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the reflective layer 305 may be made of an alloy of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium (AlNd), molybdenum-niobium (MoNb), or molybdenum-nickel-titanium (MoNiTi). The reflective layer 305 may have a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi.

[0084] In one exemplary embodiment, as shown in FIG6A , the display substrate may further include multiple conductive structures. At least portions of the multiple conductive structures may be located within the first via hole K1, and the conductive structures may be configured to connect the light-emitting devices of the corresponding sub-pixels to the connection electrodes. The multiple conductive structures may include a first conductive structure 111, a second conductive structure 112, and a third conductive structure 113. As shown in FIG6A , the first light-emitting device 301 may be connected to the first connection electrode 202-1 via the first conductive structure 111, the second light-emitting device 302 may be connected to the second connection electrode 202-2 via the second conductive structure 112, and the third light-emitting device 303 may be connected to the third connection electrode 202-3 via the third conductive structure 113. For example, a portion of the first conductive structure 111 may be located within the first via hole K1, and the remaining portion of the first conductive structure 111 may be located within the second via hole K2. For example, a portion of the second conductive structure 112 may be located within the first via hole K1, and the remaining portion of the second conductive structure 112 may be located within the second via hole K2. Alternatively, the entire second conductive structure 112 may be located within the first via hole K1 . For example, the entire third conductive structure 113 may be located within the first via hole K1 .

[0085] In one exemplary embodiment, as shown in FIG6A , the microcavity adjustment layer 306 may include multiple adjustment sections, each of which may include at least a first adjustment section 306-1, a second adjustment section 306-2, and a third adjustment section 306-3. The thicknesses of the first adjustment section 306-1, the second adjustment section 306-2, and the third adjustment section 306-3 are all different. In the disclosed embodiment, the thickness direction is perpendicular to the plane of the display substrate. As shown in FIG6A , the first adjustment section 306-1 has a first thickness h1, the second adjustment section 306-2 has a second thickness h2, and the third adjustment section 306-3 has a third thickness h3, with h1 being greater than h2, and h2 being greater than h3. In the disclosed embodiment, by providing adjustment sections with different thicknesses, the microcavity structures formed by the three sub-pixels can have different microcavity lengths. In the disclosed embodiment, the microcavity length refers to the distance of the optical resonant cavity between the cathode and the reflective layer of the sub-pixel.

[0086] As shown in Figure 6A, the first subpixel P1 has a first microcavity length H1, the second subpixel P2 has a second microcavity length H2, and the third subpixel P3 has a third microcavity length H3, with H1 being greater than H2, and H2 being greater than H3. The display substrate provided by the disclosed embodiments can utilize a strong microcavity effect to enhance the light emitted by the organic light-emitting layer of each subpixel near the resonant wavelength of the microcavity length and broaden its spectrum, while weakening the light at other wavelengths not corresponding to the resonant wavelength and narrowing its spectrum. This results in the light-emitting structure layer in the first subpixel P1 primarily emitting light of the first color, the light-emitting structure layer in the second subpixel P2 primarily emitting light of the second color, and the light-emitting structure layer in the third subpixel P3 primarily emitting light of the third color. Because the color of light emitted by the light-emitting structure layer in each subpixel is the same as the color of light allowed to pass through the color filter of that subpixel, the light energy loss caused by light passing through the color filter can be minimized, thereby improving the light extraction efficiency of the display substrate and enhancing the display quality of the display product.

[0087] In one exemplary embodiment, the thickness of the first adjustment portion 306-1 can range from 1300 angstroms to 1700 angstroms, and the thickness of the second adjustment portion 306-2 can range from 1200 angstroms to 1600 angstroms. The thickness of the third adjustment portion 306-3 can range from 200 angstroms to 600 angstroms. By limiting the thickness ranges of the first, second, and third adjustment portions, large thickness steps in the microcavity adjustment layer can be avoided, as can steep slopes in the anode layer of the light-emitting structure layer, thereby improving the reliability of the light-emitting device. By limiting the thickness range of the third adjustment portion, parasitic capacitance between the third light-emitting device and the reflective layer can be avoided, thereby improving the luminous performance of the third light-emitting device.

[0088] In an exemplary embodiment, the light-emitting structure layer 103 may further include a light-emitting composite layer 307 and a pixel definition layer 308 located on the side of the microcavity adjustment layer 306 away from the base substrate 101. The light-emitting composite layer 307 may include multiple light-emitting devices, and the pixel definition layer 308 has multiple opening areas. The pixel definition layer 308 may include multiple partitions 308a, and the partitions 308a are arranged around the opening areas. The light emitted by the light-emitting devices can be emitted through the corresponding opening areas. The detailed structure of the partitions 308a can be found in the description of Figure 6B. The light-emitting composite layer 307 may include an anode layer, an organic light-emitting layer, and a cathode layer arranged in sequence along a direction away from the base substrate 101. The organic light-emitting layer can emit light under the drive of the anode layer and the cathode layer.

[0089] In one exemplary embodiment, the anode layer may be made of a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO). The anode layer may be a single layer structure or a multilayer composite structure, such as ITO / Al / ITO. The thickness of the anode layer may range from 120 angstroms to 200 angstroms.

[0090] Figure 6B is a partially enlarged schematic diagram of the area marked A in Figure 6A. As shown in Figure 6B, the first conductive structure 111 may include a first segment 111-1 and a second segment 111-2 connected to each other. In Figure 6B, the first segment 111-1 is not colored to facilitate identification. The first segment 111-1 is located within the first via K1, and the second segment 111-2 is located within the second via K2. The orthographic projection of the second segment 111-2 on the plane of the display substrate is located within the orthographic projection of the first segment 111-1 on the plane of the display substrate, and the orthographic projection area of ​​the second segment 111-2 on the plane of the display substrate is smaller than the orthographic projection area of ​​the first segment 111-1 on the plane of the display substrate. The first conductive structure 111 is designed as a combination of a first segment 111-1 and a second segment 111-2, and an orthographic projection relationship is defined between the first segment 111-1 and the second segment 111-2. During the display substrate manufacturing process, a via hole for accommodating the first conductive structure 111 can be formed using a yellow light overlay process, ensuring high dimensional accuracy of the via hole. For example, the first segment 111-1 can be a cylinder, and the second segment 111-2 can be a cylinder.

[0091] In one exemplary embodiment, as shown in FIG6B , the first light-emitting device 301 may include a first electrode 301-1, a first organic light-emitting layer 301-3, and a second electrode 301-2. The first electrode 301-1 is located in the anode layer, the first organic light-emitting layer 301-3 is located in the organic light-emitting layer, and the second electrode 301-2 is located in the cathode layer. The first electrode 301-1 may be connected to the second electrode of the transistor via a first connecting electrode, the first organic light-emitting layer 301-3 is connected to the first electrode 301-1, and the second electrode 301-2 is connected to the first organic light-emitting layer 301-3. The second electrode 301-2 may be connected to a second power line. The first organic light-emitting layer 301-3 emits light when driven by the first and second electrodes 301-1 and 301-2. In an embodiment of the present disclosure, the second power line is configured to continuously provide a low-level signal to the light-emitting device. The first electrode 301-1 may be the anode of the first light-emitting device 301, and the second electrode 301-2 may be the cathode of the first light-emitting device 301.

[0092] In one exemplary embodiment, as shown in FIG6B , at least a portion of the first electrode 301-1 may be located on a side of the microcavity adjustment layer 306 away from the reflective layer 305. For example, the entire first electrode 301-1 may be located on a side of the microcavity adjustment layer 306 away from the reflective layer 305. Alternatively, a portion of the first electrode 301-1 may be located on a side of the microcavity adjustment layer 306 away from the reflective layer 305, and the remaining portion of the first electrode 301-1 may be located within the second via hole K2, with the remaining portion of the first electrode 301-1 along the thickness direction of the display substrate not exceeding 50% of the depth of the second via hole K2. In the disclosed embodiment, by limiting the depth of the first electrode 301-1 within the second via hole K2 (the dimension along the thickness direction of the display substrate), the impedance of the first electrode due to slope reduction can be reduced, thereby reducing the power consumption of the light-emitting device and improving the overall performance of the display product.

[0093] In one exemplary embodiment, as shown in FIG6B , the first electrode 301-1 may include a first portion 301a, a second portion 301b, and a third portion 301c that are connected. The first portion 301a and the third portion 301c may both be located on the side of the microcavity adjustment layer 306 away from the reflective layer 305. The second portion 301b may be located within the second via hole K2, with the edge of the orthographic projection of the second portion 301b onto the plane of the display substrate coinciding with the edge of the orthographic projection of the second via hole K2 onto the plane of the display substrate. As shown in FIG6B , along the aperture direction of the second via hole K2, the thickness of the second portion 301b may range from greater than or equal to 30% of the thickness of the first portion 301a and less than or equal to the thickness of the first portion 301a. For example, the thickness of the first portion 301a may be 200 angstroms, the thickness of the second portion 301b may be 60 angstroms, or the thickness of the first portion 301a may be 100 angstroms. In the embodiment of the present disclosure, by limiting the thickness difference between the first portion 301a and the second portion 301b, the overall impedance of the first electrode 301-1 in the second via hole K2 region can be reduced, thereby improving the luminous efficiency of the light-emitting device.

[0094] As shown in Figure 6B, the second via K2 has a first end and a second end that are arranged opposite each other. The first end is farther away from the reflective layer 305 than the second end, and the aperture of the first end is the same as the aperture of the second end. The second via K2 can be produced using a semi-back etching method, which can eliminate the need for a yellow light overlay step. Yellow light overlay requires that the upper layer aperture is smaller than the lower layer aperture to ensure overlay accuracy. Adding a yellow light overlay step will increase the aperture of the first via K1 by 0.04 to 0.1 microns. Therefore, by making the aperture of the first and second ends of the second via K2 the same, the aperture of the first via K1 can be reduced.

[0095] In one exemplary embodiment, as shown in FIG6B , the second light-emitting device 302 may include a third electrode 302-3, a second organic light-emitting layer 302-5, and a fourth electrode 302-4. The third electrode 302-3 is located in the anode layer, the second organic light-emitting layer 302-5 is located in the organic light-emitting layer, and the fourth electrode 302-4 is located in the cathode layer. The third electrode 302-3 may be connected to the second electrode of the transistor via a second connecting electrode, the second organic light-emitting layer 302-5 is connected to the third electrode 302-3, and the fourth electrode 302-4 is connected to the second organic light-emitting layer 302-5. The fourth electrode 302-4 may be connected to a second power line. The second organic light-emitting layer 302-5 emits light when driven by the third electrode 302-3 and the fourth electrode 302-4. The third electrode 302-3 may be the anode of the second light-emitting device 302, and the fourth electrode 302-4 may be the cathode of the second light-emitting device 302.

[0096] In one exemplary embodiment, the third light-emitting device 303 may include a fifth electrode, a third organic light-emitting layer, and a sixth electrode. The fifth electrode is located in the anode layer, the third organic light-emitting layer is located in the organic light-emitting layer, and the sixth electrode is located in the cathode layer. The fifth electrode may be connected to the second electrode of the transistor via a third connecting electrode, the third organic light-emitting layer is connected to the fifth electrode, and the sixth electrode is connected to the third organic light-emitting layer. The sixth electrode may be connected to a second power line. The third organic light-emitting layer emits light when driven by the fifth and sixth electrodes. The fifth electrode may be the anode of the third light-emitting device 303, and the sixth electrode may be the cathode of the third light-emitting device 303. The cathodes of the first light-emitting device 301, the second light-emitting device 302, and the third light-emitting device 303 may be interconnected and integrated. In the disclosed embodiment, the coordination between the third and fifth electrodes and the second via hole can be similar to the coordination between the first electrode and the second via hole, and will not be further described here. In the disclosed embodiment, the third conductive structure and the second conductive structure can be designed similarly to the first conductive structure, and will not be further described here.

[0097] In an exemplary embodiment, as shown in FIG6B , the pixel definition layer may include a plurality of partitions 308a. The structures of the plurality of partitions 308a may be the same or different, as shown in FIG6B , taking the structure of one of the partitions as an example. The partition 308a may include a plurality of film layers, and the plurality of film layers may include a first sublayer 308-1, a second sublayer 308-2, and a third sublayer 308-3 that are sequentially arranged in a direction away from the reflective layer 305, the orthographic projection of the second sublayer 308-2 on the plane where the display substrate is located may be located within the orthographic projection of the first sublayer 308-1 on the plane where the display substrate is located, and the orthographic projection area of ​​the second sublayer 308-2 on the plane where the display substrate is located is smaller than the orthographic projection area of ​​the first sublayer 308-1 on the plane where the display substrate is located, and the orthographic projection of the third sublayer 308-3 on the plane where the display substrate is located includes the orthographic projection of the second sublayer 308-2 ... The orthographic projection area of ​​8-3 on the plane where the display substrate is located is larger than the orthographic projection area of ​​the second sub-layer 308-2 on the plane where the display substrate is located, and the orthographic projection of the third sub-layer 308-3 on the plane where the display substrate is located is located within the orthographic projection of the first sub-layer 308-1 on the plane where the display substrate is located. As shown in Figure 6B, the multiple film layers of the partition 308a form an undercut structure, which can reduce the size of the partition, improve the aperture ratio of the display substrate, and is conducive to the disconnection of the organic light-emitting layer at the partition, which can avoid crosstalk between adjacent sub-pixels and improve the display quality of the display product. The partition with an undercut structure can avoid the problem of cathode puncture or breakage caused by deformation of its edge.

[0098] In one exemplary embodiment, as shown in FIG. 6B , the materials of the first sub-layer 308 - 1 and the third sub-layer 308 - 3 may include silicon oxide (SiO x ), for example, the silicon oxide may be silicon oxide. The material of the second sub-layer 308-2 may include silicon nitride (SiN x In the embodiment of the present disclosure, the material of the second sub-layer 308-2 is designed to be different from the materials of the first sub-layer 308-1 and the third sub-layer 308-3 so that the partition portion is conducive to forming an undercut structure.

[0099] In one exemplary embodiment, as shown in FIG6B , the reflective layer 305 may have a plurality of first via holes K1, each having a maximum aperture of d1, which may range from 0.5 μm to 0.7 μm. For example, the first via holes K1 may be circular, rectangular, or elliptical. The microcavity adjustment layer 306 may have a plurality of second via holes K2, each having a maximum aperture of d2, which is smaller than d1, and which may range from 0.3 μm to 0.5 μm. The central axis of the second via hole K2 along its length is collinear or parallel to the central axis of the first via hole K1 along its length.

[0100] In an exemplary embodiment, as shown in FIG6B , the light-emitting structure layer 103 may further include an isolation layer 309, which is located within the first via hole K1 and is disposed around the first segment 111 - 1. The orthographic projection of the isolation layer 309 on the plane where the display substrate is located may be annular, and the ring width of the isolation layer 309 may range from 0.2 μm to 0.3 μm, thereby ensuring that no induced capacitance is generated in the first via hole region and that the sub-pixel has a larger opening area.

[0101] In an exemplary embodiment, the first adjustment portion 306-1 has a first thickness h1, the second adjustment portion 306-2 has a second thickness h2, and the third adjustment portion 306-3 has a third thickness h3, and h1 is greater than h2, and h2 is greater than h3, and the third thickness h3 is greater than the maximum ring width of the isolation layer 309. Such a design can reduce the parasitic capacitance between the conductive structure and the reflective layer, and can improve the display quality of the display device.

[0102] In an exemplary embodiment, the material of the isolation layer 309 may be an inorganic material or an organic material. The inorganic material is, for example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO x ) etc. Organic materials, for example, any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, etc.

[0103] In an exemplary embodiment, as shown in FIG6B , the orthographic projection of the first segment 111 - 1 on the plane where the display substrate is located may be a circle, and the first diameter of the first segment 111 - 1 is d3, then the difference between d3 and d2 may be greater than or equal to 0.04 microns and less than or equal to 0.1 microns, and d3 is greater than d2.

[0104] In one exemplary embodiment, as shown in FIG6B , the orthographic projection of the first portion 301a of the first electrode 301-1 on the plane of the display substrate and the orthographic projection of the separator 308a on the plane of the display substrate form a first overlapping region. The length of the first overlapping region is denoted as d4, and d4 can range from 0.25 microns to 0.45 microns. In the disclosed embodiment, by limiting the length d4 of the first overlapping region, the luminous efficiency of the first light-emitting device can be improved. The separator 308a can also protect the edge of the first electrode 301-1, preventing water and oxygen from invading the first light-emitting device through the edge of the first electrode 301-1, thereby improving the reliability of the first light-emitting device.

[0105] In one exemplary embodiment, as shown in FIG6B , the orthographic projection of the third portion 301c of the first electrode 301-1 on the plane of the display substrate and the orthographic projection of the separator 308a on the plane of the display substrate form a second overlapping region. The length of the second overlapping region is denoted as d5, and d5 can range from 0.04 microns to 0.1 microns. In the disclosed embodiment, limiting the length d5 ​​of the second overlapping region can prevent water and oxygen from invading the first conductive structure through the edge of the third portion 301c, thereby improving the reliability of the electrical connection of the first conductive structure.

[0106] In one exemplary embodiment, as shown in FIG6B , a gap d6 exists between the orthographic projection of the first electrode 301-1 on the plane of the display substrate and the orthographic projection of the third electrode 302-3 on the plane of the display substrate. The gap d6 can range from 0.2 microns to 0.5 microns. In the disclosed embodiment, by limiting the gap d6 between the first electrode 301-1 and the third electrode 302-3, electrical connection between the first and second light-emitting devices can be avoided, enabling independent control of the first and second light-emitting devices, thereby improving the control accuracy of the display product.

[0107] In one exemplary embodiment, as shown in FIG6B , a gap d6 exists between the orthographic projection of the first electrode 301-1 on the plane of the display substrate and the orthographic projection of the third electrode 302-3 on the plane of the display substrate. This gap d6 can be greater than the difference between the diameters of the first via K1 and the second via K2. By reserving a sufficient gap d6, process precision requirements can be lowered, reducing the manufacturing cost of the display device. Generally, due to the supply relationships of the various components of the display substrate, the light-emitting device and the conductive structure are manufactured by different manufacturers. Due to differences in manufacturing precision between manufacturers, the precision of the light-emitting device is often lower than that of the conductive structure. Therefore, reserving a sufficient gap d6 can ensure process feasibility and reduce the manufacturing cost of the display device. In one exemplary embodiment, the edge of the third portion 301c on the orthographic projection of the display substrate plane, which is adjacent to the second light-emitting device, can be located within the orthographic projection of the isolation layer 309 on the plane of the display substrate. This can increase the gap d6 and reduce signal crosstalk between two adjacent sub-pixels.

[0108] In one exemplary embodiment, as shown in FIG6B , the orthographic projection of the third electrode 302-3 on the plane of the display substrate and the orthographic projection of the separator 308a on the plane of the display substrate form a third overlapping region. The length of the third overlapping region is designated d7, and d7 can range from 0.6 microns to 1.0 microns. In the disclosed embodiment, limiting the length d7 of the third overlapping region improves the luminous efficiency of the second light-emitting device. Furthermore, the separator 308a protects the edge of the third electrode 302-3, preventing water and oxygen from intruding into the second light-emitting device through the edge of the third electrode 302-3, thereby improving the reliability of the second light-emitting device.

[0109] In an exemplary embodiment, as shown in FIG6B , the orthographic projection of the partition 308a on the plane where the display substrate is located may include the orthographic projection of the first via K1 on the plane where the display substrate is located. For example, the orthographic projection of the partition 308a on the plane where the display substrate is located is larger than the orthographic projection of the first via K1 on the plane where the display substrate is located. This can avoid the occupation of the area of ​​the light-emitting region of the light-emitting device by setting the first via K1. For a single light-emitting device, a full-surface reflective layer design can be implemented, which can improve the light extraction efficiency of a single sub-pixel and the overall aperture ratio of the display substrate. By using the display substrate provided in the embodiment of the present disclosure, the aperture ratio of the display substrate can be greater than 65%.

[0110] Figure 6C is an enlarged schematic diagram of a partial cross-section of a display substrate according to another embodiment of the present disclosure. As shown in Figure 6C, the orthographic projection of the third portion 301c of the first electrode 301-1 on the plane of the display substrate can be located within the orthographic projection of the first adjustment portion 306-1 on the plane of the display substrate, and the orthographic projection of the third electrode 302-3 on the plane of the display substrate can be located within the orthographic projection of the second adjustment portion 306-2 on the plane of the display substrate. Based on the presence of a gap d6 between the orthographic projection of the first electrode 301-1 and the orthographic projection of the third electrode 302-3 on the plane of the display substrate, and because the thickness of the first adjustment portion 306-1 is greater than the thickness of the second adjustment portion 306-2, a gap exists between the third portion 301c and the third electrode 302-3 along the thickness direction of the display substrate, further reducing the risk of crosstalk between adjacent sub-pixels.

[0111] FIG7 is a second schematic diagram of a partial cross-sectional structure of a display substrate according to an embodiment of the present disclosure. The cutting position of the cross-sectional schematic diagram shown in FIG7 does not pass through the first via hole and the second via hole. In contrast, the cutting position of the cross-sectional schematic diagram shown in FIG6A passes through the first via hole and the second via hole. As shown in FIG7 , there is an overlapping area between the orthographic projection of the first electrode 301-1 on the plane where the display substrate is located and the orthographic projection of the partition 308a on the plane where the display substrate is located. The length of the overlapping area is marked as d8, and the range of d8 can be 0.6 microns to 1.0 microns. In the embodiment of the present disclosure, by limiting the length d8 of the overlapping area, it is possible to prevent water and oxygen from invading the first light-emitting device through the edge of the first electrode 301-1, thereby improving the reliability of the first light-emitting device. For example, d8 can be equal to the sum of d4, d2, and d5.

[0112] The structure of a display substrate is described below using an example of its fabrication process. The "patterning process" referred to in the embodiments of this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials. For organic materials, it includes processes such as organic material coating, mask exposure, and development. The deposition process can employ any one or more of sputtering, evaporation, and chemical vapor deposition; the coating process can employ any one or more of spray coating, spin coating, and inkjet printing; and the etching process can employ any one or more of dry etching and wet etching, though this disclosure does not limit these processes. A "thin film" refers to a thin layer of a material deposited on a substrate using deposition, coating, or other processes. If a "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If a "thin film" requires a patterning process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The term "A and B in the same layer" as used in this disclosure means that A and B are formed through the same patterning process.

[0113] The preparation process of the display substrate may include the following steps, taking a pixel unit as an example, as shown in FIG8A to FIG8N:

[0114] (11) Forming a photoresist pattern. Forming the photoresist pattern may include: forming a circuit structure layer 201 on one side of the base substrate 101, sequentially depositing a first conductive film 11, a second conductive film 12, and a third conductive film 13 on a side of the circuit structure layer 201 away from the base substrate 101, forming a photoresist film on a side of the third conductive film 13 away from the base substrate 101, and patterning the photoresist film through a patterning process to form a photoresist pattern 10 located on a side of the third conductive film 13 away from the base substrate 101, as shown in FIG8A.

[0115] The circuit structure layer 201 may include multiple pixel driving circuits, each of which may include multiple transistors and storage capacitors. The transistors may include a gate electrode, a first electrode, and a second electrode. In one example, the semiconductor layer of the transistor may be a complementary metal oxide semiconductor (CMOS) layer.

[0116] (12) Forming a metal wiring layer pattern. Forming a metal wiring layer pattern may include: applying a patterning process to the base substrate 101 having the aforementioned pattern formed thereon, so that the first conductive film 11, the second conductive film 12, and the third conductive film 13 form a connection layer 202, and the connection layer 202 may include a plurality of connection electrodes, and the plurality of connection electrodes may include at least a first connection electrode 202-1, a second connection electrode 202-2, and a third connection electrode 202-3, as shown in FIG8B. The first connection electrode 202-1 is configured to connect a first light-emitting device to be formed subsequently and a pixel driving circuit electrically connected thereto. The second connection electrode 202-2 is configured to connect a second light-emitting device to be formed subsequently and a pixel driving circuit electrically connected thereto. The third connection electrode 202-3 is configured to connect a third light-emitting device to be formed subsequently and a pixel driving circuit electrically connected thereto.

[0117] Forming the metal trace pattern may further include depositing a fourth conductive film on the side of the substrate 101 having the aforementioned pattern formed thereon to form a metal trace layer 14, as shown in FIG8B . A gap is provided between two adjacent connection electrodes, and the metal trace layer 14 may be located within the gap. The surface of the metal trace layer 14 facing away from the substrate 101 may be flush with the surface of the connection layer 202 facing away from the substrate 101.

[0118] (13) Forming a reflective layer pattern. Forming the reflective layer pattern may include: sequentially depositing a first insulating film, a fifth conductive film, a sixth conductive film, and a seventh conductive film on one side of the base substrate 101 on which the aforementioned pattern is formed, patterning the seventh conductive film through a patterning process so that the fifth conductive film, the sixth conductive film, and the seventh conductive film form a reflective layer pattern, and forming the first insulating film into an insulating layer pattern, as shown in FIG8C .

[0119] As shown in FIG8C , the reflective layer 305 may have a plurality of first via holes K1. The first via holes K1 penetrate the reflective layer 305 and the insulating layer 304 along the thickness direction of the display substrate and expose a portion of the surface of the connecting electrode away from the base substrate 101. The first via holes K1 are configured to connect subsequently formed light-emitting devices to corresponding connecting electrodes via the via holes.

[0120] As shown in FIG8C , the reflective layer 305 may include a plurality of reflective electrodes, which may include at least a first reflective electrode 305-1, a second reflective electrode 305-2, and a third reflective electrode 305-3. The first reflective electrode 305-1 is configured to cause light emitted by a subsequently formed first light-emitting device to generate a micro-resonant cavity effect, the second reflective electrode 305-2 is configured to cause light emitted by a subsequently formed second light-emitting device to generate a micro-resonant cavity effect, and the third reflective electrode 305-3 is configured to cause light emitted by a subsequently formed third light-emitting device to generate a micro-resonant cavity effect.

[0121] (14) Forming an isolation layer pattern. Forming the isolation layer pattern may include: depositing a second insulating film 15 on one side of the base substrate 101 on which the aforementioned pattern is formed, as shown in FIG8D . The second insulating film 15 covers the sidewalls of the first via K1, but does not completely fill the first via K1. The second insulating film 15 exposes a portion of the surface of the connecting electrode away from the base substrate 101. The second insulating film 15 can be used to isolate the subsequently formed conductive structure from the reflective layer 305.

[0122] Forming the isolation layer pattern may further include patterning the second insulating film 15 to form an isolation layer 309, as shown in FIG8E. The surface of the isolation layer 309 away from the base substrate 101 is substantially flush with the surface of the reflective layer 305 away from the base substrate 101.

[0123] (15) Forming an initial conductive structure pattern. Forming the initial conductive structure pattern may include: depositing an eighth conductive film on one side of the base substrate 101 having the aforementioned pattern formed thereon, and patterning the eighth conductive film through a patterning process to form an initial conductive structure pattern located within the first via hole K1, as shown in FIG8E . For example, the eighth conductive film may be made of tungsten.

[0124] As shown in FIG8E , the initial pattern of the conductive structure may include a plurality of first segments 111-1, wherein the first segment 111-1 is located within the first via K1, and the surface of the first segment 111-1 on the side away from the substrate 101 may be substantially flush with the surface of the reflective layer 305 on the side away from the substrate 101, or the surface of the first segment 111-1 on the side away from the substrate 101 may be closer to the substrate 101 than the surface of the reflective layer 305 on the side away from the substrate 101. This design allows the light-emitting device corresponding to the sub-pixel with the smallest microcavity length to be directly connected to the surface of the first segment 111-1 on the side away from the substrate 101, thereby saving process steps and reducing manufacturing costs. In the preparation method of the embodiment of the present disclosure, the first conductive structure, the second conductive structure, and the third conductive structure having the same partial structures located within the first via K1 are used as an example.

[0125] (16) Forming a first adjustment layer pattern. Forming the first adjustment layer pattern may include: depositing a third insulating film on a side of the base substrate 101 on which the aforementioned pattern is formed, and patterning the third insulating film through a patterning process to form a first adjustment layer pattern located on a side of the reflective layer 305 away from the base substrate 101, as shown in FIG8F .

[0126] As shown in FIG8F , the orthographic projection of the first adjustment layer 21 on the plane where the display substrate is located may at least partially overlap with the orthographic projection of the first reflective electrode 305-1 on the plane where the display substrate is located. For example, the orthographic projection of the first adjustment layer 21 on the plane where the display substrate is located may be located within the orthographic projection of the first reflective electrode 305-1 on the plane where the display substrate is located. The first adjustment layer 21 constitutes a part of the first adjustment portion, and the first adjustment portion is used to enable the first sub-pixel P1 to have a first microcavity length.

[0127] (17) Forming a second adjustment layer pattern. Forming the second adjustment layer pattern may include: depositing a fourth insulating film on a side of the base substrate 101 on which the aforementioned pattern is formed, and patterning the fourth insulating film through a patterning process to form a second adjustment layer pattern located on a side of the first adjustment layer 21 away from the base substrate 101, as shown in FIG8G .

[0128] As shown in Figure 8G, the orthographic projection of the second adjustment layer 22 on the plane of the display substrate can at least partially overlap with the orthographic projection of the first reflective electrode 305-1 on the plane of the display substrate, and the orthographic projection of the second adjustment layer 22 on the plane of the display substrate can at least partially overlap with the orthographic projection of the second reflective electrode 305-2 on the plane of the display substrate. For example, the orthographic projection of the second adjustment layer 22 on the plane of the display substrate can include the orthographic projection of the first reflective electrode 305-1 on the plane of the display substrate and the orthographic projection of the second reflective electrode 305-2 on the plane of the display substrate. Portions of the first adjustment layer 21 and the second adjustment layer 22 together constitute part of a first adjustment portion, which is used to enable the first subpixel P1 to have a first microcavity length. The remaining portion of the second adjustment layer 22 constitutes part of a second adjustment portion, which is used to enable the second subpixel P2 to have a second microcavity length.

[0129] (18) Forming a third adjustment layer initial pattern. Forming the third adjustment layer initial pattern may include: depositing a fifth insulating film on a side of the base substrate 101 on which the aforementioned pattern is formed, and patterning the fifth insulating film through a patterning process to form a third adjustment layer initial pattern 23-1 located on a side of the second adjustment layer 22 away from the base substrate 101, as shown in FIG8H.

[0130] As shown in Figure 8H, the orthographic projection of the third adjustment layer initial pattern 23-1 on the plane where the display substrate is located may include the orthographic projection of the first reflective electrode 305-1 on the plane where the display substrate is located, the orthographic projection of the second reflective electrode 305-2 on the plane where the display substrate is located, and the orthographic projection of the third reflective electrode 305-3 on the plane where the display substrate is located.

[0131] As shown in FIG8H , the first adjustment portion 306-1 includes the first adjustment layer 21, a portion of the second adjustment layer 22, and a portion of the third adjustment layer initial pattern 23-1. The second adjustment portion 306-2 includes the remaining portion of the second adjustment layer 22 and a portion of the third adjustment layer initial pattern 23-1. The third adjustment portion 306-3 includes the remaining portion of the third adjustment layer initial pattern 23-1. The third adjustment portion is used to ensure that the third subpixel P3 has a third microcavity length.

[0132] As shown in FIG8H , the third adjustment layer initial pattern 23-1 may have a plurality of second via holes K2. The fourth insulating film and the fifth insulating film within the second via holes K2 are both etched away, exposing a portion of the surface of the first segment 111-1 on a side away from the base substrate 101. The second via holes K2 are configured such that the subsequently formed second segment is located within the via holes.

[0133] As shown in FIG8H , the second via K2 has a first end K11 and a second end K12 that are oppositely disposed. The first end K11 is further away from the reflective layer 305 than the second end K12, and the aperture of the first end K11 is the same as the aperture of the second end K12. The second via K2 can be fabricated using a semi-back etching process, which eliminates the need for a single-layer overlay process. Overlay requires that the upper layer aperture be smaller than the lower layer aperture to ensure overlay accuracy. Adding a single overlay process increases the aperture of the first via K1 by 0.04 to 0.1 microns. Therefore, by making the aperture of the first end K11 the same as the aperture of the second end K12, the aperture of the first via K1 can be reduced.

[0134] (19) Forming a final conductive structure pattern. Forming the final conductive structure pattern may include: depositing a ninth conductive film on one side of the base substrate 101 on which the aforementioned pattern is formed, and patterning the ninth conductive film through a patterning process to form a final conductive structure pattern located within the second via hole K2, as shown in FIG8I .

[0135] As shown in FIG8I , the conductive structure final pattern may include a plurality of second segments 111-2. The second segments 111-2 are located within the second via K2. The surface of the second segments 111-2 facing away from the reflective layer 305 may be substantially flush with the first end K11 of the second via K2. Alternatively, the surface of the second segments 111-2 facing away from the reflective layer 305 may be closer to the reflective layer 305 than the first end K11. The orthographic projection of the second segments 111-2 on the plane of the display substrate may be located within the orthographic projection of the first segments 111-1 on the plane of the display substrate.

[0136] As shown in FIG8I , the first segment 111-1 and the second segment 111-2 within the first subpixel P1 collectively constitute a first conductive structure 111. The first conductive structure 111 is configured such that a first light-emitting device formed subsequently is connected to the first connecting electrode 202-1 via the first conductive structure 111. The first segment 111-1 and the second segment 111-2 within the second subpixel P2 collectively constitute a second conductive structure 112. The second conductive structure 112 is configured such that a second light-emitting device formed subsequently is connected to the second connecting electrode 202-2 via the second conductive structure 112. The first segment 111-1 within the third subpixel P3 is also a third conductive structure 113. The third conductive structure 113 is configured such that a third light-emitting device formed subsequently is connected to the third connecting electrode 202-3 via the third conductive structure 113.

[0137] (20) Forming a third adjustment layer pattern. Forming the third adjustment layer pattern may include: patterning the fifth insulating film located within the third sub-pixel P3 through a patterning process to form the third adjustment layer pattern, as shown in FIG8J .

[0138] As shown in FIG. 8J , the third adjustment layer 23 may have a plurality of second via holes K2 , and the fifth insulating film within the second via holes K2 is etched away to expose a portion of the surface of the first section 111 - 1 away from the base substrate 101 .

[0139] (21) Forming an anode layer pattern. Forming the anode layer pattern may include: depositing a tenth conductive film on a side of the base substrate 101 on which the aforementioned pattern is formed, and patterning the tenth conductive film through a patterning process to form an anode layer pattern located on a side of the third adjustment layer 23 away from the base substrate 101, as shown in FIG8K .

[0140] As shown in Figure 8K, the anode layer pattern may include multiple anodes of multiple light-emitting devices. The multiple anodes are arranged at intervals to avoid electrical connection crosstalk between different light-emitting devices. As shown in Figure 8K, the anode layer pattern may include a first electrode 301-1, a third electrode 302-3, and a fifth electrode 303-5.

[0141] (22) Forming a pixel definition layer pattern. Forming the pixel definition layer pattern may include: sequentially depositing a sixth insulating film, a seventh insulating film, and an eighth insulating film on one side of the substrate 101 on which the aforementioned pattern is formed, and patterning the eighth insulating film through a patterning process to form a pixel definition layer pattern located on the side of the anode layer away from the substrate 101, as shown in FIG8L .

[0142] As shown in FIG8L , the pixel definition layer 308 may include a plurality of partitions 308 a. The partitions 308 a may include a plurality of film layers, which may include a first sublayer 308-1, a second sublayer 308-2, and a third sublayer 308-3 sequentially arranged in a direction away from the reflective layer 305. The orthographic projection of the second sublayer 308-2 on the plane where the display substrate is located may be within the orthographic projection of the first sublayer 308-1 on the plane where the display substrate is located, and the orthographic projection area of ​​the second sublayer 308-2 on the plane where the display substrate is located is smaller than the orthographic projection area of ​​the first sublayer 308-1 on the plane where the display substrate is located. The orthographic projection of the third sub-layer 308-3 on the plane where the display substrate is located includes the orthographic projection of the second sub-layer 308-2 on the plane where the display substrate is located, and the orthographic projection area of ​​the third sub-layer 308-3 on the plane where the display substrate is located is larger than the orthographic projection area of ​​the second sub-layer 308-2 on the plane where the display substrate is located, and the orthographic projection of the third sub-layer 308-3 on the plane where the display substrate is located is within the orthographic projection of the first sub-layer 308-1 on the plane where the display substrate is located. As shown in Figure 8L, the multiple film layers of the partition 308a form a bottom cut structure.

[0143] The materials of the first sub-layer 308-1 and the third sub-layer 308-3 can be SiO x The material of the second sub-layer 308-2 can be SiN x , such a design is conducive to forming an undercut structure. The patterning process for forming the pixel definition layer pattern may include the following four steps:

[0144] In the first step, carbon tetrafluoride (CF4) is used to etch the sixth insulating film, the seventh insulating film and the eighth insulating film, and SiO x With SiN x The etching selectivity is greater than 1.0 and less than 1.5. The etching selectivity refers to the ratio of the etching rate of one material to that of another material under the same etching conditions.

[0145] In the second step, a photoresist layer is formed on one side of the eighth insulating film and etched using an etching gas containing oxygen ions. The orthographic projection of the photoresist layer on the plane of the display substrate is located within the orthographic projection of the eighth insulating film on the plane of the display substrate, and the photoresist layer exposes a portion of the surface of the eighth insulating film on the side facing away from the seventh insulating film.

[0146] In the third step, carbon tetrafluoride (CF4) is used to etch the eighth insulating film not covered by the photoresist layer, SiO x With SiN x The etching selectivity ratio is greater than 1.0 and less than 1.5.

[0147] The fourth step is to use sulfur hexafluoride (SF6) to etch SiN x With SiO x The etching selectivity ratio is greater than 6, SiN x The etching rate is much higher than that of SiO x , so an undercut structure can be formed.

[0148] (23) Forming an organic light-emitting layer pattern. Forming the organic light-emitting layer pattern may include: depositing an organic light-emitting film on one side of the base substrate 101 having the aforementioned pattern formed thereon, and patterning the organic light-emitting film through a patterning process to form an organic light-emitting layer pattern, as shown in FIG8M .

[0149] As shown in FIG8M , the organic light-emitting layer pattern may include a first organic light-emitting layer 301-3, a second organic light-emitting layer 302-5, and a third organic light-emitting layer 303-7. The first organic light-emitting layer 301-3 may be located within the opening region of the first sub-pixel P1, the second organic light-emitting layer 302-5 may be located within the opening region of the second sub-pixel P2, and the third organic light-emitting layer 303-7 may be located within the opening region of the third sub-pixel P3.

[0150] (24) Forming a cathode layer pattern. Forming the cathode layer pattern may include: depositing an eleventh conductive film on one side of the base substrate 101 having the aforementioned pattern formed thereon, and patterning the eleventh conductive film through a patterning process to form a cathode layer pattern, as shown in FIG8N .

[0151] 8N , the cathode layer pattern may include a second electrode 301 - 2 , a fourth electrode 302 - 4 , and a sixth electrode 303 - 6 . For example, the second electrode 301 - 2 , the fourth electrode 302 - 4 , and the sixth electrode 303 - 6 may be an integrated structure connected to each other.

[0152] The present disclosure also provides a display device. The display device includes the display substrate described in any of the preceding embodiments. The display device can be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. The present disclosure is not limited to this.

[0153] Although the embodiments disclosed herein are as described above, the contents described are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or implementations are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the implementations without departing from the scope of the present disclosure.

Claims

1. A display substrate includes a substrate substrate and a light-emitting structure layer on one side of the substrate substrate. The light-emitting structure layer includes a reflective layer and a light-emitting composite layer that are sequentially stacked in a direction away from the substrate substrate. The reflective layer has a plurality of first vias, and the light-emitting composite layer includes a first light-emitting device, a second light-emitting device, and a third light-emitting device arranged in sequence. The light-emitting structure layer further includes a first conductive structure, and the first conductive structure is located between the light-emitting composite layer and the substrate substrate. At least part of the surface of the first light-emitting device contacts at least part of the surface of the first conductive structure on the side away from the substrate substrate. At least part of the first conductive structure is located within the first vias. Along the thickness direction of the display substrate, the first conductive structure includes at least two sections. The projection of the section close to the light-emitting composite layer on the plane of the display substrate is located within the projection of the section adjacent to this section and away from the light-emitting composite layer on the plane of the display substrate, and the area of the projection of the section close to the light-emitting composite layer on the plane of the display substrate is smaller than the area of the projection of the section adjacent to this section and away from the light-emitting composite layer on the plane of the display substrate.

2. The display substrate according to claim 1 includes a plurality of sub-pixels. The plurality of sub-pixels at least include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel includes the first light-emitting device and is configured to emit light of a first color. The second sub-pixel includes a second light-emitting device and is configured to emit light of a second color. The third sub-pixel includes a third light-emitting device and is configured to emit light of a third color, and the first color, the second color, and the third color are all one of the primary colors. The light-emitting structure layer further includes a microcavity adjustment layer. The microcavity adjustment layer is located between the reflective layer and the light-emitting composite layer. The microcavity adjustment layer is configured to make the first sub-pixel, the second sub-pixel, and the third sub-pixel have different microcavity lengths.

3. The display substrate according to claim 2 wherein the microcavity adjustment layer includes a first adjustment part, a second adjustment part, and a third adjustment part arranged in sequence. The first adjustment part is configured to make the first sub-pixel have a first microcavity length H1, and the first adjustment part has a first thickness h1. The second adjustment part is configured to make the second sub-pixel have a second microcavity length H2, and the second adjustment part has a second thickness h2. The third adjustment part is configured to make the third sub-pixel have a third microcavity length H3, and the third adjustment part has a third thickness h3. wherein H1 > H2 > H3, and h1 > h2 > h3.

4. The display substrate according to claim 3 wherein the thickness range of the third adjustment part is from 200 angstroms to 600 angstroms.

5. The display substrate according to claim 4 wherein the thickness range of the first adjustment part is from 1300 angstroms to 1700 angstroms, and the thickness range of the second adjustment part is from 1200 angstroms to 1600 angstroms.

6. The display substrate according to any one of claims 2 to 5, wherein, the microcavity adjustment layer has a plurality of second vias, and the plurality of second vias are arranged in one-to-one correspondence with and communicate with the plurality of first vias; the first conductive structure includes two sections, namely a first section and a second section, and the second section is closer to the light-emitting composite layer than the first section. The first section is located within the first via, and the second section is located within the second via.

7. The display substrate according to claim 6, wherein, the positive projection of the first section on the plane of the display substrate has a first outer edge, and the positive projection of the second section on the plane of the display substrate has a second outer edge; wherein, the first outer edge surrounds the second outer edge, and there is a gap between the first outer edge and the second outer edge, and the range of the gap is greater than or equal to 0.04 micrometers and less than or equal to 0.1 micrometers.

8. The display substrate according to claim 6, wherein, the positive projection of the second section on the plane of the display substrate coincides with the positive projection of the second via on the plane of the display substrate.

9. The display substrate according to claim 6, wherein, the surface of the first section on the side away from the substrate is flush with the surface of the reflective layer on the side away from the substrate; or, the surface of the first section on the side away from the substrate is closer to the substrate than the surface of the reflective layer on the side away from the substrate.

10. The display substrate according to any one of claims 2 to 5, wherein, the microcavity adjustment layer includes a first adjustment part, a second adjustment part, and a third adjustment part arranged in sequence, and the thicknesses of the first adjustment part, the second adjustment part, and the third adjustment part are different; the second adjustment part has a plurality of second vias, and the plurality of second vias are arranged in one-to-one correspondence with and communicate with the plurality of first vias; the light-emitting structure layer further includes a second conductive structure, and the second conductive structure is located between the light-emitting composite layer and the substrate, and the second light-emitting device is in contact with at least part of the surface of the second conductive structure on the side away from the substrate; at least part of the second conductive structure is located within the first via.

11. The display substrate according to any one of claims 3 to 5, wherein, the first light-emitting device includes a first electrode, a first organic light-emitting layer, and a second electrode stacked, and the first electrode is closer to the substrate than the second electrode; wherein, at least part of the first electrode is located on the side of the microcavity adjustment layer away from the substrate.

12. The display substrate according to claim 11, wherein, the microcavity adjustment layer has a plurality of second vias, and the plurality of second vias are arranged in one-to-one correspondence with and communicate with the plurality of first vias; the first electrode includes a first part and a second part connected to each other; the first part is located on the side of the microcavity adjustment layer away from the substrate, and the second part is located within the second via.

13. The display substrate according to claim 12, wherein, Along the aperture direction of the second via hole, the thickness of the second part is greater than or equal to 30% of the thickness of the first part and less than or equal to the thickness of the first part.

14. The display substrate according to claim 12, wherein, the dimension of the second part in the thickness direction of the display substrate does not exceed 50% of the hole depth of the second via hole.

15. The display substrate according to claim 12, wherein, the first electrode further includes a third part, the third part is located on the side of the microcavity adjustment layer away from the substrate, and the third part and the first part are respectively located on opposite sides of the second part.

16. The display substrate according to claim 15, wherein, the dimension range of the orthographic projection of the third part in the plane of the display substrate along the aperture direction of the second via hole is greater than or equal to 0.04 μm and less than or equal to 0.1 μm.

17. The display substrate according to claim 15, wherein, the light-emitting structure layer further includes an isolation layer, the isolation layer is located within the first via hole, and the isolation layer surrounds the first conductive structure; the edge of the orthographic projection of the third part in the plane of the display substrate near the second light-emitting device is located within the range of the orthographic projection of the isolation layer in the plane of the display substrate.

18. The display substrate according to claim 15, wherein, the second light-emitting device includes a third electrode, a second organic light-emitting layer, and a fourth electrode stacked, and the third electrode is closer to the substrate than the fourth electrode; wherein, there is a gap between the orthographic projection of the third part in the plane of the display substrate and the orthographic projection of the third electrode in the plane of the display substrate, and the range of the gap is greater than or equal to 0.2 μm and less than or equal to 0.5 μm.

19. The display substrate according to claim 18, wherein, the gap is greater than the difference between the aperture of the first via hole and the aperture of the second via hole.

20. The display substrate according to claim 18, wherein, the orthographic projection of the third part in the plane of the display substrate is located within the orthographic projection of the first adjustment part in the plane of the display substrate, and the orthographic projection of the third electrode in the plane of the display substrate is located within the orthographic projection of the second adjustment part in the plane of the display substrate.

21. The display substrate according to any one of claims 3 to 5, wherein, the light-emitting structure layer further includes an isolation layer, the isolation layer is located within the first via hole, and the isolation layer surrounds the first conductive structure.

22. The display substrate according to claim 21, wherein, the surface of the isolation layer away from the substrate is flush with the surface of the reflective layer away from the substrate.

23. The display substrate according to claim 21, wherein, the range of the ring width of the isolation layer is greater than or equal to 0.2 μm and less than or equal to 0.3 μm.

24. The display substrate according to claim 21, wherein, the third thickness is greater than the maximum value of the ring width of the isolation layer.

25. A display device, comprising a display substrate as described in any one of claims 1 to 24.

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