Display driving assembly, display module and display device

Abstract

A display driving assembly (300), a display module and a display device. The display driving assembly (300) comprises a driving chip (310), the driving chip (310) comprising a first region (Q1) and a second region (Q2), wherein the first region (Q1) comprises a signal input interface (JK); and the second region (Q2) comprises: a first electrically conductive layer (312) and a first insulating layer (313), which are arranged on a first substrate (311); a plurality of output sub-regions (SC) arranged on the first substrate (311), each output sub-region (SC) comprising a plurality of pin units (YJD), and each pin unit (YJD) comprising a plurality of first pins (YJ1); a plurality of output units (SCD) arranged on the first substrate (311), the output units (SCD) being electrically connected to the plurality of first pins (YJ1) by means of a multiplexing unit (MX); and a first window unit (CKD1) arranged in the first insulating layer (313), the first window unit (CKD1) comprising a plurality of windows, which comprise a plurality of first windows (CK1) and a plurality of second windows (CK2). The plurality of pin units (YJD) comprise first pin units (YJD1) and second pin units (YJD2), the plurality of first windows (CK1) expose some of the first pins (YJ1) of the first pin units (YJD1), the plurality of second windows (CK2) expose some of the first pins (YJ1) of the second pin units (YJD2), and for any two windows of the plurality of first windows (CK1) and the plurality of second windows (CK2), the first pins (YJ1) exposed from the two windows are electrically connected to different output units (SCD).

Description

Display driver component, display module and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display driver component, a display module, and a display device. Background Art

[0002] Currently, driving lines (such as data lines) on a display panel are controlled and driven by a display driver chip, which can be disposed on a printed circuit board (PCB) or a flexible circuit board (FPCB) to form a chip-on-film (COF).

[0003] Compared with the solution of placing the display driver chip on the printed circuit board, the display driver chip can be placed on the side or back side of the display panel through the chip-on-film method, which is conducive to achieving a narrow frame.

[0004] Summary of the Invention

[0005] In one aspect, a display driver component is provided, comprising a driver chip, wherein the driver chip comprises a first area and a second area, the first area and the second area are arranged along a first direction, the first area comprises at least one signal input interface, and the second area comprises: a first substrate; a first conductive layer arranged on the first substrate; a first insulating layer arranged on a side of the first conductive layer away from the first substrate; a plurality of output sub-areas arranged on the first substrate, the plurality of output sub-areas arranged along the second direction, at least one of the output sub-areas comprising a plurality of pin units, the plurality of pin units arranged along the first direction, at least one of the pin units comprising a plurality of first pins; a plurality of output units arranged on the first substrate, at least one of the output units being electrically connected to the plurality of first pins via a multiplexing unit, and different The first pins electrically connected to the output units are different; a first window unit is arranged in the first insulating layer, the first window unit includes a plurality of windows, the plurality of windows in the first window unit include a plurality of first windows and a plurality of second windows, the plurality of second windows are located on a side of the plurality of first windows close to the first area; wherein the plurality of pin units include a first pin unit and a second pin unit, the second pin unit is located on a side of the first pin unit close to the first area, the plurality of first windows expose part of the first pins in the first pin unit, the plurality of second windows expose part of the first pins in the second pin unit, and for any two windows among the plurality of first windows and the plurality of second windows, the first pins exposed by the two windows are electrically connected to different output units.

[0006] According to some exemplary embodiments, the display driver component further includes a flexible circuit board, the flexible circuit board including: a second substrate; a first lead layer and a second lead layer provided on the second substrate, the first lead layer being located on a side of the second substrate facing the driver chip, and the second lead layer being located on a side of the second substrate facing away from the driver chip; a plurality of first leads, a plurality of second leads, and a plurality of first connecting lines provided on the second substrate, the plurality of first leads and the plurality of first connecting lines being located in the first lead layer, the plurality of second leads being located in the second lead layer, and the orthographic projections of the plurality of first connecting lines on the second substrate being located on a side where the orthographic projections of the plurality of first leads on the second substrate are close to the orthographic projection of the first region on the second substrate; wherein the first pin exposed by the first window is electrically connected to the plurality of first leads, and the first pin exposed by the second window is electrically connected to the plurality of second leads through the plurality of first connecting lines.

[0007] According to some exemplary embodiments, the display driving component further includes a flexible circuit board, the flexible circuit board including: a second substrate; a first lead layer and a third lead layer arranged on the second substrate, the first lead layer being located on a side of the second substrate facing the driving chip, and the third lead layer being located between the first lead layer and the second substrate; a plurality of first leads and a plurality of third leads being arranged on the second substrate, the plurality of first leads being located in the first lead layer, the plurality of third leads being located in the third lead layer, and the orthographic projections of the plurality of first leads on the second substrate do not overlap with the orthographic projections of the plurality of second leads on the second substrate; wherein the first pin exposed by the first window is electrically connected to the plurality of first leads, and the first pin exposed by the second window is electrically connected to the plurality of third leads.

[0008] According to some exemplary embodiments, the flexible circuit board further includes: at least one fourth lead layer provided on the second substrate, the at least one fourth lead layer being located between the third lead layer and the second substrate; at least one fourth lead group provided on the second substrate, each fourth lead group including a plurality of fourth leads, the fourth leads in the same fourth lead group being located in the same fourth lead layer, and the fourth leads in different fourth lead groups being located in different fourth lead layers; the plurality of pin units further including at least one third pin unit, the third pin unit being located on a side of the second pin unit away from the first pin unit; at least one fourth lead group provided in the first insulating layer A second window unit, at least one of the second window units includes multiple third windows, and the second window unit is located on the side of the first window unit close to the first area; in at least one of the second window units, the third window exposes the first pin in the same third pin unit, and the third windows of different second window units expose the first pin in different third pin units; in at least one of the third pin units, the first pin exposed by the third window is electrically connected to the fourth lead in at least one of the fourth lead groups, and the first pins in different third pin units are electrically connected to the fourth leads in different fourth lead groups.

[0009] According to some exemplary embodiments, the orthographic projection of the fourth lead in the 2n-1th fourth lead layer on the second substrate defines a first pattern, and the orthographic projection of the fourth lead in the 2nth fourth lead layer on the second substrate defines a second pattern; the orthographic projection of the first pattern on the second substrate partially overlaps with the orthographic projections of the multiple first leads on the second substrate, and the orthographic projection of the second pattern on the second substrate partially overlaps with the orthographic projections of the multiple third leads on the second substrate; and n is a positive integer.

[0010] According to some exemplary embodiments, the first window unit further includes: a third window unit arranged in the first insulating layer, the third window unit including a plurality of fourth windows and a plurality of fifth windows; the plurality of fourth windows expose the first pins in the first pin unit that are not exposed by the first window, and the plurality of fifth windows expose the first pins in the second pin unit that are not exposed by the second window.

[0011] According to some exemplary embodiments, at least one of the multiplexing units includes multiple gating modules, at least one of the gating modules is electrically connected to at least one of the first pins, and different gating modules are electrically connected to different first pins; for any two of the multiple first windows and the multiple second windows, the port numbers of the gating modules electrically connected to the first pins exposed by the two windows are the same.

[0012] According to some exemplary embodiments, the output unit includes a first output unit and a second output unit, and the multiple selection modules of at least one of the multiplexing units include a first selection module; the first output unit is electrically connected to the first pin in the first pin unit through the first selection module of the multiplexing unit, and the second output unit is electrically connected to the first pin in the second pin unit through the first selection module of the multiplexing unit.

[0013] According to some exemplary embodiments, at least one of the pin units includes N first pin groups, and in the same pin unit, at least one of the first pin groups includes a plurality of first pins arranged along the second direction, and the N first pin groups are arranged obliquely along a third direction, and the first direction, the second direction and the third direction intersect with each other; at least one of the first pins includes a first side and a second side arranged opposite to each other along the second direction, and in at least one first pin group YJZ, the first sides of two adjacent first pins define a first range on the first substrate, and the orthographic projections of at least M first pins on the first substrate overlap with the first range; wherein, N and M are both positive integers, and M≥3.

[0014] According to some exemplary embodiments, the first window unit includes multiple first window groups and multiple second window groups, at least one first window group includes multiple first windows arranged along a fourth direction, and at least one second window group includes multiple second windows arranged along the fourth direction; wherein, the multiple first window groups are arranged along the second direction, and the multiple second window groups are arranged along the second direction, and the first direction, the second direction, the third direction and the fourth direction intersect with each other; in at least one first window group, at least one first window exposes the first pin in at least one first pin group, and different first windows expose the first pin in different first pin groups; in at least one second window group, at least one second window exposes the first pin in at least one first pin group, and different second windows expose the first pin in different first pin groups.

[0015] According to some exemplary embodiments, the driver chip also includes: a plurality of second pins arranged on the first substrate; a first anti-static module and a first power compensation module arranged on the first substrate; an electrostatic release interface and a power compensation interface arranged in the first area; wherein, the first anti-static module is electrically connected to the electrostatic release interface through a part of the plurality of second pins, and the first power compensation module is electrically connected to the power compensation interface through another part of the plurality of second pins; the second area includes a first compensation sub-area and a second compensation sub-area, the first compensation sub-area separates two adjacent output sub-areas, the second compensation sub-area is located on the side of the plurality of output sub-areas close to the first area, and the plurality of second pins are located in at least one of the first compensation sub-area and the second compensation sub-area.

[0016] According to some exemplary embodiments, the multiple second pins include an anti-static compensation pin and a power compensation pin; the first anti-static module is electrically connected to the anti-static compensation pin, and the first power compensation module is electrically connected to the power compensation pin; the anti-static compensation pin and the power compensation pin are provided in any two adjacent output sub-areas; and / or, the anti-static compensation pin and the power compensation pin are provided on the side of each output sub-area close to the first area.

[0017] According to some exemplary embodiments, the display driver assembly further includes a flexible circuit board, the flexible circuit board including: a second substrate; a first lead layer disposed on the second substrate, the first lead layer being located on a side of the second substrate facing the driver chip; a fifth lead, a sixth lead, and a seventh lead disposed on the second substrate and located in the first lead layer; wherein the power compensation interface includes a first voltage terminal and a second voltage terminal, the power compensation pins include a first compensation pin and a second compensation pin, the anti-static compensation pin is electrically connected to the electrostatic release interface via the fifth lead, the first compensation pin is electrically connected to the first voltage terminal via the sixth lead, and the second compensation pin is electrically connected to the second voltage terminal via the seventh lead; in the second compensation sub-area, the fourth lead, the fifth lead, and the sixth lead extend along the second direction, and in the first compensation sub-area, the fourth lead, the fifth lead, and the sixth lead are bent toward a side away from the first compensation sub-area; and the orthographic projections of the fourth lead, the fifth lead, and the sixth lead on the first substrate do not overlap.

[0018] According to some exemplary embodiments, the display driver component further includes a flexible circuit board, the flexible circuit board including: a second substrate; a first lead layer provided on the second substrate, the first lead layer being located on a side of the second substrate facing the driver chip, the third lead layer being located between the first lead layer and the second substrate; a fifth lead, a sixth lead, a seventh lead, an eighth lead, a ninth lead, and a tenth lead provided on the second substrate and located in the first lead layer, and a transition portion located in the third lead layer; the fourth lead, the fifth lead, and the sixth lead being located in the first compensation sub-region and extending along the first direction, the eighth lead, the ninth lead, and the tenth lead being located in the second compensation sub-region and extending along the second direction; wherein The power compensation interface includes a first voltage end and a second voltage end, the power compensation pin includes a first compensation pin and a second compensation pin, the anti-static compensation pin is electrically connected to the fifth lead, the first compensation pin is electrically connected to the sixth lead, and the second compensation pin is electrically connected to the seventh lead; the fifth lead is electrically connected to the electrostatic release interface through the eighth lead, the sixth lead is electrically connected to the first voltage end through the ninth lead, and the seventh lead is electrically connected to the second voltage end through the tenth lead; at least two of the fifth lead, the sixth lead, the seventh lead, the eighth lead, the ninth lead and the tenth lead have overlapping orthographic projections on the first substrate, and, in the overlapping area, one of them is transferred through the transfer portion.

[0019] According to some exemplary embodiments, the driver chip further includes: a signal expansion interface arranged in the first area; a signal expansion pin arranged on the first substrate, the signal expansion pin being located in the first compensation sub-area and being located on the side of the multiple second pins away from the first area; the flexible circuit board 320 further includes: a second connecting line and an eleventh lead arranged on the second substrate, the second connecting line being located in the first lead layer, and the eleventh lead being located in the second lead layer; wherein the signal expansion pin is electrically connected to the eleventh lead through the second connecting line, and the eleventh lead is electrically connected to the signal expansion interface.

[0020] According to some exemplary embodiments, at least one first via is provided on the second substrate, a size of the first via is greater than or equal to a spacing between two adjacent first pins in the second direction, the second connecting line and the eleventh lead are electrically connected through the first via, and the first via is located on a side of the signal extension pin away from the first area; wherein, the jth first via is located on a side of the j+1th first via away from the first area, and for the second connecting line and the eleventh lead electrically connected through the j+1th first via, the second connecting line at least partially surrounds the jth first via; and j is a positive integer.

[0021] According to some exemplary embodiments, projections of the second connecting line and the eleventh lead on the first substrate are located between orthographic projections of two adjacent output sub-regions on the first substrate.

[0022] According to some exemplary embodiments, the driver chip also includes a first power supply module and a control module; the first power supply module is electrically connected to the first power supply, and the first power supply module and the first power supply compensation module are electrically connected to at least one of the output sub-areas through the control module, and the control module is configured to: in response to a selection instruction, connect or disconnect the output sub-area electrically connected thereto from the first power supply module, and / or connect or disconnect the output sub-area electrically connected thereto from the first power supply compensation module.

[0023] According to some exemplary embodiments, at least two of the first pins are arranged along the second direction, and at least two of the second pins are arranged along the second direction; in the second direction, two adjacent first pins have a first spacing, and two adjacent second pins have a second spacing, and the second spacing is greater than or equal to the first spacing.

[0024] In another aspect, a display module is provided, wherein the display module includes a display driving component as described in any one of the above.

[0025] In yet another aspect, a display device is provided, wherein the display device includes the display module as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0027] FIG1 schematically shows a pair of scaled display modules;

[0028] FIG2 schematically shows a schematic diagram of a display module in an embodiment of the present disclosure;

[0029] FIG3 schematically shows a plan view of a display panel according to an embodiment of the present disclosure;

[0030] FIG4 schematically shows a plan view of a display driving assembly according to an embodiment of the present disclosure;

[0031] FIG5 schematically shows a schematic diagram of a display driving assembly after being bent according to an embodiment of the present disclosure;

[0032] FIG6 schematically shows one of the plan views of a driver chip according to an embodiment of the present disclosure;

[0033] FIG7 schematically shows a second plan view of a driver chip according to an embodiment of the present disclosure;

[0034] 8A and 8B schematically illustrate schematic diagrams of electrical connections among an output unit, a multiplexing unit, and a plurality of first pins according to an embodiment of the present disclosure;

[0035] FIG9 schematically shows one of the schematic diagrams of the electrical connection between the first pin and the output lead according to an embodiment of the present disclosure. FIG9 only shows the first pin exposed by the first window CK1 and the second window CK2;

[0036] FIG10 schematically shows a schematic diagram of the pin number of the first pin in FIG9 ;

[0037] FIG11 schematically shows a cross-sectional view along the section line BB′ in FIG9 ;

[0038] FIG12 schematically shows a second schematic diagram of electrical connection between the first pin and the output lead according to an embodiment of the present disclosure;

[0039] FIG13 schematically shows a cross-sectional view along the section line CC′ in FIG12 ;

[0040] FIG14 schematically shows a schematic diagram of a second window unit in an embodiment of the present disclosure;

[0041] FIG15 schematically shows a third schematic diagram of electrical connection between the first pin and the output lead according to an embodiment of the present disclosure;

[0042] FIG16 schematically shows a cross-sectional view along the section line DD′ in FIG15 ;

[0043] FIG17 schematically shows one of the schematic diagrams of the second pin according to an embodiment of the present disclosure;

[0044] FIG18 schematically shows a schematic diagram of a first anti-static module and a first power compensation module according to an embodiment of the present disclosure;

[0045] FIG19 schematically shows a second schematic diagram of the second pin according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0047] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0048] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0049] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0050] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0051] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0052] It should be noted that, in this article, the term "same layer" refers to a layer structure formed by patterning a film layer for forming a specific pattern using the same film-forming process and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. Multiple elements, components, structures, and / or parts of the "same layer and the same material" are composed of the same material and are formed through the same patterning process. Generally, multiple elements, components, structures, and / or parts of the "same layer and the same material" have approximately the same thickness.

[0053] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display panel, that is, the dimension along the light emitting direction of the display panel, or the dimension along the normal direction of the display device.

[0054] FIG1 schematically shows a diagram of a display module in a pair of proportions.

[0055] Referring to Figure 1 , in a comparative example, a display module includes a display driver assembly 300 and a display panel 200. The display driver assembly 300 includes a driver chip 110 and a flexible circuit board 120. The driver chip 110 is disposed on the flexible circuit board 120, thereby forming a chip-on-film (COF). For example, the flexible circuit board 120 includes a first substrate 121 and a plurality of first wiring harnesses 122 disposed on the first substrate 121. Each first wiring harness 122 includes a plurality of output traces. The driver chip 110 is electrically connected to the display panel 200 via the plurality of first wiring harnesses 122 disposed on the flexible circuit board 120.

[0056] The driver chip 110 includes: a second substrate 111, and a plurality of output units arranged on the second substrate 111, wherein the output unit may refer to an internal circuit in the driver chip 110 for outputting a data voltage signal and is therefore not shown in the figure. The driver chip 110 also includes: a plurality of first pins Y1 arranged on the second substrate 111. The output units are arranged in a one-to-one correspondence with the first pins Y1, for example, each output unit is electrically connected to a first pin Y1. A plurality of drive lines 210 are provided on the display panel 200, and each first pin Y1 is electrically connected to a drive line 210 through a first wiring harness 122, thereby providing a corresponding drive signal thereto to achieve a display function. Exemplarily, the drive line L may include a data line, and each first pin Y1 is electrically connected to a data line, and different first pins Y1 are electrically connected to different data lines, thereby providing corresponding data voltage signals to each data line.

[0057] On the flexible circuit board 120, each output lead is electrically connected to a first pin Y1 on the driver chip 110, thereby forming an output channel. Currently, display panels have varying resolution requirements. Conventional resolution display panels generally require fewer than 4,000 output channels. High-resolution display panels, on the other hand, have much higher requirements for the number of output channels. For example, some current high-resolution display panels require more than 10,000 output channels.

[0058] To accommodate various output channel requirements of display panels, flexible circuit boards 120 can be configured accordingly. For example, in one example, a flexible circuit board 120 having two lead layers is provided. This flexible circuit board 120 divides the output leads into two lead layers, enabling the provision of up to 4,000 output leads, thereby meeting the output channel requirements of display panels with conventional resolutions. In another example, a flexible circuit board 120 having three lead layers is provided. This flexible circuit board 120 divides the output leads into three lead layers, thereby enabling the provision of more than 4,000 output leads, thereby meeting the output channel requirements of display panels with high resolutions.

[0059] The current driver chip 110 is designed to match the flexible circuit board 120. For example, the first pin Y1 on the driver chip 110 corresponds one-to-one with the output lead on the flexible circuit board 120. Specifically, the output lead includes a first end for electrically connecting to the first pin Y1, and the arrangement of the first pin Y1 and the first end are consistent. Therefore, when dealing with a different flexible circuit board 120, the arrangement of the first pin Y1 on the driver chip 110 needs to be redesigned. Because the output units and the first pin Y1 are also arranged one-to-one, when the arrangement of the first pin Y1 is changed, the internal circuitry of the driver chip, including the output units, must also be modified accordingly, resulting in high design costs and complex implementation.

[0060] In view of this, an embodiment of the present disclosure provides a display driving component, including a driving chip, wherein the driving chip includes a first area and a second area, the first area and the second area are arranged along a first direction, the first area includes at least one signal input interface, and the second area includes: a first substrate, a first conductive layer arranged on the first substrate, a first insulating layer arranged on the side of the first conductive layer away from the first substrate, a plurality of output sub-areas arranged on the first substrate, a plurality of output units arranged on the first substrate, and a first window unit arranged in the first insulating layer.

[0061] In which, multiple output sub-areas are arranged along the second direction, at least one output sub-area includes multiple pin units, multiple pin units are arranged along the first direction, and at least one pin unit includes multiple first pins. At least one output unit is electrically connected to multiple first pins through a multiplexing unit, and different output units are electrically connected to different first pins. The first window unit includes multiple windows, and the multiple windows in the first window unit include multiple first windows and multiple second windows, and the multiple second windows are located on the side of the multiple first windows close to the first area. The multiple pin units include a first pin unit and a second pin unit, and the second pin unit is located on the side of the first pin unit close to the first area. The multiple first windows expose part of the first pins in the first pin unit, and the multiple second windows expose part of the first pins in the second pin unit. For any two windows in the first window unit, the first pins exposed by the two windows are electrically connected to different output units.

[0062] In the embodiment of the present disclosure, the output unit is connected to multiple first pins via a multiplexing unit. Therefore, the number of first pins can be multiplied without changing the internal circuitry of the driver chip, such as the output unit. Furthermore, the first and second windows expose a minimum portion of the multiple first pins, allowing the driver chip to adapt to at least a flexible circuit board with two lead layers. For flexible circuit boards with more lead layers, simply increasing the number of windows and adjusting the multiplexing unit's gear position is sufficient, without requiring changes to the driver chip's internal circuitry. This ensures that the driver chip of the embodiment of the present disclosure has high compatibility.

[0063] The display driving component in the embodiment of the present disclosure will be described in detail below with reference to FIG. 2 to FIG.

[0064] FIG2 schematically shows a schematic diagram of a display module in an embodiment of the present disclosure.

[0065] 2 , the display module includes a display driver component 300 and a display panel 400. The display panel 400 includes a plurality of drive lines 410, and the display driver component 300 is at least configured to provide drive signals to the drive lines 410. For example, the drive lines 410 may include data lines, and accordingly, the drive signals may include data voltage signals. However, the embodiments of the present disclosure are not limited thereto. For example, the drive lines 410 may also include reference signal lines, etc.

[0066] FIG3 schematically shows a plan view of a display panel according to an embodiment of the present disclosure.

[0067] 3 , the display panel includes a display area AA and a peripheral area NA located on at least one side of the display area AA.

[0068] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a polygon (e.g., a rectangle) with straight edges, a circle or an ellipse with curved edges, or a semicircle or a semiellipse with both straight and curved edges. In the embodiment of the present disclosure, the display area AA is provided as a region having a quadrilateral shape with straight edges. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0069] The display panel 400 may further include a base substrate 420 and a plurality of pixel units P disposed on the base substrate 420 and located in the display area AA. The plurality of pixel units P may be arranged in an array along a fifth direction Z1 and a sixth direction Z2. The fifth direction Z1 intersects the sixth direction Z2. For example, the fifth direction Z1 may include the vertical direction in FIG. 3 , and the sixth direction Z2 may include the horizontal direction in FIG. 3 . That is, the fifth direction Z1 and the sixth direction Z2 are perpendicular to each other.

[0070] Each pixel unit P may include multiple sub-pixels PX. For example, the pixel unit P may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. Exemplarily, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0071] The plurality of sub-pixels PX may be arranged in an array along the fifth direction Z1 and the sixth direction Z2, but the embodiments of the present disclosure are not limited thereto. For ease of description, the embodiments of the present disclosure refer to the plurality of sub-pixels PX arranged along the fifth direction Z1 as a column of sub-pixels PX, and the plurality of sub-pixels PX arranged along the sixth direction Z2 as a row of sub-pixels PX.

[0072] The display panel 400 further includes a plurality of gate lines GL and a plurality of data lines DL disposed on the base substrate 420 and located at least in the display area AA. The plurality of data lines DL extend along a fifth direction Z1, and the plurality of gate lines GL extend along a sixth direction Z2. For example, one sub-pixel PX is connected to one data line DL and one gate line GL, sub-pixels PX in the same row are connected to the same gate line GL, sub-pixels PX in different rows are connected to different gate lines GL, sub-pixels PX in the same column are connected to the same data line DL, and sub-pixels PX in different columns are connected to different data lines DL.

[0073] The peripheral area NA may be disposed on at least one side of the display area AA. For example, the peripheral area NA may surround the display area AA. In an embodiment of the present disclosure, the peripheral area NA may include a vertical portion extending in the fifth direction Z1 and a horizontal portion extending in the sixth direction Z2.

[0074] The display panel 400 may further include a gate drive circuit 430 and a display binding terminal 440 that are arranged on the base substrate 420 and located in the peripheral area NA. For example, the gate drive circuit 430 may be located on at least one side of the display area AA. In the embodiment shown in Figure 3, the gate drive circuit 430 is located on the left and right sides of the display area AA, respectively. It should be noted that the left and right sides may be the left and right sides of the display panel 400 (screen) viewed by the human eye during display. For example, the display binding terminal 440 may be located on at least one side of the display area AA. In the embodiment shown in Figure 3, the display binding terminal 440 is located on the lower side of the display area AA. It should be noted that the lower side may be the lower side of the display panel 400 (screen) viewed by the human eye during display. The display binding terminal 440 is used to bind to the display driver component 300.

[0075] It should be noted that although Figure 3 shows that the gate driving circuit 430 is located on the left and right sides of the display area AA and the display binding terminal 440 is located on the lower side of the display area AA, the embodiments of the present disclosure are not limited to this. The gate driving circuit 430 and the display binding terminal 440 can be located at any suitable position in the peripheral area NA.

[0076] In an embodiment of the present disclosure, the gate driver circuit 430 may utilize GOA technology, also known as Gate Driver on Array (GOA). In GOA technology, the gate driver circuit 430 is directly disposed on the array substrate, replacing an external chip. Each GOA unit functions as a first-level shift register, with each shift register level connected to a gate line GL. Each level of shift register sequentially outputs scan signals in turn, achieving progressive scanning of the sub-pixels PX. In some embodiments, each shift register level may also be connected to multiple gate lines GL. This adapts to the development trend of high resolution and narrow bezels in the display panel 400.

[0077] FIG4 schematically shows a plan view of a display driving assembly according to an embodiment of the present disclosure.

[0078] With reference to Figures 2 and 4 , the display driver assembly 300 of the present embodiment includes a driver chip 310 and a flexible circuit board 320. The driver chip 310 is disposed on the flexible circuit board 320 to form a chip-on-film (COF). For example, the flexible circuit board 320 includes a first binding terminal BD1 and a second binding terminal BD2. The first binding terminal BD1 is used to bind to the display panel 400, and the second binding terminal BD2 is used to bind to the printed circuit board (PCB). The driver chip 310 is located between the first binding terminal BD1 and the second binding terminal BD2. The driver chip 310 is electrically connected to the first binding terminal BD1 and, in turn, to the display panel 400 via an output lead 322 located on the flexible circuit board 320. The output lead 322 may include at least one of the first lead, the second lead, the third lead, and the fourth lead, which will be discussed below. The driver chip 310 is electrically connected to the second binding terminal BD1 and, in turn, to the printed circuit board via an input lead 323 located on the flexible circuit board 320.

[0079] It should be noted that, for clarity, the display driver assembly 300 in FIG. 4 is in an unfolded state. In this state, the first binding end BD1 may refer to the upper end of the flexible circuit board 320 , and the second binding end BD2 may refer to the lower end of the flexible circuit board 320 .

[0080] FIG5 schematically shows a schematic diagram of a display driving assembly after being bent according to an embodiment of the present disclosure.

[0081] 5 , after the display driver component 300 is bound to the display panel 400 , the display driver component 300 is in a bent state, with its first binding end BD1 bound to the display binding end 440 on the display panel 400 , and the second binding end BD2 bent to the back side of the display panel 400 , so that it can be bound to the printed circuit board 500 located on the back side of the display panel 400 .

[0082] FIG6 schematically shows one plan view of a driver chip according to an embodiment of the present disclosure, and FIG7 schematically shows a second plan view of a driver chip according to an embodiment of the present disclosure.

[0083] 6 and 7 , the driver chip 310 includes a first region Q1 and a second region Q2, which are arranged along a first direction Y. For example, the first direction Y may be the vertical direction in FIG. The first region Q1 includes at least one signal input interface JK. For example, the first region Q1 includes multiple signal input interfaces JK, which may be arranged along a second direction X. For example, the second direction X may be the horizontal direction in FIG. The signal input interface JK may be electrically connected to the second binding terminal BD2 via an input lead 323 on the flexible printed circuit board 320, and further electrically connected to the printed circuit board 500 via the second binding terminal BD2.

[0084] The second region Q2 includes a first substrate 311, a first conductive layer 312 disposed on the first substrate 311, a first insulating layer 313 disposed on a side of the first conductive layer 312 facing away from the first substrate 311, a plurality of output sub-regions SC disposed on the first substrate 311, a plurality of output cells disposed on the first substrate 311, and a first window cell CKD1 disposed in the first insulating layer 313. The output cells may refer to internal circuits in the driver chip 310 for outputting data voltage signals.

[0085] The multiple output sub-regions SC are arranged along the second direction X, at least one output sub-region SC includes a plurality of pin units YJD, the multiple pin units YJD are arranged along the first direction Y, and at least one pin unit YJD includes a plurality of first pins YJ1.

[0086] In an embodiment of the present disclosure, multiple output sub-areas SC are arranged along the horizontal direction in Figure 6. Optionally, multiple output sub-areas SC are spaced apart from each other. In the area between any two output sub-areas SC, extension pins for functions such as power compensation, anti-static compensation, and signal expansion can be set. The details will be introduced in detail below and will not be repeated here.

[0087] In the embodiment of the present disclosure, the plurality of first pins YJ1 are electrically connected to the first binding end BD1 via an output lead 322 on the flexible circuit board 320. In the same pin unit YJD, the output leads 322 electrically connected to the plurality of first pins YJ1 are located in the same film layer, while the output leads 322 electrically connected to the first pins YJ1 in different pin units YJD are located in different film layers. For example, the first pin YJ1 in the first pin unit YJD is electrically connected to the first lead, and the first pin YJ1 in the second pin unit YJD is electrically connected to the second lead, and the first lead and the second lead are arranged in different layers.

[0088] In the embodiment shown in FIG6 , a plurality of first pins YJ1 arranged along the second direction X are referred to as a row of first pins YJ1 (hereinafter also referred to as a first pin group). Every three rows of first pins YJ1 constitute a pin unit YJD. The first pins YJ1 in different pin units YJD are different. That is, there are no duplicate first pins YJ1 in any two pin units YJD. The plurality of pin units YJD are arranged along the vertical direction in FIG6 .

[0089] 8A and 8B schematically illustrate schematic diagrams of electrical connections among an output unit, a multiplexing unit, and a plurality of first pins according to an embodiment of the present disclosure.

[0090] 6 to 8B , at least one output unit SCD is electrically connected to a plurality of first pins YJ1 through the multiplexing unit MX, and different output units SCD are electrically connected to different first pins YJ1 .

[0091] In an embodiment of the present disclosure, the multiplexing unit MX may include multiple gating modules. For example, the multiple gating modules include a first gating module M1, a second gating module M2, a third gating module M3, a fourth gating module M4, a fifth gating module M5, and a sixth gating module M6. Each gating module is electrically connected to a first pin YJ1, and different gating modules are electrically connected to different first pins YJ1. For example, each first pin YJ1 has a pin number. Referring to FIG8A , the pin numbers of the multiple first pins YJ1 are 101 to 312. For the first output unit SCD in FIG8B , the pin numbers of the first pins YJ1 to which the multiple gating modules are electrically connected are "101," "103," "105," "107," "109," and "111," respectively. For the second output unit SCD in FIG8B , the pin numbers of the first pins YJ1 to which the multiple gating modules are electrically connected are "102," "104," "106," "108," "110," and "112," respectively, and so on. The gating module is configured to activate in response to a gating instruction, thereby connecting the output unit SCD to the corresponding first pin YJ1. Multiple gating modules can be activated sequentially according to a preset timing sequence, and each output unit SCD can output a corresponding drive signal in accordance with the activation timing of the gating module. For example, when the first gating module M1 is activated, the output unit SCD outputs a first drive signal; when the second gating module M2 is activated, the output unit SCD outputs a second drive signal, and so on. Thus, a single output unit SCD can be used to form multiple output channels, thereby increasing the total number of output channels of a single driver chip 310 without changing the number of output units SCD.

[0092] In the embodiment of the present disclosure, the total number of first pins YJ1 on the driver chip 310 can be multiplied by using the multiplexing unit MX without changing the number of output units SCD in the driver chip 310. The total number of first pins YJ1 can even be increased to more than 10,000. The number of windows can then be controlled to determine the actual number of exposed first pins YJ1. Therefore, the driver chip 310 of the present disclosure can adapt to any flexible circuit board 320 regardless of the number of wiring layers.

[0093] Specifically, the first window unit CKD1 includes multiple windows, each of which includes multiple first windows and multiple second windows. The multiple second windows are located on a side of the multiple first windows that is closer to the first region Q1. The multiple pin units YJD include a first pin unit YJD1 and a second pin unit YJD2. The second pin unit YJD2 is located on a side of the first pin unit YJD1 that is closer to the first region Q1. The multiple first windows expose a portion of the first pins YJ1 in the first pin units YJD1, and the multiple second windows expose a portion of the first pins YJ1 in the second pin units YJD2.

[0094] In the embodiments of the present disclosure, the driver chip 310 can be adapted to various flexible circuit boards 320 by adjusting the number and position of the openings in the first insulating layer 313. For example, in one example, the flexible circuit board 320 may include two lead layers, in another example, the flexible circuit board 320 may include three lead layers, and in another example, the flexible circuit board 320 may include four or more lead layers. The embodiments of the present disclosure are not listed one by one.

[0095] In the embodiment of the present disclosure, there can be multiple pin units YJD, each of which is electrically connected to leads on the same layer, and different pin units YJD are electrically connected to leads on different layers. The first insulating layer 313 is provided with at least a first window CK1 and a second window CK2. Through the first window CK1 and the second window CK2, portions of the first pins YJ1 in the first pin unit YJD1 and the second pin unit YJD2 in the driver chip 310 can be exposed. In this way, the driver chip 310 can at least adapt to the flexible circuit board 320 having two lead layers.

[0096] Fig. 9 schematically shows one of the schematic diagrams of the electrical connection between the first pin and the output lead according to an embodiment of the present disclosure, wherein Fig. 9 only shows the first pin exposed by the first window CK1 and the second window CK2.

[0097] Referring to Figure 9 , a flexible circuit board 320 has two lead layers and a plurality of output leads 322. The plurality of output leads 322 include a first lead 3221 located in one of the lead layers and a second lead 3222 located in the other lead layer. The first lead YJ1 exposed by the first window CK1 can be electrically connected to the first lead 3221 on the flexible circuit board 320, while the first lead YJ1 exposed by the second window CK2 can be electrically connected to the second lead 3222 on the flexible circuit board 320 via a first connection line LJ1. Referring to Figures 7 and 9 , the plurality of second windows CK2 are located below the plurality of first windows CK1. In this way, the exposed first pin YJ1 can be divided into two parts, and the two parts are arranged along the first direction Y. This pin distribution method is consistent with the arrangement method of the first lead 3221 and the second lead 3222 mentioned above, so that the flexible circuit board 320 can be directly pressed on the driver chip 310, and the binding of the flexible circuit board 320 and the driver chip 310 can be completed. That is, the driver chip 310 in the embodiment of the present disclosure can adapt to the flexible circuit board 320 with two lead layers.

[0098] FIG. 10 schematically shows a schematic diagram of the pin number of the first pin in FIG. 9 .

[0099] 8A , 8B and 10 , in the embodiment of the present disclosure, for any two windows in the first window unit CKD1 , the first pins YJ1 exposed by the two windows are electrically connected to different output units SCD.

[0100] For the flexible circuit board 320 having two lead layers, through the above method, each output lead 322 on the flexible circuit board 320 can be connected to a corresponding output unit SCD. At this time, only one selection module (for example, the first selection module M1) in the multiplexing unit MX needs to be operated to achieve adaptation of the flexible circuit board 320.

[0101] For a flexible circuit board 320 having multiple lead layers, when the number of its output leads 322 is greater than the number of output units SCD of the driver chip 310, more windows can be opened on the first insulating layer 313 to expose more first pins YJ1. Since one output unit SCD is connected to multiple first pins YJ1 through the multiplexing unit MX, it is only necessary to adjust the gear position of the multiplexing unit MX so that a specified number of selection modules in the multiplexing unit MX are operated to achieve adaptation of this flexible circuit board 320.

[0102] In summary, in the embodiments of the present disclosure, the output unit SCD is connected to multiple first pins YJ1 via the multiplexing unit MX. Therefore, the number of first pins YJ1 can be multiplied without changing the internal circuitry of the driver chip, such as the output unit SCD. Furthermore, the first and second windows CK1 and CK2 expose a minimum portion of the multiple first pins YJ1, enabling the driver chip 320 to adapt to at least a flexible circuit board 310 having two lead layers. For flexible circuit boards 320 with more lead layers, simply increasing the number of windows and adjusting the position of the multiplexing unit MX are sufficient, without requiring changes to the internal circuitry of the driver chip. This ensures that the driver chip 320 of the embodiments of the present disclosure has high compatibility.

[0103] The display driver component 300 of the embodiment of the present disclosure will be further described below with reference to FIG. 2 to FIG. 19 .

[0104] FIG. 11 schematically shows a cross-sectional view along the section line BB′ in FIG. 9 .

[0105] 11 , in some specific embodiments, the display driving assembly 300 further includes a flexible circuit board 320 , which includes a second substrate 324 , a first lead layer 325 and a second lead layer 326 disposed on the second substrate 324 , a plurality of first leads 3221 , a plurality of second leads 3222 , and a plurality of first connection lines LJ1 disposed on the second substrate 324 .

[0106] The first lead layer 325 is located on the side of the second substrate 324 facing the driver chip 310, and the second lead layer 326 is located on the side of the second substrate 324 facing away from the driver chip 310. Multiple first leads 3221 and multiple first connection wires LJ1 are located in the first lead layer 325, and multiple second leads 3222 are located in the second lead layer 326. The orthographic projections of the multiple first connection wires LJ1 on the second substrate 324 are located on a side of the orthographic projections of the multiple first leads 3221 on the second substrate 324 that is close to the orthographic projection of the first region Q1 on the second substrate 324.

[0107] In the embodiment of the present disclosure, two lead layers (a first lead layer 325 and a second lead layer 326) are provided on the flexible circuit board 320. The two lead layers are located on opposite sides of the second substrate 324. Referring to FIG. 11 , the first lead layer 325 is closer to the driver chip 310 than the second substrate 324, and the second substrate 324 is closer to the driver chip 310 than the second lead layer 326.

[0108] The second substrate 324 is provided with a first transfer hole V1 that passes through the second substrate 324. Each first connection line LJ1 is electrically connected to a second lead 3222 through a first transfer hole V1, and different first connection lines LJ1 are electrically connected to different second leads 3222. Because the first transfer hole V1 needs to pass through the second substrate 324, the opening size of the first transfer hole V1 is relatively large and is much larger than the distance d1 between two adjacent first leads YJ1 in the second direction X. Therefore, the first transfer hole V1 is arranged on a side away from the first lead YJ1. For example, in an embodiment of the present disclosure, the first transfer hole V1 is arranged on a side of the first lead YJ1 that is close to the first region Q1, thereby avoiding the first lead YJ1 and each output lead 322, and preventing the first transfer hole V1 from overlapping with the first lead YJ1 and causing different first leads YJ1 to short-circuit.

[0109] The first lead YJ1 exposed by the first window CK1 is electrically connected to the plurality of first lead lines 3221 , and the first lead YJ1 exposed by the second window CK2 is electrically connected to the plurality of second lead lines 3222 via the plurality of first connection lines LJ1 .

[0110] In the embodiment of the present disclosure, for the first pins YJ1 exposed by the first window CK1, each first pin YJ1 is electrically connected to a first lead 3221, and different first pins YJ1 are electrically connected to different first leads 3221. For the first pins YJ1 exposed by the second window CK2, each first pin YJ1 is electrically connected to a first connection line LJ1, and different first pins YJ1 are electrically connected to different first connection lines LJ1. As described above, the first pins YJ1 exposed by the first window CK1 are located on the side of the first pins YJ1 exposed by the second window CK2 away from the first region Q1. Therefore, the first lead 3221 can be made to extend directly from the location of the first pin YJ1 toward the side away from the first region Q1 until it is electrically connected to the first binding end BD1. Since the first transfer hole V1 is arranged on the side of the first pin YJ1 close to the first area Q1, the first connection line LJ1 can be extended from the position of the first pin YJ1 toward the side close to the first area Q1 until it reaches the first transfer hole V1, and then electrically connected to the second lead 3222 at the first transfer hole V1. Thereafter, the second lead 3222 extends toward the side away from the first area Q1 until it is electrically connected to the first binding end BD1.

[0111] Optionally, the orthographic projections of the first lead 3221 and the second lead 3222 on the first substrate 311 are spaced apart, thereby reducing or even avoiding parasitic capacitance between the first lead 3221 and the second lead 3222. For example, in the second direction X, the first lead 3221 and the second lead 3222 are staggered. Exemplarily, the orthographic projection of the first lead 3221 on the first substrate 311 is located between the orthographic projections of two adjacent second leads 3222 on the first substrate 311, or the orthographic projection of the second lead 3222 on the first substrate 311 is located between the orthographic projections of two adjacent first leads 3221 on the first substrate 311. It should be noted that in the embodiments of the present disclosure, "two adjacent second leads 3222" or similar expressions mean that there are no other second leads 3222 between the two second leads 3222.

[0112] Figure 12 schematically illustrates a second schematic diagram of the electrical connection between the first pin and the output lead according to an embodiment of the present disclosure. Figure 13 schematically illustrates a cross-sectional view taken along line CC′ in Figure 12. In addition to showing the first pin YJ1 exposed by the first window CK1 and the second window CK2, Figure 12 also shows the first pin YJ1 exposed by the fourth window CK4 and the fifth window CK5. The fourth window CK4 and the fifth window CK5 will be described in detail below and are not detailed here.

[0113] 12 and 13 , in some specific embodiments, the display driving assembly 300 further includes a flexible circuit board 320 , which includes a second substrate 324 , a first lead layer 325 and a third lead layer 327 disposed on the second substrate 324 , and a plurality of first leads 3221 and a plurality of third leads 3223 disposed on the second substrate 324 .

[0114] The first lead layer 325 is located on the side of the second substrate 324 facing the driver chip 310, and the third lead layer 327 is located between the first lead layer 325 and the second substrate 324. A plurality of first leads 3221 are located in the first lead layer 325, and a plurality of third leads 3223 are located in the third lead layer 327.

[0115] In the embodiment of the present disclosure, the flexible circuit board 320 is also provided with two lead layers (a first lead layer 325 and a third lead layer 327). However, unlike the previous embodiment, these two lead layers are located on the same side of the second substrate 324. Referring to Figure 13, the second lead layer 326 is closer to the driver chip 310 than the second substrate 324, while the first lead layer 325 is closer to the driver chip 310 than the second lead layer 326.

[0116] A second insulating layer 328 is disposed between the first lead layer 325 and the third lead layer 327, insulating and separating the first lead layer 325 and the third lead layer 327. Second transfer holes are provided through the second insulating layer 328. Each second lead 3222 is electrically connected to a first pin YJ1 via a second transfer hole, and different second leads 3222 are electrically connected to different first pins YJ1. Because the second transfer holes do not need to penetrate the second substrate 324, the opening size of the second transfer holes is relatively small and can be smaller than the spacing d1 between two adjacent first pins YJ1. Therefore, the orthographic projection of the second transfer holes on the first substrate 311 can overlap with the first pins YJ1.

[0117] The first lead YJ1 exposed by the first window CK1 is electrically connected to the plurality of first lead lines 3221 , and the first lead YJ1 exposed by the second window CK2 is electrically connected to the plurality of third lead lines 3223 .

[0118] In the embodiment of the present disclosure, for the first pin YJ1 exposed by the first window CK1, each first pin YJ1 is electrically connected to a first lead 3221, and different first pins YJ1 are electrically connected to different first leads 3221. For the first pin YJ1 exposed by the second window CK2, each first pin YJ1 is electrically connected to a second lead 3222, and different first pins YJ1 are electrically connected to different second leads 3222. The first lead 3221 and the third lead 3223 both start from the first pin YJ1 electrically connected thereto, extend toward a side away from the first region Q1, and are electrically connected to the first binding end BD1. Compared to the second lead 3222 in the aforementioned embodiment, the third lead 3223 in this embodiment has a shorter routing distance and lower loss.

[0119] 12 , the orthographic projections of the plurality of first leads 3221 on the second substrate 324 do not overlap with the orthographic projections of the plurality of second leads 3222 on the second substrate 324, thereby reducing or even eliminating parasitic capacitance between the first leads 3221 and the third leads 3223. For example, the first leads 3221 and the third leads 3223 are staggered in the second direction X. For example, the orthographic projection of a first lead 3221 on the first substrate 311 is located between the orthographic projections of two adjacent third leads 3223 on the first substrate 311, or the orthographic projection of a third lead 3223 on the first substrate 311 is located between the orthographic projections of two adjacent first leads 3221 on the first substrate 311.

[0120] It should be noted that, in the embodiment of the present disclosure, a second lead layer 326, a first connecting line LJ1 and a first transfer hole V1 may also be provided, but unlike the aforementioned embodiment, in the embodiment of the present disclosure, the first pin YJ1 electrically connected to the first connecting line LJ1 may be: the first pin YJ1 in a pin unit YJD closest to the first region Q1, the first pin YJ1 in other pin units YJD directly extends toward the first binding end BD1 through the first lead 3221 and the third lead 3223, and is electrically connected thereto, while the first pin YJ1 in the pin unit YJD closest to the first region Q1 first extends toward the first region Q1 through the first connecting line LJ1, and then is connected to the second lead 3222 through the first transfer hole V1, and then extends toward the first binding end BD1 through the second lead 3222 until it is electrically connected to the first binding end BD1.

[0121] Figure 14 schematically illustrates a second window unit according to an embodiment of the present disclosure, Figure 15 schematically illustrates a third schematic diagram of the electrical connection between the first pin and the output lead according to an embodiment of the present disclosure, and Figure 16 schematically illustrates a cross-sectional view along line DD′ in Figure 15. In addition to illustrating the first pin YJ1 exposed by the first window CK1, the second window CK2, the fourth window CK4, and the fifth window CK5, Figure 15 also illustrates the first pin YJ1 exposed by the third window CK3.

[0122] 14 to 16 , in some specific embodiments, the flexible circuit board 320 further includes: at least one fourth lead layer 329 disposed on the second substrate 324 , at least one fourth lead group disposed on the second substrate 324 , and at least one second window unit CKD2 disposed in the first insulating layer 313 .

[0123] Among them, the fourth lead layer 329 is located between the third lead layer 327 and the second base 324, at least one fourth lead group includes multiple fourth leads 3224, the fourth leads 3224 in the same fourth lead group are located in the same fourth lead layer 329, and the fourth leads 3224 in different fourth lead groups are located in different fourth lead layers 329.

[0124] It should be noted that in the embodiment of the present disclosure, the first lead 3221, the second lead 3222, the third lead 3223 and the fourth lead 3224 can also be collectively referred to as output leads 322, each output lead 322 is connected to a first pin YJ1, thereby forming an output channel, and different output leads 322 are connected to different first pins YJ1.

[0125] In the embodiment of the present disclosure, one or more fourth lead layers 329 may be provided on the flexible circuit board 320. The greater the number of fourth lead layers 329, the greater the number of output leads 322 that can be provided on the flexible circuit board 320. The plurality of fourth lead layers 329 are sequentially arranged in a direction approaching the second substrate 324, and each fourth lead layer 329 may be provided with a plurality of fourth leads 3224. A third insulating layer 3210 is provided between two adjacent fourth lead layers 329 to insulate and separate the fourth leads 3224 in the two adjacent fourth lead layers 329.

[0126] The plurality of pin units YJD further include at least one third pin unit YJD3 , and the third pin unit YJD3 is located on a side of the second pin unit YJD2 away from the first pin unit YJD1 .

[0127] In the embodiment of the present disclosure, one or more third pin units YJD3 may be provided on the driver chip 310. The plurality of third pin units YJD3 are arranged in a direction gradually approaching the first region Q1. The greater the number of third pin units YJD3, the more first pins YJ1 are provided on the driver chip 310.

[0128] At least one second window unit CKD2 includes a plurality of third windows CK3, and the second window unit CKD2 is located on a side of the first window unit CKD1 near the first region Q1. In at least one second window unit CKD2, the third window CK3 exposes the first pin YJ1 of the same third pin unit YJD3, while the third window CK3 of a different second window unit CKD2 exposes the first pin YJ1 of a different third pin unit YJD3. In at least one third pin unit YJD3, the first pin YJ1 exposed by the third window CK3 is electrically connected to a fourth lead 3224 in at least one fourth lead group, while the first pin YJ1 of a different third pin unit YJD3 is electrically connected to a fourth lead 3224 in a different fourth lead group.

[0129] In the embodiment of the present disclosure, one or more second window units CKD2 may be provided on the driver chip 310. The plurality of second window units CKD2 are arranged in a direction gradually approaching the first region Q1. The greater the number of second window units CKD2, the more first pins YJ1 are exposed on the driver chip 310.

[0130] In the embodiment of the present disclosure, the second window units CKD2 are arranged in a one-to-one correspondence with the fourth lead layers 329. For example, for each additional fourth lead layer 329 on the flexible circuit board 320, a corresponding second window unit CKD2 can be added to the driver chip 310. With respect to the third pin units YJD3 exposed by the second window units CKD2, each third pin unit YJD3 is also arranged in a one-to-one correspondence with the fourth lead layer 329. For example, for each third pin unit YJD3, the first pin YJ1 therein is electrically connected only to the fourth lead 3224 in the corresponding fourth lead layer 329.

[0131] In the embodiments of the present disclosure, the first window CK1 and the second window CK2 may also be referred to as basic output windows, and the first pins YJ1 exposed by the first window CK1 and the second window CK2 may also be referred to as basic output pins. These basic output pins enable the driver chip 310 to be compatible with at least a flexible circuit board 320 having two lead layers. Accordingly, the third window CK3 may also be referred to as an extended output window. Through the third window CK3, additional first pins YJ1 may be exposed, in addition to the first window CK1 and the second window CK2, thereby enabling the driver chip 310 to be compatible with a flexible circuit board 320 having more lead layers, thereby providing more output channels.

[0132] Optionally, in the same second window unit CKD2, multiple third windows CK3 can expose part of the first pin YJ1 in a third pin unit YJD3. Taking a second window unit CKD2 as an example, when only the first window CK1 and the second window CK2 are provided on the first pin unit YJD1 and the second pin unit YJD2 on the driver chip 310, multiple third windows CK3 can be made to expose part of the first pin YJ1 in the third pin unit YJD3. In this case, the first window CK1, the second window CK2, and the third window CK3 can be arranged in the same manner, so that the first pins YJ1 exposed by these windows are arranged consistently, which is conducive to binding with the flexible circuit board 320.

[0133] It should be noted that the third windows CK3 in the plurality of second window units CKD2 are arranged in the same manner, and therefore, the embodiments of the present disclosure will not be listed one by one.

[0134] 15 , in some specific embodiments, the orthographic projections of the fourth leads 3224 in the 2n-1th fourth lead layer 329 on the second substrate 324 define a first pattern, and the orthographic projections of the fourth leads 3224 in the 2nth fourth lead layer 329 on the second substrate 324 define a second pattern. The orthographic projection of the first pattern on the second substrate 324 partially overlaps with the orthographic projections of the plurality of first leads 3221 on the second substrate 324, and the orthographic projection of the second pattern on the second substrate 324 partially overlaps with the orthographic projections of the plurality of third leads 3223 on the second substrate 324. n is a positive integer.

[0135] In the embodiment of the present disclosure, the first pattern (or the second pattern) may refer to a pattern enclosed by the boundary of the orthographic projection of the fourth lead 3224 on the second substrate 324. In this way, the total area occupied by the output leads 322 can be reduced. At the same time, for any two overlapping output leads 322, there is a lead layer between the two output leads 322. In this way, on the one hand, the two output leads 322 can be kept at a larger distance to reduce the parasitic capacitance between the two, and on the other hand, the lead layer between the two output leads 322 can be used to shield, thereby further reducing the parasitic capacitance between the two output leads 322. For example, the first lead 3221 overlaps with the fourth lead 3224 in the first fourth lead layer 329, and the third lead layer 327 is between them. The third lead 3223 overlaps with the fourth lead 3224 in the second fourth lead layer 329, and the first fourth lead layer 329 is between them, and so on.

[0136] 12 and 15 , in some specific embodiments, the first window unit CKD1 further includes a plurality of fourth windows CK4 and a plurality of fifth windows CK5. The plurality of fourth windows CK4 expose the first pins YJ1 of the first pin unit YJD1 that are not exposed by the first window CK1, and the plurality of fifth windows CK5 expose the first pins YJ1 of the second pin unit YJD2 that are not exposed by the second window CK2.

[0137] In an embodiment of the present disclosure, a plurality of first windows CK1 expose a portion of the first pins YJ1 in the first pin unit YJD1, and a plurality of fourth windows CK4 expose the remaining first pins YJ1 in the first pin unit YJD1, thereby exposing all of the first pins YJ1 in the first pin unit YJD1. A plurality of second windows CK2 expose a portion of the first pins YJ1 in the second pin unit YJD2, and a plurality of fifth windows CK5 expose the remaining first pins YJ1 in the second pin unit YJD2, thereby exposing all of the first pins YJ1 in the second pin unit YJD2.

[0138] Optionally, in the same second window unit CKD2, multiple third windows CK3 can also expose all first pins YJ1 in a third pin unit YJD3. Taking a second window unit CKD2 as an example, when a fourth window CK4 and a fifth window CK5 are provided on the driver chip 310, multiple third windows CK3 can expose all first pins YJ1 in a third pin unit YJD3.

[0139] In an embodiment of the present disclosure, the first window CK1, the second window CK2, the third window CK3, the fourth window CK4 and the fifth window CK5 can also be collectively referred to as output windows. Each output window exposes a first pin YJ1, and different output windows expose different first pins YJ1. Furthermore, all the first pins YJ1 can be exposed, thereby maximizing the output channel.

[0140] 8A and 8B , in some specific embodiments, at least one multiplexing unit MX includes a plurality of gating modules, at least one gating module being electrically connected to at least one first pin YJ1, and different gating modules being electrically connected to different first pins YJ1. For any two of the plurality of first windows CK1 and the plurality of second windows CK2, the gating modules electrically connected to the first pins YJ1 exposed by the two windows have the same port number.

[0141] In an embodiment of the present disclosure, each output unit SCD is connected to multiple first pins YJ1 via a multiplexing unit MX, with different output units SCD being connected to different first pins YJ1. Each multiplexing unit MX includes multiple strobe modules, each of which can be turned on or off in response to a strobe signal. When a strobe module is turned on, it can electrically connect the first pin YJ1 electrically connected to the output unit SCD, thereby allowing the electrical signal of the output unit SCD to be transmitted to the first pin YJ1, and then transmitted to the first binding terminal BD1 of the flexible circuit board 320 via the corresponding output lead 322.

[0142] In the embodiments of the present disclosure, for a multiplexing unit MX, its gating modules can be activated sequentially, and only one gating module can be activated at a time. Accordingly, the output unit SCD can configure the output signal based on the activation order of the gating modules, so that when each gating module is activated, it can output the corresponding output signal.

[0143] For example, when 2000 output units SCD are provided in the driver chip 310, each output unit SCD is connected to a multiplexing unit MX. Assuming that each multiplexing unit MX includes 6 selection modules, 12,000 output signals can be realized. Through a sufficient number of first pins YJ1 and output leads 322 on the flexible circuit board 320, 12,000 output channels can be realized, thereby meeting the output channel quantity requirement of the high-resolution display panel 400.

[0144] In some specific embodiments, the output unit SCD includes a first output unit SCD1 and a second output unit SCD2, and the plurality of strobe modules of the at least one multiplexing unit MX includes a first strobe module. The first output unit SCD1 is electrically connected to the first pin YJ1 of the first pin unit YJD1 via the first strobe module of the multiplexing unit MX, and the second output unit SCD2 is electrically connected to the first pin YJ1 of the second pin unit YJD2 via the first strobe module of the multiplexing unit MX.

[0145] In other words, for any output unit SCD, the first pin YJ1 electrically connected to the first strobe module is located in one of the first pin unit YJD1 and the second pin unit YJD2. In this way, the first pin YJ1 electrically connected to the first strobe module can be grouped into the first pin unit YJD1 and the second pin unit YJD2. In this case, the first pin YJ1 electrically connected to the first strobe module in the first pin unit YJD1 and the second pin unit YJD2 can be exposed through the first window CK1 and the second window CK2, respectively. Simultaneously, only the first strobe module in the multiplexing unit MX is controlled to operate, thereby adapting to the flexible circuit board 320 having two lead layers.

[0146] 8A , in some specific embodiments, at least one pin unit YJD includes N first pin groups YJZ. Within the same pin unit YJD, at least one first pin group YJZ includes a plurality of first pins YJ1 arranged along a second direction X. At least one first pin YJ1 includes a first side S1 and a second side S2 oppositely disposed along the second direction X. In the at least one first pin group YJZ, the orthographic projections of the first sides S1 of two adjacent first pins YJ1 on the first substrate 311 define a first range F1, and the orthographic projections of at least M first pins YJ1 on the first substrate 311 overlap with the first range F1. Here, M ≥ 2.

[0147] 8A , in an embodiment of the present disclosure, for any first pin group YJZ, multiple first pins YJ1 are located in the same row, and first pins YJ1 in different first pin groups YJZ are located in different rows. For example, each pin unit YJD includes three first pin groups YJZ. In other words, each pin unit YJD includes three rows of first pins YJ1.

[0148] In the same pin unit YJD, N first pin groups YJZ are arranged along the third direction, and the first direction Y, the second direction X and the third direction intersect with each other. For two adjacent pin units YJD, the arrangement of the first pin groups YJZ therein can be the same or different. When the first pin groups YJZ of two adjacent pin units YJD adopt the same arrangement, the first pin group YJZ of one of the pin units YJD can be displaced to a certain extent in the second direction X. For example, the second pin unit YJD2 is offset to the right as a whole compared to the first pin unit YJD1. This is conducive to misaligning the output leads 322 electrically connected to the two pin units YJD, thereby reducing wiring bends.

[0149] 8A , the first side S1 of the first lead YJ1 may refer to the left side of the first lead YJ1, and the second side S2 of the first lead YJ1 may refer to the right side of the first lead YJ1. In a first lead group YJZ (or in a row of first leads YJ1), the first sides S1 of two adjacent first leads YJ1 define a first range F1 on the orthographic projection of the first substrate 311. The first range F1 may refer to, for two adjacent first leads YJ1, a range defined by the first side S1 of one as the left boundary and the first side S1 of the other as the right boundary.

[0150] In the embodiment of the present disclosure, the value of M can be calculated based on parameters such as the available width of the driver chip 310 and the width of the output lead 322. Optionally, when the driver chip is provided with two pin units YJD, M can be 6, that is, 6 first pins YJ1 can be provided within the first range F1. When the size of the driver chip 310 only allows 2,000 first pins YJ1 to be provided in one row, this method can expand the number of first pins YJ1 to 12,000.

[0151] Optionally, when three pin units YJD are set in the driver chip, M can be 9, that is, 9 first pins YJ1 can be set within the first range F1. When the size of the driver chip 310 only allows 1,300 first pins YJ1 to be set in a row, in this way, the number of first pins YJ1 can also be expanded to more than 11,000.

[0152] It should be understood that the greater the number of pin units YJD, the larger the value of M, thereby allowing for the expansion of more first pins YJ1. It should be noted that the value of M can be determined based on actual needs, for example, M can also be 4, 8, 12, etc., and the embodiments of this disclosure will not be listed one by one.

[0153] 7 , in some embodiments, the first window unit CKD1 includes a plurality of first window groups CKZ1 and a plurality of second window groups CKZ2. At least one first window group CKZ1 includes a plurality of first windows CK1 arranged along a fourth direction, and at least one second window group CKZ2 includes a plurality of second windows CK2 arranged along the fourth direction. The plurality of first window groups CKZ1 are arranged along a second direction X, and the plurality of second window groups CKZ2 are arranged along the second direction X. The first direction Y, the second direction X, the third direction, and the fourth direction intersect with each other.

[0154] 7 , the first window group CKZ1 may include a row of first windows CK1 arranged at an angle, and the second window group CKZ2 may include a row of second windows CK2 arranged at an angle. For example, the degree of inclination in the fourth direction is greater than the degree of inclination in the third direction, thereby facilitating alignment of the exposed first lead YJ1 with the arrangement of the output leads 322 on the flexible circuit board 320. The degree of inclination in the third direction (or fourth direction) may refer to the degree of inclination of the third direction (or fourth direction) relative to the first direction Y (vertical direction). For example, the greater the angle between the third direction (or fourth direction) and the first direction Y, the greater the degree of inclination.

[0155] 7 , 8A , and 11 , in at least one first window group CKZ1, at least one first window CK1 exposes a first pin YJ1 in at least one first pin group YJZ, and different first windows CK1 expose first pins YJ1 in different first pin groups YJZ. In at least one second window group CKZ2, at least one second window CK2 exposes a first pin YJ1 in at least one first pin group YJZ, and different second windows CK2 expose first pins YJ1 in different first pin groups YJZ.

[0156] Referring to Figure 8A , in each pin unit YJD, the multiple first pins YJ1 arranged along the second direction X (i.e., a first pin group YJZ) are referred to as a row of first pins YJ1, and the multiple first pins YJ1 arranged along the third direction are referred to as a column of first pins YJ1. Each first window group CKZ1 includes multiple first windows CK1 arranged along the fourth direction. Taking the first pin unit YJD1 as an example, in the first window group CKZ1, the first first window CK1 exposes the first pin YJ1 in the first row and first column, the second first window CK1 exposes the first pin YJ1 in the second row and first column, the third first window CK1 exposes the first pin YJ1 in the third row and first column, and so on.

[0157] The second pin unit YJD2 and the second window CK2 can be configured in the same manner, so they will not be described in detail here.

[0158] In the embodiment of the present disclosure, it is assumed that a total of 12,000 first pins YJ1 are provided on the driver chip 310, and 2,000 output units SCD are provided in the driver chip 310. Then, the multiplexing unit MX can include 6 strobe modules. In this case, each output unit SCD can be electrically connected to six first pins YJ1 through one multiplexing unit MX, so that the 2,000 output units SCD can be electrically connected to the 12,000 first pins YJ1 respectively.

[0159] In the embodiment of the present disclosure, to accommodate a flexible circuit board 320 having at least two lead layers, 2,000 output units (SCD) are divided into 1,000 first output units (SCD1) and 1,000 second output units (SCD2). Thus, one first output unit (SCD1) and one second output unit (SCD2) are electrically connected to a total of 12 first pins (YJ1). Therefore, these 12 first pins (YJ1) can be considered a minimum sequence unit (SMU). Based on this SMU, the 12,000 first pins (YJ1) are labeled with pin numbers. With reference to Figures 8A and 8B , 36 first pins (YJ1) constitute a minimum repeating unit (SMU).

[0160] In an embodiment of the present disclosure, in a plurality of pin units YJD, the pin numbers of the first pins YJ1 located in the same row and column are connected in sequence. Referring to Figure 8A, three pin units YJD are provided on the driver chip 310, and each pin unit YJD includes three rows of first pins YJ1. In an embodiment of the present disclosure, the first pins YJ1 in the first row and first column of the three pin units YJD are first marked with pin numbers in sequence, which are "101", "102", and "103" respectively. Afterwards, the first pins YJ1 in the second row and first column of the three pin units YJD are marked with pin numbers in sequence, which are "104", "105", and "106" respectively. Afterwards, the first pins YJ1 in the third row and first column of the three pin units YJD are marked with pin numbers in sequence, which are "107", "108", and "109" respectively. Afterwards, the first pins YJ1 in the first row and second column of the three pin units YJD are marked with pin numbers in sequence, which are "110", "111", and "112" respectively. At this point, the pin numbers of a minimum-numbered unit (12 pin numbers) have been marked. Next, the next round of pin marking begins, starting with the first pin YJ1 in the second row and second column of the three-pin unit YJD, until all 12 pin numbers are marked. This continues in this manner, completing the marking of a minimum-numbered repeating unit.

[0161] Optionally, in an embodiment of the present disclosure, the first output unit SCD1 is electrically connected to the first pin YJ1 with an odd pin number through the multiplexing unit MX. For example, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "01" through the first selection module M1, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "03" through the second selection module M2, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "05" through the third selection module M3, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "07" through the fourth selection module M4, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "09" through the fifth selection module M5, and the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "11" through the sixth selection module M6.

[0162] Optionally, the second output unit SCD2 is electrically connected to the first pin YJ1 with an even pin number through the multiplexing unit MX. For example, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "02" through the first selection module M1, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "04" through the second selection module M2, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "06" through the third selection module M3, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "08" through the fourth selection module M4, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "10" through the fifth selection module M5, and the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "12" through the sixth selection module M6.

[0163] At this point, the first pin YJ1 electrically connected to each output cell SCD is dispersed across the three pin units YJD. Meanwhile, the first pin YJ1 electrically connected to each output cell SCD via the first selection module M1 is concentrated in the first pin unit YJD1 and the second pin unit YJD2. Subsequently, depending on the type of flexible printed circuit board 320, it can be determined which first pins YJ1 on the driver chip 310 are exposed.

[0164] For example, when only the first lead layer 325 and the second lead layer 326 of the aforementioned embodiment are provided on the flexible circuit board 320, a first window unit CKD1 can be provided to expose the first pin YJ1 electrically connected to the first selection module M1 in the first pin unit YJD1 and the second pin unit YJD2. For example, taking the first pin unit YJD1 as an example, within a first window group CKZ1, the first first window CK1 exposes the first pin YJ1 in the first row and first column, the second first window CK1 exposes the first pin YJ1 in the second row and second column, and the third first window CK1 exposes the first pin YJ1 in the third row and third column. Thus, the first pin YJ1 exposed by each first window CK1 is electrically connected to the first selection module M1, and the first pin YJ1 exposed by different first windows CK1 is electrically connected to different output units SCD.

[0165] Taking the second pin unit YJD2 as an example, in a second window group CKZ2, the first second window CK2 exposes the first pin YJ1 in the first row and first column, the second second window CK2 exposes the first pin YJ1 in the second row and second column, and the third second window CK2 exposes the first pin YJ1 in the third row and third column. Thus, the first pin YJ1 exposed by each second window CK2 is electrically connected to the first selection module M1, and the first pin YJ1 exposed by different second windows CK2 is electrically connected to different output units SCD. Furthermore, for any first window CK1 and second window CK2, the first pin YJ1 exposed by both is also electrically connected to different output units SCD. Furthermore, the arrangement of the first window CK1 and the second window CK2 allows the flexible circuit board 320 having two lead layers to be directly pressed onto the driver chip 310, thereby completing the binding alignment, thereby simplifying the binding process and reducing the number of transfer structures.

[0166] When the flexible circuit board 320 is provided with the first lead layer 325, the third lead layer 327 and the fourth lead layer 329 in the aforementioned embodiment and has 12,000 output leads 322, the embodiment of the present disclosure can expose all the first pins YJ1 through the first window CK1 to the fifth window CK5, thereby forming 12,000 output channels.

[0167] It should be noted that the above is merely an exemplary description and does not constitute a limitation on the embodiments of the present disclosure. For example, in a first window group CKZ1 (or a second window group CKZ2), multiple first windows CK1 (or second windows CK2) may also be arranged along the second direction X. In this case, the connection method between the first pin YJ1 and the output unit SCD needs to be adaptively adjusted as long as these first windows CK1 (or second windows CK2) can expose the required first pin YJ1.

[0168] FIG17 schematically shows one schematic diagram of a second pin according to an embodiment of the present disclosure, and FIG18 schematically shows a schematic diagram of a first anti-static module and a first power compensation module according to an embodiment of the present disclosure.

[0169] 17 and 18 , in some specific embodiments, the driver chip 310 further includes: a plurality of second pins YJ2 arranged on the first substrate 311, a first anti-static module 510 and a first power compensation module 520 arranged on the first substrate 311, and an electrostatic release interface EK and a power compensation interface VK arranged in the first area Q1.

[0170] The first anti-static module 510 is electrically connected to the electrostatic discharge interface EK via a portion of the plurality of second pins YJ2, and the first power compensation module 520 is electrically connected to the power compensation interface VK via another portion of the plurality of second pins YJ2. The second region Q2 includes a first compensation sub-area BC1 and a second compensation sub-area BC2. The first compensation sub-area BC1 separates two adjacent output sub-areas SC. The second compensation sub-area BC2 is located on one side of the plurality of output sub-areas SC that is closer to the first region Q1. The plurality of second pins YJ2 are located in at least one of the first compensation sub-area BC1 and the second compensation sub-area BC2.

[0171] 17 , the electrostatic discharge interface EK and the power compensation interface VK are located at the lower end of the driver chip 310. Optionally, the signal input interface JK may include a plurality of third pins YJ3, and the plurality of third pins YJ3 may be arranged along the second direction X. The third pins YJ3 may be electrically connected to the input leads 323 on the flexible circuit board 320, thereby providing input signals to the driver chip 310. The electrostatic discharge interface EK and the power compensation interface VK may be arranged in the same row as the plurality of third pins YJ3. For example, the electrostatic discharge interface EK and the power compensation interface VK may be located between two adjacent third pins YJ3. However, the embodiments of the present disclosure are not limited to this. For example, in some embodiments, the electrostatic discharge interface EK and the power compensation interface VK are arranged in the same row, and the plurality of third pins YJ3 are located separately in a row.

[0172] In an embodiment of the present disclosure, the electrostatic discharge interface EK and the power compensation interface VK can be electrically connected to the second binding end BD2 through the leads on the flexible circuit board 320, and then electrically connected to devices such as the printed circuit board 500 located on the back side of the display panel 400, thereby forming an electrostatic release path and a power reinforcement path.

[0173] Compared to the conventional driver chip 310, the number of first pins YJ1 in the embodiment of the present disclosure is significantly increased. Therefore, the embodiment of the present disclosure adds a first anti-static module 510, a first power compensation module 520, a second pin YJ2, an electrostatic discharge interface EK, and a power compensation interface VK to the driver chip 310. The first anti-static module 510 is electrically connected to the electrostatic discharge interface EK through the second pin YJ2 on the one hand, and can also be electrically connected to the first circuit DL1 in the output sub-area SC on the other hand, thereby performing anti-static compensation on the first circuit DL1. Correspondingly, the first power compensation module 520 is electrically connected to the power compensation interface VK through the second pin YJ2 on the one hand, and can also be electrically connected to the second circuit DL2 in the output sub-area SC on the other hand, thereby performing power compensation on these second circuits DL2. It should be noted that the first circuit DL1 and the second circuit DL2 in the output sub-area SC include but are not limited to: various circuits connected between the output unit SCD and the first pin YJ1, these circuits can process the signal output by the output unit SCD and transmit the processed signal to the first pin YJ1, for example, these circuits may include the multiplexing unit MX in the aforementioned embodiment, etc.

[0174] Optionally, the first anti-static module 510 may include a power clamp circuit, and the first power compensation module 520 may include a power bias control circuit. The embodiment of the present disclosure is equivalent to providing anti-static compensation and power compensation to the relevant circuits in the output sub-area SC in the form of an external compensation circuit.

[0175] In some specific embodiments, the plurality of second pins YJ2 include an anti-static compensation pin EYJ and a power compensation pin VYJ.

[0176] The first anti-static module 510 is electrically connected to the anti-static compensation pin EYJ, and the first power compensation module 520 is electrically connected to the power compensation pin VYJ.

[0177] In some embodiments, anti-static compensation pins EYJ and power compensation pins VYJ are provided in any two adjacent output sub-areas SC, so that multiple anti-static compensation pins EYJ and power compensation pins VYJ are evenly distributed among multiple output sub-areas SC.

[0178] In some embodiments, each output sub-region SC is provided with an anti-static compensation pin EYJ and a power compensation pin VYJ on a side close to the first region Q1, so that the multiple anti-static compensation pins EYJ and power compensation pins VYJ are evenly distributed under the multiple output sub-regions SC.

[0179] In this way, as many anti-static compensation pins EYJ and power compensation pins VYJ as possible can be provided around each output sub-region SC to reduce compensation blind spots.

[0180] It should be noted that the arrangement of the anti-static compensation pin EYJ and the power compensation pin VYJ can be determined according to actual needs, and the embodiments of the present disclosure do not limit this. For example, between two adjacent output sub-areas SC, the number of anti-static compensation pins EYJ and power compensation pins VYJ can be the same or different, but between each two output sub-areas SC, the arrangement of the anti-static compensation pin EYJ and the power compensation pin VYJ can be consistent, thereby improving the uniformity of the pin arrangement.

[0181] In some specific embodiments, the display driving component 300 also includes a flexible circuit board 320, which includes: a second substrate 324, a first lead layer 325 arranged on the second substrate 324, a fifth lead 3225, a sixth lead 3226 and a seventh lead 3227 arranged on the second substrate 324 and located in the first lead layer 325.

[0182] The first lead layer 325 is located on the side of the second substrate 324 facing the driver chip 310. For details, please refer to the previous embodiment and will not be repeated here. The power compensation interface VK includes a first voltage terminal V1 and a second voltage terminal V2. The power compensation pin VYJ includes a first compensation pin VYJ1 and a second compensation pin VYJ2. The anti-static compensation pin EYJ is electrically connected to the electrostatic discharge interface EK via a fifth lead 3225. The first compensation pin VYJ1 is electrically connected to the first voltage terminal V1 via a sixth lead 3226. The second compensation pin VYJ2 is electrically connected to the second voltage terminal V2 via a seventh lead 3227. For example, one of the first voltage terminal V1 and the second voltage terminal V2 can be used to provide a high-level voltage signal, while the other can be used to provide a low-level voltage signal.

[0183] In the embodiment of the present disclosure, the flexible circuit board 320 may be the flexible circuit board 320 including the first lead layer 325 and the second lead layer 326 as described in the aforementioned embodiment. When the fifth lead 3225 (sixth lead 3226 and seventh lead 3227) needs to be connected via a via, a hole needs to be drilled in the second substrate 324 of the flexible circuit board 320 to allow the fifth lead 3225 (sixth lead 3226 and seventh lead 3227) to pass through the via hole and connect to the corresponding lead in the second lead layer 326. However, as mentioned above, if a hole is drilled in the second substrate 324, the hole diameter is generally large, which can easily lead to problems such as short circuits.

[0184] In view of this, in the embodiment of the present disclosure, in the second compensation sub-region BC2, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 extend along the second direction X. In the first compensation sub-region BC1, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 are bent toward a side away from the first compensation sub-region BC1. The orthographic projections of the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 on the first substrate 311 do not overlap.

[0185] Referring to FIG17 , in the second compensation sub-area BC2, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 extend horizontally in the figure. In the first compensation sub-area BC1, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 all bend upward, with substantially the same orientation, but without overlapping, thereby forming a nested structure. This arrangement allows multiple ESD compensation pins EYJ (the first compensation pin VYJ1 or the second compensation pin VYJ2) to be electrically connected via the same fifth lead 3225 (the sixth lead 3226 or the seventh lead 3227), thereby reducing the number of wiring traces. Furthermore, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 can be kept from overlapping, thereby avoiding wiring crossover and eliminating the need for drilling holes in the second substrate 324.

[0186] In some specific embodiments, the driver chip 310 further includes a signal expansion interface KZ disposed in the first region Q1 and a signal expansion pin KZYJ disposed on the first substrate 311. The flexible circuit board 320 further includes a second lead layer 326, a second connection line LJ2, and an eleventh lead 32211 disposed on the second substrate 324. The second connection line LJ2 is located in the first lead layer 325, and the eleventh lead 32211 is located in the second lead layer 326.

[0187] The signal extension pin KZYJ is located in the first compensation sub-area BC1 and on the side of the plurality of second pins YJ2 away from the first region Q1. The signal extension pin KZYJ is electrically connected to the eleventh lead 32211 via the second connection line LJ2, and the eleventh lead 32211 is electrically connected to the signal extension interface KZ.

[0188] In the embodiment of the present disclosure, the signal expansion pins KZYJ are used to connect additional signals, such as digital signals, to the relevant circuits in the output sub-area SC. Referring to Figure 17 , the signal expansion pins KZYJ are located above the second pin YJ2. The number and arrangement of the signal expansion pins KZYJ can be determined based on actual needs and are not limited in the embodiment of the present disclosure.

[0189] In the embodiment of the present disclosure, the second connection line LJ2 starts at the signal expansion interface KZ and extends toward the side away from the first region Q1. After reaching the designated position, it is electrically connected to the eleventh lead 32211 in the second lead layer 326 through a via hole provided in the second substrate 324. The eleventh lead 32211 extends toward the side closer to the first region Q1 until it is electrically connected to the signal expansion interface KZ located in the first region Q1. The signal expansion interface KZ can be electrically connected to the second binding terminal BD2 via the leads on the flexible circuit board 320, and then electrically connected to devices such as the printed circuit board 500 located on the back side of the display panel 400, thereby forming a signal expansion path.

[0190] In some specific embodiments, at least one first via H1 is provided on the second substrate 324. The size of the first via H1 is greater than or equal to the distance between two adjacent first pins YJ1 in the second direction X. The second connecting line LJ2 and the eleventh lead 32211 are electrically connected through the first via H1. The first via H1 is located on the side of the signal extension pin KZYJ away from the first region Q1.

[0191] Among them, the j-th first via H1 is located on the side of the j+1-th first via H1 away from the first region Q1, for the second connecting line LJ2 and the eleventh lead 32211 electrically connected through the j+1-th first via H1, the orthographic projection of the eleventh lead 32211 on the second substrate 324 at least partially surrounds the orthographic projection of the j-th first via H1 on the second substrate 324, and j is a positive integer.

[0192] Referring to Figure 17, the j-th first via H1 is located above the j+1-th first via H1. For the second connecting line LJ2 and the eleventh lead 32211 electrically connected through the j+1-th first via H1, the eleventh lead 32211 is divided into two bundles, which are respectively located on the left and right sides of the j+1-th first via H1, and in the second compensation sub-area BC2, one bundle extends toward the left and the other bundle extends toward the right, so that the same signal extension pin KZYJ can be connected to the same eleventh lead 32211.

[0193] In the embodiment of the present disclosure, a plurality of first vias H1 may be provided on the second substrate 324. In addition to the first vias H1, the second substrate 324 may also be provided with second vias H2. The second vias H2 are used to connect the first connection line LJ1 to the second lead 3222. With reference to FIG9 and FIG17 , the orthographic projection of the first vias H1 on the second substrate 324 is located outside the orthographic projection of the driver chip 310 on the second substrate 324. Optionally, the orthographic projection of the second vias H2 on the second substrate 324 is located within the orthographic projection of the output sub-region SC on the second substrate 324. Optionally, the opening sizes of the first vias H1 and the second vias H2 are substantially the same.

[0194] In some specific embodiments, the projections of the second connection line LJ2 and the eleventh lead line 32211 on the first substrate 311 are located between the orthographic projections of two adjacent output sub-regions SC on the first substrate 311. Referring to FIG17 , the second connection line LJ2 and the eleventh lead line 32211 do not pass through the output sub-region SC, thereby avoiding interference with the leads in the output sub-region SC.

[0195] It should be noted that FIG17 only shows two output sub-areas SC and their surrounding structures on the driver chip 310. It can be understood that in the embodiment of the present disclosure, any two output sub-areas SC and their surrounding structures can be the same as this, so the embodiment of the present disclosure will not be repeated.

[0196] FIG19 schematically shows a second schematic diagram of the second pin according to an embodiment of the present disclosure.

[0197] 18 and 19 , in some specific embodiments, the display driving assembly 300 further includes a flexible circuit board 320 , which includes: a second substrate 324 , a fifth lead 3225 , a sixth lead 3226 , a seventh lead 3227 , an eighth lead 3228 , a ninth lead 3229 , and a tenth lead 32210 disposed on the second substrate 324 and located in the first lead layer 325 , and a transition portion located in the third lead layer 327 .

[0198] In an embodiment of the present disclosure, the flexible circuit board 320 may be the flexible circuit board 320 including the first lead layer 325 and the third lead layer 327 in the aforementioned embodiment. Since the first lead layer 325 and the third lead layer 327 are located on the same side of the second substrate 324, when the fifth lead 3225 (sixth lead 3226 and seventh lead 3227) need to be bridged, it is only necessary to punch a hole in the insulating layer between the first lead layer 325 and the third lead layer 327. The hole diameter is small, so problems such as short circuits can be avoided.

[0199] Specifically, the first lead layer 325 is located on the side of the second substrate 324 facing the driver chip 310, and the third lead layer 327 is located between the first lead layer 325 and the second substrate 324. For details, please refer to the previous embodiment and will not be repeated here. The fourth lead 3224, the fifth lead 3225, and the sixth lead 3226 are located in the first compensation sub-area BC1 and extend along the first direction Y. The eighth lead 3228, the ninth lead 3229, and the tenth lead 32210 are located in the second compensation sub-area BC2 and extend along the second direction X. The power compensation interface VK includes a first voltage terminal V1 and a second voltage terminal V2. The power compensation pin VYJ includes a first compensation pin VYJ1 and a second compensation pin VYJ2. The anti-static compensation pin EYJ is electrically connected to the fifth lead 3225, the first compensation pin VYJ1 is electrically connected to the sixth lead 3226, and the second compensation pin VYJ2 is electrically connected to the seventh lead 3227. The fifth lead 3225 is electrically connected to the electrostatic discharge interface EK via the eighth lead 3228. The sixth lead 3226 is electrically connected to the first voltage terminal V1 via the ninth lead 3229. The seventh lead 3227 is electrically connected to the second voltage terminal V2 via the tenth lead 32210. The orthographic projections of at least two of the fifth lead 3225, the sixth lead 3226, the seventh lead 3227, the eighth lead 3228, the ninth lead 3229, and the tenth lead 32210 on the first substrate 311 overlap, and in the overlapping region, one of the leads is connected via a transition portion.

[0200] 19 , in the second compensation sub-area BC2, the eighth lead 3228, the ninth lead 3229, and the tenth lead 32210 extend in the horizontal direction in the figure. In the first compensation sub-area BC1, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 all extend in the first direction Y. The ninth lead 3229 overlaps with the fifth lead 3225 and therefore requires a jumper connection. The tenth lead 32210 overlaps with both the fifth lead 3225 and the sixth lead 3226 and therefore requires two jumpers. This approach reduces the wiring length, thereby reducing electrical loss on these leads.

[0201] 18 , in some specific embodiments, the driver chip 310 further includes a first power supply module 530 and a control module 540. The first power supply module 530 is electrically connected to the first power source 550. The first power supply module 530 and the first power compensation module 520 are electrically connected to at least one output sub-region SC via the control module 540. The control module 540 is configured to, in response to a control instruction, connect or disconnect the output sub-region SC electrically connected thereto from the first power supply module 530 and / or connect or disconnect the output sub-region SC electrically connected thereto from the first power compensation module 520 during a frame period.

[0202] In the embodiment of the present disclosure, the first power supply module 530 can be the basic power supply module originally included in the driver chip 310, and the power compensation module is a newly added power supply module in the embodiment of the present disclosure. The control module 540 can control whether to supply power to the output sub-region SC during a frame cycle to achieve partial refresh. For example, during a frame cycle, the control module 540 disconnects the output sub-region SC electrically connected thereto from both the first power supply module 530 and the first power compensation module 520. At this time, power supply to the output sub-region SC is stopped during the frame cycle. Then, during the frame cycle, the data line electrically connected to the first pin YJ1 in the output sub-region SC will maintain the data voltage signal of the previous frame, and then the columns of sub-pixels electrically connected to these data lines will maintain the display image of the previous frame. The control module 540 turns on the output sub-area SC electrically connected to it and the first power supply module 530 and the first power compensation module 520. At this time, during the frame period, power is continued to be supplied to the output sub-area SC. Then, during the frame period, the data line electrically connected to the first pin YJ1 in the output sub-area SC is refreshed to a new data voltage signal, and then, several columns of sub-pixels electrically connected to these data lines are refreshed to a new display screen.

[0203] That is, in the embodiments of the present disclosure, the power supply state of each output sub-area SC can be independently controlled during each frame period, thereby controlling whether several columns of sub-pixels retain the previous frame image. Thus, the display area AA can be divided into multiple first display sub-areas based on several columns of sub-pixels. That is, in the row direction, the display area AA can be divided into multiple first display sub-areas, and the refresh state of each first display sub-area can be controlled to achieve partial refresh.

[0204] In some specific embodiments, the gate lines GL can also be used to control whether several rows of sub-pixels PX maintain the previous frame. For example, in one frame period, a valid signal is selected to be provided to the gate lines GL of several rows of sub-pixels PX so that the current data voltage signal on the data line DL can be written into the sub-pixel PX. At this time, these rows of sub-pixels PX can refresh the picture. In this frame period, an invalid signal is selected to be provided to the gate lines GL of another several rows of sub-pixels PX. At this time, the current data voltage signal on the data line DL will not be written into the sub-pixel PX, and these rows of sub-pixels PX will maintain the previous frame. Thus, the embodiments of the present disclosure can divide the display area AA into multiple second display sub-areas based on several rows of sub-pixels PX, that is, divide the display area AA into multiple second display sub-areas in the column direction.

[0205] In this way, multiple first display sub-areas and multiple second display sub-areas intersect with each other, and the overlapping area between the two can define multiple display blocks. Therefore, the embodiment of the present disclosure can achieve local refresh based on the display block as the dimension, with more precise control, which is conducive to reducing power consumption.

[0206] 17 and 19 , in some specific embodiments, at least two first pins YJ1 are arranged along the second direction X, and at least two second pins YJ2 are arranged along the second direction X;

[0207] In the second direction X, two adjacent first pins YJ1 have a first distance therebetween, and two adjacent second pins YJ2 have a second distance therebetween, and the second distance is greater than or equal to the first distance.

[0208] In the embodiments of the present disclosure, the first spacing may refer to the average spacing or maximum spacing between two adjacent first pins YJ1; the second spacing may refer to the average spacing or maximum spacing between two adjacent second pins YJ2. The second spacing is used to adjust the number of second pins YJ2 that can be placed between two adjacent output sub-regions SC.

[0209] In the embodiment of the present disclosure, the second spacing is equal to the first spacing, so that as many second pins YJ2 as possible can be placed between two adjacent output sub-regions SC.

[0210] In summary, compared with traditional display driver components, the display driver components of the embodiment of the present disclosure have high compatibility (can support both high output channels and low output channels), and can also independently control the power supply of each output sub-area SC, thereby achieving more refined local refresh to reduce power consumption and greatly improve the competitiveness of the product.

[0211] At least some embodiments of the present disclosure further provide a display module, wherein a display panel 400 includes the display panel 400 of the aforementioned embodiment, which has a display area AA and a peripheral area NA, and related structures therein. For example, the display panel 400 can be a liquid crystal display panel (LCD) or an organic electroluminescent display panel (OLED).

[0212] At least some embodiments of the present disclosure further provide a display device, which may include any device or product having a display function. For example, the display device may be a smartphone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0213] It should be understood that the above-mentioned display module and display device have all the characteristics and advantages of the above-mentioned display driver component and display driver component. For details, please refer to the above description and will not be repeated here.

[0214] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, even if such combinations and / or couplings are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or couplings fall within the scope of the present disclosure.

[0215] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A display driver component, comprising a driver chip, in, The driver chip includes a first area and a second area, the first area and the second area are arranged along a first direction, the first area includes at least one signal input interface, and the second area includes: first base; a first conductive layer disposed on the first substrate; A first insulating layer disposed on a side of the first conductive layer away from the first substrate; A plurality of output sub-regions are arranged on the first substrate, the plurality of output sub-regions are arranged along the second direction, at least one of the output sub-regions comprises a plurality of pin units, the plurality of pin units are arranged along the first direction, and at least one of the pin units comprises a plurality of first pins; A plurality of output units are arranged on the first substrate, at least one of the output units is electrically connected to a plurality of the first pins through a multiplexing unit, and different output units are electrically connected to different first pins; A first window unit is provided in the first insulating layer, the first window unit includes a plurality of windows, the plurality of windows in the first window unit include a plurality of first windows and a plurality of second windows, the plurality of second windows are located on a side of the plurality of first windows close to the first region; Among them, the multiple pin units include a first pin unit and a second pin unit, the second pin unit is located on a side of the first pin unit close to the first area, the multiple first windows expose part of the first pins in the first pin unit, and the multiple second windows expose part of the first pins in the second pin unit, and for any two windows among the multiple first windows and the multiple second windows, the first pins exposed by the two windows are electrically connected to different output units.

2. The display driver assembly according to claim 1, in, The display driving assembly further includes a flexible circuit board, and the flexible circuit board includes: Second base; A first lead layer and a second lead layer are arranged on the second substrate, wherein the first lead layer is located on a side of the second substrate facing the driver chip, and the second lead layer is located on a side of the second substrate facing away from the driver chip; A plurality of first leads, a plurality of second leads and a plurality of first connecting lines are arranged on the second substrate, wherein the plurality of first leads and the plurality of first connecting lines are located in the first lead layer, and the plurality of second leads are located in the In the second lead layer, the orthographic projections of the plurality of first connection lines on the second substrate are located on a side where the orthographic projections of the plurality of first lead lines on the second substrate are close to the orthographic projections of the first region on the second substrate; The first pin exposed by the first window is electrically connected to the plurality of first leads, and the first pin exposed by the second window is electrically connected to the plurality of second leads through the plurality of first connection lines.

3. The display driver assembly according to claim 1, in, The display driving assembly further includes a flexible circuit board, and the flexible circuit board includes: Second base; A first lead layer and a third lead layer disposed on the second substrate, the first lead layer being located on a side of the second substrate facing the driving chip, and the third lead layer being located between the first lead layer and the second substrate; A plurality of first leads and a plurality of third leads disposed on the second substrate, the plurality of first leads being located in the first lead layer, the plurality of third leads being located in the third lead layer, and a positive projection of the plurality of first leads on the second substrate not overlapping a positive projection of the plurality of second leads on the second substrate; Wherein, the first pins exposed by the first window are electrically connected to the plurality of first leads, and the first pins exposed by the second window are electrically connected to the plurality of third leads.

4. The display driving assembly according to claim 3, Wherein, The flexible circuit board further includes: At least one fourth lead layer disposed on the second substrate, the at least one fourth lead layer being located between the third lead layer and the second substrate; At least one fourth lead group disposed on the second substrate, each of the fourth lead groups including a plurality of fourth leads, the fourth leads in the same fourth lead group being located in the same fourth lead layer, and the fourth leads in different fourth lead groups being located in different fourth lead layers; The plurality of pin units further includes at least one third pin unit, the third pin unit being located on a side of the second pin unit away from the first pin unit; At least one second window unit disposed in the first insulating layer, the at least one second window unit including a plurality of third windows, the second window unit being located on a side of the first window unit close to the first region; In at least one of the second window units, the third window exposes the First pins, and the third windows of different second window units expose the first pins in different third pin units; In at least one of the third pin units, the first pins exposed by the third window are electrically connected to the fourth leads in at least one of the fourth lead groups, and the first pins in different third pin units are electrically connected to the fourth leads in different fourth lead groups.

5. The display driving assembly according to claim 4, Wherein, The positive projection of the fourth leads in the (2n - 1)-th fourth lead layer on the second substrate defines a first pattern, and the positive projection of the fourth leads in the 2n-th fourth lead layer on the second substrate defines a second pattern; The positive projection of the first pattern on the second substrate partially overlaps the positive projection of the plurality of first leads on the second substrate, and the positive projection of the second pattern on the second substrate partially overlaps the positive projection of the plurality of third leads on the second substrate; The n is a positive integer.

6. The display driving assembly according to claim 1, Wherein, The first window unit further includes: a third window unit disposed in the first insulating layer, the third window unit including a plurality of fourth windows and a plurality of fifth windows; The plurality of fourth windows expose the first pins in the first pin unit that are not exposed by the first window, and the plurality of fifth windows expose the first pins in the second pin unit that are not exposed by the second window.

7. The display driving component according to claim 1, wherein, At least one of the multiplexing units includes a plurality of gating modules, at least one of the gating modules is electrically connected to at least one of the first pins, and different gating modules are electrically connected to different first pins; For any two windows among the plurality of first windows and the plurality of second windows, the port numbers of the gating modules electrically connected to the first pins exposed by the two windows are the same.

8. The display driving component according to claim 7, wherein, The output unit includes a first output unit and a second output unit, and the plurality of gating modules of at least one of the multiplexing units includes a first gating module; The first output unit is electrically connected to the first pins in the first pin unit through the first gating module of the multiplexing unit element, and the second output unit is electrically connected to the first pins in the second pin unit through the first gating module of the multiplexing unit.

9. The display driving component according to claim 1, wherein, At least one of the pin units includes N first pin groups. In the same pin unit, at least one of the first pin groups includes a plurality of the first pins arranged along the second direction, and the N first pin groups are arranged obliquely along the third direction, and the first direction, the second direction, and the third direction intersect each other; At least one of the first pins includes a first side and a second side that are oppositely arranged along the second direction. In at least one first pin group YJZ, the first sides of two adjacent first pins define a first range on the first substrate, and at least M first pins overlap with the first range in the orthographic projection on the first substrate; wherein, both N and M are positive integers, and M≥3.

10. The display driving component according to claim 9, wherein, The first window unit includes a plurality of first window groups and a plurality of second window groups. At least one of the first window groups includes a plurality of the first windows arranged along the fourth direction, and at least one of the second window groups includes a plurality of the second windows arranged along the fourth direction; wherein, the plurality of first window groups are arranged along the second direction, the plurality of second window groups are arranged along the second direction, and the first direction, the second direction, the third direction, and the fourth direction intersect each other; In at least one of the first window groups, at least one of the first windows exposes the first pins in at least one of the first pin groups, and different first windows expose the first pins in different first pin groups; In at least one of the second window groups, at least one of the second windows exposes the first pins in at least one of the first pin groups, and different second windows expose the first pins in different first pin groups.

11. The display driving component according to claim 1, wherein, the driving chip further includes: a plurality of second pins disposed on the first substrate; a first anti-static module and a first power compensation module disposed on the first substrate; an electrostatic discharge interface and a power compensation interface disposed in the first region; wherein, the first anti-static module is electrically connected to the electrostatic discharge interface through a part of the plurality of second pins, and the first power compensation module is electrically connected to the power compensation interface through another part of the plurality of second pins; The second region includes a first compensation sub-region and a second compensation sub-region. The first compensation sub-region separates two adjacent output sub-regions, and the second compensation sub-region is located on a side of the plurality of output sub-regions close to the first region. The plurality of second pins are located in at least one of the first compensation sub-region and the second compensation sub-region.

12. The display driving component according to claim 11, wherein, the plurality of second pins include anti-static compensation pins and power compensation pins; the first anti-static module is electrically connected to the anti-static compensation pins, and the first power compensation module is electrically connected to the power compensation pins; the anti-static compensation pins and the power compensation pins are disposed in any two adjacent output sub-regions; and / or, the anti-static compensation pins and the power compensation pins are disposed on a side of each output sub-region close to the first region.

13. The display driving component according to claim 12, wherein, the display driving component further includes a flexible circuit board, and the flexible circuit board includes: a second substrate; a first lead layer disposed on the second substrate, and the first lead layer is located on a side of the second substrate facing the driving chip; a fifth lead, a sixth lead, and a seventh lead disposed on the second substrate and located in the first lead layer; wherein, the power compensation interface includes a first voltage terminal and a second voltage terminal, the power compensation pins include a first compensation pin and a second compensation pin, the anti-static compensation pins are electrically connected to the electrostatic discharge interface through the fifth lead, the first compensation pin is electrically connected to the first voltage terminal through the sixth lead, and the second compensation pin is electrically connected to the second voltage terminal through the seventh lead; in the second compensation sub-region, the fourth lead, the fifth lead, and the sixth lead extend along the second direction, and in the first compensation sub-region, the fourth lead, the fifth lead, and the sixth lead are bent toward a side away from the first compensation sub-region; orthographic projections of the fourth lead, the fifth lead, and the sixth lead on the first substrate do not overlap each other.

14. The display driving component according to claim 12, wherein, The display driving assembly further includes a flexible circuit board, and the flexible circuit board includes: Second base; A first lead layer is provided on the second substrate, the first lead layer is located on a side of the second substrate facing the driving chip, and the third lead layer is located between the first lead layer and the second substrate; A fifth lead, a sixth lead, a seventh lead, an eighth lead, a ninth lead and a tenth lead disposed on the second substrate and located in the first lead layer, and a transition portion located in the third lead layer; the fourth lead, the fifth lead and the sixth lead are located in the first compensation sub-area and extend along the first direction, and the eighth lead, the ninth lead and the tenth lead are located in the second compensation sub-area and extend along the second direction; Wherein, the power compensation interface includes a first voltage terminal and a second voltage terminal, the power compensation pin includes a first compensation pin and a second compensation pin, the anti-static compensation pin is electrically connected to the fifth lead, the first compensation pin is electrically connected to the sixth lead, and the second compensation pin is electrically connected to the seventh lead; The fifth lead is electrically connected to the electrostatic release interface through the eighth lead, the sixth lead is electrically connected to the first voltage terminal through the ninth lead, and the seventh lead is electrically connected to the second voltage terminal through the tenth lead; Orthographic projections of at least two of the fifth lead, the sixth lead, the seventh lead, the eighth lead, the ninth lead, and the tenth lead on the first substrate overlap, and, in the overlapping area, one of them is transferred through the transfer portion.

15. The display driving component according to claim 13, in, The driver chip also includes: A signal expansion interface disposed in the first area; a signal expansion pin disposed on the first substrate, the signal expansion pin being located in the first compensation sub-area and located on a side of the plurality of second pins away from the first area; The flexible circuit board 320 further includes: A second connecting line and an eleventh lead line are arranged on the second substrate, the second connecting line is located in the first lead line layer, and the eleventh lead line is located in the second lead line layer; The signal extension pin is electrically connected to the eleventh lead through a second connecting line. The lead is electrically connected to the signal expansion interface.

16. The display driving component according to claim 15, in, At least one first via hole is formed on the second substrate, the size of the first via hole is greater than or equal to the distance between two adjacent first pins in the second direction, the second connecting wire and the eleventh lead are electrically connected through the first via hole, and the first via hole is located on a side of the signal extension pin away from the first area; The jth first via hole is located on a side of the j+1th first via hole away from the first region, and for the second connecting wire and the eleventh lead wire electrically connected through the j+1th first via hole, the second connecting wire at least partially surrounds the jth first via hole; Said j is a positive integer.

17. The display driving component according to claim 15, wherein, the projections of the second connection line and the eleventh lead on the first substrate are located between the orthographic projections of two adjacent output sub-regions on the first substrate.

18. The display driving component according to claim 11, wherein, the driving chip further includes a first power supply module and a control module; the first power supply module is electrically connected to a first power supply, and the first power supply module and the first power supply compensation module are electrically connected to at least one of the output sub-regions through the control module. The control module is configured to: in response to a strobe instruction, conduct or disconnect the output sub-region electrically connected thereto from the first power supply module, and / or conduct or disconnect the output sub-region electrically connected thereto from the first power supply compensation module.

19. The display driving component according to claim 11, wherein, at least two of the first pins are arranged along the second direction, and at least two of the second pins are arranged along the second direction; in the second direction, there is a first pitch between two adjacent first pins, and a second pitch between two adjacent second pins, and the second pitch is greater than or equal to the first pitch.

20. A display module, wherein, it includes the display driving component according to any one of claims 1-19.

21. A display device, wherein, it includes the display module according to claim 20.

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