Driving apparatus, display terminal, system, method, device, and storage medium

Abstract

The present disclosure relates to the technical field of display, and provides a driving apparatus, a display terminal, a system, a method, a device, and a storage medium. The driving apparatus comprises: a graphics card, configured to read preset first extended display identification data corresponding to a first display mode from a storage module in the first display mode, generate first display data corresponding to the first display mode on the basis of the first extended display identification data and send same to an integrated control chip; the integrated control chip, configured to generate a first clock signal and first drive data in the first display mode on the basis of the received first display data, and send the first clock signal to a display panel and send the first drive data to a driver chip; and the driver chip, configured to convert the first drive data into a first data voltage signal, and send the first data voltage signal to the display panel, such that the display panel drives pixels for image display on the basis of the received first clock signal and first data voltage signal.

Description

Drive device, display terminal, system, method, device and storage medium Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a driving device, a display terminal, a system, a method, a device, and a storage medium. Background Art

[0002] As display products achieve higher resolutions and refresh rates, pixel charging times are shortening. However, due to limitations in process technology and the driver capabilities of the integrated chips within most display products, improving pixel charging times is becoming increasingly difficult, hindering the development of high-end display products.

[0003] Therefore, the current mainstream research direction is to ensure that pixel charging time is sufficient while being compatible with high resolution and high refresh rate to meet user application requirements for high refresh rate. However, the inventors have found that most display products are often limited by the inherent functions and matching conditions of the display control chip (Scalar IC) and the timing control chip (TCON IC), and are unable to support multi-frequency display functions.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a driving device, a display terminal, a system, a method, a device and a storage medium.

[0006] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a driving device, which is applied to a display terminal; the operating mode of the display terminal includes a hardware super-resolution first display mode; the driving device includes a graphics card, an integrated control chip, a storage module and a driver chip;

[0007] The graphics card is configured to, in the first display mode, read pre-set first extended display identification data corresponding to the first display mode from the storage module, generate first display data corresponding to the first display mode according to the first extended display identification data, and send the generated first display data to the integrated control chip;

[0008] The integrated control chip is configured to generate a first clock signal and first driving data according to the received first display data in the first display mode, and send the first clock signal to the display panel and send the first driving data to the driving chip;

[0009] The driver chip is configured to convert the first driving data into a first data voltage signal and send the first data voltage signal to the display panel, so that the display panel drives pixels to display images according to the received first clock signal and the first data voltage signal.

[0010] In some embodiments, the integrated control chip includes an input interface, an internal OSD module, a filtering module, a clock module, a data signal processing module, and an output interface;

[0011] The internal OSD module is configured to start the first display mode in response to an instruction to start the first display mode;

[0012] The filtering module is configured to, in response to receiving the first display data from the input interface, filter the first display data to generate first intermediate data, and send the first intermediate data to the clock module and the data signal processing module respectively;

[0013] The clock module is configured to convert the first intermediate data into the first clock signal and send the first clock signal to the display panel;

[0014] The data signal processing module is configured to convert the first intermediate data into the first driving data and send the first driving data to the driving chip through the output interface.

[0015] In some embodiments, the storage module includes an external memory;

[0016] The internal OSD module is specifically configured to call the first display mode code from the external memory and deploy it to the filtering module in response to an instruction to start the first display mode;

[0017] The filtering module is specifically configured to deploy the first display mode code; in response to receiving the first display data from the input interface, filter the first display data using the first display mode code to generate the first intermediate data, and send it to the clock module and the data signal processing module respectively.

[0018] In some embodiments, the storage module further includes an external register;

[0019] The internal OSD module is further configured to, in response to an instruction to start the first display mode, read the first extended display identification data from the external memory and send the first extended display identification data to the external register;

[0020] The graphics card is specifically configured to read the first extended display identification data from the external register, generate first display data corresponding to the first display mode according to the first extended display identification data, and send the first display data to the integrated control chip.

[0021] In some embodiments, the input interface is at least one of an HDMI interface, a DP interface, a VGA interface, and a Type-C interface; the output interface is any one of a mini-LVDS interface and a P2P interface.

[0022] In some embodiments, the integrated control chip further includes a backlight control module; the driving device further includes a power chip;

[0023] The backlight control module is configured to generate a backlight control instruction according to the working mode and send the backlight control instruction to the power chip;

[0024] The power chip is configured to control the on / off state of the backlight module of the display panel in response to the received backlight control instruction.

[0025] In some embodiments, the first display mode is determined based on a user's selection of a first display mode option in an OSD menu; the OSD menu is displayed on a user interface UI of the display panel.

[0026] In some embodiments, the driving device further includes an external switch module;

[0027] The external switch module is configured to control the display terminal to enter the first display mode in response to a first trigger operation of a user.

[0028] In some embodiments, the operating mode further includes a second display mode;

[0029] The refresh rate corresponding to the first display mode is greater than the refresh rate corresponding to the second display mode, and / or the resolution of the first display mode is greater than the resolution corresponding to the second display mode.

[0030] In some embodiments, the graphics card is further configured to, in the second display mode, read pre-set second extended display identification data corresponding to the second display mode from the storage module, generate second display data corresponding to the second display mode according to the second extended display identification data, and send the second display data to the integrated control chip;

[0031] The integrated control chip is further configured to, in the second display mode, generate a second clock signal and second drive data according to the received second display data, and send the second clock signal to the display panel and send the second drive data to the driver chip;

[0032] The driver chip is further configured to convert the second drive data into a second data voltage signal and send the second data voltage signal to the display panel, so that the display panel drives the pixels to display the picture according to the received second clock signal and the second data voltage signal.

[0033] In some embodiments, the integrated control chip further includes an audio control module;

[0034] The audio control module is configured to convert the received audio data into an audio signal and send the audio signal to the audio output port.

[0035] In some embodiments, the integrated control chip further includes an image detection module;

[0036] The image detection module is configured to detect whether there is any abnormality in the image to be displayed in the first display data provided by the graphics card, and control the polarity of the driving mode of the display panel to be reversed if it is determined that there is any abnormality in the image to be displayed.

[0037] In a second aspect, an embodiment of the present disclosure further provides a display terminal, comprising a driving device as described in any one of the first aspects.

[0038] In some embodiments, the display terminal further includes a display panel;

[0039] The display panel is configured to display an OSD menu in a user interface; the OSD menu includes controls representing the first display mode; and in response to a user selecting the controls for the first display mode, an instruction to start the first display mode is sent to the integrated control chip.

[0040] In a third aspect, an embodiment of the present disclosure further provides a display system, which includes the display terminal as described in the second aspect.

[0041] In some embodiments, the display system further comprises a processor;

[0042] The processor is configured to traverse all software installed on the display panel and determine whether OSD software exists; if it is determined that the display panel does not have the OSD software installed, send installation information to the integrated control chip;

[0043] The integrated control chip is further configured to read a first download URL of the OSD software from the storage module in response to the received installation information, and send the first download URL in the form of a picture to the user interface of the display panel for display, so that the user can link to the corresponding first preset web page based on the first download address to download the OSD software.

[0044] In some embodiments, the display system further includes a backend server;

[0045] The processor is further configured to, upon determining that the display panel has the OSD software installed, read version identification information of the OSD software currently running on the display panel and serial identification information of the display terminal, and upload the information to the backend server; and, in response to a first update instruction, send first update information to the integrated control chip;

[0046] The backend server is configured to, in response to the received version identification information and the received sequence identification information, determine whether the OSD software indicated by the version identification information is the latest version, and, if it is determined that the OSD software indicated by the version identification information is not the latest version, send the first update instruction to the processor of the display terminal indicated by the sequence identification information;

[0047] The integrated control chip is further configured to read a first download URL of the OSD software from the storage module in response to the received first update information, and send the first download URL in the form of a picture to the user interface of the display panel for display, so that the user can link to the corresponding first preset web page based on the first download address to download the latest version of the OSD software.

[0048] In some embodiments, the image includes one of a pop-up window, a control, and a widget.

[0049] In some embodiments, the display panel is configured to display the first preset web page and send a first download instruction to the processor in response to a user clicking on the first download URL;

[0050] The backend server is further configured to display the installation package of the latest version of the OSD software on the first preset webpage in response to a command issued by the processor according to the first download instruction.

[0051] In some embodiments, the display system further includes a processor; the display system further includes a background server;

[0052] The processor is configured to read the verification identification information of the first display mode code and the serial identification information of the display terminal pre-stored in the storage module and upload them to the backend server; and, in response to the second update instruction, send second update information to the integrated control chip;

[0053] The backend server is configured to, in response to the received verification identification information and the sequence identification information, determine whether the first display mode code indicated by the verification identification information is the latest version, and if the first display mode code is not the latest version, send the second update instruction to the processor of the display terminal indicated by the sequence identification information;

[0054] The integrated control chip is further configured to read a second download URL of the first display mode code from the storage module in response to the received second update information, and send the second download URL in the form of a picture to the user interface of the display panel for display, so that the user can link to the corresponding second preset web page based on the second download address to download the first display mode code.

[0055] In some embodiments, the display panel is configured to display the second preset web page and send a second download instruction to the processor in response to a user clicking on the second download URL;

[0056] The backend server is configured to display the installation package of the latest version of the first display mode code on the second preset webpage in response to a command issued by the processor according to the second download instruction.

[0057] In some embodiments, the storage module includes an external memory; the external memory includes a current version storage unit, a backup version storage unit, and a stable version storage unit; the stable version storage unit is used to store the first display mode code at the time of shipment; the current version storage unit is used to store the first display mode code downloaded during the update phase; the backup version storage unit is used to periodically back up the first display mode code in the current version storage unit;

[0058] The processor is further configured to, in response to an instruction indicating an abnormal update of the first display mode code, detect whether the first display mode code stored in the current version storage unit is abnormal; if the first display mode code stored in the current version storage unit is abnormal, detect whether the first display mode code stored in the backup version storage unit is abnormal; if the first display mode code stored in the backup version storage unit is not abnormal, call the latest version of the first display mode code in the backup version storage unit to the current version storage unit for storage; if the first display mode code stored in the backup version storage unit is abnormal, call the first display mode code at the time of shipment from the stable version storage unit to the backup version storage unit for storage.

[0059] In a fourth aspect, an embodiment of the present disclosure further provides a display method, which is applied to a display terminal; the operating mode of the display terminal includes a first display mode; in the first display mode, the display method includes:

[0060] Reading pre-set first extended display identification data corresponding to the first display mode;

[0061] generating first display data corresponding to the first display mode according to the first extended display identification data;

[0062] generating a first clock signal and first driving data according to the received first display data, and sending the first clock signal to the display panel;

[0063] converting the first driving data into a first data voltage signal;

[0064] Pixels are driven according to the first clock signal and the first data voltage signal to display a picture.

[0065] In some embodiments, driving pixels to display images according to the first clock signal and the first data voltage signal includes:

[0066] In response to the first clock signal, the i-th row of gate drive data is output to the i-th row of pixels, and mixed data of the i-th row of gate drive data and the i+2-th half row of gate drive data is output to the i+1-th row of pixels, and in response to the first data voltage signal, the screen is displayed, where i is a positive integer greater than 1.

[0067] In the fifth aspect, an embodiment of the present disclosure further provides a computer device, which includes: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the display method described in the fourth aspect are performed.

[0068] In the sixth aspect, an embodiment of the present disclosure further provides a computer non-volatile readable storage medium, wherein a computer program is stored on the computer non-volatile readable storage medium, and when the computer program is executed by a processor, the steps of the display method as described in the fourth aspect of claim are executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] FIG1 is a schematic diagram of a circuit structure of a related display device;

[0070] FIG2 is a schematic diagram of a circuit structure of a driving device provided by an embodiment of the present disclosure;

[0071] FIG3 is a schematic diagram of the circuit architecture of an integrated control chip provided in an embodiment of the present disclosure;

[0072] FIG4 is a schematic diagram of a specific circuit architecture of a driving device provided by an embodiment of the present disclosure;

[0073] FIG5a is a schematic diagram of an exemplary integrated control chip provided in an embodiment of the present disclosure;

[0074] FIG5 b is a schematic diagram of another exemplary integrated control chip provided in an embodiment of the present disclosure;

[0075] FIG6 a is a schematic diagram of the flow of various functional modules in the first display mode provided by an embodiment of the present disclosure;

[0076] FIG6 b is a schematic diagram of a specific flow of each functional module in the first display mode provided by an embodiment of the present disclosure;

[0077] FIG7 is a schematic diagram of a display terminal provided in an embodiment of the present disclosure;

[0078] FIG8 is a schematic diagram of a specific circuit architecture of a display terminal provided by an embodiment of the present disclosure;

[0079] FIG9 is a flow chart of a display method provided by an embodiment of the present disclosure;

[0080] FIG10 is a schematic diagram of a process of HSR data processing according to an embodiment of the present disclosure;

[0081] FIG11 is a timing diagram of clock driving of a GOA circuit in a second display mode provided by an embodiment of the present disclosure;

[0082] FIG12 a is a timing diagram of a GOA circuit with TP signals blanking in even rows in a first display mode provided by an embodiment of the present disclosure;

[0083] FIG12 b is a timing diagram of a GOA circuit with TP signals blanking in odd rows in the first display mode provided by an embodiment of the present disclosure;

[0084] FIG13 is a schematic diagram of a display system provided by an embodiment of the present disclosure;

[0085] FIG14 is a flowchart of downloading OSD software according to an embodiment of the present disclosure;

[0086] FIG15 is a flowchart of updating OSD software according to an embodiment of the present disclosure;

[0087] FIG16 is a flowchart of updating OSD software according to an embodiment of the present disclosure;

[0088] FIG17 is a schematic diagram of an external memory provided by an embodiment of the present disclosure;

[0089] FIG18 is a schematic structural diagram of a computer device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0090] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0091] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "an" or "the" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0092] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0093] Before introducing the present disclosure, the special terms involved in the present disclosure are introduced in detail.

[0094] 1. Hardware Super Resolution (HSR) is a software technology that achieves differential display through timing adjustment. Specifically, in each frame, only the pixels in the odd or even rows are rendered, while the other row is displayed by fusing information from two adjacent rows. HSR technology fuses the pixels in the even rows, resulting in more natural color and line transitions across the entire image, and improved clarity.

[0095] 2. EDID (Extended Display Identification Data) consists of a 128-byte data structure and is stored in the video display device, also known as the receiver. EDID specifies the characteristics of the receiver and must contain a main data block, also known as VESA block 0. Block 0 lists the resolution and refresh rate of the display terminal, other supported resolutions and refresh rates, and color characteristics. The resolution is usually the same as the physical resolution of the display terminal, but it may be different. EDID also includes a series of auxiliary information, such as the vendor, model, serial number, production date, physical image size, display transfer characteristics (gamma), and color characteristics (RGB primary colors and white point).

[0096] 3. OSD (On-Screen Display) is an on-screen menu-based adjustment method. Also known as an image overlay module, it is primarily used to display various images and text information on the screen, such as menus, subtitles, and logos. Typically, pressing the Menu button pops up a rectangular menu of various display adjustment options. This menu allows you to adjust various display parameters, including color, mode, and geometry, to achieve optimal performance.

[0097] 4. High Definition Multimedia Interface (HDMI) is a fully digital video and sound transmission interface that can send uncompressed audio and video signals.

[0098] 5. DisplayPort (DP) is a digital video interface developed by a consortium of PC and chip manufacturers and standardized by the Video Electronics Standards Association (VESA). This certification- and royalty-free interface is primarily used to connect video sources to devices such as displays, and also supports audio, USB, and other data. It was designed to replace traditional VGA, DVI, and FPD-Link (LVDS) interfaces. It is backwards compatible with legacy interfaces such as HDMI and DVI via active or passive adapters.

[0099] 6. VGA (Video Graphics Array) interface is a special interface for computers to output data using the VGA standard.

[0100] 7. Type-C is a USB interface standard with a smaller size than Type-A and Type-B.

[0101] 8. Low Voltage Differential Signaling (LVDS) is a low-swing differential signaling technology that enables signal transmission at rates of several hundred Mbps across differential PCB pairs or balanced cables. Its low voltage swing and low current drive output achieve low noise and low power consumption. The LVDS interface generally supports transmission rates above 155 Mbps (approximately 77 MHz). Mini-LVDS is a high-speed serial interface that generates very low electromagnetic interference and provides high bandwidth for display drivers, making it suitable for transmitting data voltage signals for display panels.

[0102] 9. P2P, or peer-to-peer, is a computer network communication model that transmits data directly to the target device without going through an intermediate server. A P2P interface is an interface that meets P2P specifications.

[0103] In the related art, Figure 1 is a schematic diagram of the circuit architecture of the related display device. As shown in Figure 1, the conventional display device includes an independent TCON IC, an independent Scalar IC and a display panel 01. The Scalar IC receives the display data provided by the graphics card through the HDMI interface and the DP interface, and converts it into an LVDS signal and transmits it to the TCON IC. The independent TCON IC and the independent Scalar IC are respectively located on two printed circuit boards (PCBs) and are connected by a flexible flat cable (FFC). The two need to match the same transmission interface, so the signal transmission of the TCON IC and the Scalar IC is limited by the interface matching conditions. At the same time, the connection part of the FFC requires a certain material cost, which limits the lightweight design of the display product. In addition, the independent TCON IC and the independent Scalar IC are easily prone to derivative problems, such as electromagnetic interference (EMI).

[0104] In view of this, embodiments of the present disclosure provide a driving device, a display terminal, a system, a method, a device, and a storage medium, which substantially eliminate one or more of the problems caused by the limitations and defects of the related art.

[0105] In a first aspect, embodiments of the present disclosure provide a drive device, which is primarily used in a display terminal. The display terminal includes a first display mode and a second display mode. The refresh rate corresponding to the first display mode is greater than the refresh rate corresponding to the second display mode, and / or the physical resolution of the first display mode is greater than the physical resolution of the second display mode.

[0106] For example, in the second display mode, the physical resolution of the display panel (i.e., display screen) in the display terminal is 3840×2160, and the refresh rate is 240Hz; in the first display mode, the physical resolution of the display panel (i.e., display screen) in the display terminal is 3840×2160, and the refresh rate is 480Hz.

[0107] Therefore, the present disclosure can achieve a multiple increase in the refresh rate of the display terminal by turning on the first display mode.

[0108] The specific process of realizing the first display mode based on the driving device is described in detail below.

[0109] FIG2 is a schematic diagram of the circuit architecture of a driving device provided by an embodiment of the present disclosure. As shown in FIG2 , the driving device 100 mainly includes a graphics card 10, an integrated control chip 20, a storage module 30, and a driving chip 40. Among them:

[0110] The graphics card 10 is configured to read pre-set first extended display identification data corresponding to the first display mode from the storage module 30 in the first display mode, and generate first display data corresponding to the first display mode according to the first extended display identification data, and send it to the integrated control chip 20.

[0111] In the first display mode, the display terminal has already activated the first display mode. The driver device 100 applied to the display terminal is also in the first display mode. The storage module 30 stores first extended display identification data corresponding to the first display mode. The first extended display identification data, for example, is EDID data corresponding to the first display mode, primarily including a physical resolution and a refresh rate, referred to as the first resolution and the first refresh rate. The first resolution is smaller than the actual physical resolution of the display terminal, and the first refresh rate is equal to the refresh rate corresponding to the actual first display mode of the display terminal, and higher than the refresh rate corresponding to the second display mode.

[0112] The graphics card 10 can actively read the first extended display identification data from the storage module 30, and after a series of processing, generate the first display data corresponding to the first display mode. The first display data is information about the image to be displayed on the display screen, for example, including data of the image to be displayed, the first resolution and the first refresh rate of the image to be displayed, etc. The first resolution is less than or equal to the actual physical resolution of the display terminal, for example, the first resolution is 1 / α of the actual physical resolution of the display terminal, and α is a positive integer greater than or equal to 1. Optionally, α=4. The first refresh rate is higher than the refresh rate of the display terminal in the second display mode, for example, the first refresh rate is β times the refresh rate of the display terminal in the second display mode, and β is a positive integer greater than or equal to 1. Optionally, β=2.

[0113] The integrated control chip 20 is configured to generate a first clock signal and first driving data according to the received first display data in the first display mode, and send the first clock signal to the display panel and the first driving data to the driving chip 40 .

[0114] The integrated control chip 20 is an all-in-one chip that integrates the TCON IC and the Scalar IC, possessing both TCON IC and Scalar IC functions. Specifically, the integrated control chip 20 includes a filter module 203, a clock module 204, and a data signal processing module 205. The filter module 203 is part of the Scalar IC, while the clock module 204 and data signal processing module 205 are also part of the TCON IC.

[0115] The filtering module 203 is configured to receive the first display data in the first display mode, filter the first display data to generate first intermediate data, and send the first intermediate data to the clock module 204 and the data signal processing module 205. The first intermediate data is the filtered first display data, mainly including the data of the image to be displayed, the second resolution and the second refresh rate of the image to be displayed, etc. The second resolution is m times the first resolution, that is, the second resolution is m / α of the actual physical resolution of the display terminal, and m is a positive integer greater than or equal to 1. Optionally, α=4, m=2. The second refresh rate is equal to the first refresh rate, so the second refresh rate is β times the refresh rate of the display terminal in the second display mode. Optionally, β=2.

[0116] The clock module 204 is configured to convert the first intermediate data into a first clock signal. The first clock signal is a clock signal transmitted to a gate drive on array (GOA) circuit in the display panel.

[0117] The data signal processing module 205 is configured to convert the first intermediate data into first driving data. The first driving data is data matching the output format of the mini LVDS interface and is mainly used to drive the pixel to emit light.

[0118] The driving chip 40 is configured to convert the first driving data into a first data voltage signal and send the first data voltage signal to the display panel so that the display panel drives the pixels to display images according to the received first clock signal and the first data voltage signal.

[0119] The first data voltage signal is a data signal transmitted to a switching transistor in a pixel driving circuit in the display panel.

[0120] The resolution corresponding to the first clock signal is the same as the second resolution, and the refresh rate corresponding to the first clock signal is the same as the second refresh rate. The resolution corresponding to the first data voltage signal is the same as the second resolution, and the refresh rate corresponding to the first data voltage signal is the same as the second refresh rate. At this time, the display panel drives the pixels according to the received first clock signal and the first data voltage signal, and can display images at the third resolution and the third refresh rate.

[0121] The third resolution is the actual physical resolution of the display terminal. The third refresh rate is the same as the second refresh rate, that is, β times the refresh rate of the display terminal in the second display mode. Therefore, it can be seen that when the present disclosure is driven in the above manner, the actual physical resolution of the display terminal in the first display mode remains unchanged, and the refresh rate is increased by β times.

[0122] In addition, in the related art shown in FIG. 1 , for the separate TCON IC and Scalar IC, the Scaler IC needs to be passed between the graphics card 10 and the TCON IC. When performing the first display mode switch, it is also necessary to ensure the synchronous switching of the LVDS signals between the Scalar IC and the TCON IC. The switching time is relatively long. In order to avoid abnormal images being seen during the switching process, the backlight source usually needs to be turned off, so the backlight off time is prolonged.

[0123] The driver device 100 disclosed herein, while capable of multiplying the refresh rate of a display terminal, utilizes an integrated control chip 20, simplifying the circuit architecture and reducing the overall circuit board footprint of the driver device 100, thereby achieving a lower-cost and thinner display terminal. Furthermore, compared to related art designs that employ separate TCON ICs and Scalar ICs, the integrated control chip 20 disclosed herein eliminates the need for matching transmission interfaces between the TCON IC and Scalar IC, avoiding issues associated with signal interface matching (e.g., electromagnetic interference). This eliminates the need for synchronous switching of LVDS signals between the two, thereby reducing the time required to shut down the backlight during the switching process.

[0124] In some embodiments, FIG3 is a schematic diagram of the circuit architecture of an integrated control chip provided in an embodiment of the present disclosure. As shown in FIG3 , the integrated control chip 20 includes an input interface 201, an internal OSD module 202, a filtering module 203, a clock module 204, a data signal processing module 205, and an output interface 206.

[0125] The internal OSD module 202 is configured to start the first display mode in response to an instruction to start the first display mode.

[0126] Exemplarily, the instruction to activate the first display mode may be initiated based on OSD software installed on the display terminal. For example, the OSD software supports displaying an OSD menu on the display panel, where the OSD menu includes options for displaying the terminal's operating modes, such as controls representing the first display mode and controls representing the second display mode. In response to a user clicking on a control for the first display mode, the OSD software may send an instruction to activate the first display mode to the internal OSD module 202. The internal OSD module 202 communicates with the OSD software, so the internal OSD module 202 can receive the instruction to activate the first display mode sent by the OSD software, thereby activating the first display mode.

[0127] For example, the instruction to activate the first display mode may also be initiated by an external switch module. For example, the external switch module is a switch integrated into the driver device 100, such as a button or an inductive sensor. When the switch is turned on, it corresponds to the first display mode, and when the switch is turned off, it corresponds to the second display mode. Therefore, the external switch module can send an instruction to activate the first display mode to the internal OSD module 202 in response to the user's first trigger operation.

[0128] Starting the first display mode includes, for example, the process of the internal OSD module 202 executing the call of the first display mode code and sending it to the filter module 203. Alternatively, the process includes the process of the internal OSD module 202 reading the first extended display identification data and sending it to the external register 302.

[0129] The display terminal provided in this embodiment can also support one-key switching of the first display mode, which is not limited by the functional matching limitations of the whole device Scalar IC and the module TCON IC, saving the timing switching of the Scalar IC and the TCON IC.

[0130] The filtering module 203 is configured to, in response to receiving the first display data from the input interface 201 , filter the first display data to generate first intermediate data, and send the first intermediate data to the clock module 204 and the data signal processing module 205 respectively.

[0131] The filter module 203 and the graphics card 10 transmit related signals via the input interface 201. Therefore, the filter module 203 can receive the first display data sent by the graphics card 10 via the input interface 201.

[0132] Exemplarily, the input interface 202 includes but is not limited to at least one of an HDMI interface, a DP interface, a VGA interface, and a Type-C interface.

[0133] Exemplarily, the filtering module 203 is, for example, a scaling function module.

[0134] The first display data includes data of an image to be displayed, a first resolution and a first refresh rate of the image to be displayed, etc. The first resolution is less than or equal to the actual physical resolution of the display terminal; and the first refresh rate is higher than the refresh rate of the display terminal in the second display mode.

[0135] The first intermediate data is the filtered data of the first display data. The specific filtering process can be understood as a scaling process of the image to be displayed, with the refresh rate remaining unchanged and the resolution increased. For example, the first intermediate data includes data of the image to be displayed, the second resolution and the second refresh rate of the image to be displayed. The second resolution is higher than the first resolution, and the second refresh rate is equal to the first refresh rate. Optionally, the second resolution is twice the first resolution, for example, the first resolution is 1920×1080px and the second resolution is 3840×1080px. The first refresh rate and the second refresh rate are both 480Hz.

[0136] The clock module 204 is configured to convert the first intermediate data into a first clock signal that can be received by the GOA circuit, and send the first clock signal to the display panel.

[0137] The clock module 204 is electrically connected to the GOA circuit via a plurality of clock signal lines.

[0138] The resolution corresponding to the first clock signal is the same as the second resolution, and the refresh rate corresponding to the first clock signal is the same as the second refresh rate, for example, 3840×1080px, 480Hz.

[0139] The data signal processing module 205 is configured to convert the first intermediate data into first driving data that can be processed by the driving chip 40 , and send the first driving data to the driving chip 40 through the output interface 206 .

[0140] Exemplarily, the data signal processing module 205 is, for example, a mini-LVDS module, which outputs the first driving data in the form of a mini-LVDS signal.

[0141] Exemplarily, the data signal processing module 205 is, for example, a P2P module, which outputs the first driving data in the form of a P2P signal.

[0142] The resolution corresponding to the first data voltage signal is the same as the second resolution, and the refresh rate corresponding to the first data voltage signal is the same as the second refresh rate, for example, 3840×1080px, 480Hz.

[0143] Exemplarily, the output interface 206 includes but is not limited to any one of a mini-LVDS interface and a P2P interface. When the data processing module 205 is a mini-LVDS module, the output interface 206 is a mini-LVDS interface; when the data processing module 205 is a P2P module, the output interface 206 is a P2P interface.

[0144] In some embodiments, FIG4 is a schematic diagram of a specific circuit architecture of a driving device provided by an embodiment of the present disclosure. As shown in FIG4 , the storage module 30 includes an external memory 301 .

[0145] The internal OSD module 202 is further configured to call the first display mode code from the external memory 301 and deploy it to the filtering module 203 in response to the instruction to start the first display mode.

[0146] The external memory 301 includes but is not limited to flash memory (FLASH). The external memory 301 pre-stores a first display mode code corresponding to the first display mode. The first display mode code can be understood as a tool that can support multi-frequency conversion, such as converting a low refresh rate to a high refresh rate.

[0147] Before decoding the first display data, the filtering module 203 is further configured to deploy the first display mode code. Thus, after deploying the first display mode code, the filtering module 203 can, in response to receiving the first display data from the input interface 201, filter the first display data using the first display mode code to generate first intermediate data, which is then sent to the clock module 204 and the data signal processing module 205.

[0148] In some embodiments, as shown in FIG. 4 , the storage module 30 further includes an external register 302 .

[0149] In addition to executing the above-mentioned processing of calling the first display mode code, the internal OSD module 202 is also configured to read the first extended display identification data (EDID) from the external memory 301 in response to the instruction to start the first display mode, and send the first extended display identification data to the external register 302.

[0150] The external register 302 includes but is not limited to the register (EEP). In addition to pre-storing the first display mode code corresponding to the first display mode, the external memory 301 also pre-stores the first extended display identification data corresponding to the first display mode.

[0151] The internal OSD module 202 starts the first display mode. In addition to calling and deploying the first display mode code to increase the refresh rate, it also needs to read the first extended display identification data corresponding to the first display mode from the external memory 301 and transfer it to the external register 302 for storage so that the graphics card 10 can read it.

[0152] The graphics card 10 is specifically configured to read the first extended display identification data from the external register 302 , generate first display data corresponding to the first display mode according to the first extended display identification data, and send the first display data to the integrated control chip 20 .

[0153] The graphics card 10 actively reads the temporarily stored information from the external register 302. In the first display mode, the external register 302 is updated with the first extended display identification data. Therefore, the graphics card 10 can read the first extended display identification data from the external register 302 in the first display mode.

[0154] In some embodiments, the input interface 201 is at least one of HDMI, DP, VGA, and Type-C, and the output interface 206 is any one of mini-LVDS and P2P.

[0155] Alternatively, FIG5a is a schematic diagram of an exemplary integrated control chip provided by an embodiment of the present disclosure. As shown in FIG5a , input interface 201 is HDMI and VGA. Output interface 206 is mini-LVDS. This is primarily used in low-end FHD resolution products with refresh rates below 100Hz.

[0156] Alternatively, FIG5b is a schematic diagram of another exemplary integrated control chip provided by an embodiment of the present disclosure. As shown in FIG5b , input interface 201 is HDMI and DP. Output interface 206 is P2P. This chip is primarily used in mid- to high-end products with FHD, QHD, or UHD resolutions and high refresh rates.

[0157] Optionally, the input interface 201 may also support common interfaces of display panels, such as VGA and Type-C.

[0158] In some embodiments, as shown in FIG. 4 , the integrated control chip 20 further includes a backlight control module 207 ; the driving device 100 further includes a power chip 50 .

[0159] Exemplarily, the power chip 50 is a backlight unit (BLU) power IC, which is mainly used to control the on / off state of the backlight unit.

[0160] The backlight control module 207 is configured to generate a backlight control instruction according to the working mode and send it to the power chip 50. The power chip 50 is configured to control the on / off state of the backlight module in response to the received backlight control instruction.

[0161] The operating mode is divided into a second display mode and a first display mode. The backlight control module 207 mainly generates backlight control instructions based on the current operating mode to control the on / off state of the backlight module. When the operating mode is the second display mode, the backlight control module 207 generates a backlight control instruction indicating the second display mode state in response to the instruction sent by the internal OSD module 202 to start the second display mode, and sends the instruction to the power chip 50. In response to the backlight control instruction indicating the second display mode state, the power chip 50 sends a first backlight control signal to the backlight module to control the backlight module to be in the on state. Alternatively, when the operating mode is the first display mode, the backlight control module 207 generates a backlight control instruction indicating the first display mode state in response to the instruction sent by the internal OSD module 202 to start the first display mode, and sends the instruction to the power chip 50. In response to the backlight control instruction indicating the first display mode state, the power chip 50 sends a second backlight control signal to the backlight module to control the backlight module to be in the off state.

[0162] In order to facilitate understanding of the specific working process of each functional module in the driving device 100 in the first display mode, a complete example is used below to explain in detail.

[0163] Figure 6a is a flow chart of each functional module in the first display mode provided by an embodiment of the present disclosure, as shown in Figure 6a, specifically including: ① In the first display mode, the integrated control chip 20 generates a backlight control instruction in response to the OSD software or the external switch module sending the first display mode instruction; ② The integrated control chip 20 calls the first display mode code from the external memory 301 and deploys it; at the same time, ③ the integrated control chip 20 reads the first extended display identification data from the external memory 301, and updates the first extended display data to the external register 302; ④ the graphics card 10 reads the first extended display identification data from the external register 302 through a preset transmission interface (such as HDMI / DP); ⑤ the graphics card 10 outputs the first display data through the preset transmission interface (protocol-connected to the input interface 201 of the integrated control chip 20); ⑥ the integrated control chip 20 receives the first display data, filters the first display data using the first display mode code, and outputs a first clock signal and first drive data; ⑦ the drive chip 40 converts the first drive data into a first data voltage signal and outputs it to the display panel.

[0164] FIG6 b is a schematic diagram of a specific flow of each functional module in the first display mode provided by an embodiment of the present disclosure, as shown in FIG6 b , specifically including: ① in the first display mode, the internal OSD module 202 generates a backlight control instruction in response to the instruction of the first display mode sent by the OSD software or the external switch module; ② the internal OSD module 202 calls the first display mode code from the external memory 301 and deploys it to the filtering module 203; ③ the internal OSD module 202 reads the first extended display identification data from the external memory 301 and updates it to the external register 302; ④ the graphics card 10 receives the first extended display identification data from the external memory 301 through a preset transmission interface (such as HDMI / DP) The first extended display identification data is read from the register 302; ⑤ the graphics card 10 outputs the first display data through a preset transmission interface (protocol-connected to the input interface 201 of the integrated control chip 20); ⑥ the filtering module 203 receives the first display data through the input interface 201, filters the first display data using the first display mode code, and outputs first intermediate data; ⑦ the clock module 204 receives the first intermediate data and outputs a first clock signal; ⑧ the data signal processing module 205 receives the first intermediate data and outputs the first drive data through the output interface 206; ⑨ the driver chip 40 converts the first drive data into a first data voltage signal and outputs it to the display panel.

[0165] For example, the data processing flow is described using UHD at 240Hz as an example. In the second display mode: the graphics card 10 outputs 3840×2160, 240Hz data; in the first display mode, the graphics card 10 outputs 1920×1080 480Hz data, which is processed by the integrated control chip 20 to 3840×1080 480Hz data, and output to the GOA circuit and driver chip 40 (also known as Driver IC) of the display panel. The integrated control chip 20 can switch from the normal working mode to the first display mode, and can realize the reception and transmission of data at normal frequency and double frequency to ensure the normal display of the display panel. For the GOA drive of the display panel, in the second display mode, the screen display is realized by line-by-line scanning; in the first display mode (for example, double refresh rate mode), N rows are charged by normal scanning, and N+1 rows are charged by mixed charging of adjacent odd rows (or even rows). In the first display mode (for example, double refresh rate mode), the 3840×1080480Hz data output by the integrated control chip 20 can be converted into 3840×2160480Hz data displayed by the display panel, thereby realizing the input of 1920×1080480Hz data from the graphics card 10 → the display panel displays 3840×2160480Hz.

[0166] In the driving device 100 provided by the embodiment of the present disclosure, in the first display mode, the graphics card 10 only needs to cooperate in reading and outputting the resolution and refresh rate information required for the first display mode; the remaining work is implemented by the remaining modules in the driving device 100. The first display mode operation is achieved by the integrated control chip 20 in coordination with the graphics card 10, the power chip 50, the driver chip 40, the external register 302 and the external memory 301. The integrated control chip 20 can be linked with the OSD menu presented on the user interface (UI) by the OSD software. The OSD menu contains controls for one-click access to the first display mode. Through the circuit architecture of the driving device 100 provided by the present disclosure, especially the integrated control chip 20 integrating the TCON IC and the Scalar IC, the 1920×1080 480Hz data output by the graphics card 10 can be displayed on the display panel as a 3840×2160 480Hz HSR display effect, thereby saving 1 / 2 of the computing power of the graphics card 10 and increasing the refresh rate by 1 times.

[0167] The working modes of the display terminal include a first display mode and a second display mode. The above embodiments have described the processing of the first display mode in detail, and the working process of the second display mode will be described below.

[0168] In some embodiments, as shown in Figure 2, the graphics card 10 is further configured to read pre-set second extended display identification data corresponding to the second display mode from the storage module 30 in the second display mode, and generate second display data corresponding to the second display mode based on the second extended display identification data, and send it to the integrated control chip 20.

[0169] In the second display mode, the storage module 30 stores second extended display identification data corresponding to the second display mode. The second extended display identification data is, for example, EDID data corresponding to the second display mode, mainly including the actual physical resolution and refresh rate of the display panel.

[0170] The graphics card 10 can actively read the second extended display identification data from the storage module 30 and, after a series of processing, generate second display data corresponding to the second display mode. The second display data is information about the image to be displayed on the display screen, such as the data of the image to be displayed, the actual physical resolution and refresh rate of the display panel, etc.

[0171] The integrated control chip 20 is further configured to generate a second clock signal and second driving data according to the received second display data in the second display mode, and send the second clock signal to the display panel and the second driving data to the driving chip 40.

[0172] The resolution corresponding to the second clock signal is the actual physical resolution of the display panel, and the refresh rate corresponding to the second clock signal is the refresh rate in the second display mode. The resolution corresponding to the second drive data is the actual physical resolution of the display panel, and the refresh rate corresponding to the second drive data is the refresh rate in the second display mode.

[0173] The driving chip 40 is further configured to convert the second driving data into a second data voltage signal and send the second data voltage signal to the display panel so that the display panel drives the pixels to display the picture according to the received second clock signal and the second data voltage signal.

[0174] The resolution corresponding to the second data voltage signal is the actual physical resolution of the display panel, and the refresh rate corresponding to the second data voltage signal is the refresh rate in the second display mode.

[0175] In some embodiments, as shown in FIG. 4 , in the second display mode, the internal OSD module 202 is configured to activate the second display mode in response to an instruction to activate the second display mode.

[0176] Exemplarily, the instruction to start the second display mode can be initiated based on OSD software installed on the display terminal. For example, the OSD software supports displaying an OSD menu on the display panel. The OSD menu has controls corresponding to different operating modes of the display terminal, such as controls representing the first display mode and controls representing the second display mode. In response to a user clicking on a control for the second display mode, the OSD software can send an instruction to start the second display mode to the internal OSD module 202. The internal OSD module 202 communicates with the OSD software, so the internal OSD module 202 can receive the instruction to start the second display mode sent by the OSD software, thereby starting the second display mode.

[0177] For example, the instruction to activate the second display mode may also be initiated by an external switch module. For example, the external switch module is a switch integrated into the driver device 100, such as a button or an inductive sensor. Turning the switch on corresponds to the second display mode, and turning the switch off corresponds to the second display mode. Therefore, the external switch module can send an instruction to activate the first display mode to the internal OSD module 202 in response to the user's first trigger operation.

[0178] Starting the second display mode includes, for example, the process of the internal OSD module 202 executing the second display mode code and sending it to the filter module 203. Alternatively, the process includes the process of the internal OSD module 202 reading the second extended display identification data and sending it to the external register 302.

[0179] In the second display mode, the filtering module 203 is configured to, in response to receiving the second display data from the input interface 201 , filter the second display data to generate second intermediate data, and send the second intermediate data to the clock module 204 and the data signal processing module 205 .

[0180] The resolution corresponding to the second intermediate data is the actual physical resolution of the display panel, and the refresh rate corresponding to the second intermediate data is the refresh rate in the second display mode.

[0181] In the second display mode, the clock module 204 is configured to convert the second intermediate data into a second clock signal that can be received by the GOA circuit, and send the second clock signal to the display panel.

[0182] The data signal processing module 205 is configured to convert the second intermediate data into second driving data that can be processed by the driving chip 40 , and send the second driving data to the driving chip 40 through the output interface 206 .

[0183] In some embodiments, as shown in FIG. 4 , the internal OSD module 202 is further configured to call the second display mode code from the external memory 301 and deploy it to the filtering module 203 in response to an instruction to start the second display mode.

[0184] Before decoding the second display data, the filtering module 203 is further configured to deploy the second display mode code. Thus, after deploying the second display mode code, the filtering module 203 can, in response to receiving the second display data from the input interface 201, filter the second display data using the second display mode code to generate second intermediate data, which is then sent to the clock module 204 and the data signal processing module 205.

[0185] In some embodiments, as shown in Figure 4, in addition to executing the above-mentioned processing of calling the second display mode code, the internal OSD module 202 is also configured to read the second extended display identification data from the external memory 301 in response to the instruction to start the second display mode, and send the second extended display identification data to the external register 302.

[0186] The external register 302 includes but is not limited to the register (EEP). In addition to pre-storing the second display mode code corresponding to the first display mode, the external memory 301 also pre-stores the second extended display identification data corresponding to the second display mode.

[0187] The internal OSD module 202 starts the second display mode. In addition to calling and deploying the second display mode code, it also needs to read the second extended display identification data corresponding to the second display mode from the external memory 301 and transfer it to the external register 302 for storage so that the graphics card 10 can read it.

[0188] The graphics card 10 is specifically configured to read the second extended display identification data from the external register 302 , generate second display data corresponding to the second display mode according to the second extended display identification data, and send the second display data to the integrated control chip 20 .

[0189] The graphics card 10 actively reads the temporarily stored information from the external register 302. In the second display mode, the external register 302 is updated with the second extended display identification data. Therefore, the graphics card 10 can read the second extended display identification data from the external register 302 in the second display mode.

[0190] In some embodiments, as shown in FIG. 4 , the integrated control chip 20 further includes an audio control module 208 .

[0191] The audio control module 208 is configured to convert the received audio data into an audio signal and send it to the audio output port. For example, the audio control module 208 receives the audio data sent from the front-end host through the HDMI interface or the DP interface and outputs it through the audio output port, such as to headphones.

[0192] In some embodiments, as shown in FIG. 4 , the integrated control chip 20 further includes an image detection module 209 .

[0193] The image detection module 209 is configured to detect whether there is any abnormality in the image to be displayed in the first display data in response to receiving the first display data provided by the graphics card, and control the polarity of the driving mode of the display panel to be reversed if it is determined that there is any abnormality in the image to be displayed.

[0194] Exemplarily, the image detection module 209 is a pattern detection function (PDF) module.

[0195] In a second aspect, an embodiment of the present disclosure further provides a display terminal, specifically comprising a driving device 100 as described in any embodiment of the first aspect or a combination thereof.

[0196] FIG7 is a schematic diagram of a display terminal provided by an embodiment of the present disclosure. As shown in FIG7 , the display terminal includes a display panel 200 and a driver device 100. The display panel 200 includes a GOA circuit and pixels, and the pixels include a pixel driver circuit and a light-emitting device. The driver device 100 includes a graphics card 10, an integrated control chip 20, a storage module 30, and a driver chip 40.

[0197] Exemplarily, the display panel 200 may be a liquid crystal display panel; or, may be an OLED display panel.

[0198] The graphics card 10 is configured to read pre-set first extended display identification data corresponding to the first display mode from the storage module 30 in the first display mode, and generate first display data corresponding to the first display mode according to the first extended display identification data, and send it to the integrated control chip 20.

[0199] The integrated control chip 20 is configured to generate a first clock signal and first driving data according to the received first display data in the first display mode, and send the first clock signal to the display panel 200 and the first driving data to the driving chip 40.

[0200] The driving chip 40 is configured to convert the first driving data into a first data voltage signal and send the first data voltage signal to the display panel 200 .

[0201] The display panel 200 is configured to drive pixels to display images according to the first clock signal and the first data voltage signal in response to receiving the first clock signal and the first data voltage signal.

[0202] The first clock signal is given to the GOA circuit, which outputs a row scan signal according to the first clock signal. The first data voltage signal is given to the pixel driving circuit, which drives the light emitting device to emit light according to the first data voltage signal.

[0203] The display terminal provided by the present disclosure can achieve a multi-fold increase in the display terminal's refresh rate. Furthermore, by utilizing an integrated control chip 20, the circuit architecture is simplified, reducing the overall circuit board footprint of the driver device 100, and achieving a lower cost and thinner display terminal. Furthermore, compared to related art designs that employ separate TCON ICs and Scalar ICs, the integrated control chip 20 of the present disclosure eliminates the need for matching transmission interfaces between the TCON IC and Scalar IC, avoiding issues associated with signal interface matching (e.g., electromagnetic interference). This eliminates the need for synchronous switching of LVDS signals between the two, thereby reducing the time required to shut down the backlight during the switching process.

[0204] In some embodiments, the display panel 200 includes OSD software, such as OSD software. The OSD software is configured to display an OSD menu in a user interface; the OSD menu includes an operating mode control representing a first display mode; and in response to a user selecting the control for the first display mode, send an instruction to the integrated control chip 20 to activate the first display mode.

[0205] Optionally, the OSD menu includes controls representing the first display mode and controls representing the second display mode. The OSD software is further configured to send an instruction to start the second display mode to the internal OSD module 202 in response to a user selecting the control representing the second display mode.

[0206] FIG8 is a schematic diagram of the specific circuit architecture of a display terminal provided by an embodiment of the present disclosure. As shown in FIG8 , the display terminal includes a display panel 200 and a driver device 100. The display panel 200 includes a GOA circuit, pixels, and OSD software. The driver device 100 includes a graphics card 10, an integrated control chip 20, external registers 302, external memory 301, a driver chip 40, and a power chip 50.

[0207] In the display terminal provided by the embodiment of the present disclosure, in the first display mode, the graphics card 10 only needs to cooperate in reading and outputting the resolution and refresh rate information required for the first display mode; the remaining work is implemented by the remaining modules. The first display mode operation is achieved by the integrated control chip 20 in coordination with the graphics card 10, the power chip 50, the driver chip 40, the external register 302, the external memory 301 and the display panel 200 modules. The integrated control chip 20 is linked to the OSD menu presented on the user interface (UI) by the OSD software, and the OSD menu contains a one-click direct access control for the first display mode. Through the circuit architecture of the display terminal provided by the present disclosure, especially the integrated control chip 20 integrating the TCON IC and the Scalar IC, the 1920×1080 480Hz data output by the graphics card 10 can be displayed on the display panel 200 as a 3840×2160 480Hz HSR display effect, thereby saving 1 / 2 of the computing power of the graphics card 10 and increasing the refresh rate by 1 times. In addition, the display terminal provided by the embodiment of the present disclosure can also support one-key switching of the first display mode, which is not limited by the functional matching limitations of the whole device Scalar IC and the module TCON IC, saving the timing switching of the Scalar IC and the TCON IC.

[0208] On the third aspect, the embodiment of the present disclosure also provides a display method corresponding to the display terminal. Since the principle of solving the problem by the method in the embodiment of the present disclosure is similar to the above-mentioned display terminal in the embodiment of the present disclosure, the implementation of the method can refer to the implementation of the display terminal and its internal driving device, and the repeated parts will not be repeated.

[0209] The embodiment of the present disclosure further provides a display method, which is mainly applied to a display terminal, and the execution subject is also the display terminal. The working mode of the display terminal includes a first display mode.

[0210] FIG9 is a flow chart of a display method provided by an embodiment of the present disclosure. As shown in FIG9 , in the first display mode, the method includes steps S11 to S15, wherein:

[0211] S11. Reading preset first extended display identification data corresponding to the first display mode.

[0212] S12: Generate first display data corresponding to the first display mode according to the first extended display identification data.

[0213] The specific execution process of the above steps S11 and S12 can refer to the functional description of the above graphics card 10, and the repeated parts will not be repeated.

[0214] S13 . Generate a first clock signal and first driving data according to the received first display data, and send the first clock signal to the display panel.

[0215] The specific execution process of this step S13 can refer to the functional description of the above-mentioned integrated control chip 20, and the repeated parts will not be repeated.

[0216] S14: Convert the first driving data into a first data voltage signal.

[0217] The specific execution process of this step S14 can refer to the functional description of the driving chip 40 mentioned above, and the repeated parts will not be repeated.

[0218] S15 , driving pixels according to the first clock signal and the first data voltage signal to display a picture.

[0219] The specific execution process of this step S15 can refer to the functional description of the display panel 200 above, and the repeated parts will not be repeated.

[0220] The display method provided by the present disclosure can achieve a multiple-fold increase in the refresh rate of the display terminal. On the basis of achieving a multiple-fold increase in the refresh rate of the display terminal, an integrated control chip is used for data processing, thereby avoiding interface matching and synchronous switching of LVDS signals, improving data processing efficiency, and thus improving mode conversion efficiency.

[0221] In some embodiments, with respect to step S15, pixels are scanned row by row according to the first clock signal and the first data voltage signal, wherein the i-th row is normally charged and the i+1-th row is mixedly charged. The so-called "mixed charging" can be understood as a mixture of the gate drive data of the i-th row and the gate drive data of the i+2-th half row to form the gate drive data of the i+1-th row.

[0222] For example, in response to the first clock signal, the i-th row of gate drive data is output to the i-th row of pixels, and mixed data of the i-th row of gate drive data and the i+2-th half row of gate drive data is output to the i+1-th row of pixels, and in response to the first data voltage signal, the screen is displayed, where i is a positive integer greater than 1.

[0223] FIG10 is a flow chart of HSR data processing according to an embodiment of the present disclosure. As shown in FIG10 , the physical resolution of the display panel is 3840×2160 pix, and the conversion from a refresh rate of 240 Hz to a refresh rate of 480 Hz is achieved, wherein steps S21 to S29 are included:

[0224] S21: The display terminal starts a first display mode.

[0225] S22: Turn off the backlight source of the backlight module.

[0226] S23. The integrated control chip reads first extended display identification data from the external memory, wherein the resolution and refresh rate are 1920×2160, 480 Hz data respectively.

[0227] S24 , the external register updates the first extended display identification data, wherein the resolution and refresh rate are 1920×2160, 480 Hz data respectively.

[0228] S25. The graphics card reads the first extended display identification data from the external register, wherein the resolution and refresh rate are 1920×2160, 480 Hz data respectively.

[0229] S26. The graphics card outputs first display data, wherein the resolution and refresh rate are 1920×2160, 480 Hz respectively.

[0230] S27. The integrated control chip generates a first clock signal according to the received first display data, wherein the resolution and refresh rate are 3840×1080, 480 Hz data respectively, and generates first drive data, wherein the resolution and refresh rate are 3840×1080, 480 Hz data respectively.

[0231] S28. The driving chip outputs a first data voltage signal, wherein the resolution and refresh rate are 3840×1080, 480 Hz data respectively.

[0232] S29. The display panel scans pixels row by row according to the first clock signal and the first data voltage signal, wherein the i-th row is normally charged and the i+1-th row is mixed charged, and the resolution and refresh rate of the displayed image are 3840×2160, 480 Hz data respectively.

[0233] This embodiment uses the above-mentioned display driving method to achieve a multiple-fold increase in the refresh rate of the display terminal. The 1920×1080,480Hz data output by the graphics card is displayed on the display panel as a 3840×2160,480Hz HSR display effect, thereby saving 1 / 2 of the graphics card computing power and increasing the refresh rate by 1 times.

[0234] For example, FIG11 is a timing diagram of the GOA circuit in the second display mode provided by an embodiment of the present disclosure, FIG12a is a timing diagram of the GOA circuit with the TP signal of the even rows blanked in the first display mode provided by an embodiment of the present disclosure, and FIG12b is a timing diagram of the GOA circuit with the TP signal of the odd rows blanked in the first display mode provided by an embodiment of the present disclosure, wherein STV represents the input signal of the first-stage GOA circuit in the cascaded GOA circuit; TP represents the latched output signal, which is a signal generated by the data signal processing module 205 based on the first intermediate data for controlling the time when the first drive data is emitted; G1 to G6 respectively represent the first clock signals transmitted by the six clock signal lines. The pixels arranged in an array in the display panel all meet the row scanning design under the second display mode (e.g., single refresh rate) and the first display mode (e.g., double refresh rate):

[0235] It should be noted that, no matter in the second display mode or the first display mode, the charging time of a single row of pixels does not change.

[0236] As shown in FIG11 , in the second display mode, the clock drive of the GOA circuit scans row by row at a single refresh rate, that is, each row is charged normally at a single refresh rate.

[0237] Taking a UHD 240Hz display with a GOA circuit connected to six clock signal lines as an example, the driving process for normal charging of row i and mixed charging of row i+1 is described in detail. As shown in Figures 12a and 12b, in the first display mode, the clock drive of the GOA circuit scans row by row at double the refresh rate, meaning that each row is charged normally at double the refresh rate. In particular, when the clock drive scans row by row at double the refresh rate, the clock period of the first clock signal is shortened by half, simultaneously advancing the charging time by half a row.

[0238] As shown in Figures 12a and 12b, the display panel includes two sets of cascaded GOA circuits to achieve single- and double-row scanning drive switching. At the same time, a driving clock mode is added to the integrated control chip 20. The relationship with the gate drive data output by the GOA circuit is that, driven by this first clock signal, the GOA circuit outputs a line of real data, such as the gate drive data of the i-th row under normal circumstances, and outputs a line of mixed data, such as a mixture of the gate drive data of the i-th row and the gate drive data of the i+2-th half row. The interlaced TP signal is blanked, thereby doubling the refresh rate of the display image, for example, from 240Hz to 480Hz.

[0239] In a fourth aspect, an embodiment of the present disclosure further provides a display system, comprising a display terminal according to any embodiment of the second aspect or a combination thereof.

[0240] FIG13 is a schematic diagram of a display system provided by an embodiment of the present disclosure. As shown in FIG13 , the display system includes a display terminal and a processor 300. The display terminal, for example, includes a display panel 200 and a drive device 100. The processor 300 can be a central processing unit (CPU) integrated in a host; alternatively, it can be a CPU integrated in a display terminal.

[0241] In some embodiments, as shown in Figure 13, the processor 300 is configured to traverse all software installed on the display panel 200 to determine whether OSD software exists; if it is determined that the display panel does not have OSD software installed, the processor 300 sends installation information to the integrated control chip 20; the integrated control chip 20 is further configured to read the first download URL of the OSD software from the storage module 30 in response to the received installation information, and send the first download URL in the form of a picture to the user interface of the display panel for display, so that the user can link to the corresponding first preset web page based on the first download address to download the OSD software.

[0242] In order to more clearly understand the execution process of downloading OSD software, the following is an explanation of the complete process.

[0243] FIG14 is a flow chart of downloading OSD software provided by an embodiment of the present disclosure. As shown in FIG14 , the processor specifically executes steps S31 to S33 , and the integrated control chip specifically executes steps S34 to S35 .

[0244] S31. The processor traverses all software installed on the display panel.

[0245] The processor records in advance the identity of each software installed on the display terminal.

[0246] For example, the processor 300 may be configured with the OSD software that needs to be installed when it leaves the factory. Therefore, the processor 300 detects whether it has a network connection, and if it has a network connection, based on the identity of the OSD software, it regularly traverses all the software installed on the display panel and determines whether the OSD software exists.

[0247] S32. The processor determines whether the OSD software exists. If not, S33 is executed in sequence. If so, the processor executes the following update process of S41 (not shown in the figure).

[0248] S33. The processor sends installation information to the integrated control chip.

[0249] If the OSD software's identity does not match the identity of all software installed on the display panel, it can be determined that the OSD software is not installed on the display panel, and installation information needs to be sent to the integrated control chip. The installation information is used to represent the instruction information for installing the OSD software.

[0250] S34. The integrated control chip reads the first download URL of the OSD software from the storage module in response to the received installation information.

[0251] The integrated control chip includes an internal OSD module. The internal OSD module reads a first download URL of the OSD software from an external memory in response to the received installation information.

[0252] S35. The integrated control chip sends the first download URL in the form of a picture to the user interface of the display panel for display, so that the user can link to the corresponding first preset web page based on the first download address to download the OSD software.

[0253] The internal OSD module can control the image output, send the first download URL in the form of a picture to the user interface of the display panel for display, and guide the user to download the OSD software version that matches their model.

[0254] The first download address can be linked to a first preset webpage, which pre-stores the latest version of the OSD software.

[0255] It should be noted that the first downloading URL pre-stored in the external memory remains unchanged, and the installation package of the OSD software in the first preset webpage linked to the first downloading URL will be updated from time to time.

[0256] Illustratively, images include but are not limited to any form of pop-up windows, controls, and widgets.

[0257] This embodiment provides a novel method for downloading OSD software, allowing users to conveniently remotely download OSD software to multiple display panels with the same architecture while connected to a network, thereby improving download efficiency. Furthermore, compared to related techniques that directly store OSD software in a large-capacity memory, the present disclosure utilizes a small external memory to store the first download address, allowing for remote downloading while connected to a network, thus saving memory resources and costs.

[0258] In some embodiments, as shown in FIG13 , the display system further includes a backend server 2000. The processor 300 is further configured to, upon determining that the display panel has OSD software installed, read the version identification information of the OSD software currently running on the display panel and the serial identification information of the display terminal, and upload the information to the backend server 2000; and, in response to a first update instruction, send first update information to the integrated control chip 20. The backend server 2000 is configured to, in response to the received version identification information and serial identification information, determine whether the OSD software indicated by the version identification information is the latest version, and, if it is determined that the OSD software indicated by the version identification information is not the latest version, send the first update instruction to the processor 300 of the display terminal indicated by the serial identification information. The integrated control chip 20 is further configured to, in response to the received first update information, read a first download URL of the OSD software from the storage module, and send the first download URL in the form of an image to the user interface of the display panel 200 for display, so that the user can download the OSD software by linking to the corresponding first preset webpage based on the first download address.

[0259] In order to more clearly understand the execution process of updating OSD software, a complete process is described below.

[0260] FIG15 is a flowchart of updating OSD software provided by an embodiment of the present disclosure. As shown in FIG15 , the processor specifically executes steps S41 and S44 , the background server specifically executes steps S42 and S43 , and the integrated control chip specifically executes steps S45 and S46 .

[0261] Following the above step S32, the processor determines whether the OSD software exists. If so, the processor executes S41 in sequence.

[0262] S41 : The processor reads the version identification information of the OSD software currently running on the display panel and the serial identification information of the display terminal, and uploads them to the background server.

[0263] The version identification information can represent the version number of the OSD software, which is used to determine whether the OSD software corresponding to the version identification information is the latest version. The serial identification information can represent the serial number of the display terminal, which is used by the backend server to send corresponding information to the corresponding display terminal.

[0264] S42: The backend server responds to the received version identification information and serial identification information and determines whether the OSD software indicated by the version identification information is the latest version. If yes, the process ends. If not, S43 is executed sequentially.

[0265] S43. The backend server sends a first update instruction to the processor of the display terminal indicated by the sequence identification information.

[0266] S44. The processor sends first update information to the integrated control chip in response to the first update instruction.

[0267] S45 . The integrated control chip reads a first download URL of the OSD software from the storage module in response to the received first update information.

[0268] The integrated control chip includes an internal OSD module. The internal OSD module reads a first download URL of the OSD software from an external memory in response to the received first update information.

[0269] S46. The integrated control chip sends the first download URL in the form of a picture to the user interface of the display panel for display, so that the user can link to the corresponding first preset web page based on the first download address to download the latest version of the OSD software.

[0270] The internal OSD module can control the image output, send the first download URL in the form of a picture to the user interface of the display panel for display, and guide the user to download the latest version of the OSD software.

[0271] Illustratively, images include but are not limited to any form of pop-up windows, controls, and widgets.

[0272] This embodiment provides a novel OSD software update method that allows users to conveniently remotely update OSD software for multiple types of display panels with the same architecture while connected to a network, thereby improving update efficiency. Furthermore, compared to related techniques that directly store updated OSD software versions in large-capacity memory, the present disclosure utilizes a small external memory to store the first download address, allowing for remote updates while connected to a network, thus saving memory resources and costs.

[0273] In some embodiments, the display panel is configured to, in response to a user clicking a first download URL, display a first preset webpage and send a first download instruction to a backend server. The backend server is further configured to, in response to a command issued by the processor based on the first download instruction, display an installation package for the latest version of the OSD software on the first preset webpage.

[0274] In this embodiment, the backend server automatically maintains and pushes the latest version of the OSD software to the first preset web page linked to it when the user clicks on the first download URL.

[0275] In some embodiments, as shown in Figure 13, the processor 300 is configured to read the verification identification information of the first display mode code and the serial identification information of the display terminal pre-stored in the storage module, and upload them to the background server 2000; and, in response to the second update instruction, send the second update information to the integrated control chip; the background server 2000 is configured to determine whether the first display mode code indicated by the verification identification information is the latest version in response to the received verification identification information and serial identification information, and if the first display mode code is not the latest version, send the second update instruction to the processor 300 of the display terminal indicated by the serial identification information; the integrated control chip 20 is also configured to read the second download URL of the first display mode code from the storage module in response to the received second update information, and send the second download URL in the form of a picture to the user interface of the display panel 200 for display, so that the user can link to the corresponding second preset web page based on the second download address to download the first display mode code.

[0276] In order to more clearly understand the execution process of updating the first display mode code, a complete process is described below.

[0277] FIG16 is a flowchart of updating OSD software provided by an embodiment of the present disclosure. As shown in FIG16 , the processor specifically executes steps S51 and S54 , the background server specifically executes steps S52 and S53 , and the integrated control chip specifically executes steps S55 and S56 .

[0278] S51: The processor reads the verification identification information of the first display mode code and the sequence identification information of the display terminal pre-stored in the storage module, and uploads them to the background server.

[0279] For example, the processor may periodically read the first display mode code pre-stored in the storage module to detect whether it is the latest version. Alternatively, the processor may read the first display mode code pre-stored in the storage module in response to a user-initiated instruction.

[0280] The verification identification information may represent the version number of the first display mode code, and is used to subsequently determine whether the first display mode code corresponding to the verification identification information is the latest version.

[0281] Exemplarily, the storage module includes an external memory, and the processor can read the verification identification information of the first display mode code and the sequence identification information of the display terminal in the external memory through an IIC interface.

[0282] S52: The backend server responds to the received verification identification information and sequence identification information and determines whether the first display mode code indicated by the verification identification information is the latest version. If yes, the process ends. If not, S53 is executed sequentially.

[0283] S53: Send a second update instruction to the processor of the display terminal indicated by the sequence identification information.

[0284] S54: The processor sends second update information to the integrated control chip in response to the second update instruction.

[0285] S55 . The integrated control chip reads a second download URL of the first display mode code from the storage module in response to the received second update information.

[0286] The integrated control chip includes an internal OSD module. The internal OSD module reads a second download URL of the first display mode code from the external memory in response to the received second update information.

[0287] S56. The integrated control chip sends the second download URL in the form of a picture to the user interface of the display panel for display, so that the user can link to the corresponding second preset web page based on the second download address to download the first display mode code.

[0288] The internal OSD module can control the image output, send the second download URL in the form of a picture to the user interface of the display panel for display, and guide the user to download the latest version of the first display mode code.

[0289] Illustratively, images include but are not limited to any form of pop-up windows, controls, and widgets.

[0290] This embodiment provides a novel method for updating the first display mode code, allowing users to conveniently remotely update the first display mode code for multiple types of display panels with the same architecture while connected to a network, thereby improving update efficiency. Furthermore, compared to related techniques that directly store the updated version of the first display mode code in a large-capacity memory, the present disclosure utilizes a small external memory to store the second download address, allowing for remote updates while connected to a network, thus saving memory resources and costs.

[0291] In some embodiments, the display panel is configured to display a second preset web page and send a second download instruction to the processor in response to a user clicking on a second download URL; the backend server is configured to display the installation package of the latest version of the first display mode code on the second preset web page in response to a command issued by the processor according to the second download instruction.

[0292] The first display mode code downloaded by the user is transmitted to the external memory through the IIC interface and DP / HDMI for storage, so as to be called in the first display mode.

[0293] In this embodiment, the backend server automatically maintains and pushes the first display mode code of the latest version to the second preset web page linked to it when the user clicks on the second download URL.

[0294] In some embodiments, considering that the first display mode code update process may encounter unexpected situations such as sudden power outages, the present disclosure also provides a solution for partitioning the storage space of the external memory and copying the stored first display mode code to different partitions. The specific description is as follows:

[0295] Figure 17 is a schematic diagram of the external memory provided by an embodiment of the present disclosure. As shown in Figure 17, the storage module 30 includes an external memory 301; the external memory 301 includes a current version storage unit 3011, a backup version storage unit 3012 and a stable version storage unit 3013; the stable version storage unit 3013 is used to store the first display mode code at the time of leaving the factory; the current version storage unit 3011 is used to store the first display mode code downloaded during the update phase; the backup version storage unit 3012 is used to periodically back up the first display mode code in the current version storage unit 3011.

[0296] Exemplarily, the processor 300 is also configured to respond to an instruction indicating an abnormal update of the first display mode code and detect whether the first display mode code stored in the current version storage unit 3011 is abnormal; if there is an abnormality in the first display mode code stored in the current version storage unit 3011, detect whether the first display mode code stored in the backup version storage unit 3012 is abnormal; if there is no abnormality in the first display mode code stored in the backup version storage unit 3012, call the latest version of the first display mode code in the backup version storage unit 3012 to store in the current version storage unit; if there is an abnormality in the first display mode code stored in the backup version storage unit 3012, call the first display mode code at the time of shipment from the stable version storage unit 3013 to store in the backup version storage unit 3012 to ensure the normal operation of the first display mode of the display terminal.

[0297] In a fifth aspect, embodiments of the present disclosure further provide a computer device. FIG18 is a schematic diagram of the structure of a computer device provided by embodiments of the present disclosure. As shown in FIG18 , the computer device includes: one or more processors 601, a memory 602, and one or more I / O interfaces 603. The memory 602 stores one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement any of the display methods described in the above embodiments. The one or more I / O interfaces 603 are connected between the processor and the memory and are configured to implement information exchange between the processor and the memory.

[0298] Among them, the processor 601 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 602 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) 603 is connected between the processor 601 and the memory 602, and can realize information interaction between the processor 601 and the memory 602, including but not limited to a data bus (Bus), etc.

[0299] In some embodiments, the processor 601 , the memory 602 , and the I / O interface 603 are connected to each other via a bus 604 , and further connected to other components of the computing device.

[0300] In a sixth aspect, according to an embodiment of the present disclosure, a non-transitory computer-readable storage medium is further provided. The non-transitory computer-readable storage medium stores a computer program, wherein when the program is executed by a processor, the steps of the display method in any of the above embodiments are implemented.

[0301] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a machine-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), the above-mentioned functions defined in the system of the present disclosure are executed.

[0302] It should be noted that the computer non-transitory readable medium shown in the present disclosure can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any non-transitory computer-readable storage medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the non-transitory computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical cable, RF, etc., or any suitable combination thereof.

[0303] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architectures, functions and operations of the devices, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the aforementioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two connected boxes can actually represent execution in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0304] The circuits or sub-circuits described in the embodiments of the present disclosure may be implemented in software or hardware. The described circuits or sub-circuits may also be provided in a processor. For example, they may be described as: a processor comprising: a receiving circuit and a processing circuit, wherein the processing module comprises a writing sub-circuit and a reading sub-circuit. The names of these circuits or sub-circuits do not, in certain circumstances, constitute limitations on the circuits or sub-circuits themselves. For example, a receiving circuit may also be described as "receiving a video signal."

[0305] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A driving device, applied to a display terminal; the operating mode of the display terminal includes a first display mode; the driving device includes a graphics card, an integrated control chip, a storage module, and a driving chip; The graphics card is configured to, in the first display mode, read pre-set first extended display identification data corresponding to the first display mode from the storage module, generate first display data corresponding to the first display mode according to the first extended display identification data, and send the generated first display data to the integrated control chip; The integrated control chip is configured to generate a first clock signal and first driving data according to the received first display data in the first display mode, and send the first clock signal to the display panel and send the first driving data to the driving chip; The driver chip is configured to convert the first driving data into a first data voltage signal and send the first data voltage signal to the display panel, so that the display panel drives pixels to display images according to the received first clock signal and the first data voltage signal.

2. The driving device according to claim 1, wherein: The integrated control chip includes an input interface, an internal OSD module, a filter module, a clock module, a data signal processing module and an output interface; The internal OSD module is configured to start the first display mode in response to an instruction to start the first display mode; The filtering module is configured to, in response to receiving the first display data from the input interface, filter the first display data to generate first intermediate data, and send the first intermediate data to the clock module and the data signal processing module respectively; The clock module is configured to convert the first intermediate data into the first clock signal and send the first clock signal to the display panel; The data signal processing module is configured to convert the first intermediate data into the first driving data and send the first driving data to the driving chip through the output interface.

3. The driving device according to claim 2, wherein: The storage module includes an external memory; The internal OSD module is specifically configured to call the first display mode code from the external memory and deploy it to the filtering module in response to an instruction to start the first display mode; The filtering module is specifically configured to deploy the first display mode code; in response to receiving the first display data from the input interface, filter the first display data using the first display mode code to generate the first intermediate data, and send it to the clock module and the data signal processing module respectively.

4. The driving device according to claim 3, wherein: The storage module also includes an external register; The internal OSD module is further configured to, in response to an instruction to start the first display mode, read the first extended display identification data from the external memory and send the first extended display identification data to the external register; The graphics card is specifically configured to read the first extended display identification data from the external register, generate first display data corresponding to the first display mode according to the first extended display identification data, and send the first display data to the integrated control chip.

5. The driving device according to claim 2, wherein: The input interface is at least one of an HDMI interface, a DP interface, a VGA interface, and a Type-C interface; the output interface is any one of a mini-LVDS interface and a P2P interface.

6. The driving device according to claim 1, wherein: The integrated control chip further includes a backlight control module; the driving device further includes a power supply chip; The backlight control module is configured to generate a backlight control instruction according to the working mode and send the backlight control instruction to the power chip; The power chip is configured to control the on / off state of the backlight module of the display panel in response to the received backlight control instruction.

7. The driving device according to claim 1, wherein: The first display mode is determined based on a user's selection of a first display mode option in an OSD menu; the OSD menu is displayed on a user interface UI of the display panel.

8. The driving device according to claim 1, wherein: The driving device further includes an external switch module; The external switch module is configured to control the display terminal to enter the first display mode in response to a first trigger operation of a user.

9. The driving device according to claim 8, wherein: The working mode also includes a second display mode; The refresh rate corresponding to the first display mode is greater than the refresh rate corresponding to the second display mode, and / or the resolution of the first display mode is greater than the resolution corresponding to the second display mode.

10. The driving device according to claim 9, wherein: The graphics card is further configured to, in the second display mode, read pre-set second extended display identification data corresponding to the second display mode from the storage module, generate second display data corresponding to the second display mode according to the second extended display identification data, and send the second display data to the integrated control chip; The integrated control chip is further configured to, in the second display mode, generate a second clock signal and second drive data according to the received second display data, and send the second clock signal to the display panel and send the second drive data to the driver chip; The driver chip is further configured to convert the second drive data into a second data voltage signal and send the second data voltage signal to the display panel, so that the display panel drives the pixels to display the picture according to the received second clock signal and the second data voltage signal.

11. The driving device according to claim 1, wherein: The integrated control chip also includes an audio control module; The audio control module is configured to convert the received audio data into an audio signal and send the audio signal to the audio output port.

12. The driving device according to claim 1, wherein The integrated control chip also includes a picture detection module; The image detection module is configured to detect whether there is any abnormality in the image to be displayed in the first display data in response to the first display data provided by the graphics card, and control the polarity of the driving mode of the display panel to be reversed if it is determined that there is an abnormality in the image to be displayed.

13. A display terminal comprising the driving device according to any one of claims 1 to 12.

14. The display terminal according to claim 13, wherein: The display terminal also includes a display panel; The display panel is configured to display an OSD menu in a user interface; the OSD menu includes a control representing the first display mode; In response to a user selecting a control of the first display mode, an instruction for starting the first display mode is sent to the integrated control chip.

15. A display system comprising the display terminal according to claim 13 or 14.

16. The display system according to claim 15, wherein: The display system further includes a processor; The processor is configured to traverse all software installed on the display panel and determine whether OSD software exists; if it is determined that the display panel does not have the OSD software installed, send installation information to the integrated control chip; The integrated control chip is further configured to read a first download URL of the OSD software from the storage module in response to the received installation information, and send the first download URL in the form of a picture to the user interface of the display panel for display, so that the user can link to the corresponding first preset web page based on the first download address to download the OSD software.

17. The display system according to claim 16, wherein: The display system also includes a background server; The processor is further configured to, when determining that the display panel has the OSD software installed, read version identification information of the OSD software currently running on the display panel and serial identification information of the display terminal, and upload the information to the background server; and, in response to a first update instruction, sending first update information to the integrated control chip; The backend server is configured to respond to the received version identification information and the sequence sequence identification information, determining whether the OSD software indicated by the version identification information is the latest version, and sending the first update instruction to the processor of the display terminal indicated by the sequence identification information if it is determined that the OSD software indicated by the version identification information is not the latest version; The integrated control chip is further configured to read a first download URL of the OSD software from the storage module in response to the received first update information, and send the first download URL in the form of a picture to the user interface of the display panel for display, so that the user can link to the corresponding first preset web page based on the first download address to download the latest version of the OSD software.

18. The display system according to claim 16 or 17, wherein: The image includes one of a pop-up window, a control, and a widget.

19. The display system according to claim 17, wherein: The display panel is configured to display the first preset web page and send a first download instruction to the processor in response to a user clicking on the first download URL; The backend server is further configured to display the installation package of the latest version of the OSD software on the first preset webpage in response to a command issued by the processor according to the first download instruction.

20. The display system according to claim 15, wherein: The display system further includes a processor; the display system further includes a background server; The processor is configured to read the verification identification information of the first display mode code and the serial identification information of the display terminal pre-stored in the storage module, and upload them to the background server; and, in response to a second update instruction, sending second update information to the integrated control chip; The backend server is configured to, in response to the received verification identification information and the sequence identification information, determine whether the first display mode code indicated by the verification identification information is the latest version, and if the first display mode code is not the latest version, send the second update instruction to the processor of the display terminal indicated by the sequence identification information; The integrated control chip is further configured to read the second download URL of the first display mode code from the storage module in response to the received second update information, and send the second download URL to the user interface of the display panel in the form of a picture for display, so that the user can view the second download URL based on the second update information. The second download address is linked to a corresponding second preset webpage to download the first display mode code.

21. The display system according to claim 20, wherein: The display panel is configured to display the second preset web page and send a second download instruction to the processor in response to a user clicking on the second download URL; The backend server is configured to display the installation package of the latest version of the first display mode code on the second preset webpage in response to a command issued by the processor according to the second download instruction.

22. The display system according to claim 21, wherein: The storage module includes an external memory; the external memory includes a current version storage unit, a backup version storage unit and a stable version storage unit; The stable version storage unit is used to store the first display mode code at the time of shipment; The current version storage unit is used to store the first display mode code downloaded during the update phase; The backup version storage unit is used to periodically back up the first display mode code in the current version storage unit; The processor is further configured to, in response to an instruction indicating an abnormal update of the first display mode code, detect whether the first display mode code stored in the current version storage unit is abnormal; if the first display mode code stored in the current version storage unit is abnormal, detect whether the first display mode code stored in the backup version storage unit is abnormal; if the first display mode code stored in the backup version storage unit is not abnormal, call the latest version of the first display mode code in the backup version storage unit to the current version storage unit for storage; if the first display mode code stored in the backup version storage unit is abnormal, call the first display mode code at the time of shipment from the stable version storage unit to the backup version storage unit for storage.

23. A display method, applied to a display terminal; The operating mode of the display terminal includes a first display mode; In the first display mode, the display method includes: Reading pre-set first extended display identification data corresponding to the first display mode; generating first display data corresponding to the first display mode according to the first extended display identification data; generating a first clock signal and first driving data according to the received first display data, and sending the first clock signal to the display panel; converting the first driving data into a first data voltage signal; Pixels are driven according to the first clock signal and the first data voltage signal to display a picture.

24. The display method according to claim 23, wherein: The step of driving pixels to display images according to the first clock signal and the first data voltage signal includes: In response to the first clock signal, the i-th row of gate drive data is output to the i-th row of pixels, and mixed data of the i-th row of gate drive data and the i+2-th half row of gate drive data is output to the i+1-th row of pixels, and in response to the first data voltage signal, the screen is displayed, where i is a positive integer greater than 1.

25. A computer device, wherein: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the computer device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the display method according to claim 23 or 24 are performed.

26. A computer non-transitory readable storage medium, wherein: The computer non-transitory readable storage medium stores a computer program, which, when executed by a processor, executes the steps of the display method according to claim 23 or 24.

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