Back-contact cell, cell string, cell module and photovoltaic system

Abstract

The present application relates to the technical field of solar cells. Provided are a back-contact cell (100), a cell string (201), a cell module (200) and a photovoltaic system (1000). In the back-contact cell (100), several first doped layers (12) and several second doped layers (13) are provided on a back surface (11) of a silicon substrate (10), wherein the several first doped layers (12) and the several second doped layers (13) are sequentially and alternately arranged in a first direction and extend in a second direction; and in the second direction, the silicon substrate (10) has a first edge (101) and a second edge (102) which are opposite each other. Several first fingers (20) and several second fingers (30) are alternately arranged spaced apart from each other in the first direction. Each first finger (20) is provided with several first discontinuous regions (21) spaced apart from each other in the second direction, each second finger (30) is provided with several second discontinuous regions (31) spaced apart from each other in the second direction, and the first fingers (20) do not extend to the first edge (101) of the silicon substrate (10). A first edge busbar line (40) is arranged close to the first edge (101) and extends in the first direction, and the first edge busbar line (40) is electrically connected to the first fingers (20). A second edge busbar line (50) extends in the first direction, is arranged between the first edge busbar line (40) and the first edge (101), and is located above the second doped layer (13), and the second edge busbar line (50) comes into contact with at least one second doped layer (13) and is electrically connected to one end of some of the second fingers (30) close to the first edge (101).

Description

Back contact cells, cell strings, cell modules and photovoltaic systems

[0001] Priority information

[0002] This application claims priority and benefits of patent application No. 202311671762.X filed with the State Intellectual Property Office of China on December 7, 2023, and the entire text of which is incorporated herein by reference. Technical Field

[0003] The present application relates to the technical field of solar cells, and in particular to a back-contact cell sheet, a cell string, a cell assembly and a photovoltaic system. Background Art

[0004] A back-contact solar cell is a type of cell in which both a P-type doped layer and an N-type doped layer are arranged on the back of a silicon wafer. In a back-contact solar cell, the back side is provided with alternating auxiliary grids and alternating main grids. The main grids and auxiliary grids are arranged in a cross-pattern. To prevent leakage, the auxiliary grids are usually disconnected at the opposite polarity main grids. In related art, the auxiliary grids on the back side of a back-contact solar cell typically do not extend to the edges of the silicon wafer. Part of the edge will have a portion without a metal auxiliary grid, resulting in a portion of the edge where carriers cannot be collected, resulting in low carrier collection efficiency, efficiency loss, and low efficiency of the cell.

[0005] Summary of the Invention

[0006] The present application provides a back-contact cell, a cell string, a cell assembly and a photovoltaic system.

[0007] The present application is implemented as follows: the back contact cell of the embodiment of the present application comprises:

[0008] a silicon substrate, wherein a plurality of first doped layers and a plurality of second doped layers are provided on a back surface of the silicon substrate, the plurality of first doped layers and the plurality of second doped layers are alternately arranged in sequence along a first direction and extend along a second direction, the first direction intersecting the second direction, and the silicon substrate having a first edge and a second edge opposite to each other in the second direction;

[0009] a plurality of first auxiliary gates and a plurality of second auxiliary gates alternately arranged along the first direction, wherein the first auxiliary gates are arranged above the first doped layer, and the second auxiliary gates are arranged above the second doped layer; the first auxiliary gates have a plurality of first discontinuity regions spaced apart in the second direction, and the second auxiliary gates have a plurality of second discontinuity regions spaced apart in the second direction, the first discontinuity regions on adjacent first auxiliary gates correspond to each other in the first direction, and the second discontinuity regions on adjacent second auxiliary gates correspond to each other in the first direction, and the first discontinuity regions and the second discontinuity regions are alternately arranged in sequence in the second direction, and the first auxiliary gates do not extend to the first edge of the silicon substrate;

[0010] a first edge bus bar line disposed close to the first edge and extending along the first direction, the first edge bus bar line being electrically connected to the first auxiliary grid; and

[0011] A second edge busbar line is extended along the first direction, the second edge busbar line is arranged between the first edge busbar line and the first edge and is located above the second doped layer, the second edge busbar line is in contact with at least one of the second doped layers and is electrically connected to an end of a portion of the second sub-grid close to the first edge.

[0012] The present application also provides a battery string, comprising several back-contact battery cells as described above, wherein in two adjacent back-contact battery cells, the first discontinuity region of one back-contact battery cell corresponds to the second discontinuity region of the other back-contact battery cell in the first direction.

[0013] The present application also provides a battery assembly, which includes several of the above-mentioned battery strings.

[0014] The present application also provides a photovoltaic system, which includes the above-mentioned battery assembly.

[0015] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG1 is a schematic structural diagram of a back-contact cell provided in an embodiment of the present application;

[0017] FIG2 is a partially enlarged schematic diagram of a back-contact cell provided in an embodiment of the present application;

[0018] FIG3 is a schematic cross-sectional view of the back contact cell in FIG1 at the second edge busbar line;

[0019] FIG4 is another partially enlarged schematic diagram of a back-contact cell provided in an embodiment of the present application;

[0020] FIG5 is a schematic cross-sectional view of the back contact cell in FIG1 at the fourth edge busbar line;

[0021] FIG6 is another partially enlarged schematic diagram of a back-contact solar cell provided in an embodiment of the present application;

[0022] FIG7 is another schematic structural diagram of a back-contact cell provided in an embodiment of the present application;

[0023] FIG8 is a schematic cross-sectional view of the back contact cell in FIG7 at the fourth edge busbar line;

[0024] FIG9 is a schematic structural diagram of a battery string provided in an embodiment of the present application;

[0025] FIG10 is a schematic structural diagram of a photovoltaic system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, in which the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. It should be noted that the embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are merely used to explain the present application and are not intended to limit the present application.

[0027] In the description of this application, it should be understood that the terms "up", "down", "left", "right", "horizontal", "longitudinal", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "several" means two or more, unless otherwise specifically defined.

[0029] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0030] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art will appreciate the application of other processes and / or the use scenarios of other materials.

[0031] Example 1

[0032] 1 and 2 , a back-contact cell 100 in an embodiment of the present application may include a silicon substrate 10 , a plurality of first sub-grids 20 , a plurality of second sub-grids 30 , a first edge bus bar 40 , and a second edge bus bar 50 .

[0033] 3 , a plurality of first doped layers 12 and a plurality of second doped layers 13 are provided on the back side 11 of the silicon substrate 10. The plurality of first doped layers 12 and the plurality of second doped layers 13 are alternately arranged in sequence along a first direction and extend along a second direction. The first direction intersects the second direction. In the second direction, the silicon substrate 10 has a first edge 101 and a second edge 102 that are opposite to each other.

[0034] The first doped layer 12 and the second doped layer 13 have opposite polarities. For example, the first doped layer 12 may be a P-type doped layer, and the second doped layer 13 may be an N-type doped layer. For another example, the first doped layer 12 may be an N-type doped layer, and the second doped layer 13 may be a P-type doped layer. This is not particularly limited herein. The first doped layer 12 and the second doped layer 13 may be preferably spaced apart, and both the first doped layer 12 and the second doped layer 13 may extend to the first edge 101 and the second edge 102 of the silicon substrate 10. Preferably, the first direction may be the longitudinal direction of the back-contact cell 100, and the second direction may be the lateral direction of the back-contact cell 100, with the first and second directions being perpendicular to each other. Of course, in other embodiments, the first and second directions may not be perpendicular, or may not be lateral and longitudinal directions. For example, the first and second directions may be diagonal directions of the silicon substrate 10, respectively. This is not particularly limited herein.

[0035] As shown in Figure 1, several first sub-gates 20 and several second sub-gates 30 are alternately arranged along the first direction. The first sub-gates 20 are arranged above the first doped layer 12, and the second sub-gates 30 are arranged on the second doped layer 13. The first sub-gates 20 are used to collect current in the first doped layer 12, and the second sub-gates 30 are used to collect current in the second doped layer 13.

[0036] As shown in FIG1 , the first auxiliary gate 20 has a plurality of first discontinuity regions 21 spaced apart in the second direction, and the second auxiliary gate 30 has a plurality of second discontinuity regions 31 spaced apart in the second direction. The first discontinuity regions 21 on adjacent first auxiliary gates 20 correspond to each other in the first direction, and the second discontinuity regions 31 on adjacent second auxiliary gates 30 correspond to each other in the first direction. In the second direction, the first discontinuity regions 21 and the second discontinuity regions 31 are alternately arranged in sequence, and the first auxiliary gate 20 does not extend to the first edge 101 of the silicon substrate 10.

[0037] It should be noted that "the first discontinuity regions 21 on adjacent first sub-grids 20 correspond to each other in the first direction, and the second discontinuity regions 31 on adjacent second sub-grids 30 correspond to each other in the first direction" means that, in the first direction, the first discontinuity regions 21 are substantially aligned, and the second discontinuity regions 31 are also substantially aligned. "In the second direction, the first discontinuity regions 21 and the second discontinuity regions 31 are alternately arranged" means that, in the entire back contact cell 100, the first discontinuity regions 21 and the second discontinuity regions 31 are alternately arranged in the second direction.

[0038] Specifically, the first interrupted area 21 and the second interrupted area 31 may be used to set a main grid and / or a welding strip to achieve busbar output.

[0039] 1 and 2 , the first edge bus bar line 40 is disposed near the first edge 101 and extends along the first direction. The first edge bus bar line 40 is electrically connected to the first sub-grid 20 .

[0040] The second edge bus line 50 extends along the first direction and is arranged between the first edge bus line 40 and the first edge 101 and is located above the second doped layer 13. The second edge bus line 50 contacts at least one second doped layer 13 and is electrically connected to an end of a portion of the second sub-gate 30 close to the first edge 101.

[0041] Specifically, the second edge busbar line 50 can be directly connected to a portion of the second sub-grid 30 or connected to a portion of the second sub-grid 30 through other connecting lines (such as the first auxiliary grid line 60 described below). It should be noted that "a portion of the second sub-grid 30" refers to one second sub-grid 30 or multiple second sub-grids 30 but not all of the second sub-grids 30.

[0042] In the related art, the back side grid of the back contact solar cell usually does not extend to the edges of both sides of the silicon wafer, because if it extends to the edge, in order to realize the current collection of the grid at the edge area, it is necessary to set a main grid and / or a welding strip at the edge to connect to the grid at the edge area. If the grid with the opposite polarity to the main grid and / or welding strip extends to the edge of the silicon wafer, in order to avoid the welding strip at the edge position from contacting the opposite grid, an insulating glue needs to be applied between the welding strip at the edge position and each opposite grid, resulting in a significant increase in cost, and it is also easy to cause glue leakage, thereby causing the cell to bend and warp. However, if the grid does not extend to the edge of the silicon wafer, there will be a part of the edge without a metal grid, resulting in a part of the edge where the carriers cannot be collected, resulting in a low carrier collection efficiency, efficiency loss, and low efficiency of the cell.

[0043] In the back-contact cell 100 of the embodiment of the present application, the first auxiliary grid 20 does not extend to the first edge 101 of the silicon substrate 10, the first edge bus line 40 is arranged near the first edge 101 and extends along the first direction, the first edge bus line 40 is electrically connected to the first auxiliary grid 20, the second edge bus line 50 is extended along the first direction and is arranged between the first edge bus line 40 and the first edge 101, the second edge bus line 50 is in contact with at least one second doped layer 13 and is electrically connected to an end of a portion of the second auxiliary grid 30 near the first edge 101. In this way, by setting the second edge bus line 50 between the first edge 101 and the first edge bus line 40 and making the second edge bus line 50 contact with at least one second doped layer 13 and connected to part of the second auxiliary grid 30, the second edge bus line 50 can collect the current of the second doped layer 13 in the edge area of ​​the first edge 101 and converge it to the adjacent same-polarity main grid and / or welding strip through part of the second auxiliary grid 30 to realize current collection, which can effectively reduce the efficiency loss in the edge area of ​​the first edge 101 and improve the efficiency of the battery cell.

[0044] Furthermore, since only a portion of the second auxiliary grid 30 is connected to the second edge busbar line 50, during the subsequent welding of the opposite polarity welding strip (e.g., the edge welding strip 203 in FIG9 ), the welding strip will only cross a portion of the second auxiliary grid 30 or the connecting line connecting the second auxiliary grid 30 and the second edge busbar line 50 (e.g., the first auxiliary grid line 60 described below). There are fewer intersection points, and only a small number of points need to be provided with insulating glue to avoid leakage, which can effectively reduce costs. At the same time, the points where the insulating glue is applied are isolated points, and it is not easy to cause glue leakage and thus cause bending and warping of the cell. In other words, the technical solution of the present application can reduce the cost of insulating glue and avoid bending and warping of the cell due to glue leakage, while also effectively reducing efficiency loss and ensuring the efficiency of the cell. In addition, by providing the first edge busbar line 40, the anti-break function of the first auxiliary grid 20 can also be realized, thereby avoiding the occurrence of breakage of the first auxiliary grid 20 as much as possible.

[0045] Specifically, in the embodiments of the present application, the polarities of the first doped layer 12 and the second doped layer 13 are opposite, and the polarities of the first sub-grid 20 and the second sub-grid 30 are also opposite. For example, the first sub-grid 20 is a positive sub-grid line for collecting positive current in the positive region, and the second sub-grid 30 is a negative sub-grid line for collecting negative current in the negative region; or, the first sub-grid 20 is a negative sub-grid line for collecting negative current in the negative region, and the second sub-grid 30 is a positive grid line for collecting positive current in the positive region. The positive sub-grid line is provided in the P-type doped layer of the back-contact cell 100, and the negative sub-grid line is provided in the N-type doped layer of the back-contact cell 100.

[0046] In the embodiments of the present application, the back-contact cell 100 may be substantially rectangular. Substantially rectangular means that the back-contact cell 100 may be square, rectangular, or rectangular with standard chamfered or rounded corners. This configuration is determined based on actual production needs and is not limited here. Furthermore, the number of first and second auxiliary grids 20, 30 is determined based on the actual area of ​​the back-contact cell 100, and the width and distance between the first and second auxiliary grids 20, 30, and is not specifically limited here.

[0047] In the embodiment of the present application, “the first auxiliary gate 20 is formed with a plurality of first discontinuous regions 21 ” means that the first auxiliary gate 20 is a discontinuous structure, and the first auxiliary gate 20 is partitioned at the first discontinuous regions 21 , that is, the first discontinuous regions 21 partition the first auxiliary gate 20 into a plurality of parts. Similarly, “the second auxiliary gate 30 is formed with a plurality of second discontinuous regions 31 ” means that the second auxiliary gate 30 is a discontinuous structure, and the second auxiliary gate 30 is partitioned at the second discontinuous regions 31 , that is, the second discontinuous regions 31 partition the second auxiliary gate 30 into a plurality of parts.

[0048] In the embodiment shown in the figure, "first edge 101" refers to the left edge in Figure 1, and "second edge 102" refers to the right edge in Figure 1. The first edge bus bar line 40 and the second edge bus bar line 50 can be arranged parallel to the first edge 101 and the second edge 102, and the first sub-grid 20 and the second sub-grid 30 are arranged perpendicular to the first edge 101 and the second edge 102.

[0049] In the embodiment of the present application, to reduce the difficulty of manufacturing, preferably, no first sub-grid 20 is provided between the first edge bus bar line 40 and the first edge 101, and preferably, no first sub-grid 20 and second sub-grid 30 are provided between the second edge bus bar line 50 and the first edge 101. Of course, it is understood that, in some embodiments, the second sub-grid 30 may be provided between the second edge bus bar line 50 and the first edge 101 without the first sub-grid 20, and this is not limited to the specific embodiment.

[0050] Furthermore, in the embodiment of the present application, the first auxiliary grid 20 and the second auxiliary grid 30 may be aluminum grid lines, silver grid lines, copper grid lines, or silver-clad copper grid lines, which are not limited here.

[0051] It is understandable that in the embodiment of the present application, the first auxiliary gate 20 and the second auxiliary gate 30 can be selected to be gate lines of the same or different metal types, for example, the first auxiliary gate 20 and the second auxiliary gate 30 are both aluminum gate lines; or the first auxiliary gate 20 is aluminum gate lines and the second auxiliary gate 30 is silver gate lines.

[0052] As shown in Figures 2 and 3, it is not difficult to understand that the second edge bus grid line 50 is in contact with the second doped layer 13 to realize the collection of current of the second doped layer 13 in the edge area. Therefore, in the embodiment of the present application, in the first discontinuity region 21 of the first auxiliary grid 20 and the second discontinuity region 31 of the second auxiliary grid 30, the first discontinuity region 21 is closest to the first edge 101, that is, in the second direction, the first discontinuity region 21 and the second discontinuity region 31 are arranged alternately in sequence, and at the position corresponding to the first discontinuity region 21, the second auxiliary grid 30 is not disconnected, and a main grid and / or welding strip in contact with the second auxiliary grid 30 can be set at the position corresponding to the first discontinuity region 21 to realize the collection of current of the first edge bus grid line 40.

[0053] Example 2

[0054] Referring to FIG. 2 , in some embodiments, a portion of the second auxiliary gate 30 is insulated and passes through the first edge bus bar line 40 to be electrically connected to the second edge bus bar line 50 .

[0055] Thus, after collecting the current of the second doped layer 13 in the edge region of the first edge 101 , the second edge bus line 50 can collect the current to the nearest main grid and / or welding strip of the same polarity through the second auxiliary grid 30 passing through the first edge bus line 40 to realize current collection.

[0056] Specifically, as shown in FIG2 , in such an embodiment, the plurality of second sub-grids 30 may include a plurality of first collecting sub-grids 32 and a plurality of first penetrating sub-grids 33 . The plurality of first collecting sub-grids 32 are all located on the side of the first edge bus bar line 40 facing the second edge 102 , and the first penetrating sub-grids 33 are insulated and penetrate the first edge bus bar line 40 to connect with the second edge bus bar line 50 .

[0057] That is to say, in such an embodiment, there is no first collecting sub-grid 32 between the first edge bus bar line 40 and the first edge 101. Between the first edge bus bar line 40 and the first edge 101, only the position where the first edge bus bar line 40 is penetrated has the first penetrating sub-grid 33, and the remaining positions do not have sub-grids (including the first sub-grid 20 and the second sub-grid 30).

[0058] It should be noted that, in the embodiment of the present application, “part of the second sub-grid 30 is insulated and penetrates the first edge bus line 40” can be understood as, in the first direction, there are several spaced-apart partition areas on the first edge bus line 40, and the first penetrating sub-grid 33 passes through the first edge bus line 40 through the partition area and does not contact the first edge bus line 40, so as to achieve physical penetration and insulation isolation.

[0059] It is understood that in such an embodiment, the number of first through-grids 33 can be single or multiple, and the specific number can be determined according to the size of the solar cell. When there are multiple first through-grids 33, the multiple first through-grids 33 can be spaced apart along the first direction, and the distance between two adjacent first through-grids 33 can be determined according to the size of the solar cell. Preferably, the first through-grids 33 can be evenly spaced along the first direction on the silicon substrate 10 according to the size of the silicon substrate 10, but this is not limited to this.

[0060] It is not difficult to understand that in such an embodiment, the second edge bus line 50 can collect the current of the second doped layer 13 in the edge area of ​​the first edge 101, and then collect it to the nearest main grid and / or welding strip of the same polarity (such as the welding strip 202 below) through the first through-grid 33 running through the first edge bus line 40 to achieve convergence. By setting multiple first through-grids 33, the convergence path can be effectively shortened and the loss can be reduced.

[0061] Example 3

[0062] 1 and 2 , in some embodiments, in the first direction, the silicon substrate 10 further has a third edge 103 and a fourth edge 104 opposite to each other, and the third edge 103 is connected to the first edge 101 via a first chamfer 105 ;

[0063] In the direction from the third edge 103 to the fourth edge 104 , the second sub-grids 30 and the first sub-grids 20 are alternately arranged in sequence. A first auxiliary grid line 60 is provided at the first chamfer 105 . The first auxiliary grid line 60 connects the second edge bus bar line 50 and the second sub-grid 30 closest to the third edge 103 .

[0064] Thus, by disposing the first auxiliary grid line 60 at the first chamfer 105 , the current collected by the second edge bus grid line 50 can be converged to the second auxiliary grid 30 at the third edge 103 and then to the nearest main grid and / or welding strip.

[0065] Specifically, as shown in FIG1 , the third edge 103 is the upper edge of the silicon substrate 10, the fourth edge 104 is the lower edge of the silicon substrate 10, and the first edge 101 and the third edge 103 form a first chamfer 105. In such an embodiment, a first auxiliary gate line 60 is provided at the first chamfer 105 to connect the second edge bus grid line 50 and the uppermost second sub-grid 30. The current collected by the second edge bus grid line 50 can be converged through the first auxiliary gate line 60 and the second sub-grid 30 connected to the first auxiliary gate line 60 to the adjacent main grid and / or welding strip. That is, the second edge bus grid line 50 can be electrically connected to the uppermost second sub-grid 30 through the first auxiliary gate line 60.

[0066] It is understandable that in such an embodiment, the first through-grid 33 and the first auxiliary grid line 60 in the above-mentioned second embodiment can be provided to achieve current confluence, or the first through-grid 33 in the above-mentioned second embodiment can be omitted and the current confluence can be achieved through the first auxiliary grid line 60 at the first chamfer 105. Of course, in order to avoid excessive loss due to the long transmission path of the confluence, it is preferred to achieve current confluence through the first through-grid 33 or through the first through-grid 33 and the first auxiliary grid line 60, which is not limited here.

[0067] As shown in FIG2 , in some embodiments, the first auxiliary gate line 60 may be arranged parallel to the first chamfer 105. This can make the gate line structure of the back surface 11 simpler to manufacture.

[0068] Furthermore, in some embodiments, the first auxiliary gate line 60 may be located above the second doping layer 13 and contact at least one second doping layer 13 .

[0069] In this way, the first auxiliary gate line 60 can realize current convergence while also collecting current at the edge region at the first chamfer 105 , thereby further reducing efficiency loss and improving the efficiency of the solar cell.

[0070] Continuing to refer to FIG. 1 and FIG. 2 , in some embodiments, a second auxiliary gate line 70 may be further provided at the first chamfer 105, and the second auxiliary gate line 70 connects the first auxiliary gate 20 and the first edge bus gate line 40 located at the first chamfer 105. It should be noted that the "first auxiliary gate 20 located at the first chamfer 105" refers to a plurality of first auxiliary gates 20 that are not directly connected to the first edge bus gate line 40 and whose extension lines along the second direction intersect the first chamfer 105, such as the two uppermost first auxiliary gates 20 in FIG. 2 .

[0071] In this way, the first sub-grids 20 at the first chamfer 105 can be connected by setting the second auxiliary gate line 70 to achieve conduction between the first sub-grids 20 at the first chamfer 105. When the welding strip (such as the edge welding strip 203 below) is subsequently welded, it is only necessary to contact the welding strip with the second auxiliary gate line 70 to achieve the collection of the current of the first sub-grid 20 at the first chamfer 105. This can avoid the situation where the welding strip cannot contact all the first sub-grids 20 at the first chamfer 105 when welding the welding strip due to the existence of the first chamfer 105, resulting in the current of the first sub-grid 20 at the first chamfer 105 cannot be collected.

[0072] Specifically, as shown in Figure 2, in such an embodiment, the second auxiliary gate line 70 can also be arranged parallel to the first chamfer 105, that is, at the first chamfer 105, from the outside to the inside, the first chamfer 105, the first auxiliary gate line 60 and the second auxiliary gate line 70 are arranged in parallel in sequence.

[0073] As shown in FIG2 , it is not difficult to understand that, since the first auxiliary grid 20 has a first discontinuous region 21 at a position closest to the first edge 101, in order to achieve current convergence of the first auxiliary grid 20 near the first edge 101, a welding ribbon needs to be provided at the position of the first edge 101 to achieve conductive connection with the first auxiliary grid 20 to achieve current convergence. However, due to the presence of the first chamfer 105, the length of the top first auxiliary grid 20 is relatively short, and the welding ribbon cannot contact the top first auxiliary grid 20 when it is provided vertically. If the welding ribbon is too close to the inside, it is easy to contact the second auxiliary grid 30 of opposite polarity and cause leakage. Therefore, by providing the second auxiliary grid line 70, the first auxiliary grid 20 at the first chamfer 105 can be connected into a whole. When welding the welding ribbon, it only needs to contact the first edge bus grid line 40, or contact the first edge bus grid line 40 and the second auxiliary grid line 70 at the same time, or contact the remaining first auxiliary grids 20 and the second auxiliary grid line 79 connected to the first edge bus grid line 40 to achieve current convergence of all the first auxiliary grids 20.

[0074] Example 4

[0075] In some embodiments, the distance between the first edge bus bar line 40 and the first edge 101 (ie, the distance between the first edge bus bar line 40 and the first edge 101 in the second direction) is 0.5 mm to 2 mm.

[0076] In this way, setting the spacing between the first edge busbar line 40 and the first edge 101 within this reasonable range can effectively avoid the situation where the distance between the two is too large, resulting in too large an area of ​​the edge region without a secondary grid and causing excessive efficiency loss. It can also avoid the situation where the distance between the two is too small, resulting in cold solder joints and cracks when subsequently welding the solder strip at the first edge busbar line 40, thereby ensuring the reliability and stability of the welding.

[0077] Specifically, in such an embodiment, the distance between the first edge bus line 40 and the first edge 101 can be, for example, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.2mm, 1.4mm, 1.6mm, 1.8mm, 2mm or any value between 0.5mm-2mm, and is not limited here.

[0078] Furthermore, in an embodiment of the present application, the distance between the first edge bus bar 40 and the first edge 101 is preferably 0.8 mm to 1.2 mm, for example, 0.9 mm, etc. In this way, while reducing the difficulty of the process, it is possible to effectively avoid excessive distance resulting in excessive area of ​​the edge area and excessive efficiency loss, while also ensuring the stability and reliability of welding.

[0079] Example 5

[0080] In some embodiments, the distance between the second edge busbar line 50 and the first edge 101 (ie, the distance between the two in the second direction) is 0.3 mm to 1.2 mm.

[0081] In this way, on the one hand, it can avoid that the distance between the second edge bus line 50 and the first edge 101 is too small, which will greatly increase the difficulty of printing the second edge bus line 50; on the other hand, it can avoid that the distance between the second edge bus line 50 and the first edge 101 is too large, which will cause excessive efficiency loss.

[0082] Specifically, in such an embodiment, the distance between the second edge bus line 50 and the first edge 101 can be, for example, 0.3mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.2mm or any value between 0.3mm-1.2mm, which is not limited here.

[0083] Furthermore, in an embodiment of the present application, the distance between the second edge bus line 50 and the first edge 101 is preferably 0.3mm-0.6mm, for example 0.5mm, etc. In this way, the process difficulty can be reduced while effectively avoiding the excessive distance that leads to an excessively large area of ​​the edge area and excessive efficiency loss. That is, the printing difficulty can be reduced while avoiding excessive efficiency loss.

[0084] Example 6

[0085] In some embodiments, the width of the second edge bus bar line 50 may be 20 um-200 um.

[0086] In this way, setting the width of the second edge bus line 50 within this reasonable range can avoid the second edge bus line 50 being too small, resulting in too small a current capacity and causing a fuse during the bus, and can also avoid the second edge bus line 50 being too large, resulting in a significant increase in cost.

[0087] Specifically, in such an embodiment, the width of the second edge bus line 50 may be, for example, 20um, 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um, 110um, 120um, 130um, 140um, 150um, 160um, 170um, 180um, 190um, 200um or any value between 20um-200um, and is not limited here.

[0088] In some embodiments, the width of the second edge bus line 50 may be greater than the width of the first edge bus line 40 .

[0089] In this way, since the second edge bus line 50 is used to collect the current of each second doping layer 13 in the edge area, it plays the role of collection and convergence. Therefore, the width of the second edge bus line 50 can be set to be larger than the width of the first edge bus line 40, in order to improve the current flow capacity of the second edge bus line 50 to ensure the stability of the battery cell.

[0090] Example 7

[0091] Please refer to Figure 3. In some embodiments, a passivation film layer 107 is further provided on the first doping layer 12 and the second doping layer 13. The second edge bus line 50 is arranged on the passivation film layer 107. In the area corresponding to the second edge bus line 50 (that is, the projection area of ​​the second edge bus line 50 on the passivation film layer 107), a first opening 1071 is opened at a position corresponding to the second doping layer 13 on the passivation film layer 107. The second edge bus line 50 is in contact with the second doping layer 13 through the first opening 1071.

[0092] In this way, by opening the first opening 1071 at a position corresponding to the second doping layer 13 on the passivation film layer 107, the second edge bus line 50 can achieve stable contact with the second doping layer 13 below the edge area during printing to collect current, while also avoiding leakage caused by the second edge bus line 50 contacting the first doping layer 12.

[0093] Specifically, in such an embodiment, a first opening 1071 can be formed in the passivation film layer 107 by laser drilling. To maximize current collection, the first opening 1071 can be preferably formed on all second doped layers 13. The second edge busbar line 50 contacts all second doped layers 13 through the first opening 1071 to maximize current collection. It is understood that in such an embodiment, the first opening 1071 can be formed on all second doped layers 13 or on some second doped layers 13, and the specific details are not limited here.

[0094] Example 8

[0095] Referring to FIG. 1 , FIG. 4 and FIG. 5 , in some embodiments, the back-contact cell 100 may further include a third edge bus bar line 80 and a fourth edge bus bar line 90 .

[0096] The third edge bus line 80 is close to the second edge 102 and extends along the first direction. The third edge bus line 80 is electrically connected to the second auxiliary gate 30. The second auxiliary gate 30 does not extend to the second edge 102 of the silicon substrate 10. The third edge bus line 80 has opposite polarity to the first edge bus line 40.

[0097] The fourth edge bus line 90 is also extended along the first direction. The fourth edge bus line 90 is arranged between the third edge bus line 80 and the second edge 102 and is located above the first doped layer 12. The fourth edge bus line 90 has an opposite polarity to the second edge bus line 50 and contacts at least one first doped layer 12 and is electrically connected to an end of a portion of the first sub-gate 20 close to the second edge 102.

[0098] In this way, a fourth edge bus line 90 is arranged between the second edge 102 and the third edge bus line 80. The fourth edge bus line 90 is in contact with at least one first doped layer 12 and is connected to a portion of the first auxiliary grid 20 line. The fourth edge bus line 90 can collect the current of the first doped layer 12 in the edge area at the second edge 102 and converge it to the adjacent same-polarity main grid and / or welding strip through a portion of the first auxiliary grid 20 to realize current collection, which can further reduce the efficiency loss in the edge area of ​​the second edge 102 and further improve the efficiency of the battery cell.

[0099] Furthermore, as shown in FIG4 , since only a portion of the first sub-grid 20 is connected to the fourth edge busbar line 90 , during the subsequent welding of opposite-polarity welding ribbons (e.g., the edge welding ribbon 203 in FIG9 ), the ribbon will only intersect with a portion of the first sub-grid 20 . With fewer intersections, only a small number of insulating adhesives need to be applied at these locations to prevent leakage, effectively reducing costs. Furthermore, since the insulating adhesive is applied at isolated locations, it is not prone to leaking adhesives and causing bending and warping of the cell. Furthermore, the provision of the third edge busbar line 80 can also achieve the anti-breakage function of the second sub-grid 30 , minimizing the risk of breakage of the second sub-grid 30 .

[0100] Specifically, in such an embodiment, the third edge bus line 80 at the second edge 102 has opposite polarity to the first edge bus line 40 at the first edge 101, with one being a positive bus line and the other being a negative bus line. The fourth edge bus line 90 at the second edge 102 has opposite polarity to the second edge bus line 50 at the first edge 101, with one being a positive bus line and the other being a negative bus line.

[0101] The second edge bus line 50 is used to collect current from the second doping layer 13 in the edge region of the first edge 101 , and the fourth edge bus line 90 is used to collect current from the first doping layer 12 in the edge region of the second edge 102 .

[0102] It is understandable that in such an embodiment, the third edge bus line 80 has substantially the same structure and material as the first edge bus line 40 , and the fourth edge bus line 90 has substantially the same structure and material as the second edge bus line 50 , which will not be described in detail here.

[0103] As shown in Figure 1, it is not difficult to understand that the fourth edge bus line 90 is in contact with the first doped layer 12 to realize the collection of current of the first doped layer 12 in the edge area. Therefore, as shown in Figure 4, in this embodiment, the number of the first discontinuity region 21 and the second discontinuity region 31 is an even number. Among the first discontinuity region 21 of the first auxiliary grid 20 and the second discontinuity region 31 of the second auxiliary grid 30, the second discontinuity region 31 is closest to the second edge 102, that is, in the second direction, the first discontinuity region 21 and the second discontinuity region 31 are arranged alternately in sequence, and the discontinuity region closest to the second edge 102 is the second discontinuity region 31. At the position corresponding to the second discontinuity region 31, the first auxiliary grid 20 is not disconnected, and a main grid and / or welding strip in contact with the first auxiliary grid 20 can be set at the position corresponding to the second discontinuity region 31 to converge the current collected by the fourth edge bus line 90.

[0104] Example 9

[0105] Referring to FIG. 1 and FIG. 4 , in some embodiments, a portion of the first auxiliary gate 20 is insulated and penetrates the third edge bus bar line 80 and is connected to the fourth edge bus bar line 90 .

[0106] Thus, after collecting the current in the edge region, the fourth edge bus bar line 90 can collect the current to the nearest bus bar and / or welding strip of the same polarity through the first auxiliary grid 20 passing through the third edge bus bar line 80 to realize current collection.

[0107] Specifically, as shown in FIG4 , in such an embodiment, the plurality of first sub-grids 20 may include a plurality of second collecting sub-grids 22 and a plurality of second penetrating sub-grids 23 . The plurality of second collecting sub-grids 22 are all located on the side of the third edge bus bar line 80 facing the first edge 101 , and the second penetrating sub-grids 23 are insulated and penetrate the third edge bus bar line 80 to connect with the fourth edge bus bar line 90 .

[0108] That is, in such an embodiment, there is no second collecting sub-grid 22 between the third edge bus bar line 80 and the second edge 102. Between the third edge bus bar line 80 and the second edge 102, only the position where the second edge bus bar line 50 is penetrated has the second penetrating sub-grid 23, and no other positions have sub-grids (including the first sub-grid 20 and the second sub-grid 30).

[0109] It should be noted that, in the embodiment of the present application, “part of the first sub-grid 20 is insulated and penetrates the third edge bus line 80” can be understood as that in the first direction, the third edge bus line 80 has a plurality of spaced-apart partition areas, and the second penetrating sub-grid 23 passes through the third edge bus line 80 through the partition area and does not contact the third edge bus line 80, so as to achieve physical penetration and insulation isolation.

[0110] It is understood that in such an embodiment, the number of second through-grids 23 can be single or multiple, and the specific number can be determined according to the size of the solar cell. When there are multiple second through-grids 23, the multiple second through-grids 23 can be spaced apart along the first direction, and the distance between two adjacent second through-grids 23 can be determined according to the size of the solar cell. Preferably, the second through-grids 23 can be evenly spaced along the first direction on the silicon substrate 10 according to the size of the silicon substrate 10, and the specific number is not limited here.

[0111] It is not difficult to understand that in such an embodiment, the fourth edge bus line 90 can collect the current of the first doped layer 12 in the edge area of ​​the second edge 102, and then collect it to the nearest main grid and / or welding strip of the same polarity (such as the welding strip 202 below) through the second through-grid 23 running through the third edge bus line 80 to achieve convergence. By setting multiple second through-grids 23, the convergence path can be effectively shortened and the loss can be reduced.

[0112] Example 10

[0113] 1 and 4 , in some embodiments, in the first direction, the silicon substrate 10 further has a third edge 103 and a fourth edge 104 opposite to each other, and the third edge 103 is connected to the second edge 102 via a second chamfer 106 ;

[0114] In the direction from the third edge 103 to the fourth edge 104, the second sub-grids 30 and the first sub-grids 20 are arranged alternately in sequence, and a third auxiliary grid line 110 is provided at the second chamfer 106. The third auxiliary grid line 110 connects the second sub-grids 30 located at the second chamfer 106 and the third edge bus bar line 80. It should be noted that the "second sub-grids 30 located at the second chamfer 106" refers to a plurality of second sub-grids 30 that are not directly connected to the third edge bus bar line 80 and whose extension lines along the second direction intersect the second chamfer 106, such as the two uppermost second sub-grids 30 in FIG.

[0115] In this way, by setting the third auxiliary gate line 110, the second auxiliary gates 30 at the second chamfer 106 can be connected to achieve conduction between the second auxiliary gates 30 at the second chamfer 106. When the welding strip (such as the edge welding strip 203 below) is subsequently welded, it is only necessary to contact the welding strip with the third auxiliary gate line 110 to achieve the collection of the current of the second auxiliary gate 30 at the second chamfer 106. This can avoid the situation where the welding strip cannot contact all the second auxiliary gates 30 at the second chamfer 106 due to the existence of the second chamfer 106, resulting in the current of the second auxiliary gate 30 at the second chamfer 106 cannot be collected.

[0116] Specifically, as shown in FIG. 4 , in such an embodiment, the third auxiliary gate line 110 may be arranged parallel to the second chamfer 106 , which may make the gate line structure of the back surface 11 simpler to manufacture.

[0117] As shown in FIG4 , it is not difficult to understand that, since the second auxiliary grid 30 has a second discontinuous area 31 at a position closest to the second edge 102, in order to achieve the convergence of the second auxiliary grid 30 near the second edge 102, it is necessary to set a welding strip at the position of the second edge 102 to achieve conductive connection with the second auxiliary grid 30 to achieve convergence. However, due to the existence of the second chamfer 106, the length of the second auxiliary grid 30 at the top is relatively short, and the welding strip cannot be in contact with the second auxiliary grid 30 at the top when it is vertically arranged. If the welding strip is too close to the inside, it will It is easy to contact the first sub-grid 20 of the opposite polarity and cause leakage. Therefore, by providing the third auxiliary grid line 110, the second sub-grid 30 at the second chamfer 106 can be connected into a whole. When welding the welding ribbon, it is only necessary to contact the welding ribbon with the third edge bus grid line 80, or with the third edge bus grid line 80 and the third auxiliary grid line 110 at the same time, or with the remaining second sub-grids 30 connected to the third edge bus grid line 80 and the third auxiliary grid line 110 to achieve the current convergence of all the second sub-grids 30.

[0118] Example 11

[0119] Referring to FIG. 6 , in some embodiments, the third edge busbar line 80 may include a first bus segment 81 and a second bus segment 82. The first bus segment 81 connects to the second sub-grid 30 located at the second chamfer 106. Similarly, in such embodiments, "second sub-grid 30 located at the second chamfer 106" refers to a plurality of second sub-grids 30 that are not directly connected to the third edge busbar line 80 and whose extension lines along the second direction intersect the second chamfer 106, such as the top two second sub-grids 30 in FIG. 6 . The second bus segment 81 connects to the second sub-grids 30 other than those located at the second chamfer 106. It will be understood that, as shown in FIG. 6 , in such embodiments, due to the presence of the second through-sub-grid 23, the second bus segment 82 is a discontinuous structure.

[0120] In this way, the second sub-grids 30 at the second chamfer 106 can be connected into a whole through the first bus section 81. When setting the welding strip, in order to achieve the convergence of the second sub-grids 30 at the second chamfer 106, it is only necessary to contact the welding strip with any second sub-grid 30 at the second chamfer 106 to achieve the convergence of all the second sub-grids 30 at the second chamfer 106.

[0121] Furthermore, as shown in FIG. 6 , in such an embodiment, the first bus segment 81 and the second bus segment 82 are spaced apart along the second direction, and the second bus segment 82 is closer to the second edge 102 than the first bus segment 81 .

[0122] Specifically, in such an embodiment, the top of the first bus section 81 can be connected to the end of the topmost second sub-grid 30 and extend along the first direction, so that all the second sub-grids 30 at the second chamfer 106 can be connected into a whole.

[0123] It is not difficult to understand that the difference between this embodiment and the above-mentioned embodiment 10 is that in the embodiment 10, the second auxiliary gate 30 at the second chamfer 106 is connected into a whole by setting a third auxiliary gate line 110 parallel to the second chamfer 106, while in this embodiment, the second auxiliary gate 30 at the second chamfer 106 is connected into a whole by the first bus section 81. Both can also be used at the same time, and there is no specific limitation here.

[0124] Example 12

[0125] Please refer to Figure 5. A passivation film layer 107 is provided on the first doping layer 12 and the second doping layer 13. The fourth edge bus line 90 is arranged on the passivation film layer 107. In the area corresponding to the fourth edge bus line 90 (that is, the projection area of ​​the fourth edge bus line 90 on the passivation film layer 107), a second opening 1072 is opened at the position corresponding to the first doping layer 12 on the passivation film layer 107. The fourth edge bus line 90 contacts the first doping layer 12 through the second opening 1072.

[0126] In this way, by opening a second opening 1072 at a position corresponding to the first doping layer 12 on the passivation film layer 107, the fourth edge bus line 90 can achieve stable contact with the first doping layer 12 below the edge area during printing to collect current, while also avoiding leakage caused by the fourth edge bus line 90 contacting the second doping layer 13.

[0127] Specifically, in such an embodiment, second openings 1072 can be formed in the passivation film layer 107 by laser drilling. To maximize current collection, second openings 1072 can preferably be formed in all first doped layers 12. The fourth edge busbar line 90 contacts all first doped layers 12 through the second openings 1072 to maximize current collection. Of course, in some embodiments, second openings 1072 can also be formed in part of the first doped layers 12, and this is not limited to this.

[0128] Example 13

[0129] 7 , in some embodiments, the third edge bus line 80 may also be electrically connected to the first auxiliary gate 20 , and the first auxiliary gate 20 does not extend to the second edge 102 of the silicon substrate 10 . The third edge bus line 80 has the same polarity as the first edge bus line 40 .

[0130] Meanwhile, in such an embodiment, the fourth edge bus line 90 has the same polarity as the second edge bus line 50 and contacts at least one second doping layer 13 and is electrically connected to a portion of the second auxiliary gate 30 near the second edge 102 .

[0131] In such an embodiment, the difference from the example in FIG. 1 is that in the example shown in FIG. 7 , the third edge bus line 80 has the same polarity as the first edge bus line 40 , and the fourth edge bus line 90 has the same polarity as the second edge bus line 50 , whereas in the example shown in FIG. 1 , the third edge bus line 80 has an opposite polarity to the first edge bus line 40 , and the fourth edge bus line 90 has an opposite polarity to the second edge bus line 50 .

[0132] Specifically, in such an embodiment, the third edge bus line 80 and the fourth edge bus line 90 at the second edge 102 are symmetrically arranged with the first edge bus line 40 and the second edge bus line 50 at the first edge 101, and all of their structures are the same as the structure at the first edge 101, and the number of the first discontinuity area 21 and the second discontinuity area 31 is an odd number.

[0133] It is understandable that in such an embodiment, the third edge bus line 80 has substantially the same structure and material as the first edge bus line 40 , and the fourth edge bus line 90 has substantially the same structure and material as the second edge bus line 50 , which will not be described in detail here.

[0134] Similarly, as shown in Figure 7, it is not difficult to understand that the fourth edge bus line 90 is in contact with the second doped layer 13 to realize the collection of current of the second doped layer 13 in the edge area of ​​the second edge 102. Therefore, as shown in Figure 7, in this embodiment, in the first discontinuity region 21 of the first auxiliary gate 20 and the second discontinuity region 31 of the second auxiliary gate 30, the one closest to the second edge 102 is also the first discontinuity region 21, that is, in the second direction, the first discontinuity region 21 and the second discontinuity region 31 are arranged alternately in sequence, and the discontinuity region closest to the second edge 102 is also the first discontinuity region 21. At the position corresponding to the first discontinuity region 21, the second auxiliary gate 30 is not disconnected, and a main gate and / or welding point in contact with the second auxiliary gate 30 can be set at the position corresponding to the first discontinuity region 21 to realize the current collection of the third edge bus line 80.

[0135] Example 14

[0136] 7 , in some embodiments, a portion of the second auxiliary gate 30 is insulated and penetrates the third edge bus bar line 80 to be electrically connected to the fourth edge bus bar line 90 .

[0137] Thus, after collecting the current in the edge area of ​​the second edge 102 , the fourth edge bus bar line 90 can collect the current to the nearest bus bar and / or welding strip of the same polarity through the second auxiliary grid 30 passing through the third edge bus bar line 80 to realize current collection.

[0138] Specifically, as shown in FIG7 , as described above, in such an embodiment, the plurality of second sub-grids 30 may include a plurality of first collecting sub-grids 32 and a plurality of first through-grids 33 . With respect to the second edge 102 , the plurality of first collecting sub-grids 32 are all located on the side of the third edge bus bar line 80 facing the first edge 101 , and the first through-grids 33 are insulated and penetrate the third edge bus bar line 80 to connect with the fourth edge bus bar line 90 .

[0139] That is, in such an embodiment, there is no first collecting sub-grid 32 between the third edge bus bar line 80 and the second edge 102, and between the fourth edge bus bar line 90 and the second edge 102, only the position where the third edge bus bar line 80 is penetrated has the first penetrating sub-grid 33.

[0140] It should be noted that, in the embodiment of the present application, “part of the second sub-grid 30 is insulated and penetrates the third edge bus line 80” can be understood as that in the first direction, there are several spaced-apart partition areas on the third edge bus line 80, and the first penetrating sub-grid 33 passes through the third edge bus line 80 through the partition area and does not contact the third edge bus line 80, so as to achieve physical penetration and insulation isolation.

[0141] Similarly, in such an embodiment, the number of first through-grids 33 can be single or multiple, depending on the size of the cell. When there are multiple first through-grids 33, the multiple first through-grids 33 can be spaced apart along the first direction, and the distance between two adjacent first through-grids 33 can be determined based on the size of the cell. Preferably, the first through-grids 33 can be evenly spaced along the first direction on the silicon substrate 10 based on the size of the silicon substrate 10, but this is not a limitation here.

[0142] It should be noted that, in such an embodiment, the first through-sub-grid 33 passing through the third edge bus grid line 80 may be the same grid line as the first through-sub-grid passing through the first edge bus grid line 40 or may not be the same grid line. There is no specific restriction here. Preferably, they are the same grid line. When the two are the same grid line, the grid line structure at the first edge 101 is completely symmetrical with the grid line structure at the second edge 102.

[0143] Please refer to Figure 8. In such an embodiment, on the area corresponding to the fourth edge bus line 90 (i.e., the projection area of ​​the fourth edge bus line 90 on the passivation film layer 107), a third opening 1073 is opened at a position corresponding to the second doped layer 13 on the passivation film layer 107, and the fourth edge bus line 90 is in contact with the second doped layer 13 through the third opening 1073.

[0144] In this way, by opening the third opening 1073 at a position corresponding to the second doping layer 13 on the passivation film layer 107, the fourth edge bus line 90 can achieve stable contact with the second doping layer 13 below the edge area during printing to collect current, while also avoiding leakage caused by the fourth edge bus line 90 contacting the first doping layer 12.

[0145] Specifically, in such an embodiment, the structure of the fourth edge bus line 90 and the third opening 1073 can be the same as the structure of the second edge bus line 50 and the first opening 1071 described above, and the structures of the two can be symmetrical to each other. In this embodiment, the third opening 1073 can be formed on the passivation film layer 107 by laser drilling. In order to maximize the collection of current, the third opening 1073 can preferably be opened on all second doped layers 13, and the fourth edge bus line 90 can contact all second doped layers 13 through the third opening 1073 to maximize the collection of current. Of course, in some embodiments, the third opening 1073 can also be opened on part of the second doped layer 13, and the specific details are not limited here.

[0146] Example 15

[0147] 7 , in some embodiments, in the first direction, the silicon substrate 10 further has a third edge 103 and a fourth edge 104 opposite to each other, and the third edge 103 is connected to the second edge 102 via a second chamfer 106 ;

[0148] In the direction from the third edge 103 to the fourth edge 104 , the second sub-grids 30 and the first sub-grids 20 are alternately arranged in sequence, and a fourth auxiliary grid line 120 is provided at the second chamfer 106 . The fourth auxiliary grid line 120 connects the fourth edge bus bar line 90 and the second sub-grid 30 closest to the third edge 103 .

[0149] Thus, by disposing the fourth auxiliary grid line 120 at the second chamfer 106 , the current collected by the fourth edge bus grid line 90 can be converged to the second auxiliary grid 30 at the third edge 103 and then to the nearest main grid and / or welding strip.

[0150] 7 , the third edge 103 is the upper edge of the silicon substrate 10 , the fourth edge 104 is the lower edge of the silicon substrate 10 , the first edge 101 and the third edge 103 form a first chamfer 105 , and the second edge 102 and the third edge 103 form a second chamfer 106 .

[0151] As shown in FIG. 7 , in such an embodiment, the first chamfer 105 is symmetrical to the second chamfer 106 , and the fourth auxiliary gate line 120 is symmetrical to the first auxiliary gate line 60 .

[0152] It is understandable that in such an embodiment, the first through-grid 33 and the third auxiliary grid line 110 may be provided to achieve current confluence, or the first through-grid 33 may not be provided, and current confluence may be achieved through the fourth auxiliary grid line 120 at the second chamfer 106. Of course, to avoid excessive loss due to an excessively long transmission path for the confluence, current confluence may be preferably achieved through the first through-grid 33 or through the first through-grid 33 and the fourth auxiliary grid line 120, and this is not limited here.

[0153] In some embodiments, the fourth auxiliary gate line 120 is arranged parallel to the second chamfer 106. This can make the gate line structure of the back surface 11 simpler to manufacture.

[0154] Furthermore, in some embodiments, the fourth auxiliary gate line 120 may be located above the second doping layer 13 and contact at least one second doping layer 13 .

[0155] In this way, the fourth auxiliary gate line 120 can realize current convergence while also collecting current at the edge region at the second chamfer 106 , thereby further reducing efficiency loss and improving cell efficiency.

[0156] Continuing with FIG7 , in some embodiments, a fifth auxiliary gate line 130 may be further provided at the first chamfer 105. The fifth auxiliary gate line 130 connects the first auxiliary gate 20 and the third edge bus line 80 at the second chamfer 106. Similarly, it should be noted that the “second auxiliary gate 30 at the second chamfer 106” refers to a plurality of second auxiliary gates 30 that are not directly connected to the third edge bus line 80 and whose extension lines along the second direction intersect the second chamfer 106, such as the two uppermost second auxiliary gates 30 in FIG7 .

[0157] In this way, by setting the fifth auxiliary gate line 130, the first auxiliary gates 20 at the second chamfer 106 can be connected to achieve conduction between the first auxiliary gates 20 at the second chamfer 106. When the welding strip is subsequently welded, it is only necessary to contact the welding strip with the fifth auxiliary gate line 130 to achieve the collection of the current of the first auxiliary gate 20 at the second chamfer 106. This can avoid the situation where the welding strip 202 cannot contact all the first auxiliary gates 20 at the second chamfer 106 due to the existence of the second chamfer 106, resulting in the current of the first auxiliary gate 20 at the second chamfer 106 cannot be collected.

[0158] Specifically, as shown in Figure 7, in such an embodiment, the fifth auxiliary gate line 130 can also be arranged parallel to the second chamfer 106, that is, at the second chamfer 106, from the outside to the inside, the second chamfer 106, the fourth auxiliary gate line 120 and the fifth auxiliary gate line 130 are arranged in parallel in sequence, and the fifth auxiliary gate line 130 is arranged symmetrically with the second auxiliary gate line 70.

[0159] Example 16

[0160] In some embodiments, the distance between the third edge bus bar line 80 and the second edge 102 (ie, the distance between the third edge bus bar line 80 and the second edge 102 in the second direction) is 0.5 mm to 2 mm.

[0161] In this way, setting the spacing between the third edge bus grid line 80 and the second edge 102 within this reasonable range can effectively avoid the distance between the two being too large, resulting in too large an area of ​​the edge region without a secondary grid and causing excessive efficiency loss. It can also avoid the distance between the two being too small, resulting in cold solder joints and cracks when subsequently welding the solder strip at the third edge bus grid line 80, thereby ensuring the reliability and stability of welding.

[0162] Specifically, in such an embodiment, the distance between the third edge bus line 80 and the second edge 102 can be, for example, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.2mm, 1.4mm, 1.6mm, 1.8mm, 2mm or any value between 0.5mm-2mm, and is not limited here.

[0163] Furthermore, in an embodiment of the present application, the distance between the third edge busbar line 80 and the second edge 102 is preferably 0.8 mm-1.2 mm, for example 0.9 mm, etc. In this way, while reducing the process difficulty, it is possible to effectively avoid the excessive distance resulting in an excessively large area of ​​the edge region where no auxiliary grid is set, resulting in excessive efficiency loss, while also ensuring the stability and reliability of welding.

[0164] Example 17

[0165] In some embodiments, the distance between the fourth edge busbar line 90 and the second edge 102 (ie, the distance between the second edge and the fourth edge) is 0.3 mm to 1.2 mm.

[0166] In this way, on the one hand, it is possible to avoid the distance between the fourth edge bus line 90 and the second edge 102 being too small, which would greatly increase the difficulty of printing the fourth edge bus line 90; on the other hand, it is possible to avoid the distance between the fourth edge bus line 90 and the second edge 102 being too large, which would cause the area of ​​the edge without the auxiliary grid to be too large, resulting in excessive efficiency loss.

[0167] Specifically, in such an embodiment, the distance between the fourth edge bus line 90 and the second edge 102 can be, for example, 0.3mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.2mm or any value between 0.3mm-1.2mm, and is not limited here.

[0168] Furthermore, in an embodiment of the present application, the distance between the fourth edge busbar line 90 and the second edge 102 is preferably 0.3mm-0.6mm, for example 0.5mm, etc. In this way, the process difficulty can be reduced while effectively avoiding the excessive distance resulting in excessive efficiency loss caused by the area of ​​the edge region where the auxiliary grid is not set being too large. That is, the printing difficulty can be reduced while avoiding excessive efficiency loss.

[0169] Example 18

[0170] In some embodiments, the width of the fourth edge bus bar line 90 is 20 μm-200 μm.

[0171] In this way, setting the width of the fourth edge bus line 90 within this reasonable range can avoid the fourth edge bus line 90 being too small, resulting in too small a current capacity and causing a fuse to occur during the bus, and can also avoid the fourth edge bus line 90 being too large, resulting in a significant increase in cost.

[0172] Specifically, in such an embodiment, the width of the fourth edge bus line 90 may be, for example, 20um, 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um, 110um, 120um, 130um, 140um, 150um, 160um, 170um, 180um, 190um, 200um or any value between 20um-200um, and is not limited here.

[0173] In some embodiments, the width of the fourth edge bus line 90 is greater than the width of the third edge bus line 80 .

[0174] In this way, since the fourth edge bus line 90 is used to collect the current of each second doping layer 13 in the edge area, it plays the role of collection and convergence. Therefore, the width of the fourth edge bus line 90 can be set to be larger than the width of the third edge bus line 80, in order to improve the current flow capacity of the fourth edge bus line 90 to ensure the stability of the battery cell.

[0175] Example 19

[0176] In some embodiments, in the second direction, the back-contact solar cell 100 may further include a first busbar (not shown) and a second busbar (not shown) alternately arranged in sequence. The first busbar is arranged at the second discontinuity region 31 and contacts the first auxiliary grid 20. The second busbar is arranged at the first discontinuity region 21 and contacts the second auxiliary grid 30. In this way, the arrangement of the first and second busbars can achieve current convergence and output.

[0177] Specifically, in such an embodiment, the first main gate is arranged at the second discontinuity region 31 of the second sub-gate 30 to achieve contact with the first sub-gate 20 to achieve current output, and the second main gate is arranged at the first discontinuity region 21 of the first sub-gate 20 in contact with the second sub-gate 30 to achieve current output.

[0178] In addition, it can be understood that, as shown in Figure 8, in some embodiments, the back contact cell 100 may not be provided with a main grid, but instead a welding strip 202 is provided at the positions corresponding to the first discontinuity area 21 and the second discontinuity area 31 to achieve busbar output while forming the cell string 201, that is, the main grid is replaced by the welding strip 202.

[0179] Example 20

[0180] Please refer to Figures 9 and 10. The present application also provides a photovoltaic system 1000. The photovoltaic system 1000 may include the battery assembly 200 in the embodiment of the present application. The battery assembly 200 in the embodiment of the present application may include several battery strings 201 in the embodiment of the present application. As shown in Figure 9, the battery string 201 may include several back-contact battery cells 100 and several welding strips 202 in the embodiment of the present application.

[0181] It is understandable that the back contact cell 100 in the embodiment of the present application can be a whole cell or a half cell, and there is no specific limitation here.

[0182] As shown in FIG9 , in two adjacent back-contact battery cells 100 , the first discontinuous area 21 of one back-contact battery cell 100 corresponds to the second discontinuous area 31 of the other back-contact battery cell 100 in the first direction, and welding strips 202 are provided at the first discontinuous area 21 and the second discontinuous area 31 . Each first discontinuous area 21 and each second discontinuous area 31 is correspondingly provided with a welding strip 202 .

[0183] Among them, in two adjacent back-contact solar cells 100, the first secondary grid 20 of one back-contact solar cell 100 is connected to the welding ribbon 202 at the first discontinuity area 21, and the second secondary grid 30 of the other back-contact solar cell 100 is connected to the welding ribbon 202 at the second discontinuity area 31.

[0184] In the battery string 201 of the embodiment of the present application, there are the following connection methods:

[0185] 1. As shown in FIG9 , in two adjacent back-contact solar cells 100 , the first edge 101 has a first edge bus bar line 40 and a second edge bus bar line 50 , and the second edge 102 has a third edge bus bar line 80 and a fourth edge bus bar line 90 . The polarity of the first edge bus bar line 40 is opposite to that of the third edge bus bar line 80 , and the polarity of the second edge bus bar line 50 is opposite to that of the fourth edge bus bar line 90 .

[0186] In the battery string 201, the first edge 101 of one of the two adjacent back-contact battery cells 100 is aligned with the second edge 102 of the other, so that the first edge busbar line 40 and the third edge busbar line 80 of the two battery cells are located on the same side, and the second edge busbar line 50 and the fourth edge busbar line 90 are located on the same side. In the two back-contact battery cells 100, the middle area is connected by the welding ribbon 202, and the edge area is connected by the edge welding ribbon 202 located at the first edge 101 and the second edge 102. 03 are welded together to achieve series connection, and it is only necessary to apply insulating glue on the edge welding strip 203 and the grid lines of different polarities (such as the first through-sub-grid 33 and the second through-sub-grid 23 in Figure 9). As shown in Figure 8, the edge welding strips 203 are conductively connected to the first edge bus grid line 40 and the third edge bus grid line 80 located on the same side. The edge welding strips 203 can be set along the first direction, and they can be welded to the first edge bus grid line 40 and the third edge bus grid line 80 or to the first sub-grid 20 and the second sub-grid 30.

[0187] 2. In two adjacent back-contact cells 100 , only the first edge 101 has the first edge busbar line 40 and the second edge busbar line 50 ;

[0188] In this case, in two adjacent back-contact cell pieces 100, the first edge bus lines 40 located on the same side have opposite polarities, the first sub-grids of the first edge bus lines 40 also have opposite polarities, and the second edge bus lines 50 also have opposite polarities. That is, in two adjacent back-contact cell pieces 100, the first edge bus lines 40 of one are P-type grid lines, and the first edge bus lines 40 of the other are N-type grid lines. The two back-contact cell pieces 100 are welded together via a welding strip located at the first edge 101 to achieve series connection.

[0189] As shown in FIG9 , in some embodiments, in a battery string 201, the edge welding strip 203 can be directly welded to the first edge bus bar line 40 and the third edge bus bar line 80, and the two can be in contact or overlapping. Of course, in some embodiments, the edge welding strip 203 can also be located on the inner side of the first edge bus bar line 40 and the third edge bus bar line 80 (that is, on the side of the first edge bus bar line 40 facing away from the first edge 101). In two adjacent back-contact battery cells 100, the edge welding strip 203 is welded to the first auxiliary grid 20 in one of the back-contact battery cells 100, and is welded to the second auxiliary grid 30 in the other back-contact battery cell 100.

[0190] Of course, it can be understood that in some embodiments, main grids may be provided at both the first discontinuity region 21 and the second discontinuity region 31, and the welding strip 202 may be welded to the first main grid and the second main grid mentioned above. That is to say, in this application, the back contact cell 100 may be a cell with a main grid or a cell without a main grid, and there is no specific limitation here.

[0191] Throughout this specification, reference to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0192] In addition, the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A back contact battery cell, characterized in that: include: A silicon substrate, wherein a plurality of first doping layers and a plurality of second doping layers are disposed on the back side of the silicon substrate, wherein the plurality of first doping layers and the plurality of second doping layers are alternately arranged in sequence along a first direction and extend along a second direction, wherein the first direction intersects the second direction, and in the second direction, the silicon substrate has a first edge and a second edge opposite to each other; A plurality of first sub-gates and a plurality of second sub-gates are alternately arranged along the first direction, the first sub-gate is arranged above the first doped layer, and the second sub-gate is arranged above the second doped layer; the first sub-gate has a plurality of first discontinuous regions at intervals in the second direction, and the second sub-gate has a plurality of second discontinuous regions at intervals in the second direction, the first discontinuous regions on adjacent first sub-gates correspond to each other in the first direction, and the second discontinuous regions on adjacent second sub-gates correspond to each other in the first direction, and in the second direction, the first discontinuous regions and the second discontinuous regions are alternately arranged in sequence, and the first sub-gate does not extend to the first edge of the silicon substrate; a first edge busbar line disposed close to the first edge and extending along the first direction, the first edge busbar line being electrically connected to the first auxiliary grid; and A second edge busbar line is extended along the first direction, the second edge busbar line is arranged between the first edge busbar line and the first edge and is located above the second doped layer, the second edge busbar line contacts at least one of the second doped layers and is electrically connected to an end of a portion of the second sub-grid close to the first edge.

2. The back contact cell according to claim 1, characterized in that: A portion of the second sub-gate insulation passes through the first edge bus gate line and is electrically connected to the second edge bus gate line.

3. The back contact cell according to claim 1, characterized in that: In the first direction, the silicon substrate further has a third edge and a fourth edge opposite to each other, and the third edge is connected to the first edge via a first chamfer; In the direction from the third edge to the fourth edge, the second sub-grids and the first sub-grids are arranged alternately in sequence, and a first auxiliary grid line is provided at the first chamfer, which connects the second edge bus grid line and the second sub-grid closest to the third edge.

4. The back contact cell according to claim 3, characterized in that: The first auxiliary gate line is located above the second doping layer and contacts at least one of the second doping layers.

5. The back contact cell according to claim 3, characterized in that: The first auxiliary gate line is parallel to the first chamfer.

6. The back contact cell according to claim 1, characterized in that: In the first direction, the silicon substrate further has a third edge and a fourth edge opposite to each other, and the third edge is connected to the first edge via a first chamfer; A second auxiliary gate line is disposed at the first chamfer, and the second auxiliary gate line connects the first sub-gate and the first edge bus gate line located at the first chamfer.

7. The back contact cell according to any one of claims 1 to 6, characterized in that: The distance between the first edge busbar line and the first edge is 0.5 mm-2 mm; and / or The distance between the second edge busbar line and the first edge is 0.3 mm-1.2 mm.

8. The back contact cell according to any one of claims 1 to 6, characterized in that: The width of the second edge busbar line is 20um-200um; and / or The second edge bus line has a width greater than that of the first edge bus line.

9. The back contact cell according to claim 1, characterized in that: A passivation film layer is also provided on the first doping layer and the second doping layer, and the second edge bus gate line is arranged on the passivation film layer. In the area corresponding to the second edge bus gate line, a first opening is opened at a position corresponding to the second doping layer on the passivation film layer, and the second edge bus gate line contacts the second doping layer through the first opening.

10. The back contact cell according to claim 1, characterized in that: The back contact cell also includes: a third edge bus gate line disposed close to the second edge and extending along the first direction, the third edge bus gate line being electrically connected to the second auxiliary gate, the second auxiliary gate not extending to the second edge of the silicon substrate, the third edge bus gate line having opposite polarity to the first edge bus gate line; and A fourth edge busbar line extending along the first direction, wherein the fourth edge busbar line is arranged between the third edge busbar line and the second edge and is located above the first doped layer, and the fourth edge busbar line contacts at least one of the first doped layers and is electrically connected to an end of a portion of the first sub-grid close to the second edge.

11. The back contact cell according to claim 10, characterized in that: A portion of the first sub-gate insulation penetrates through the third edge bus gate line and is connected to the fourth edge bus gate line.

12. The back contact cell according to claim 10, characterized in that: In the first direction, the silicon substrate further has a third edge and a fourth edge opposite to each other, and the third edge is connected to the second edge via a second chamfer; In the direction from the third edge to the fourth edge, the second sub-grids and the first sub-grids are arranged alternately in sequence, and a third auxiliary grid line is provided at the second chamfer, and the third auxiliary grid line connects the second sub-grid located at the second chamfer and the third edge bus grid line.

13. The back contact cell according to claim 12, characterized in that: The third auxiliary gate line is parallel to the second chamfer.

14. The back contact cell according to claim 10, characterized in that: In the first direction, the silicon substrate further has a third edge and a fourth edge opposite to each other, and the third edge is connected to the second edge via a second chamfer; The third edge busbar line includes a first busbar segment and a second busbar segment, wherein the first busbar segment is connected to the second sub-grid at the second chamfer, and the second busbar segment is connected to the second sub-grid except at the second chamfer.

15. The back contact cell according to claim 14, characterized in that: The first bus segment and the second bus segment are spaced apart along the second direction, and the second bus segment is closer to the second edge than the first bus segment.

16. The back contact cell according to claim 10, characterized in that: A passivation film layer is also provided on the first doping layer and the second doping layer, the fourth edge bus gate line is arranged on the passivation film layer, and a second opening is opened at a position corresponding to the first doping layer on the passivation film layer in an area corresponding to the fourth edge bus gate line, and the fourth edge bus gate line contacts the first doping layer through the second opening.

17. The back contact cell according to claim 1, characterized in that: The back contact cell also includes: a third edge bus gate line disposed close to the second edge and extending along the first direction, the third edge bus gate line being electrically connected to the first auxiliary gate, the first auxiliary gate not extending to the second edge of the silicon substrate, and the third edge bus gate line having the same polarity as the first edge bus gate line; and A fourth edge busbar line is arranged near the second edge and extending along the first direction, the fourth edge busbar line is arranged between the third edge busbar line and the second edge and the fourth edge busbar line is located above the second doped layer, the fourth edge busbar line is in contact with at least one of the second doped layers and is electrically connected to an end of a portion of the second sub-grid near the second edge.

18. The back contact cell according to claim 17, characterized in that: A portion of the second sub-gate insulation penetrates through the third edge bus gate line and is connected to the fourth edge bus gate line.

19. The back contact cell according to claim 17, characterized in that: In the first direction, the silicon substrate further has a third edge and a fourth edge opposite to each other, and the third edge is connected to the second edge via a second chamfer; In the direction from the third edge to the fourth edge, the second sub-grids and the first sub-grids are arranged alternately in sequence, and a fourth auxiliary grid line is provided at the second chamfer, and the fourth auxiliary grid line connects the fourth edge bus grid line and the second sub-grid closest to the third edge.

20. The back contact cell according to claim 19, characterized in that: The fourth auxiliary gate line is located above the second doping layer and contacts at least one of the second doping layers.

21. The back contact cell according to claim 19, characterized in that: The fourth auxiliary gate line is parallel to the second chamfer.

22. The back contact cell according to claim 17, characterized in that: In the first direction, the silicon substrate further has a third edge and a fourth edge opposite to each other, and the third edge is connected to the second edge via a second chamfer; A fifth auxiliary gate line is further disposed at the second chamfer, and the fifth auxiliary gate line connects the first auxiliary gate and the third edge bus gate line located at the second chamfer.

23. The back contact cell according to claim 17, characterized in that: A passivation film layer is also provided on the first doping layer and the second doping layer, the fourth edge bus gate line is arranged on the passivation film layer, and in the area corresponding to the fourth edge bus gate line, a third opening is opened at a position corresponding to the second doping layer on the passivation film layer, and the fourth edge bus gate line is in contact with the second doping layer through the third opening.

24. The back contact cell according to any one of claims 10 to 23, characterized in that: The distance between the third edge busbar line and the second edge is 0.5 mm to 2 mm; and / or The distance between the fourth edge busbar line and the second edge is 0.3 mm-1.2 mm.

25. The back contact cell according to any one of claims 10 to 23, characterized in that: The width of the fourth edge busbar line is 20um-200um; and / or The fourth edge bus line has a width greater than that of the third edge bus line.

26. The back contact cell according to claim 1, characterized in that: In the second direction, the back contact cell is also alternately provided with a first main grid and a second main grid in sequence, wherein the first main grid is arranged at the first discontinuous area and contacts the first auxiliary grid, and the second main grid is arranged at the second discontinuous area and contacts the second auxiliary grid.

27. A battery string, characterized in that: A back-contact battery cell comprising any one of claims 1 to 26, wherein in two adjacent back-contact battery cells, the first discontinuity region of one of the back-contact battery cells corresponds to the second discontinuity region of the other back-contact battery cell in the first direction.

28. A battery assembly, characterized in that: Comprising several battery strings as claimed in claim 27.

29. A photovoltaic system, characterized in that: A battery assembly comprising the battery assembly of claim 28.

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