Busbar-free electrode structure, IBC solar cell, and photovoltaic system

Abstract

A busbar-free electrode structure, IBC solar cell, and a photovoltaic system, used in the technical field of solar cells. Since first end welding points close to a third edge and disposed at a first break position are not connected to a first fine grid, but are electrically connected to a part of a second fine grid closest to the third edge, second fine grids close to a first edge can be connected together. On this basis, the first end welding points can be disposed, by means of the described electric connection manner, at a positions distant from the first edge of the silicon substrate, so that when a welding strip is subsequently welded to a first end welding point, because there is a relatively large distance between a disposed first end welding point and the first edge, the risk of hidden cracks during welding can be reduced, the cell yield can be improved, and overall convergence of the second fine grid can be achieved.

Description

Main grid-less electrode structure, IBC solar cell and photovoltaic system Technical Field

[0001] The present disclosure relates to the technical field of solar cells, and in particular to a main grid-less electrode structure, an IBC solar cell, a battery assembly, and a photovoltaic system. Background Art

[0002] Back-contact solar cells are cells with both P-type and N-type doped layers positioned on the backside of a silicon wafer. Prior art back-contact solar cells utilize a busbar-less design to reduce slurry usage and lower costs. In busbar-less back-contact cells, the backside fine grid is typically discontinuous, with solder ribbons placed in the discontinuities to achieve current convergence. To achieve this, soldering points are placed on the backside of the cell.

[0003] In the related art, the starting welding point of the welding strip is close to the edge of the battery cell, which can easily cause hidden cracks in the battery cell during the welding process, resulting in a decrease in yield.

[0004] Utility Model Content

[0005] The present disclosure provides a main grid-free electrode structure, an IBC solar cell, a battery module and a photovoltaic system, aiming to solve the technical problem that existing IBC solar cells are prone to hidden cracks in the cell during welding, resulting in reduced yield.

[0006] The present disclosure is implemented as follows: a busbar-less electrode structure of an embodiment of the present disclosure is used for an IBC solar cell, wherein the busbar-less electrode structure is disposed on the back side of a silicon substrate of the IBC solar cell, and the busbar-less electrode structure comprises:

[0007] a plurality of first fine gates and a plurality of second fine gates, wherein the plurality of first fine gates and the plurality of second fine gates are alternately arranged in sequence along a first direction and extend along a second direction, wherein the second direction intersects the first direction, wherein in the second direction, the silicon substrate has a first edge and a second edge facing each other, and in the first direction, the silicon substrate has a third edge and a fourth edge facing each other;

[0008] In the second direction, the first fine gate has a plurality of spaced first disconnected regions, and the second fine gate has a plurality of spaced second disconnected regions, the first disconnected regions and the second disconnected regions are alternately arranged in sequence, the first disconnected regions on two adjacent first fine gates correspond to each other in the first direction, and the second disconnected regions on two adjacent second fine gates correspond to each other in the first direction;

[0009] The first end welding points arranged near the third edge and located at the first disconnection area do not contact the first fine grid, and the first end welding points are electrically connected to the part of the second fine grid closest to the third edge.

[0010] Furthermore, the main gate electrode structure also includes: a first connecting gate line and a second connecting gate line arranged at the first disconnection area, the first connecting gate line and the second connecting gate line are spaced apart along the second direction and extend along the first direction, the first connecting gate line and the second connecting gate line are not in contact with the first fine gate, and the first connecting gate line and the second connecting gate line are both connected to the part of the second fine gate closest to the third edge.

[0011] Furthermore, in the first direction, the distance between the first end welding point and the third edge is 1 cm-3 cm.

[0012] Furthermore, the first connecting gate line and the second connecting gate line connect at least three second fine gates; and / or in the first direction, the length of the first connecting gate line and the second connecting gate line is at least 4 times the spacing between the first fine gate and the second fine gate.

[0013] Furthermore, the main gate electrode structure also includes a third connecting gate line, which is located at the first disconnection area and does not contact the first fine gate, and the third connecting gate line connects the first end welding point and the first connecting gate line and the second connecting gate line and the part of the second fine gate between the fourth edge.

[0014] Furthermore, the main gate-less electrode structure may further include a fourth connecting gate line and a fifth connecting gate line disposed at the first disconnected region, the fourth connecting gate line and the fifth connecting gate line being spaced apart along the second direction and extending along the first direction, the fourth connecting gate line and the fifth connecting gate line not being in contact with the first fine gate, and the fourth connecting gate line and the fifth connecting gate line both being connected to a portion of the second fine gate closest to the fourth edge;

[0015] A second end welding point is disposed near the fourth edge and located at the first disconnected area, and the second end welding point is disposed between the fourth connecting gate line and the fifth connecting gate line and contacts the fourth connecting gate line and the fifth connecting gate line.

[0016] Furthermore, in the first direction, the distance between the second end welding point and the fourth edge is 1 cm-3 cm.

[0017] Furthermore, the main gate electrode structure further includes a sixth connecting gate line, which is located at the first disconnected area and connects the second end welding point and a portion of the second fine gate between the first connecting gate line, the second connecting gate line and the third edge.

[0018] Furthermore, a seventh connecting gate line and an eighth connecting gate line are provided at the second disconnected region, the seventh connecting gate line and the eighth connecting gate line are spaced apart along the second direction and extend along the first direction, the seventh connecting gate line and the eighth connecting gate line are not in contact with the second fine gate, and the seventh connecting gate line and the eighth connecting gate line are both connected to a portion of the first fine gate closest to the third edge;

[0019] A third end welding point is disposed near the third edge and located at the second disconnected area, wherein the third end welding point is disposed between the seventh connecting gate line and the eighth connecting gate line and contacts the seventh connecting gate line and the eighth connecting gate line.

[0020] Furthermore, in the first direction, the distance between the third end welding point and the third edge is 1 cm-3 cm.

[0021] Furthermore, the seventh connecting gate line and the eighth connecting gate line connect at least three first fine gates; and / or in the first direction, the length of the seventh connecting gate line and the eighth connecting gate line is at least 4 times the spacing between the first fine gate and the second fine gate.

[0022] Furthermore, the main gate electrode structure also includes a ninth connecting gate line, which is located at the second disconnection area, and the ninth connecting gate line connects the third end welding point and the part of the first fine gate between the seventh connecting gate line and the eighth connecting gate line and the fourth edge.

[0023] Furthermore, a tenth connecting gate line and an eleventh connecting gate line are provided at the second disconnected region, the tenth connecting gate line and the eleventh connecting gate line are spaced apart along the second direction and extend along the first direction, the tenth connecting gate line and the eleventh connecting gate line do not contact the second fine gate, and the tenth connecting gate line and the eleventh connecting gate line are both connected to a portion of the first fine gate closest to the fourth edge;

[0024] A fourth end welding point is disposed near the fourth edge and located at the second disconnected area, wherein the fourth end welding point is disposed between the tenth connecting gate line and the eleventh connecting gate line and contacts the tenth connecting gate line and the eleventh connecting gate line.

[0025] Furthermore, in the first direction, the distance between the fourth end welding point and the fourth edge is 1 cm-3 cm.

[0026] Furthermore, the main gate electrode structure also includes a twelfth connecting gate line, which is located at the first disconnection area, and the twelfth connecting gate line connects the fourth end welding point and the first connecting gate line, the second connecting gate line and the part of the first fine gate between the third edge.

[0027] Furthermore, a plurality of first doped layers and a plurality of second doped layers are provided on the back side of the silicon substrate, wherein the plurality of first doped layers and the plurality of second doped layers are alternately arranged in sequence along a first direction and extend along a second direction, wherein the first direction intersects the second direction; the first fine gate is provided above the first doped layer, the second fine gate is provided above the second doped layer, and the first fine gate does not extend to the first edge of the silicon substrate;

[0028] The main gate electrode-free structure further includes:

[0029] a first edge bus bar disposed near the first edge and extending along the first direction, the first edge bus bar being electrically connected to the first fine grid; and a second edge bus bar extending along the first direction, the second edge bus bar being disposed between the first edge bus bar and the first edge and located above the second doped layer, the second edge bus bar being in contact with at least one of the second doped layers and being electrically connected to an end of a portion of the second fine grid near the first edge.

[0030] Furthermore, a portion of the second fine gate insulation passes through the first edge bus bar line and is electrically connected to the second edge bus bar line.

[0031] Furthermore, the third edge is connected to the first edge via a first chamfer;

[0032] In the direction from the third edge to the fourth edge, the second fine gates and the first fine gates are alternately arranged in sequence, and a first auxiliary gate line is provided at the first chamfer, which connects the second edge bus gate line and the second fine gate closest to the third edge.

[0033] Furthermore, the IBC solar cell sheet further comprises:

[0034] a third edge bus line disposed near the second edge and extending along the first direction, the third edge bus line being electrically connected to the second fine grid, the second fine grid not extending to the second edge, the third edge bus line having opposite polarity to the first edge bus line; and a fourth edge bus line extending along the first direction, the fourth edge bus line being disposed between the third edge bus line and the second edge and located above the first doped layer, the fourth edge bus line being in contact with at least one of the first doped layers and being electrically connected to one end of a portion of the first fine grid near the second edge.

[0035] Furthermore, a portion of the first fine gate insulation passes through the third edge bus bar line and is connected to the fourth edge bus bar line.

[0036] Furthermore, the third edge is connected to the second edge via a second chamfer;

[0037] In the direction from the third edge to the fourth edge, the second fine gates and the first fine gates are alternately arranged in sequence, and a third auxiliary gate line is provided at the second chamfer, and the third auxiliary gate line connects the second fine gate located at the second chamfer and the third edge bus gate line.

[0038] Furthermore, the main gate electrode-free structure further includes:

[0039] a third edge bus line disposed near the second edge and extending along the first direction, the third edge bus line being electrically connected to the first fine gate, the first fine gate not extending to the second edge of the silicon substrate, the third edge bus line having the same polarity as the first edge bus line; and a fourth edge bus line disposed near the second edge and extending along the first direction, the fourth edge bus line being disposed between the third edge bus line and the second edge and the fourth edge bus line being located above the second doped layer, the fourth edge bus line being in contact with at least one of the second doped layers and being electrically connected to one end of a portion of the second fine gate near the second edge.

[0040] Furthermore, a portion of the second fine gate insulation passes through the third edge bus bar line and is connected to the fourth edge bus bar line.

[0041] Furthermore, the third edge is connected to the second edge via a second chamfer;

[0042] In the direction from the third edge to the fourth edge, the second fine gates and the first fine gates are alternately arranged in sequence, and a fourth auxiliary gate line is provided at the second chamfer, and the fourth auxiliary gate line connects the fourth edge bus gate line and the second fine gate closest to the third edge.

[0043] The present disclosure also provides an IBC solar cell comprising a plurality of busbar-free electrode structures as described above.

[0044] The present disclosure also provides a battery assembly, which includes a plurality of the above-mentioned IBC solar cells.

[0045] The present disclosure also provides a photovoltaic system, which includes the above-mentioned battery assembly.

[0046] In the busbar-less electrode structure, IBC solar cell, battery module, and photovoltaic system of the embodiments of the present disclosure, since the first end welding points near the third edge and arranged at the first disconnection point do not contact the first fine grid, but are electrically connected to the portion of the second fine grid closest to the third edge, the second fine grids near the first edge can be connected together. On this basis, the first end welding points can be arranged at a position farther from the first edge of the silicon substrate through the above-mentioned electrical connection method. In this way, when the welding ribbon is subsequently welded to the first end welding points, the distance between the first end welding points and the first edge can reduce the risk of hidden cracks during welding, improve the yield of the battery cell, and also achieve overall convergence of the second fine grids. Furthermore, by arranging the first and second connecting grid lines at the first disconnection area, the first and second connecting grid lines do not contact the first fine grid, and the first and second connecting grid lines are both connected to the portion of the second fine grid closest to the third edge, arranged between the first and second connecting grid lines, and in contact with the first and second connecting grid lines. In this way, by setting the first connecting gate line and the second connecting gate line in the first disconnection area, the first end welding point can be set at a position farther away from the first edge of the silicon substrate and connected to the first connecting gate line and the second connecting gate line. Due to the setting of the first connecting gate line and the second connecting gate line, the risk of hidden cracks during welding can be further reduced, the yield of the battery cell can be improved, and the overall convergence of the second fine grid can also be achieved.

[0047] Additional aspects and advantages of the present disclosure will be given in part in the description that follows and, in part, will be obvious from the description that follows, or will be learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] FIG1 is a schematic structural diagram of an IBC solar cell provided in an embodiment of the present disclosure;

[0049] FIG2 is a partial enlarged schematic diagram of the IBC solar cell in FIG1 ;

[0050] FIG3 is another schematic structural diagram of an IBC solar cell provided in an embodiment of the present disclosure;

[0051] FIG4 is a partial enlarged schematic diagram of the IBC solar cell in FIG3 ;

[0052] FIG5 is a schematic cross-sectional view of the IBC solar cell in FIG3 at the second edge busbar line;

[0053] FIG6 is another partially enlarged schematic diagram of an IBC solar cell provided by an embodiment of the present disclosure;

[0054] FIG7 is a schematic cross-sectional view of the IBC solar cell in FIG3 at the fourth edge busbar line;

[0055] FIG8 is another partially enlarged schematic diagram of the IBC solar cell provided by an embodiment of the present disclosure;

[0056] FIG9 is another schematic structural diagram of an IBC solar cell provided in an embodiment of the present disclosure;

[0057] FIG10 is a schematic cross-sectional view of the IBC solar cell in FIG9 at the fourth edge busbar line;

[0058] FIG11 is a schematic structural diagram of a battery string provided in an embodiment of the present disclosure;

[0059] FIG12 is a schematic structural diagram of a photovoltaic system provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the present disclosure more clear, the present disclosure is further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. It should be noted that the embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure, and are not to be construed as limiting the present disclosure. In addition, it should be understood that the specific embodiments described herein are merely used to explain the present disclosure and are not intended to limit the present disclosure.

[0061] In the description of the present disclosure, it should be understood that the terms "up", "down", "left", "right", "horizontal", "longitudinal", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0062] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. Throughout the present disclosure, "several" means two or more, unless otherwise specifically defined.

[0063] In the present disclosure, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature includes the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0064] The disclosure below provides many different embodiments or examples for realizing different structures of the present disclosure. In order to simplify the disclosure of the present disclosure, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present disclosure provides examples of various specific processes and materials, but those of ordinary skill in the art will recognize the application of other processes and / or the use scenarios of other materials.

[0065] Example 1

[0066] 1 and 2 , an IBC solar cell 100 in an embodiment of the present disclosure may include a silicon substrate 10 and a busbar-less electrode structure in an embodiment of the present disclosure, wherein the busbar-less electrode structure is disposed on a back surface 11 of the silicon substrate 10 .

[0067] As shown in FIG. 1 and FIG. 2 , the main gate-less electrode structure may include a plurality of first fine gates 20 , a plurality of second fine gates 30 , a first connecting gate line 21 , a second connecting gate line 22 and a first end solder joint 23 .

[0068] A plurality of first fine gates 20 and a plurality of second fine gates 30 are alternately arranged along the first direction. In the second direction, the silicon substrate 10 has opposite first and second edges 101 and 102 . In the first direction, the silicon substrate 10 has opposite third and fourth edges 103 and 104 .

[0069] As shown in FIG. 1 , in the second direction, the first fine gate 20 has a plurality of first disconnected regions 201 spaced apart in the second direction, and the second fine gate 30 has a plurality of second disconnected regions 301 spaced apart in the second direction.

[0070] In the second direction, the first disconnected regions 201 and the second disconnected regions 301 are alternately arranged in sequence. The first disconnected regions 201 on adjacent first fine gates 20 correspond to each other in the first direction, and the second disconnected regions 301 on adjacent second fine gates 30 correspond to each other in the first direction.

[0071] It should be noted that "the first disconnection regions 201 on adjacent first fine grids 20 correspond to each other in the first direction, and the second disconnection regions 301 on adjacent second fine grids 30 correspond to each other in the first direction" means that the first disconnection regions 201 and the second disconnection regions 301 are substantially aligned in the first direction. "The first disconnection regions 201 and the second disconnection regions 301 are alternately arranged in the second direction" means that the first disconnection regions 201 and the second disconnection regions 301 are alternately arranged in the second direction throughout the IBC solar cell 100. Specifically, the first disconnection regions 201 and the second disconnection regions 301 are used to arrange welding strips to achieve busbar output.

[0072] The first connecting gate line 21 and the second connecting gate line 22 are both arranged in the first disconnected area 201. The first connecting gate line 21 and the second connecting gate line 22 are spaced apart along the second direction and extend along the first direction. The first connecting gate line 21 and the second connecting gate line 22 do not contact the first fine gate 20. The first connecting gate line 21 and the second connecting gate line 22 are both connected to the portion of the second fine gate 30 closest to the third edge 103.

[0073] The first end welding spot 23 is disposed near the third edge 103 and is located at the first disconnected region 201. The first end welding spot 23 is disposed between the first connecting gate line 21 and the second connecting gate line 22 and contacts the first connecting gate line 21 and the second connecting gate line 22. In other words, the width of the first disconnected region 201 where the first end welding spot 23 is disposed is greater than the width of the first disconnected region 201 at other locations.

[0074] In the main grid electrode-free structure and IBC solar cell in the embodiments of the present disclosure, a first connecting grid line 21 and a second connecting grid line 22 are arranged at the first disconnection area, and the first connecting grid line 21 and the second connecting grid line 22 are not in contact with the first fine grid 20. The first connecting grid line 21 and the second connecting grid line 22 are both connected to the portion of the second fine grid 30 closest to the third edge 103, and the first end welding point 23 is arranged between the first connecting grid line 21 and the second connecting grid line 22 and in contact with the first connecting grid line 21 and the second connecting grid line 22. In this way, by setting the first connecting gate line 21 and the second connecting gate line 22 in the first disconnection area 201, the second fine grid 30 near the first edge 101 can be connected together, so that the first end welding point 23 can be set at a position farther away from the first edge 101 of the silicon substrate 10 and connected to the first connecting gate line 21 and the second connecting gate line 22. In this way, when the welding strip is subsequently welded to the first end welding point 23, due to the setting of the first connecting gate line 21 and the second connecting gate line 22, the risk of hidden cracks during welding can be reduced, the yield of the battery cell can be improved, and the overall convergence of the second fine grid 30 can also be achieved.

[0075] Specifically, in the embodiment of the present disclosure, the first direction may be the longitudinal direction of the IBC solar cell 100 , and the second direction may be the transverse direction of the IBC solar cell 100 , and the two directions are perpendicular to each other.

[0076] “The first fine gate 20 forms a plurality of first disconnection regions 201” means that the first fine gate 20 is an intermittent structure, and the first fine gate 20 is disconnected at the first disconnection region 201, that is, the first disconnection region 201 divides the first fine gate 20 into several parts. Similarly, “the second fine gate 30 forms a plurality of second disconnection regions 301” means that the second fine gate 30 is an intermittent structure, and the second fine gate 30 is disconnected at the second disconnection region 301, that is, the second disconnection region 301 divides the second fine gate 30 into several parts.

[0077] In the embodiment shown in Figure 1, the "first edge 101" refers to the left edge in Figure 1, the "second edge 102" refers to the right edge in Figure 1, the third edge 103 refers to the upper edge in Figure 1, and the fourth edge 104 refers to the lower edge in Figure 1.

[0078] It should be noted that the first end solder joint 23 refers to the solder joint closest to the third edge 103 in the first disconnected region 201. The first connecting gate line 21 and the second connecting gate line 22 both connect to the portion of the second fine gate 30 closest to the third edge 103, which can be understood as the first connecting gate line 21 and the second connecting gate line 22 connecting the second fine gate 30 between the first end solder joint 23 and the third edge 103.

[0079] In some embodiments, the distance between the first end weld point 23 and the third edge 103 is 1 cm-3 cm.

[0080] In this way, by preferably setting the distance between the first end welding point 23 and the third edge 103 within this reasonable range, it can be ensured that the first end welding point 23 will not cause hidden cracks in the silicon substrate 10 during the welding process, thereby improving the yield of the battery cell.

[0081] Specifically, the distance between the first end welding point 23 and the third edge 103 can be, for example, 1 cm, 1.2 cm, 1.4 cm, 1.6 cm, 1.8 cm, 2 cm, 2.2 cm, 2.4 cm, 2.6 cm, 2.8 cm, 3 cm or any value between 1 cm and 3 cm, and is not limited here.

[0082] In some embodiments, the first connecting grid line 21 and the second connecting grid line 22 connect at least three second fine grids 30. In this way, the first end welding point 23 can be arranged farther from the third edge 103, thereby reducing the risk of hidden cracks.

[0083] Specifically, as shown in FIG. 1 and FIG. 2 , in the present disclosure, the first connecting gate line 21 and the second connecting gate line 22 may connect three second fine gates 300 located closest to the third edge 103 .

[0084] In some embodiments, in the first direction, the lengths of the first connecting grid lines 21 and the second connecting grid lines 22 are at least four times the distance between the first fine grid 20 and the second fine grid 30. This also allows the first end solder joint 23 to be positioned farther from the third edge 103, thereby reducing the risk of hidden cracks.

[0085] Specifically, as shown in Figures 1 and 2, in the first direction, the second fine gates 30 and the first fine gates 20 are arranged in sequence, the first connecting gate lines 21 and the second connecting gate lines 22 connect the three second fine gates 30 located at the third edge 103, and the lengths of the first connecting gate lines 21 and the second connecting gate lines 22 are 4 times the spacing between the first fine gates 20 and the second fine gates 30.

[0086] Please refer to Figures 1 and 2. In some embodiments, the main gate electrode structure may further include a third connecting gate line 24, which is located at the first disconnection area 201 and does not contact the first fine gate 20. The third connecting gate line 24 connects the first end welding point 23 and the first connecting gate line 21 and the second connecting gate line 22 and the portion of the second fine gate 30 between the fourth edge 104.

[0087] In this way, on the one hand, the anti-breaking function of the second fine grid 30 can be realized by setting the third connecting grid line 24. On the other hand, the connection between the third connecting grid line 24 and the first end welding point 23 can also increase the welding tension of the first end welding point 23 during welding, thereby improving the reliability of welding.

[0088] Specifically, as shown in FIG. 1 and FIG. 2 , in such an embodiment, the third connection grid line 24 may connect the first end welding point 23 and the three second fine grids 30 below the first end welding point 23 .

[0089] Example 2

[0090] Please continue to refer to Figures 1 and 2. In some embodiments, the main gate electrode structure may further include a fourth connecting gate line 25, a fifth connecting gate line 26 and a second end welding point 27. The fourth connecting gate line 25 and the fifth connecting gate line 26 are arranged at the first disconnection area 201. The fourth connecting gate line 25 and the fifth connecting gate line 26 are spaced apart along the second direction and extend along the first direction. The fourth connecting gate line 25 and the fifth connecting gate line 26 are not in contact with the first fine gate 20. The fourth connecting gate line 25 and the fifth connecting gate line 26 are both connected to the portion of the second fine gate 30 closest to the fourth edge 104.

[0091] The second end solder joint 27 is disposed near the fourth edge 104 and located at the first disconnection region 201 . The second end solder joint 27 is disposed between the fourth connection line 25 and the fifth connection line 26 and contacts the fourth connection line 25 and the fifth connection line 26 .

[0092] In this way, by setting the fourth connecting gate line 25 and the fifth connecting gate line 26, the second end welding point 27 can be at a greater distance from the fourth edge 104 of the silicon substrate 10. In this way, when the welding strip is subsequently welded to the second end welding point 27, due to the setting of the fourth connecting gate line 25 and the fifth connecting gate line 26, the risk of hidden cracks during welding can be reduced, the yield of the battery cell can be improved, and the overall convergence of the second fine grid 30 can also be achieved.

[0093] Specifically, in the present disclosure, the first end weld point 23 and the second end weld point 27 can be respectively set at the starting weld point and the ending weld point at the first disconnection area 201, and the first end weld point 23 and the second end weld point 27 are respectively set at the upper and lower ends of the battery cell. In this way, by setting the weld points at both ends of the connecting welding strip far away from the edge of the silicon substrate, hidden cracks can be avoided during welding.

[0094] Similarly, it should be noted that the second end solder joint 27 refers to the solder joint closest to the fourth edge 104 in the first disconnected region 201. The fourth connecting gate line 25 and the fifth connecting gate line 26 both connect to the portion of the second fine gate 30 closest to the fourth edge 104, which can be understood as the fourth connecting gate line 25 and the fifth connecting gate line 26 connecting the second fine gate 30 between the second end solder joint 27 and the fourth edge 104.

[0095] In some embodiments, the distance between the second end weld 27 and the fourth edge 104 is 1 cm-3 cm.

[0096] In this way, by preferably setting the distance between the second end welding point 27 and the fourth edge 104 within this reasonable range, it can be ensured that the second end welding point 27 will not cause hidden cracks in the silicon substrate during the welding process, thereby improving the yield of the battery cell.

[0097] Specifically, the distance between the second end welding point 27 and the fourth edge 104 can be, for example, 1 cm, 1.2 cm, 1.4 cm, 1.6 cm, 1.8 cm, 2 cm, 2.2 cm, 2.4 cm, 2.6 cm, 2.8 cm, 3 cm or any value between 1 cm and 3 cm, and is not limited here.

[0098] In some embodiments, the fourth connecting gate line 25 and the fifth connecting gate line 26 connect at least three second fine gates 30 .

[0099] In this way, the second end welding point 27 can be arranged farther away from the fourth edge 104 , thereby reducing the risk of hidden cracks.

[0100] Specifically, as shown in FIG. 1 and FIG. 2 , in the present disclosure, the fourth connecting gate line 25 and the fifth connecting gate line 26 may connect the three second fine gates located closest to the fourth edge 104 .

[0101] In some embodiments, in the first direction, the lengths of the fourth connecting grid line 25 and the fifth connecting grid line 26 are at least four times the distance between the first fine grid 20 and the second fine grid 30. This also allows the second end solder joint 27 to be positioned farther from the fourth edge 104, thereby reducing the risk of hidden cracks.

[0102] Specifically, as shown in Figure 1, in the first direction, the second fine gates 30 and the first fine gates 20 are arranged in sequence, the fourth connecting gate line 25 and the fifth connecting gate line 26 connect the three second fine gates 30 located at the third edge 103, and the length of the fourth connecting gate line 25 and the fifth connecting gate line 26 is 4 times the spacing between the first fine gates 20 and the second fine gates 30.

[0103] Please continue to refer to Figures 1 and 2. In some embodiments, the main gate electrode structure further includes a sixth connecting gate line 28, which is located at the first disconnection area 201. The sixth connecting gate line 28 connects the second end welding point 27 and the portion of the second fine gate 30 between the fourth connecting gate line 25 and the fifth connecting gate line 26 and the third edge 103.

[0104] In this way, on the one hand, the anti-breaking function of the second fine grid 30 can be realized by setting the sixth connecting grid line 28. On the other hand, the connection between the sixth connecting grid line 28 and the first end welding point 23 can also increase the welding tension of the first end welding point 23 during welding, thereby improving the reliability of welding.

[0105] Specifically, as shown in FIG. 1 and FIG. 2 , in such an embodiment, the sixth connecting gate line 28 may connect the three second fine gates 30 above the first end welding spot 23 and the second end welding spot 27 .

[0106] Example 3

[0107] Continuing to refer to FIG. 1 and FIG. 2 , in some embodiments, the main gate electrode-less structure may further include a seventh connecting gate line 31 , an eighth connecting gate line 32 , and a third end welding point 33 .

[0108] The seventh connecting gate line 31 and the eighth connecting gate line 32 are both disposed at the second disconnected region 301. The seventh connecting gate line 31 and the eighth connecting gate line 32 are spaced apart along the second direction and extend along the first direction. The seventh connecting gate line 31 and the eighth connecting gate line 32 do not contact the second fine gate 30. The seventh connecting gate line 31 and the eighth connecting gate line 32 are both connected to the portion of the first fine gate 20 closest to the third edge 103.

[0109] The third end solder joint 33 is disposed near the third edge 103 and located at the second disconnection region 301 . The third end solder joint 33 is disposed between the seventh and eighth connection lines 31 and 32 and contacts the seventh and eighth connection lines 31 and 32 .

[0110] In this way, by setting the seventh connecting gate line 31 and the eighth connecting gate line 32 at the second disconnection area 301, the first fine grid 20 near the third edge 103 can be connected together, so that the third end welding point 33 can be set at a position farther away from the third edge 103 of the silicon substrate 10 and connected to the seventh connecting gate line 31 and the eighth connecting gate line 32. In this way, when the welding strip is subsequently welded to the third end welding point 33, due to the setting of the seventh connecting gate line 31 and the eighth connecting gate line 32, the risk of hidden cracks during welding can be reduced, the yield of the battery cell can be improved, and the overall convergence of the first fine grid 20 can also be achieved.

[0111] Similarly, it should be noted that the third end solder joint 33 refers to the solder joint closest to the third edge 103 in the second disconnected region 301. The seventh connecting gate line 31 and the eighth connecting gate line 32 both connect to the portion of the second fine gate 30 closest to the third edge 103, which can be understood as the seventh connecting gate line 31 and the eighth connecting gate line 32 connecting the first fine gate 20 between the third end solder joint 33 and the third edge 103.

[0112] In some embodiments, the distance between the third end weld point 33 and the third edge 103 is 1 cm-3 cm.

[0113] In this way, by preferably setting the distance between the third end welding point 33 and the third edge 103 within this reasonable range, it can be ensured that the third end welding point 33 will not cause hidden cracks in the silicon substrate during the welding process, thereby improving the yield of the battery cell.

[0114] Specifically, the distance between the third end welding point 33 and the third edge 103 can be, for example, 1 cm, 1.2 cm, 1.4 cm, 1.6 cm, 1.8 cm, 2 cm, 2.2 cm, 2.4 cm, 2.6 cm, 2.8 cm, 3 cm or any value between 1 cm and 3 cm, and is not limited here.

[0115] In some embodiments, the seventh connecting gate line 31 and the eighth connecting gate line 32 connect at least three first fine gates 20 .

[0116] In this way, the third end welding point 33 can be arranged farther away from the third edge 103 , thereby reducing the risk of hidden cracks.

[0117] Specifically, as shown in FIG. 1 and FIG. 2 , in the present disclosure, the seventh connecting gate line 31 and the eighth connecting gate line 32 may connect the three first fine gates 20 located closest to the third edge 103 .

[0118] In some embodiments, in the first direction, the lengths of the seventh connecting grid line 31 and the eighth connecting grid line 32 are at least four times the distance between the first fine grid 20 and the second fine grid 30. This also allows the third end solder joint 33 to be positioned farther from the third edge 103, thereby reducing the risk of hidden cracks.

[0119] Specifically, as shown in Figure 2, in the first direction, the second fine gates 30 and the first fine gates 20 are arranged in sequence, the seventh connecting gate line 31 and the eighth connecting gate line 32 connect the three first fine gates 20 located at the third edge 103, and the length of the seventh connecting gate line 31 and the eighth connecting gate line 32 is 4 times the spacing between the first fine gates 20 and the second fine gates 30.

[0120] Please continue to refer to Figures 1 and 2. In some embodiments, the main gate electrode structure may further include a ninth connecting gate line 34, which is located at the second disconnection area 301. The ninth connecting gate line 34 connects the third end welding point 33 and the portion of the first fine gate 20 between the seventh connecting gate line 31 and the eighth connecting gate line 32 and the fourth edge 104.

[0121] In this way, on the one hand, the anti-breaking function of the first fine grid 20 can be realized by setting the ninth connecting grid line 34. On the other hand, the ninth connecting grid line 34 is connected to the third end welding point 33, which can also increase the welding tension of the third end welding point 33 during welding, thereby improving the reliability of welding.

[0122] Specifically, as shown in FIG. 2 , in such an embodiment, the ninth connecting gate line 34 may connect the third end welding point 33 and the three first fine gates 20 below the third end welding point 33 .

[0123] Example 4

[0124] Please refer to FIG. 1 and FIG. 2 again. In some embodiments, the main gate electrode-less structure may further include a tenth connecting gate line 35 , an eleventh connecting gate line 36 , and a fourth end welding point 37 .

[0125] The tenth connecting gate line 35 and the eleventh connecting gate line 36 are arranged at the first disconnection area. The tenth connecting gate line 35 and the eleventh connecting gate line 36 are spaced apart along the second direction and extend along the first direction. The tenth connecting gate line 35 and the eleventh connecting gate line 36 do not contact the second fine gate 30. The tenth connecting gate line 35 and the eleventh connecting gate line 36 are both connected to the portion of the first fine gate 20 closest to the fourth edge 104.

[0126] The fourth end solder joint 37 is set into the fourth edge 104 and located at the second disconnection area 301 . The fourth end solder joint 37 is set between the tenth connecting gate line 35 and the eleventh connecting gate line 36 and contacts the tenth connecting gate line 35 and the eleventh connecting gate line 36 .

[0127] In this way, by setting the tenth connecting gate line 35 and the eleventh connecting gate line 36, the fourth end welding point 37 can be at a greater distance from the fourth edge 104 of the silicon substrate 10. In this way, when the welding strip is subsequently welded to the fourth end welding point 37, due to the setting of the tenth connecting gate line 35 and the eleventh connecting gate line 36, the risk of hidden cracks during welding can be reduced, the yield of the battery cell can be improved, and the overall convergence of the second fine grid 30 can also be achieved.

[0128] Specifically, in the present disclosure, the third end welding point 33 and the fourth end welding point 37 can be the starting welding point and the ending welding point at the second disconnection area 301 respectively. In this way, by setting the welding points at both ends of the welding strip farther away from the edge of the silicon substrate 10, hidden cracks can be avoided during welding.

[0129] Similarly, it should be noted that the tenth connecting grid line 35 and the eleventh connecting grid line 36 both connect the portion of the second fine grid 30 closest to the fourth edge 104, which can be understood as the tenth connecting grid line 35 and the eleventh connecting grid line 36 connecting the first fine grid 20 between the fourth end welding point 37 and the fourth edge 104.

[0130] In some embodiments, the distance between the fourth end weld 37 and the fourth edge 104 is 1 cm-3 cm.

[0131] In this way, by preferably setting the distance between the fourth end welding point 37 and the fourth edge 104 within this reasonable range, it can be ensured that the fourth end welding point 37 will not cause hidden cracks in the silicon substrate during the welding process, thereby improving the yield of the battery cell.

[0132] Specifically, the distance between the fourth end welding point 37 and the fourth edge 104 can be, for example, 1 cm, 1.2 cm, 1.4 cm, 1.6 cm, 1.8 cm, 2 cm, 2.2 cm, 2.4 cm, 2.6 cm, 2.8 cm, 3 cm or any value between 1 cm and 3 cm, and is not limited here.

[0133] In some embodiments, the tenth connecting gate line 35 and the eleventh connecting gate line 36 connect at least three first fine gates 20 .

[0134] In this way, the fourth end welding point 37 can be arranged farther away from the fourth edge 104 , thereby reducing the risk of hidden cracks.

[0135] Specifically, as shown in FIG. 1 , in the present disclosure, the tenth connecting gate line 35 and the eleventh connecting gate line 36 may connect the three first fine gates 20 located closest to the fourth edge 104 .

[0136] In some embodiments, in the first direction, the lengths of the tenth connecting grid line 35 and the eleventh connecting grid line 36 are at least four times the distance between the first fine grid 20 and the second fine grid 30. This also allows the fourth end solder joint 37 to be positioned farther from the fourth edge 104, thereby reducing the risk of hidden cracks.

[0137] Specifically, as shown in Figure 1, in the first direction, the second fine gates 30 and the first fine gates 20 are arranged in sequence, the tenth connecting gate line 35 and the eleventh connecting gate line 36 connect the three first fine gates 20 located at the third edge 103, and the length of the tenth connecting gate line 35 and the eleventh connecting gate line 36 is 4 times the spacing between the first fine gates 20 and the second fine gates 30.

[0138] Please refer to Figure 2. In some embodiments, the main gate electrode structure may further include a twelfth connecting gate line 38, which is located at the second disconnection area 301. The twelfth connecting gate line 38 connects the fourth end welding point 37 and the portion of the first fine gate 20 between the tenth connecting gate line 35 and the eleventh connecting gate line 36 and the third edge 103.

[0139] In this way, on the one hand, the anti-breaking function of the second fine grid 30 can be realized by setting the twelfth connecting grid line 38. On the other hand, the connection between the twelfth connecting grid line 38 and the third end welding point 33 can also increase the welding tension of the third end welding point 33 during welding, thereby improving the reliability of welding.

[0140] Specifically, as shown in FIG. 2 , in such an embodiment, the twelfth connecting gate line 38 may connect the three first fine gates 20 above the third end welding spot 33 and the fourth end welding spot 37 .

[0141] Example 5

[0142] Referring to Figures 3 to 5, in some embodiments, the back side 11 of the silicon substrate 10 is provided with a plurality of first doped layers 12 and a plurality of second doped layers 13. The plurality of first doped layers 12 and the plurality of second doped layers 13 are alternately arranged in sequence along a first direction and extend along a second direction. The first direction intersects the second direction. In the second direction, the silicon substrate 10 has a first edge 101 and a second edge 102 relative to each other.

[0143] The busbar-less structure may further include a first edge busbar line 40 and a second edge busbar line 50. The back surface 11 of the silicon substrate 10 is provided with a plurality of first doped layers 12 and a plurality of second doped layers 13, which are alternately arranged in a first direction and extend in a second direction.

[0144] The polarity of the first doping layer 12 is opposite to that of the second doping layer 13. For example, the first doping layer 12 may be a P-type doping layer, and the second doping layer 13 may be an N-type doping layer. For another example, the first doping layer 12 may be an N-type doping layer, and the second doping layer 13 may be a P-type doping layer. There is no specific limitation here. The first doping layer 12 and the second doping layer 13 may be preferably spaced apart, and both the first doping layer 12 and the second doping layer 13 may extend to the first edge 101 and the second edge 102 of the silicon substrate 10.

[0145] The first fine gate 20 is arranged above the first doped layer 12, and the second fine gate 30 is arranged on the second doped layer 13. The first fine gate 20 is used to collect current in the first doped layer 12, and the second fine gate 30 is used to collect current in the second doped layer 13. The first fine gate 20 does not extend to the first edge 101 of the silicon substrate 10.

[0146] 3 and 4 , the first edge bus bar line 40 is disposed near the first edge 101 and extends along the first direction. The first edge bus bar line 40 is electrically connected to the first fine gate 20 .

[0147] The second edge bus line 50 extends along the first direction and is arranged between the first edge bus line 40 and the first edge 101 and is located above the second doped layer 13. The second edge bus line 50 contacts at least one second doped layer 13 and is electrically connected to an end of a portion of the second fine gate 30 close to the first edge 101.

[0148] Specifically, the second edge bus line 50 can be directly connected to a portion of the second fine gates 30 or connected to a portion of the second fine gates 30 through other connecting lines (such as the first auxiliary gate line 60 described below). It should be noted that "a portion of the second fine gate 30" refers to one second fine gate 30 or multiple second fine gates 30 but not all second fine gates 30.

[0149] It can be understood that in the relevant technology, the fine grids on the back side of the back-contact solar cell usually do not extend to the edges of both sides of the silicon wafer. Because if they extend to the edge, in order to collect the current of the fine grids in the edge area, it is necessary to set a welding strip at the edge to connect the fine grids in the edge area. If the fine grid of the opposite polarity to the welding strip extends to the edge of the silicon wafer, in order to avoid the welding strip at the edge position from contacting the opposite polarity fine grid, insulating glue needs to be coated between the welding strip at the edge position and each opposite polarity fine grid, which leads to a significant increase in cost and is also prone to glue leakage, thereby causing the battery cell to bend and warp.

[0150] However, if the fine gate does not extend to the edge of the silicon wafer, there will be a part of the edge area without the metal fine gate, resulting in a part of the edge area where the carriers cannot be collected, resulting in low carrier collection efficiency, efficiency loss, and low efficiency of the battery cell.

[0151] Therefore, in the present disclosure, by arranging a second edge bus line 50 between the first edge 101 and the first edge bus line 40 and making the second edge bus line 50 contact with at least one second doping layer 13 and connected to a portion of the second fine grid 30, the second edge bus line 50 can collect the current of the second doping layer 13 in the edge area at the first edge 101 and converge it to the adjacent same-polarity welding strip through a portion of the second fine grid 30 to realize current collection, which can effectively reduce the efficiency loss in the edge area of ​​the first edge 101 and improve the efficiency of the battery cell.

[0152] Furthermore, since only a portion of the second fine grid 30 is connected to the second edge busbar line 50, during the subsequent welding of the opposite polarity welding strip (e.g., the edge welding strip 220 described below), the welding strip will only cross a portion of the second fine grid 30 or the connecting line connecting the second fine grid 30 and the second edge busbar line 50 (e.g., the first auxiliary grid line 60 described below). There are relatively few intersection points, and only a small number of insulating glue needs to be arranged at these points to prevent leakage, which can effectively reduce costs. Furthermore, the points where the insulating glue is applied are isolated points, and it is not easy to cause glue leakage and thus bending and warping of the cell. In other words, the technical solution disclosed herein can reduce the cost of insulating glue and avoid bending and warping of the cell due to glue leakage, while also effectively reducing efficiency losses and ensuring the efficiency of the cell. Furthermore, by providing the first edge busbar line 40, the anti-break function of the first fine grid 20 can also be achieved, thereby preventing the first fine grid 20 from breaking as much as possible.

[0153] Specifically, in the embodiments of the present disclosure, the polarities of the first doped layer 12 and the second doped layer 13 are opposite, and the polarities of the first fine grid 20 and the second fine grid 30 are also opposite. For example, the first fine grid 20 is a positive fine grid line, used to collect positive current in the positive region, and the second fine grid 30 is a negative fine grid line, used to collect negative current in the negative region; or, the first fine grid 20 is a negative fine grid line, used to collect negative current in the negative region, and the second fine grid 30 is a positive grid line, used to collect positive current in the positive region. The positive fine grid lines are provided in the P-type doped layer of the IBC solar cell 100, and the negative fine grid lines are provided in the N-type doped layer of the IBC solar cell 100.

[0154] In the embodiments of the present disclosure, to reduce the difficulty of manufacturing, preferably, no first fine grid 20 is provided between the first edge bus bar line 40 and the first edge 101, and preferably, no first fine grid 20 or second fine grid 30 is provided between the second edge bus bar line 50 and the first edge 101. Of course, it is understood that, in some embodiments, the second fine grid 30 may be provided between the second edge bus bar line 50 and the first edge 101 without the first fine grid 20, and this is not limited to the specific embodiment.

[0155] Furthermore, in the embodiment of the present disclosure, the first fine grid 20 and the second fine grid 30 may be aluminum grid lines, silver grid lines, copper grid lines, or silver-clad copper grid lines, which are not limited herein.

[0156] It is understandable that in the embodiment of the present disclosure, the first fine grid 20 and the second fine grid 30 can be selected to be grid lines of the same or different metal types, for example, the first fine grid 20 and the second fine grid 30 can both be aluminum grid lines; or the first fine grid 20 can be aluminum grid lines, and the second fine grid 30 can be silver grid lines.

[0157] As shown in Figures 3 and 4, it is not difficult to understand that the second edge bus line 50 is in contact with the second doping layer 13 to realize the collection of current of the second doping layer 13 in the edge area. Therefore, in the embodiment of the present disclosure, in the first disconnection area 201 of the first fine grid 20 and the second disconnection area 301 of the second fine grid 30, the first disconnection area 201 is closest to the first edge 101, that is, in the second direction, the first disconnection area 201 and the second disconnection area 301 are arranged alternately in sequence, and at the position corresponding to the first disconnection area 201, the second fine grid 30 is not disconnected, and a welding strip in contact with the second fine grid 30 can be set at the position corresponding to the first disconnection area 201 to realize the convergence of the current of the first edge bus line 40.

[0158] Example 6

[0159] Referring to FIG. 4 , in some embodiments, a portion of the second fine gate 30 is insulated and passes through the first edge bus line 40 to be electrically connected to the second edge bus line 50 .

[0160] Thus, after collecting the current from the second doped layer 13 at the edge of the first edge 101 , the second edge bus line 50 can collect the current to the nearest soldering strip of the same polarity through the second fine grid 30 passing through the first edge bus line 40 .

[0161] Specifically, as shown in Figure 4, in such an embodiment, the plurality of second fine gates 30 may include a plurality of first collecting fine gates 302 and a plurality of first penetrating fine gates 303. The plurality of first collecting fine gates 302 are all located on the side of the first edge bus line 40 facing the second edge 102, and the first penetrating fine gates 303 are insulated and penetrate the first edge bus line 40 to connect with the second edge bus line 50.

[0162] That is to say, in such an embodiment, there is no first collecting fine grid 302 between the first edge bus line 40 and the first edge 101. Between the first edge bus line 40 and the first edge 101, only the position where the first edge bus line 40 is penetrated has the first penetrating fine grid 303, and the rest of the positions do not have fine grids (including the first fine grid 20 and the second fine grid 30).

[0163] It should be noted that, in the embodiment of the present disclosure, "part of the second fine gate 30 is insulated and passes through the first edge bus line 40" can be understood as a first direction in which there are a number of spaced-apart partition areas on the first edge bus line 40, and the first penetrating fine gate 303 passes through the first edge bus line 40 through the partition area without contacting the first edge bus line 40, so as to achieve physical penetration and insulation isolation.

[0164] It is understood that in such an embodiment, the number of first through-fine grids 303 can be single or multiple, and the specific number can be determined according to the size of the solar cell. When there are multiple first through-fine grids 303, the multiple first through-fine grids 303 can be spaced apart along the first direction, and the distance between two adjacent first through-fine grids 303 can be determined according to the size of the solar cell. Preferably, the first through-fine grids 303 can be evenly spaced along the first direction on the silicon substrate 10 according to the size of the silicon substrate 10, but this is not limited to this.

[0165] It is not difficult to understand that in such an embodiment, the second edge bus line 50 can collect the current of the second doped layer 13 in the edge area of ​​the first edge 101, and then collect it to the nearest welding strip of the same polarity (such as the welding strip 210 below) through the first through-fine grid 303 running through the first edge bus line 40 to achieve convergence. By setting multiple first through-fine grids 303, the convergence path can be effectively shortened and the loss can be reduced.

[0166] 3 and 4 , in some embodiments, the third edge 103 is connected to the first edge 101 via a first chamfer 105 ;

[0167] In the direction from the third edge 103 to the fourth edge 104 , the second fine gates 30 and the first fine gates 20 are alternately arranged in sequence. A first auxiliary gate line 60 is provided at the first chamfer 105 . The first auxiliary gate line 60 connects the second edge bus gate line 50 and the second fine gate 30 closest to the third edge 103 .

[0168] In this way, by disposing the first auxiliary grid line 60 at the first chamfer 105 , the current collected by the second edge bus grid line 50 can be converged to the second fine grid 30 at the third edge 103 and then converged to the nearest soldering strip.

[0169] Specifically, as shown in FIG3 , the third edge 103 is the upper edge of the silicon substrate 10, the fourth edge 104 is the lower edge of the silicon substrate 10, and the first edge 101 and the third edge 103 form a first chamfer 105. In such an embodiment, a first auxiliary gate line 60 is provided at the first chamfer 105 to connect the second edge bus line 50 and the uppermost second fine grid 30. The current collected by the second edge bus line 50 can be converged through the first auxiliary gate line 60 and the second fine grid 30 connected to the first auxiliary gate line 60 to the adjacent solder strip. In other words, the second edge bus line 50 can be electrically connected to the uppermost second fine grid 30 through the first auxiliary gate line 60.

[0170] It is understood that in such an embodiment, the first through-fine gate 303 and the first auxiliary gate line 60 in the above embodiment can be provided to achieve current confluence, or the first through-fine gate 303 in the above embodiment can be omitted and current confluence can be achieved through the first auxiliary gate line 60 at the first chamfer 105. Of course, to avoid excessive loss due to an excessively long transmission path for the confluence, it is preferred to achieve current confluence through the first through-fine gate 303 or through both the first through-fine gate 303 and the first auxiliary gate line 60, which is not limited here.

[0171] As shown in FIG4 , in some embodiments, the first auxiliary gate line 60 may be arranged parallel to the first chamfer 105. This can make the gate line structure of the back surface 11 simpler to manufacture.

[0172] Furthermore, in some embodiments, the first auxiliary gate line 60 may be located above the second doping layer 13 and contact at least one second doping layer 13 .

[0173] In this way, the first auxiliary gate line 60 can realize current convergence while also collecting current at the edge region at the first chamfer 105 , thereby further reducing efficiency loss and improving the efficiency of the solar cell.

[0174] Continuing to refer to Figures 3 and 4, in some embodiments, a second auxiliary gate line 70 may be further provided at the first chamfer 105, and the second auxiliary gate line 70 connects the first fine gates 20 and the first edge bus line 40 located at the first chamfer 105. It should be noted that the "first fine gates 20 located at the first chamfer 105" refers to a plurality of first fine gates 20 that are not directly connected to the first edge bus line 40 and whose extension lines along the second direction intersect the first chamfer 105, such as the two topmost first fine gates 20 in Figure 4.

[0175] In this way, the second auxiliary gate line 70 can be provided to connect the first fine grids 20 at the first chamfer 105 to achieve conduction between the first fine grids 20 at the first chamfer 105. When welding a welding strip (such as the edge welding strip 220 mentioned below) in the subsequent process, it is only necessary to contact the welding strip with the second auxiliary gate line 70 to achieve the collection of the current of the first fine grids 20 at the first chamfer 105. This can avoid the situation where the welding strip cannot contact all the first fine grids 20 at the first chamfer 105 when welding the welding strip due to the existence of the first chamfer 105, resulting in the current of the first fine grids 20 at the first chamfer 105 not being collected.

[0176] Specifically, as shown in Figure 4, in such an embodiment, the second auxiliary gate line 70 can also be arranged parallel to the first chamfer 105, that is, at the first chamfer 105, from the outside to the inside, the first chamfer 105, the first auxiliary gate line 60 and the second auxiliary gate line 70 are arranged in parallel in sequence.

[0177] As shown in FIG4 , it is readily understood that, since the first fine grid 20 has a first disconnected region 201 at a position closest to the first edge 101, a soldering ribbon is provided at the first edge 101 to electrically connect the first fine grid 20 to achieve current convergence. However, due to the presence of the first chamfer 105, the top first fine grid 20 is relatively short, and the soldering ribbon cannot contact the top first fine grid 20 when provided vertically. Furthermore, if the soldering ribbon is positioned too close to the inside, it may easily contact the second fine grid 30 of opposite polarity, resulting in leakage. Therefore, by providing the second auxiliary grid line 70, the first fine grids 20 at the first chamfer 105 can be connected as a whole. When soldering the soldering ribbon, current convergence of all first fine grids 20 need only be achieved by contacting the soldering ribbon with the first edge bus grid line 40, or with both the first edge bus grid line 40 and the second auxiliary grid line 70, or with the remaining first fine grids 20 connected to the first edge bus grid line 40 and the second auxiliary grid line 79.

[0178] In some embodiments, the distance between the first edge bus bar line 40 and the first edge 101 (ie, the distance between the first edge bus bar line 40 and the first edge 101 in the second direction) is 0.5 mm to 2 mm.

[0179] In this way, setting the spacing between the first edge bus grid line 40 and the first edge 101 within this reasonable range can effectively avoid the situation where the distance between the two is too large, resulting in too large an area of ​​the edge region without fine grids and causing excessive efficiency loss. It can also avoid the situation where the distance between the two is too small, resulting in cold solder joints and cracks when subsequently welding the solder strip at the first edge bus grid line 40, thereby ensuring the reliability and stability of the welding.

[0180] Specifically, in such an embodiment, the distance between the first edge bus line 40 and the first edge 101 can be, for example, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.2mm, 1.4mm, 1.6mm, 1.8mm, 2mm or any value between 0.5mm-2mm, and is not limited here.

[0181] Furthermore, in an embodiment of the present disclosure, the distance between the first edge bus bar 40 and the first edge 101 is preferably 0.8 mm to 1.2 mm, for example 0.9 mm, etc. This can effectively avoid excessive efficiency loss caused by excessive distance leading to excessive area of ​​the edge region while reducing the process difficulty, while also ensuring the stability and reliability of welding.

[0182] In some embodiments, the distance between the second edge bus bar line 50 and the first edge 101 (ie, the distance between the second edge bus bar line 50 and the first edge 101 in the second direction) is 0.3 mm to 1.2 mm.

[0183] In this way, on the one hand, it can avoid that the distance between the second edge bus line 50 and the first edge 101 is too small, which will greatly increase the difficulty of printing the second edge bus line 50; on the other hand, it can avoid that the distance between the second edge bus line 50 and the first edge 101 is too large, which will cause excessive efficiency loss.

[0184] Specifically, in such an embodiment, the distance between the second edge bus line 50 and the first edge 101 can be, for example, 0.3mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.2mm or any value between 0.3mm-1.2mm, which is not limited here.

[0185] Furthermore, in an embodiment of the present disclosure, the distance between the second edge bus line 50 and the first edge 101 is preferably 0.3mm-0.6mm, for example 0.5mm, etc. In this way, the process difficulty can be reduced while effectively avoiding the excessive distance that leads to an excessively large area of ​​the edge area and excessive efficiency loss. That is, the printing difficulty can be reduced while avoiding excessive efficiency loss.

[0186] In some embodiments, the width of the second edge bus bar line 50 may be 20 um-200 um.

[0187] In this way, setting the width of the second edge bus line 50 within this reasonable range can avoid the second edge bus line 50 being too small, resulting in too small a current capacity and causing a fuse during the bus, and can also avoid the second edge bus line 50 being too large, resulting in a significant increase in cost.

[0188] Specifically, in such an embodiment, the width of the second edge bus line 50 may be, for example, 20um, 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um, 110um, 120um, 130um, 140um, 150um, 160um, 170um, 180um, 190um, 200um or any value between 20um-200um, and is not limited here.

[0189] In some embodiments, the width of the second edge bus line 50 may be greater than the width of the first edge bus line 40 .

[0190] In this way, since the second edge bus line 50 is used to collect the current of each second doping layer 13 in the edge area, it plays the role of collection and convergence. Therefore, the width of the second edge bus line 50 can be set to be larger than the width of the first edge bus line 40, in order to improve the current flow capacity of the second edge bus line 50 to ensure the stability of the battery cell.

[0191] Example 7

[0192] Please refer to Figure 5. In some embodiments, a passivation film layer 107 is further provided on the first doping layer 12 and the second doping layer 13. The second edge bus line 50 is arranged on the passivation film layer 107. In the area corresponding to the second edge bus line 50 (that is, the projection area of ​​the second edge bus line 50 on the passivation film layer 107), a first opening 1071 is opened at a position corresponding to the second doping layer 13 on the passivation film layer 107. The second edge bus line 50 is in contact with the second doping layer 13 through the first opening 1071.

[0193] In this way, by opening the first opening 1071 at a position corresponding to the second doping layer 13 on the passivation film layer 107, the second edge bus line 50 can achieve stable contact with the second doping layer 13 below the edge area during printing to collect current, while also avoiding leakage caused by the second edge bus line 50 contacting the first doping layer 12.

[0194] Specifically, in such an embodiment, a first opening 1071 can be formed in the passivation film layer 107 by laser drilling. To maximize current collection, the first opening 1071 can be preferably formed on all second doped layers 13. The second edge busbar line 50 contacts all second doped layers 13 through the first opening 1071 to maximize current collection. It is understood that in such an embodiment, the first opening 1071 can be formed on all second doped layers 13 or on some second doped layers 13, and the specific details are not limited here.

[0195] Example 8

[0196] Referring to FIG. 3 , FIG. 6 and FIG. 7 , in some embodiments, the IBC solar cell 100 may further include a third edge bus bar line 80 and a fourth edge bus bar line 90 .

[0197] The third edge bus line 80 is close to the second edge 102 and extends along the first direction. The third edge bus line 80 is electrically connected to the second fine gate 30. The second fine gate 30 does not extend to the second edge 102 of the silicon substrate 10. The third edge bus line 80 has opposite polarity to the first edge bus line 40.

[0198] The fourth edge bus line 90 is also extended along the first direction. The fourth edge bus line 90 is arranged between the third edge bus line 80 and the second edge 102 and is located above the first doped layer 12. The fourth edge bus line 90 has an opposite polarity to the second edge bus line 50 and contacts at least one first doped layer 12 and is electrically connected to an end of a portion of the first fine gate 20 close to the second edge 102.

[0199] In this way, a fourth edge bus line 90 is arranged between the second edge 102 and the third edge bus line 80. The fourth edge bus line 90 is in contact with at least one first doped layer 12 and is connected to a portion of the first fine grid 20. The fourth edge bus line 90 can collect the current of the first doped layer 12 in the edge area at the second edge 102 and converge it to the adjacent same-polarity welding strip through a portion of the first fine grid 20 to realize current collection, which can further reduce the efficiency loss in the edge area of ​​the second edge 102 and further improve the efficiency of the battery cell.

[0200] Furthermore, as shown in Figures 3 and 6, since only a portion of the first fine grid 20 is connected to the fourth edge busbar line 90, during the subsequent welding of a welding ribbon of opposite polarity (e.g., edge welding ribbon 220 described below), the welding ribbon will only intersect a portion of the first fine grid 20. With fewer intersections, only a small number of points need to be coated with insulating adhesive to prevent leakage, effectively reducing costs. Furthermore, since the points where the insulating adhesive is applied are isolated, it is not likely to cause adhesive leakage and thus bending or warping of the cell. Furthermore, the provision of the third edge busbar line 80 can also achieve the anti-breakage function of the second fine grid 30, minimizing the risk of breakage of the second fine grid 30.

[0201] Specifically, in such an embodiment, the third edge bus line 80 at the second edge 102 has opposite polarity to the first edge bus line 40 at the first edge 101, with one being a positive bus line and the other being a negative bus line. The fourth edge bus line 90 at the second edge 102 has opposite polarity to the second edge bus line 50 at the first edge 101, with one being a positive bus line and the other being a negative bus line.

[0202] The second edge bus line 50 is used to collect current from the second doping layer 13 in the edge region of the first edge 101 , and the fourth edge bus line 90 is used to collect current from the first doping layer 12 in the edge region of the second edge 102 .

[0203] It is understandable that in such an embodiment, the third edge bus line 80 has substantially the same structure and material as the first edge bus line 40 , and the fourth edge bus line 90 has substantially the same structure and material as the second edge bus line 50 , which will not be described in detail here.

[0204] As shown in Figure 3, it is not difficult to understand that the fourth edge bus line 90 is in contact with the first doping layer 12 to realize the collection of current of the first doping layer 12 in the edge area. Therefore, as shown in Figure 6, in this embodiment, the number of first disconnection areas 201 and second disconnection areas 301 is an even number. In the first disconnection area 201 of the first fine grid 20 and the second disconnection area 301 of the second fine grid 30, the second disconnection area 301 is closest to the second edge 102, that is, in the second direction, the first disconnection area 201 and the second disconnection area 301 are arranged alternately in sequence, and the isolation area closest to the second edge 102 is the second disconnection area 301. At the position corresponding to the second disconnection area 301, the first fine grid 20 is not disconnected, and a welding strip in contact with the first fine grid 20 can be set at the position corresponding to the second disconnection area 301 to collect the current collected by the fourth edge bus line 90.

[0205] Example 9

[0206] Referring to FIG. 3 and FIG. 6 , in some embodiments, a portion of the first fine gate 20 is insulated and penetrates the third edge bus line 80 to connect to the fourth edge bus line 90 .

[0207] In this way, after collecting the current in the edge region, the fourth edge bus line 90 can collect the current to the nearest soldering strip of the same polarity through the first fine grid 20 passing through the third edge bus line 80 to achieve current collection.

[0208] Specifically, as shown in Figure 6, in such an embodiment, the plurality of first fine gates 20 may include a plurality of second collecting fine gates 202 and a plurality of second penetrating fine gates 203, wherein the plurality of second collecting fine gates 202 are all located on the side of the third edge bus line 80 facing the first edge 101, and the second penetrating fine gates 203 are insulated and penetrate the third edge bus line 80 to connect with the fourth edge bus line 90.

[0209] That is to say, in such an embodiment, there is no second collecting fine grid 202 between the third edge bus line 80 and the second edge 102. Between the third edge bus line 80 and the second edge 102, only the position where the second edge bus line 50 is penetrated has the second penetrating fine grid 203, and there are no fine grids (including the first fine grid 20 and the second fine grid 30) at other positions.

[0210] It should be noted that, in the embodiment of the present disclosure, "part of the first fine gate 20 is insulated and passes through the third edge bus line 80" can be understood as a first direction in which the third edge bus line 80 has a plurality of spaced-apart partition areas, and the second penetrating fine gate 203 passes through the third edge bus line 80 through the partition areas without contacting the third edge bus line 80, so as to achieve physical penetration and insulation isolation.

[0211] It is understood that in such an embodiment, the number of second through-fine grids 203 can be single or multiple, and the specific number can be determined according to the size of the cell. When there are multiple second through-fine grids 203, the multiple second through-fine grids 203 can be spaced apart along the first direction, and the distance between two adjacent second through-fine grids 203 can be determined according to the size of the cell. Preferably, the second through-fine grids 203 can be evenly spaced along the first direction on the silicon substrate 10 according to the size of the silicon substrate 10, without any specific limitation herein.

[0212] It is not difficult to understand that in such an embodiment, the fourth edge bus line 90 can collect the current of the first doped layer 12 in the edge area of ​​the second edge 102, and then collect it to the nearest welding strip of the same polarity (such as the welding strip 210 below) through the second penetrating fine grid 203 that passes through the third edge bus line 80 to achieve convergence. By setting multiple second penetrating fine grids 203, the convergence path can be effectively shortened and the loss can be reduced.

[0213] Example 10

[0214] 3 and 6 , in some embodiments, the third edge 103 is connected to the second edge 102 via a second chamfer 106 ;

[0215] Along the direction from the third edge 103 to the fourth edge 104, the second fine gates 30 and the first fine gates 20 are arranged alternately in sequence. A third auxiliary gate line 110 is provided at the second chamfer 106. The third auxiliary gate line 110 connects the second fine gates 30 located at the second chamfer 106 and the third edge bus bar line 80. It should be noted that the "second fine gates 30 located at the second chamfer 106" refers to a plurality of second fine gates 30 that are not directly connected to the third edge bus bar line 80 and whose extension lines along the second direction intersect the second chamfer 106, such as the two uppermost second fine gates 30 in FIG.

[0216] In this way, by setting the third auxiliary gate line 110, the second fine grids 30 at the second chamfer 106 can be connected to achieve conduction between the second fine grids 30 at the second chamfer 106. When the welding strip (such as the edge welding strip 220 below) is subsequently welded, it is only necessary to contact the welding strip with the third auxiliary gate line 110 to achieve the collection of current of the second fine grids 30 at the second chamfer 106. This can avoid the situation where the welding strip cannot contact all the second fine grids 30 at the second chamfer 106 due to the existence of the second chamfer 106, resulting in the current of the second fine grids 30 at the second chamfer 106 not being collected.

[0217] Specifically, as shown in FIG. 6 , in such an embodiment, the third auxiliary gate line 110 may be arranged parallel to the second chamfer 106 , which may make the gate line structure of the back surface 11 simpler to manufacture.

[0218] As shown in FIG6 , it is not difficult to understand that, since the second fine grid 30 has the second disconnected region 301 at the position closest to the second edge 102, in order to achieve the convergence of the second fine grid 30 near the second edge 102, it is necessary to provide a welding strip at the position of the second edge 102 to achieve conductive connection with the second fine grid 30 to achieve convergence. However, due to the existence of the second chamfer 106, the length of the top second fine grid 30 is relatively short, and the welding strip cannot be in contact with the top second fine grid 30 when it is vertically arranged. If the welding strip is too close to the inside, It is easy to contact the first fine grid 20 of opposite polarity and cause leakage. Therefore, by providing the third auxiliary grid line 110, the second fine grid 30 at the second chamfer 106 can be connected into a whole. When welding the welding ribbon, it is only necessary to contact the welding ribbon with the third edge bus grid line 80, or with the third edge bus grid line 80 and the third auxiliary grid line 110 at the same time, or with the remaining second fine grids 30 connected to the third edge bus grid line 80 and the third auxiliary grid line 110 to achieve current convergence of all the second fine grids 30.

[0219] Example 11

[0220] Referring to FIG8 , in some embodiments, the third edge bus line 80 may include a first bus segment 81 and a second bus segment 82. The first bus segment 81 connects to the second fine grid 30 located at the second chamfer 106. Similarly, in such embodiments, "second fine grids 30 located at the second chamfer 106" refers to a plurality of second fine grids 30 that are not directly connected to the third edge bus line 80 and whose extension lines along the second direction intersect the second chamfer 106, such as the two uppermost second fine grids 30 in FIG8 . The second bus segment 82 connects to the second fine grids 30 other than those located at the second chamfer 106. It will be appreciated that, as shown in FIG8 , in such embodiments, due to the presence of the second through fine grid 203, the second bus segment 82 is a discontinuous structure.

[0221] In this way, the second fine grids 30 at the second chamfer 106 can be connected into a whole through the first confluence section 81. When setting the welding strip, in order to achieve the confluence of the second fine grids 30 at the second chamfer 106, it is only necessary to contact the welding strip with any second fine grid 30 at the second chamfer 106 to achieve the confluence of all the second fine grids 30 at the second chamfer 106.

[0222] Furthermore, as shown in FIG. 8 , in such an embodiment, the first bus segment 81 and the second bus segment 82 are spaced apart along the second direction, and the second bus segment 82 is closer to the second edge 102 than the first bus segment 81 .

[0223] Specifically, in such an embodiment, the top of the first bus section 81 may be connected to the end of the topmost second fine grid 30 and extend along the first direction, so that all the second fine grids 30 at the second chamfer 106 are connected into a whole.

[0224] It is not difficult to understand that the difference between this embodiment and the above-mentioned embodiment 10 is that in the embodiment 10, the second fine gates 30 at the second chamfer 106 are connected into a whole by setting a third auxiliary gate line 110 parallel to the second chamfer 106, while in this embodiment, the second fine gates 30 at the second chamfer 106 are connected into a whole by the first bus section 81. Both can also be used at the same time, and there is no specific limitation here.

[0225] Example 12

[0226] Please refer to Figure 7. A passivation film layer 107 is provided on the first doping layer 12 and the second doping layer 13. The fourth edge bus line 90 is arranged on the passivation film layer 107. In the area corresponding to the fourth edge bus line 90 (that is, the projection area of ​​the fourth edge bus line 90 on the passivation film layer 107), a second opening 1072 is opened at the position corresponding to the first doping layer 12 on the passivation film layer 107. The fourth edge bus line 90 contacts the first doping layer 12 through the second opening 1072.

[0227] In this way, by opening a second opening 1072 at a position corresponding to the first doping layer 12 on the passivation film layer 107, the fourth edge bus line 90 can achieve stable contact with the first doping layer 12 below the edge area during printing to collect current, while also avoiding leakage caused by the fourth edge bus line 90 contacting the second doping layer 13.

[0228] Specifically, in such an embodiment, second openings 1072 can be formed in the passivation film layer 107 by laser drilling. To maximize current collection, second openings 1072 can preferably be formed in all first doped layers 12. The fourth edge busbar line 90 contacts all first doped layers 12 through the second openings 1072 to maximize current collection. Of course, in some embodiments, second openings 1072 can also be formed in part of the first doped layers 12, and this is not limited to this.

[0229] Example 13

[0230] 9 , in some embodiments, the third edge bus line 80 may also be electrically connected to the first fine gate 20 , and the first fine gate 20 does not extend to the second edge 102 of the silicon substrate 10 . The third edge bus line 80 has the same polarity as the first edge bus line 40 .

[0231] Meanwhile, in such an embodiment, the fourth edge bus line 90 has the same polarity as the second edge bus line 50 and contacts at least one second doped layer 13 and is electrically connected to an end of a portion of the second fine gate 30 close to the second edge 102 .

[0232] In such an embodiment, the difference from the example in FIG3 is that in the example shown in FIG9 , the third edge bus line 80 has the same polarity as the first edge bus line 40 , and the fourth edge bus line 90 has the same polarity as the second edge bus line 50 , whereas in the example shown in FIG3 , the third edge bus line 80 has an opposite polarity to the first edge bus line 40 , and the fourth edge bus line 90 has an opposite polarity to the second edge bus line 50 .

[0233] Specifically, in such an embodiment, the third edge bus line 80 and the fourth edge bus line 90 at the second edge 102 are symmetrically arranged with the first edge bus line 40 and the second edge bus line 50 at the first edge 101, and all of their structures are the same as the structure at the first edge 101, and the number of the first disconnection area 201 and the second disconnection area 301 is an odd number.

[0234] It is understandable that in such an embodiment, the third edge bus line 80 has substantially the same structure and material as the first edge bus line 40 , and the fourth edge bus line 90 has substantially the same structure and material as the second edge bus line 50 , which will not be described in detail here.

[0235] Similarly, as shown in Figure 9, it is not difficult to understand that the fourth edge bus line 90 is in contact with the second doped layer 13 to realize the collection of current in the second doped layer 13 in the edge area of ​​the second edge 102. Therefore, as shown in Figure 9, in this embodiment, in the first disconnection area 201 of the first fine gate 20 and the second disconnection area 301 of the second fine gate 30, the one closest to the second edge 102 is also the first disconnection area 201, that is, in the second direction, the first disconnection area 201 and the second disconnection area 301 are arranged alternately in sequence, and the isolation area closest to the second edge 102 is also the first disconnection area 201. At the position corresponding to the first disconnection area 201, the second fine gate 30 is not disconnected, and a welding point in contact with the second fine gate 30 can be set at the position corresponding to the first disconnection area 201 to realize the current convergence of the third edge bus line 80.

[0236] Example 14

[0237] 9 , in some embodiments, a portion of the second fine gate 30 is insulated and penetrates the third edge bus line 80 to be electrically connected to the fourth edge bus line 90 .

[0238] Thus, after collecting the current in the edge region of the second edge 102 , the fourth edge bus line 90 can collect the current to the nearest soldering strip of the same polarity through the second fine grid 30 passing through the third edge bus line 80 to achieve current collection.

[0239] Specifically, as shown in Figure 9, as described above, in such an embodiment, the plurality of second fine gates 30 may include a plurality of first collecting fine gates 302 and a plurality of first penetrating fine gates 303. Based on the second edge 102, the plurality of first collecting fine gates 302 are all located on the side of the third edge bus line 80 facing the first edge 101, and the first penetrating fine gates 303 are insulated and penetrate the third edge bus line 80 to connect with the fourth edge bus line 90.

[0240] That is, in such an embodiment, there is no first collecting fine gate 302 between the third edge bus line 80 and the second edge 102, and between the fourth edge bus line 90 and the second edge 102, only the position where the third edge bus line 80 is penetrated has the first penetrating fine gate 303.

[0241] It should be noted that, in the embodiment of the present disclosure, "part of the second fine gate 30 is insulated and passes through the third edge bus line 80" can be understood as a first direction in which the third edge bus line 80 has a plurality of spaced-apart partition areas, and the first penetrating fine gate 303 passes through the third edge bus line 80 through the partition areas without contacting the third edge bus line 80, so as to achieve physical penetration and insulation isolation.

[0242] Similarly, in such an embodiment, the number of first through-fine grids 303 can be single or multiple, and the specific number can be determined based on the size of the cell. When there are multiple first through-fine grids 303, the multiple first through-fine grids 303 can be spaced apart along the first direction, and the distance between two adjacent first through-fine grids 303 can be determined based on the size of the cell. Preferably, the first through-fine grids 303 can be evenly spaced along the first direction on the silicon substrate 10 based on the size of the silicon substrate 10, but this is not limited to this.

[0243] It should be noted that, in such an embodiment, the first penetrating fine gate 303 passing through the third edge bus line 80 may be the same gate line as the first penetrating fine gate passing through the first edge bus line 40 or may not be the same gate line. There is no specific restriction here. Preferably, they are the same gate line. When the two are the same gate line, the gate line structure at the first edge 101 is completely symmetrical with the gate line structure at the second edge 102.

[0244] Please refer to Figure 10. In such an embodiment, on the area corresponding to the fourth edge bus line 90 (i.e., the projection area of ​​the fourth edge bus line 90 on the passivation film layer 107), a third opening 1073 is opened at a position corresponding to the second doped layer 13 on the passivation film layer 107, and the fourth edge bus line 90 is in contact with the second doped layer 13 through the third opening 1073.

[0245] In this way, by opening the third opening 1073 at a position corresponding to the second doping layer 13 on the passivation film layer 107, the fourth edge bus line 90 can achieve stable contact with the second doping layer 13 below the edge area during printing to collect current, while also avoiding leakage caused by the fourth edge bus line 90 contacting the first doping layer 12.

[0246] Specifically, in such an embodiment, the structure of the fourth edge bus line 90 and the third opening 1073 can be the same as the structure of the second edge bus line 50 and the first opening 1071 described above, and the structures of the two can be symmetrical to each other. In this embodiment, the third opening 1073 can be formed on the passivation film layer 107 by laser drilling. In order to maximize the collection of current, the third opening 1073 can preferably be opened on all second doped layers 13, and the fourth edge bus line 90 can contact all second doped layers 13 through the third opening 1073 to maximize the collection of current. Of course, in some embodiments, the third opening 1073 can also be opened on part of the second doped layer 13, and the specific details are not limited here.

[0247] Example 15

[0248] Continuing to refer to FIG9 , in some embodiments, the third edge 103 is connected to the second edge 102 via a second chamfer 106 ;

[0249] In the direction from the third edge 103 to the fourth edge 104 , the second fine gates 30 and the first fine gates 20 are alternately arranged in sequence. A fourth auxiliary gate line 120 is provided at the second chamfer 106 . The fourth auxiliary gate line 120 connects the fourth edge bus bar line 90 and the second fine gate 30 closest to the third edge 103 .

[0250] Thus, by disposing the fourth auxiliary grid line 120 at the second chamfer 106 , the current collected by the fourth edge bus grid line 90 can be converged to the second fine grid 30 at the third edge 103 and then converged to the nearest soldering strip.

[0251] 9 , the third edge 103 is the upper edge of the silicon substrate 10 , the fourth edge 104 is the lower edge of the silicon substrate 10 , the first edge 101 and the third edge 103 form a first chamfer 105 , and the second edge 102 and the third edge 103 form a second chamfer 106 .

[0252] As shown in FIG. 9 , in such an embodiment, the first chamfer 105 is symmetrical to the second chamfer 106 , and the fourth auxiliary gate line 120 is symmetrical to the first auxiliary gate line 60 .

[0253] It is understood that in such an embodiment, the first through-fine gate 303 and the third auxiliary gate line 110 may be provided to achieve current confluence, or the first through-fine gate 303 may not be provided, and current confluence may be achieved through the fourth auxiliary gate line 120 at the second chamfer 106. Of course, to avoid excessive loss due to an excessively long transmission path for the confluence, current confluence may be preferably achieved through the first through-fine gate 303 or through both the first through-fine gate 303 and the fourth auxiliary gate line 120, without limitation herein.

[0254] In some embodiments, the fourth auxiliary gate line 120 is arranged parallel to the second chamfer 106. This can make the gate line structure of the back surface 11 simpler to manufacture.

[0255] Furthermore, in some embodiments, the fourth auxiliary gate line 120 may be located above the second doping layer 13 and contact at least one second doping layer 13 .

[0256] In this way, the fourth auxiliary gate line 120 can realize current convergence while also collecting current at the edge region at the second chamfer 106 , thereby further reducing efficiency loss and improving cell efficiency.

[0257] Continuing with FIG9 , in some embodiments, a fifth auxiliary gate line 130 may be further provided at the first chamfer 105. The fifth auxiliary gate line 130 connects the first fine gate 20 and the third edge bus line 80 at the second chamfer 106. Similarly, it should be noted that the "second fine gate 30 at the second chamfer 106" refers to a plurality of second fine gates 30 that are not directly connected to the third edge bus line 80 and whose extension lines along the second direction intersect the second chamfer 106, such as the two uppermost second fine gates 30 in FIG7 .

[0258] In this way, by setting the fifth auxiliary gate line 130, the first fine grids 20 at the second chamfer 106 can be connected to achieve conduction between the first fine grids 20 at the second chamfer 106. When the welding strip is subsequently welded, it is only necessary to contact the welding strip with the fifth auxiliary gate line 130 to achieve the collection of current of the first fine grids 20 at the second chamfer 106. This can avoid the situation where the welding strip 210 cannot contact all the first fine grids 20 at the second chamfer 106 due to the existence of the second chamfer 106, resulting in the current of the first fine grids 20 at the second chamfer 106 cannot be collected.

[0259] Specifically, as shown in Figure 9, in such an embodiment, the fifth auxiliary gate line 130 can also be arranged parallel to the second chamfer 106, that is, at the second chamfer 106, from the outside to the inside, the second chamfer 106, the fourth auxiliary gate line 120 and the fifth auxiliary gate line 130 are arranged in parallel in sequence, and the fifth auxiliary gate line 130 is arranged symmetrically with the second auxiliary gate line 70.

[0260] Example 16

[0261] In some embodiments, the distance between the third edge bus bar line 80 and the second edge 102 (ie, the distance between the third edge bus bar line 80 and the second edge 102 in the second direction) is 0.5 mm to 2 mm.

[0262] In this way, setting the spacing between the third edge bus grid line 80 and the second edge 102 within this reasonable range can effectively avoid the distance between the two being too large, resulting in an excessively large area of ​​the edge region without fine grids, which leads to excessive efficiency loss. It can also avoid the distance between the two being too small, resulting in cold solder joints and cracks when subsequently welding the solder strip at the third edge bus grid line 80, thereby ensuring the reliability and stability of welding.

[0263] Specifically, in such an embodiment, the distance between the third edge bus line 80 and the second edge 102 can be, for example, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.2mm, 1.4mm, 1.6mm, 1.8mm, 2mm or any value between 0.5mm-2mm, and is not limited here.

[0264] Furthermore, in the embodiment of the present disclosure, the distance between the third edge bus bar line 80 and the second edge 102 is preferably 0.8 mm to 1.2 mm, for example 0.9 mm, etc. This can effectively avoid the efficiency loss caused by the edge area not having fine grids due to the distance being too large while reducing the process difficulty, while also ensuring the stability and reliability of welding.

[0265] Example 17

[0266] In some embodiments, the distance between the fourth edge bus bar line 90 and the second edge 102 (ie, the distance between the second edge and the fourth edge) is 0.3 mm to 1.2 mm.

[0267] In this way, on the one hand, it is possible to avoid the distance between the fourth edge bus grid line 90 and the second edge 102 being too small, which would greatly increase the difficulty of printing the fourth edge bus grid line 90; on the other hand, it is possible to avoid the distance between the fourth edge bus grid line 90 and the second edge 102 being too large, which would cause the area without fine grids on the edge to be too large, resulting in excessive efficiency loss.

[0268] Specifically, in such an embodiment, the distance between the fourth edge bus line 90 and the second edge 102 can be, for example, 0.3mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.2mm or any value between 0.3mm-1.2mm, and is not limited here.

[0269] Furthermore, in an embodiment of the present disclosure, the distance between the fourth edge bus bar line 90 and the second edge 102 is preferably 0.3 mm to 0.6 mm, for example, 0.5 mm, etc. In this way, the process difficulty can be reduced while effectively avoiding the excessive distance that results in an excessively large area of ​​the edge region where no fine grid is set, resulting in excessive efficiency loss. That is, the printing difficulty can be reduced while avoiding excessive efficiency loss.

[0270] Embodiment 18

[0271] In some embodiments, the width of the fourth edge bus bar line 90 is 20 μm-200 μm.

[0272] In this way, setting the width of the fourth edge bus line 90 within this reasonable range can avoid the fourth edge bus line 90 being too small, resulting in too small a current capacity and causing a fuse to occur during the bus, and can also avoid the fourth edge bus line 90 being too large, resulting in a significant increase in cost.

[0273] Specifically, in such an embodiment, the width of the fourth edge bus line 90 may be, for example, 20um, 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um, 110um, 120um, 130um, 140um, 150um, 160um, 170um, 180um, 190um, 200um or any value between 20um-200um, and is not limited here.

[0274] In some embodiments, the width of the fourth edge bus line 90 is greater than the width of the third edge bus line 80 .

[0275] In this way, since the fourth edge bus line 90 is used to collect the current of each second doping layer 13 in the edge area, it plays the role of collection and convergence. Therefore, the width of the fourth edge bus line 90 can be set to be larger than the width of the third edge bus line 80, in order to improve the current flow capacity of the fourth edge bus line 90 to ensure the stability of the battery cell.

[0276] Example 19

[0277] 11 and 12 , the present disclosure further provides a photovoltaic system 1000. The photovoltaic system 1000 may include a battery assembly 200 according to an embodiment of the present disclosure. The battery assembly 200 according to an embodiment of the present disclosure may include several IBC solar cells 100 according to an embodiment of the present disclosure. In some embodiments, the multiple IBC solar cells 100 in the battery assembly 200 may be serially connected to form a battery string. The battery strings may be connected in series, in parallel, or in a combination of series and parallel to achieve current bus output. For example, the connection between the battery cells may be achieved by welding welding ribbons (including the welding ribbon 210 and the edge welding ribbon 220 described below), and the connection between the battery strings may be achieved by using bus bars.

[0278] It is understandable that the IBC solar cell 100 in the embodiment of the present disclosure may be a whole cell or a half cell, and is not specifically limited herein.

[0279] As shown in FIG11 , in two adjacent IBC solar cells 100, the first disconnection area 201 of one of the IBC solar cells 100 corresponds to the second disconnection area 301 of the other IBC solar cell 100 in the first direction, and welding ribbons 210 are provided at the first disconnection area 201 and the second disconnection area 301. Each first disconnection area 201 and each second disconnection area 301 is provided with a corresponding welding ribbon 210.

[0280] Among the two adjacent IBC solar cells 100, the first fine grid 20 of one IBC solar cell 100 is connected to the welding ribbon 210 at the first disconnection region 201, and the second fine grid 30 of the other IBC solar cell 100 is connected to the welding ribbon 210 at the second disconnection region 301. That is, the welding ribbon 210 at the first disconnection region 201 can be welded to the solar cell via the first end welding spot 23 and the second end welding spot 27 described above, and the welding ribbon 210 does not contact the second fine grid 30 connected to the first connecting grid line 21, the second connecting grid line 22, the fourth connecting grid line 25, and the fifth connecting grid line 26. The welding ribbon 210 at the second disconnection region 301 can be welded to the solar cell via the third end welding spot 33 and the fourth end welding spot 37 described above, and the welding ribbon 210 does not contact the first fine grid 20 connected to the seventh connecting grid line 31, the eighth connecting grid line 32, the tenth connecting grid line 35, and the eleventh connecting grid line 36.

[0281] In the battery string of the embodiment of the present disclosure, there are the following connection methods:

[0282] 1. As shown in FIG11 , in two adjacent IBC solar cells 100, the first edge 101 has a first edge busbar line 40 and a second edge busbar line 50, and the second edge 102 has a third edge busbar line 80 and a fourth edge busbar line 90. The polarity of the first edge busbar line 40 is opposite to that of the third edge busbar line 80, and the polarity of the second edge busbar line 50 is opposite to that of the fourth edge busbar line 90.

[0283] In the cell string, the first edge 101 of one of the two adjacent IBC solar cells 100 is aligned with the second edge 102 of the other, so that the first edge busbar line 40 and the third edge busbar line 80 of the two cells are located on the same side, and the second edge busbar line 50 and the fourth edge busbar line 90 are located on the same side. In the two IBC solar cells 100, the middle area is connected by the welding ribbon 210, and the edge area is connected by the edge welding ribbon 210 located at the first edge 101 and the second edge 102. 20 are welded together to achieve series connection, and it is only necessary to apply insulating glue on the edge welding strip 220 and the grid lines of different polarities (such as the first through-fine grid 303 and the second through-fine grid 203 in Figure 11). As shown in Figure 8, the edge welding strips 220 are conductively connected to the first edge bus grid line 40 and the third edge bus grid line 80 located on the same side. The edge welding strips 220 can be set along the first direction, and they can be welded to the first edge bus grid line 40 and the third edge bus grid line 80 or to the first fine grid 20 and the second fine grid 30.

[0284] 2. In two adjacent IBC solar cells 100 , only the first edge 101 has the first edge busbar line 40 and the second edge busbar line 50 ;

[0285] In this case, in two adjacent IBC solar cells 100, the first edge bus bars 40 located on the same side have opposite polarities, the first fine grid lines of the first edge bus bars 40 also have opposite polarities, and the second edge bus bars 50 also have opposite polarities. That is, in two adjacent IBC solar cells 100, the first edge bus bars 40 of one are P-type grid lines, and the first edge bus bars 40 of the other are N-type grid lines. The two IBC solar cells 100 are welded together via the welding ribbon located at the first edge 101 to achieve series connection.

[0286] As shown in FIG11 , in some embodiments, in a cell string, the edge welding ribbon 220 can be directly welded to the first edge bus bar 40 and the third edge bus bar 80, and the two can be in contact or overlapping. Of course, in some embodiments, the edge welding ribbon 220 can also be located on the inner side of the first edge bus bar 40 and the third edge bus bar 80 (i.e., on the side of the first edge bus bar 40 facing away from the first edge 101). In two adjacent IBC solar cells 100, the edge welding ribbon 220 is welded to the first fine grid 20 in one of the IBC solar cells 100, and is welded to the second fine grid 30 in the other IBC solar cell 100.

[0287] 3. In the IBC solar cell 100, there are no first edge busbar lines 40, second edge busbar lines 50, third edge busbar lines 80 and fourth edge busbar lines 90. In this case, the battery strings are connected in series in a traditional manner, which will not be described in detail here.

[0288] Throughout this specification, references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" indicate that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, illustrative uses of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0289] In addition, the above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A busbar-free electrode structure for an IBC solar cell, wherein the busbar-free electrode structure is disposed on the back side of a silicon substrate of the IBC solar cell, and the busbar-free electrode structure comprises: A plurality of first fine gates and a plurality of second fine gates, wherein the plurality of first fine gates and the plurality of second fine gates are alternately arranged in sequence along a first direction and extend along a second direction, wherein the second direction intersects the first direction, wherein in the second direction, the silicon substrate has a first edge and a second edge opposite to each other, and in the first direction, the silicon substrate has a third edge and a fourth edge opposite to each other; In the second direction, the first fine gate has a plurality of spaced first disconnected regions, and the second fine gate has a plurality of spaced second disconnected regions, the first disconnected regions and the second disconnected regions are alternately arranged in sequence, the first disconnected regions on two adjacent first fine gates correspond to each other in the first direction, and the second disconnected regions on two adjacent second fine gates correspond to each other in the first direction; The first end welding points arranged near the third edge and located at the first disconnection area are not in contact with the first fine grid, and are electrically connected to the part of the second fine grid closest to the third edge.

2. The main gate electrode-free structure according to claim 1, further comprising: A first connecting gate line and a second connecting gate line are arranged at the first disconnection area, the first connecting gate line and the second connecting gate line are arranged at intervals along the second direction and extend along the first direction, the first connecting gate line and the second connecting gate line are not in contact with the first fine gate, and the first connecting gate line and the second connecting gate line are both connected to the part of the second fine gate closest to the third edge.

3. The main gate-free electrode structure according to claim 2, wherein: In the first direction, the distance between the first end welding point and the third edge is 1 cm-3 cm.

4. The main gate electrode structure according to claim 2, wherein: The first connecting gate line and the second connecting gate line are connected to at least three second fine gates; and / or In the first direction, the lengths of the first connecting gate lines and the second connecting gate lines are at least four times the spacing between the first fine gates and the second fine gates.

5. The main gate electrode structure without main gate according to claim 2, wherein: The main gate electrode structure also includes a third connecting gate line, which is located at the first disconnected area and does not contact the first fine gate. The third connecting gate line connects the first end welding point and the part of the second fine gate between the first connecting gate line and the second connecting gate line and the fourth edge.

6. The main gate electrode structure without main gate according to claim 2, wherein: The main gate electrode structure without main gate may further include a fourth connecting gate line and a fifth connecting gate line arranged at the first disconnected area, the fourth connecting gate line and the fifth connecting gate line are arranged at intervals along the second direction and extend along the first direction, the fourth connecting gate line and the fifth connecting gate line are not in contact with the first fine gate, and the fourth connecting gate line and the fifth connecting gate line are both connected to the part of the second fine gate closest to the fourth edge; A second end welding point is disposed near the fourth edge and located at the first disconnection area, and the second end welding point is disposed between the fourth connection gate line and the fifth connection gate line and contacts the fourth connection gate line and the fifth connection gate line.

7. The main gate electrode structure according to claim 6, wherein: In the first direction, the distance between the second end welding point and the fourth edge is 1 cm-3 cm.

8. The main gate electrode structure according to claim 6, wherein: The main gate electrode structure further includes a sixth connecting gate line, which is located at the first disconnected area and connects the second end welding point and a portion of the second fine gate between the first connecting gate line, the second connecting gate line and the third edge.

9. The main gate-free electrode structure according to claim 6, wherein: a seventh connection gate line and an eighth connection gate line disposed at the second disconnected region, the seventh connection gate line and the eighth connection gate line being spaced apart along the second direction and extending along the first direction, the seventh connection gate line and the eighth connection gate line not being in contact with the second fine gate, and the seventh connection gate line and the eighth connection gate line both being connected to a portion of the first fine gate closest to the third edge; A third end welding point is arranged near the third edge and located at the second disconnection area, and the third end welding point is arranged between the seventh connection gate line and the eighth connection gate line and contacts the seventh connection gate line and the eighth connection gate line.

10. The main gate-free electrode structure according to claim 9, wherein: In the first direction, the distance between the third end welding point and the third edge is 1 cm-3 cm.

11. The main gate-free electrode structure according to claim 9, wherein: The seventh connecting gate line and the eighth connecting gate line are connected to at least three first fine gates; and / or In the first direction, the lengths of the seventh connecting gate line and the eighth connecting gate line are at least four times the spacing between the first fine gate and the second fine gate.

12. The main gate-free electrode structure according to claim 9, wherein: The main gate electrode structure further includes a ninth connecting gate line, which is located at the second disconnected area and connects the third end welding point and a portion of the first fine gate between the seventh and eighth connecting gate lines and the fourth edge.

13. The main gate-free electrode structure according to claim 9, wherein: a tenth connecting gate line and an eleventh connecting gate line disposed at the second disconnected region, the tenth connecting gate line and the eleventh connecting gate line being spaced apart along the second direction and extending along the first direction, the tenth connecting gate line and the eleventh connecting gate line not being in contact with the second fine gate, and the tenth connecting gate line and the eleventh connecting gate line both being connected to a portion of the first fine gate closest to the fourth edge; A fourth end welding point is arranged close to the fourth edge and located at the second disconnection area, and the fourth end welding point is arranged between the tenth connecting gate line and the eleventh connecting gate line and contacts the tenth connecting gate line and the eleventh connecting gate line.

14. The main gate-free electrode structure according to claim 13, wherein: In the first direction, the distance between the fourth end welding point and the fourth edge is 1 cm-3 cm.

15. The main gate electrode structure without main gate according to claim 13, wherein: The main gate electrode structure further includes a twelfth connecting gate line, which is located at the first disconnected area and connects the fourth end welding point and a portion of the first fine gate between the first connecting gate line, the second connecting gate line and the third edge.

16. The main gate-free electrode structure according to claim 2, wherein: A plurality of first doped layers and a plurality of second doped layers are provided on the back side of the silicon substrate, the plurality of first doped layers and the plurality of second doped layers are alternately arranged in sequence along a first direction and extend along a second direction, and the first direction intersects with the second direction; the first fine gate is provided above the first doped layer, the second fine gate is provided above the second doped layer, and the first fine gate does not extend to a first edge of the silicon substrate; The main gate electrode-free structure further includes: a first edge busbar line disposed close to the first edge and extending along the first direction, the first edge busbar line being electrically connected to the first fine grid; and A second edge bus line is extended along the first direction, the second edge bus line is arranged between the first edge bus line and the first edge and is located above the second doped layer, the second edge bus line is in contact with at least one of the second doped layers and is electrically connected to an end of a portion of the second fine gate close to the first edge.

17. The main gate electrode structure according to claim 16, wherein: A portion of the second fine gate insulation passes through the first edge bus gate line and is electrically connected to the second edge bus gate line.

18. The main gate-free electrode structure according to claim 16, wherein: The third edge is connected to the first edge via a first chamfer; In the direction from the third edge to the fourth edge, the second fine grids and the first fine grids are arranged alternately in sequence, and a first auxiliary grid line is provided at the first chamfer, and the first auxiliary grid line connects the second edge bus grid line and the second fine grid closest to the third edge.

19. The main gate electrode structure according to claim 16, wherein: The IBC solar cell sheet further comprises: a third edge bus line disposed close to the second edge and extending along the first direction, the third edge bus line being electrically connected to the second fine grid, the second fine grid not extending to the second edge, and having opposite polarity to the first edge bus line; and A fourth edge busbar line extending along the first direction, wherein the fourth edge busbar line is arranged between the third edge busbar line and the second edge and is located above the first doped layer, and the fourth edge busbar line contacts at least one of the first doped layers and is electrically connected to an end of a portion of the first fine gate close to the second edge.

20. The main gate-free electrode structure according to claim 19, wherein: A portion of the first fine gate insulation penetrates the third edge bus gate line and is connected to the fourth edge bus gate line.

21. The main gate-free electrode structure according to claim 19, wherein: The third edge is connected to the second edge via a second chamfer; In the direction from the third edge to the fourth edge, the second fine grids and the first fine grids are arranged alternately in sequence, and a third auxiliary grid line is provided at the second chamfer, and the third auxiliary grid line connects the second fine grid located at the second chamfer and the third edge bus grid line.

22. The main gate electrode structure according to claim 16, wherein: The main gate electrode-free structure further includes: a third edge bus gate line disposed close to the second edge and extending along the first direction, the third edge bus gate line being electrically connected to the first fine gate, the first fine gate not extending to the second edge of the silicon substrate, and the third edge bus gate line having the same polarity as the first edge bus gate line; and A fourth edge bus line is arranged near the second edge and extending along the first direction, the fourth edge bus line is arranged between the third edge bus line and the second edge and the fourth edge bus line is located above the second doped layer, the fourth edge bus line is in contact with at least one of the second doped layers and is electrically connected to an end of a portion of the second fine gate near the second edge.

23. The main gate electrode structure according to claim 22, wherein: A portion of the second fine gate insulation penetrates the third edge bus gate line and is connected to the fourth edge bus gate line.

24. The main gate electrode structure according to claim 22, wherein: The third edge is connected to the second edge via a second chamfer; In the direction from the third edge to the fourth edge, the second fine grids and the first fine grids are arranged alternately in sequence, and a fourth auxiliary grid line is provided at the second chamfer, and the fourth auxiliary grid line connects the fourth edge busbar line and the second fine grid closest to the third edge.

25. An IBC solar cell sheet, wherein: It comprises the main gate electrode structure as described in any one of claims 1 to 24.

26. A battery assembly, wherein: Comprising several IBC solar cells as claimed in claim 25.

27. A photovoltaic system, wherein: A battery assembly comprising the battery assembly of claim 26.

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