Chip packaging structure, flip chip packaging method, and electronic device

Abstract

The present application relates to the field of semiconductors, and provides a chip packaging structure, a flip chip packaging method, and an electronic device. The present application can achieve filtering of high-frequency noise without consuming resources of a bare chip and an electronic component. The chip packaging structure comprises a bare chip, an electronic component, a plurality of conductive bumps, and a first capacitor. The bare chip comprises a first wire, and the electronic component comprises a second wire and a third wire. The plurality of conductive bumps are arranged between the bare chip and the electronic device, and the plurality of conductive bumps include a first conductive bump and a second conductive bump. The first capacitor is disposed between the bare chip and the first conductive bump; the first wire is electrically connected to the second wire by means of the first capacitor and the first conductive bump; and the first wire is further electrically connected to the third wire by means of the second conductive bump. The first wire and the third wire are ground wires, and the second wire is a power supply wire; alternatively, the first wire and the third wire are power supply wires, and the second wire is a ground wire.

Description

Chip packaging structure, chip flip packaging method, electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 5, 2023, with application number 202311665822.7 and application name “Chip packaging structure, chip flip packaging method, electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductors, and in particular to a chip packaging structure, a chip flip packaging method, and an electronic device. Background Art

[0003] As chip speed, power consumption, and complexity increase, chip power integrity (PI) issues are becoming a key bottleneck to overall chip functionality and performance. Consequently, the demand for decoupling capacitors (decaps) is increasing. Decoupling capacitors are generally categorized by their placement: on-die decaps, package-mounted decaps, and board-level decaps.

[0004] However, on-chip decoupling capacitors occupy resources on the bare chip and are costly. Decoupling capacitors built into the package interfere with the routing of the package substrate, increasing assembly costs and resulting in low decoupling capacitor density. Furthermore, the decoupling capacitors are located far from the load on the bare chip, hindering the filtering of high-frequency noise. Board-level decoupling capacitors have a limited filtering range, primarily filtering low-frequency noise.

[0005] Therefore, using decoupling capacitors to filter out high-frequency noise without occupying the active area resources of the bare chip and packaging substrate is an urgent problem to be solved.

[0006] Summary of the Invention

[0007] In order to solve the above technical problems, the present application provides a chip packaging structure, a chip flip packaging method, and an electronic device. By setting a first capacitor between a bare chip and a first conductive bump, the resources of the bare chip and electronic devices are not occupied, and high-frequency noise can be filtered out.

[0008] In a first aspect, the present application provides a chip packaging structure comprising a bare chip, an electronic device, a plurality of conductive bumps, and a first capacitor. The bare chip comprises a first trace, and the electronic device comprises a second trace and a third trace. The plurality of conductive bumps are disposed between the bare chip and the electronic device, and the plurality of conductive bumps include a first conductive bump and a second conductive bump. The first capacitor is disposed between the bare chip and the first conductive bump; the first trace is electrically connected to the second trace via the first capacitor and the first conductive bump; and the first trace is further electrically connected to the third trace via the second conductive bump. The first trace and the third trace are ground traces, and the second trace is a power trace; alternatively, the first trace and the third trace are power traces, and the second trace is a ground trace.

[0009] The first capacitor in the present application is used as a decoupling capacitor. By making the first capacitor occupy part of the position of the original first conductive bump, the first capacitor is set between the bare chip and the first conductive bump. In addition, the first capacitor is also electrically connected to the second trace through the first conductive bump, so that the first capacitor is electrically connected between the power trace and the ground trace. Compared with the on-chip decoupling capacitor, the first capacitor of the present application does not need to occupy resources on the bare chip, saving costs. Compared with the packaged built-in decoupling capacitor, the first capacitor of the present application does not affect the routing of the electronic device, saving costs, and the first capacitor can be set at a high density; and the distance between the first capacitor of the present application and the active area in the bare chip is closer than the distance between the packaged built-in decoupling capacitor and the active area in the bare chip. Therefore, the first capacitor of the present application is more conducive to filtering out high-frequency noise. The distance between the first capacitor of the present application and the active area in the bare chip is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip. Therefore, the first capacitor of the present application is more conducive to filtering out high-frequency noise.

[0010] In some possible implementations, the bare chip further includes a fourth trace, the plurality of conductive bumps further includes a third conductive bump, and the fourth trace is electrically connected to the second trace via the third conductive bump. The second trace and the fourth trace are both ground traces; or the second trace and the fourth trace are both power traces. Thus, for example, in the case of a transistor electrically connected between the power trace and the ground trace, the first capacitor is electrically connected between the power trace and the ground trace, the drain of the transistor is electrically connected to the ground trace, and the source of the transistor is electrically connected to the power trace.

[0011] In some possible implementations, there are multiple first capacitors and multiple first conductive bumps, and multiple first capacitors are connected in parallel between the first trace and the second trace. In this way, different capacitance requirements can be achieved by designing the capacitance values ​​of the two first capacitors based on the parallel relationship of the two first capacitors.

[0012] In some possible implementations, the chip package structure further includes a second capacitor disposed between the first conductive bump and the electronic device, and the first trace is electrically connected to the second trace via the first capacitor, the first conductive bump, and the second capacitor.

[0013] Compared to on-chip decoupling capacitors, the second capacitor of the present application does not need to occupy resources on the bare chip, saving costs. Compared to packaged built-in decoupling capacitors, the second capacitor of the present application does not affect the routing of electronic devices, saving costs, and the second capacitor can be set at a high density; and the distance between the second capacitor of the present application and the active area in the bare chip is closer than the distance between the packaged built-in decoupling capacitor and the active area in the bare chip. Therefore, the second capacitor of the present application is more conducive to filtering out high-frequency noise. The distance between the second capacitor of the present application and the active area in the bare chip is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip. Therefore, the second capacitor of the present application is more conducive to filtering out high-frequency noise.

[0014] On this basis, different capacitance requirements can be achieved by designing the capacitance value of the first capacitor and the capacitance value of the second capacitor according to the series relationship between the first capacitor and the second capacitor.

[0015] In some possible implementations, the chip package structure further includes a first seed layer disposed between the bare chip and the plurality of conductive bumps, and a second seed layer disposed between the electronic device and the plurality of conductive bumps; the first capacitor is disposed between the first conductive bump and the first seed layer. In this manner, the first seed layer and the second seed layer can be used to prevent intermetallic reactions between the material of the plurality of conductive bumps and the first connection pad of the bare chip and the second connection pad of the electronic device.

[0016] In some possible implementations, along the direction from the bare chip toward the electronic device, the first capacitor includes a first electrode, a first dielectric layer, and a second electrode, with the first conductive bump also serving as the second electrode. Along the direction from the electronic device toward the bare chip, the second capacitor includes a third electrode, a second dielectric layer, and a fourth electrode, with the first conductive bump also serving as the fourth electrode.

[0017] In some possible implementations, the electronic device is a packaging substrate, and the bare chip is flip-packaged on the packaging substrate.

[0018] In a second aspect, the present application provides a chip flip-packaging method, comprising: sequentially forming a first capacitor and a plurality of first bumps on a bare chip to obtain a first substrate; the bare chip includes a first trace, and the plurality of first bumps include a first sub-bump and a second sub-bump; the first capacitor is located between the bare chip and the first sub-bump. Forming a plurality of second bumps on an electronic device to obtain a second substrate; the electronic device includes a second trace and a third trace, and the plurality of second bumps include a third sub-bump and a fourth sub-bump. Aligning the first substrate and the second substrate; arranging the first sub-bump and the third sub-bump in a one-to-one relationship, and arranging the second sub-bump and the fourth sub-bump in a one-to-one relationship; the first trace is electrically connected to the second trace via the first capacitor, the first sub-bump, and the third sub-bump; the first trace is also electrically connected to the third trace via the second sub-bump and the fourth sub-bump; wherein the first trace and the third trace are ground traces, and the second trace is a power trace; or, the first trace and the third trace are power traces, and the second trace is a ground trace.

[0019] In some possible implementations, before forming multiple second bumps on the electronic device, the chip flip-packaging method also includes: forming a second capacitor on the electronic device; the second capacitor is located between the third sub-bump and the electronic device, and the first trace is electrically connected to the second trace through the first capacitor, the first sub-bump, the third sub-bump, and the second capacitor.

[0020] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0021] The foregoing describes a case where the first conductive bump and the second conductive bump are electrically connected to the same first trace in the bare chip. In other possible implementations, the first conductive bump and the second conductive bump may also be electrically connected to the same trace in the package substrate. For details, see the third and fourth aspects of the specification.

[0022] In a third aspect, the present application provides a chip packaging structure comprising a bare chip, an electronic device, a plurality of conductive bumps, and a first capacitor. The bare chip comprises a first trace and a second trace, and the electronic device comprises a third trace. A plurality of conductive bumps are disposed between the bare chip and the electronic device, the plurality of conductive bumps comprising a first conductive bump and a second conductive bump. A first capacitor is disposed between the bare chip and the first conductive bump; the first trace is electrically connected to the third trace via the first capacitor and the first conductive bump, and the second trace is electrically connected to the third trace via the second conductive bump. The first trace is a ground trace, and the second and third traces are power traces; alternatively, the first trace is a power trace, and the second and third traces are ground traces.

[0023] The first capacitor in the present application is used as a decoupling capacitor. By making the first capacitor occupy part of the position of the original first conductive bump, the first capacitor is set between the bare chip and the first conductive bump. In addition, the first capacitor is also electrically connected to the third trace through the first conductive bump, so that the first capacitor is electrically connected between the power trace and the ground trace. Compared with the on-chip decoupling capacitor, the first capacitor of the present application does not need to occupy resources on the bare chip, saving costs. Compared with the packaged built-in decoupling capacitor, the first capacitor of the present application does not affect the routing of the electronic device, saving costs, and the first capacitor can be set at a high density; and the distance between the first capacitor of the present application and the active area in the bare chip is closer than the distance between the packaged built-in decoupling capacitor and the active area in the bare chip. Therefore, the first capacitor of the present application is more conducive to filtering out high-frequency noise. The distance between the first capacitor of the present application and the active area in the bare chip is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip. Therefore, the first capacitor of the present application is more conducive to filtering out high-frequency noise.

[0024] In some possible implementations, the electronic device further includes a fourth trace, the plurality of conductive bumps further includes a third conductive bump, and the fourth trace is electrically connected to the first trace via the third conductive bump. The first trace and the fourth trace are both ground traces; or the first trace and the fourth trace are both power traces. Thus, for example, in the case of a transistor electrically connected between the power trace and the ground trace, the first capacitor is electrically connected between the power trace and the ground trace, the drain of the transistor is electrically connected to the ground trace, and the source of the transistor is electrically connected to the power trace.

[0025] In some possible implementations, there are multiple first capacitors and multiple first conductive bumps, and multiple first capacitors are connected in parallel between the first trace and the third trace. In this way, different capacitance requirements can be achieved by designing the capacitance values ​​of the two first capacitors based on the parallel relationship of the two first capacitors.

[0026] In some possible implementations, the chip package structure further includes a second capacitor disposed between the first conductive bump and the electronic device, and the first trace is electrically connected to the third trace via the first capacitor, the first conductive bump, and the second capacitor.

[0027] Compared to on-chip decoupling capacitors, the second capacitor of the present application does not need to occupy resources on the bare chip, saving costs. Compared to packaged built-in decoupling capacitors, the second capacitor of the present application does not affect the routing of electronic devices, saving costs, and the second capacitor can be set at a high density; and the distance between the second capacitor of the present application and the active area in the bare chip is closer than the distance between the packaged built-in decoupling capacitor and the active area in the bare chip. Therefore, the second capacitor of the present application is more conducive to filtering out high-frequency noise. The distance between the second capacitor of the present application and the active area in the bare chip is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip. Therefore, the second capacitor of the present application is more conducive to filtering out high-frequency noise.

[0028] On this basis, different capacitance requirements can be achieved by designing the capacitance value of the first capacitor and the capacitance value of the second capacitor according to the series relationship between the first capacitor and the second capacitor.

[0029] In some possible implementations, the chip package structure further includes a first seed layer disposed between the bare chip and the plurality of conductive bumps, and a second seed layer disposed between the electronic device and the plurality of conductive bumps, with the first capacitor disposed between the first conductive bump and the seed layer. In this manner, the first seed layer and the second seed layer can be used to prevent intermetallic reactions between the material of the plurality of conductive bumps and the first connection pad of the bare chip and the second connection pad of the electronic device.

[0030] In some possible implementations, the electronic device is a packaging substrate, and the bare chip is flip-packaged on the packaging substrate.

[0031] In a fourth aspect, the present application provides a chip flip-package method, comprising: sequentially forming a first capacitor and a plurality of first bumps on a bare chip to obtain a first substrate; the bare chip includes a first trace and a second trace, and the plurality of first bumps include a first sub-bump and a second sub-bump; the first capacitor is located between the bare chip and the first sub-bump. Forming a plurality of second bumps on an electronic device to obtain a second substrate; the electronic device includes a third trace, and the plurality of second bumps include a third sub-bump and a fourth sub-bump. Aligning the first substrate and the second substrate; arranging the first sub-bump and the third sub-bump in a one-to-one relationship, and arranging the second sub-bump and the fourth sub-bump in a one-to-one relationship; the first trace is electrically connected to the third trace through the first capacitor, the first sub-bump, and the third sub-bump; the second trace is electrically connected to the third trace through the second sub-bump and the fourth sub-bump; wherein the first trace is a ground trace, and the second and third traces are power traces; or, the first trace is a power trace, and the second and third traces are ground traces.

[0032] In some possible implementations, before forming multiple second bumps on the electronic device, the chip flip-packaging method also includes: forming a second capacitor on the electronic device; the second capacitor is located between the third sub-bump and the electronic device, and the first trace is electrically connected to the third trace through the first capacitor, the first sub-bump, the third sub-bump, the second capacitor, and the third trace.

[0033] The fourth aspect and any implementation of the fourth aspect correspond to the third aspect and any implementation of the third aspect, respectively. The technical effects corresponding to the fourth aspect and any implementation of the fourth aspect can be referred to the technical effects corresponding to the third aspect and any implementation of the third aspect, and will not be repeated here.

[0034] In a fifth aspect, the present application provides an electronic device comprising a circuit board, solder balls, and the chip packaging structure described in the first aspect or the third aspect, wherein the electronic components of the chip packaging structure are soldered to the circuit board via solder balls.

[0035] The fifth aspect and any implementation of the fifth aspect correspond to the first aspect, the third aspect, and any implementation of the first and third aspects, respectively. The technical effects corresponding to the fifth aspect and any implementation of the fifth aspect can be found in the technical effects corresponding to the first aspect, the third aspect, and any implementation of the first and third aspects, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1a is a top view of a bare chip provided in an embodiment of the present application;

[0037] FIG1b is a diagram showing the connection relationship between a chip packaging structure and a circuit board provided by the related art;

[0038] FIG2 is a diagram showing the placement of decoupling capacitors according to the related art;

[0039] FIG3a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0040] FIG3b is a circuit diagram corresponding to the chip packaging structure shown in FIG3a;

[0041] FIG3c is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0042] FIG3 d is a circuit diagram corresponding to the chip packaging structure shown in FIG3 c ;

[0043] FIG4a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0044] FIG4b is a circuit diagram corresponding to the chip packaging structure shown in FIG4a;

[0045] FIG4c is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0046] FIG4 d is a circuit diagram corresponding to the chip packaging structure shown in FIG4 c ;

[0047] FIG5a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0048] FIG5 b is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0049] FIG6 a is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0050] FIG6 b is a schematic diagram of a first capacitor and a second capacitor provided in an embodiment of the present application;

[0051] FIG6 c is a schematic diagram of a first capacitor and a second capacitor provided in an embodiment of the present application;

[0052] FIG6d is a cross-sectional view taken along the line A1-A2 in FIG6c;

[0053] FIG7 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0054] FIG8 is a schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0055] FIG9 is a flow chart of the preparation of a chip packaging structure provided in an embodiment of the present application;

[0056] 10a-10h are process diagrams of forming a first capacitor and a first bump on a bare chip according to an embodiment of the present application;

[0057] 11a-11c are process diagrams of forming second bumps on a packaging substrate according to an embodiment of the present application;

[0058] 12a-12e are process diagrams of forming a second capacitor and a second bump on a packaging substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0060] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0061] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0062] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0063] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0064] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a chip.

[0065] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain chips.

[0066] For ease of explanation, the following description uses a mobile phone as an example electronic device. The mobile phone may include a circuit board, which may integrate a processor, memory, and the like. For example, the processor may be implemented by connecting circuits on one or more chips. Of course, the mobile phone may also include other components, and the circuit board may also integrate other circuit structures, which are not limited in the present embodiment.

[0067] As chip interconnect density increases and interconnect size continues to shrink, chip packaging technologies are becoming increasingly diverse. Flip-chip technology has become widely used in chip packaging, as it shortens the length of interconnects within a package, thereby better adapting to the development needs of highly integrated systems. Flip-chip technology involves directly fabricating conductive bumps on a bare chip as connection terminals, then flip-chip soldering them to a packaging substrate to achieve an electrical connection between the bare chip and the packaging substrate.

[0068] Specifically, FIG1a shows a top view of a bare chip 10, which includes a first connection pad 11, which may also be referred to as a solder pad or other term. As shown in FIG1b , the bare chip 10 is flip-chip mounted on a package substrate 20, with conductive bumps 30 contacting the first connection pad 11 of the bare chip 10 and the second connection pad 21 of the package substrate 20, respectively. This electrically connects the first connection pad 11 to the second connection pad 21 via the conductive bumps 30, thereby leading the first connection pad 11 of the bare chip 10 to the second connection pad 21 of the package substrate 20 via the conductive bumps 30.

[0069] As shown in Figure 1b, the packaging substrate 20 also includes a third connection pad 22 opposite to the second connection pad 21. The second connection pad 21 and the third connection pad 22 are electrically connected through the wiring layer in the packaging substrate 20. The bare chip 10 is soldered to the circuit board 40 through the third connection pad 22 and the solder ball in the packaging substrate 20.

[0070] As mentioned in the background, as chip speed, power consumption, and complexity increase, chip power integrity (PI) issues have gradually become a key bottleneck to the overall chip functionality and performance. Consequently, the demand for decoupling capacitors (decaps) has increased. Decoupling capacitors are generally categorized by their placement: on-chip decoupling capacitors, packaged internal decoupling capacitors, and board-level decoupling capacitors.

[0071] On-chip decoupling capacitors are formed during the back-end of line (BEOL) process of the bare chip. As shown in Figure 2, packaged decoupling capacitors typically refer to surface mount capacitors or back-mount capacitors placed on the package substrate 20. As shown in Figure 2, board-level decoupling capacitors are placed on the circuit board 40.

[0072] However, on-chip decoupling capacitors occupy resources on the bare chip 10 and are relatively costly. Decoupling capacitors built into the package affect the routing of the package substrate 20, increasing the assembly cost of the package substrate 20. The density of the decoupling capacitors is low. Furthermore, the decoupling capacitors are far from the active area in the bare chip 10, making it difficult to filter out high-frequency noise. The filtering range of board-level decoupling capacitors is limited, primarily filtering out low-frequency noise. The active area refers to the area in the bare chip 10 where the transistors fabricated using the previous process are located.

[0073] As chip speed, power consumption, and complexity increase, high-frequency noise in chip power network circuits becomes increasingly serious. Low-cost decoupling capacitor solutions to address high-frequency noise have become a research hotspot.

[0074] Based on this, an embodiment of the present application provides a chip packaging structure that can be applied to circuits that need to filter out high-frequency noise, such as chip power network circuits and signal isolation circuits.

[0075] As shown in Figures 3a and 4a, the chip package structure includes a bare chip 10, an electronic device, a plurality of conductive bumps 30, and a first capacitor 51. The electronic device can be a package substrate 20, an integrated passive device (IPD), etc. For ease of description, the following description uses the package substrate 20 as an example of the electronic device.

[0076] The bare chip 10 includes a first trace 11, and the package substrate 20 includes a second trace 21 and a third trace 22. A plurality of conductive bumps 30 are disposed between the bare chip 10 and the package substrate 20. The plurality of conductive bumps 30 include a first conductive bump 31 and a second conductive bump 32. A first capacitor 51 is disposed between the bare chip 10 and the first conductive bump 31. Alternatively, the first capacitor 51 is part of the first conductive bump 31, and within the first conductive bump 31, the first capacitor 51 is closer to the bare chip 10.

[0077] First trace 11 is electrically connected to second trace 21 via first capacitor 51 and first conductive bump 31. First trace 11 is also electrically connected to third trace 22 via second conductive bump 32. As shown in FIG3a , first trace 11 and third trace 22 are ground traces, and second trace 21 is a power trace. Alternatively, as shown in FIG4a , first trace 11 and third trace 22 are power traces, and second trace 21 is a ground trace.

[0078] The first capacitor 51 in the present application is used as a decoupling capacitor. By making the first capacitor 51 occupy part of the position of the original first conductive bump 31, the first capacitor 51 is set between the bare chip 10 and the first conductive bump 31. In addition, the first capacitor 51 is also electrically connected to the second trace 21 through the first conductive bump 31, so that the first capacitor 51 is electrically connected between the power trace and the ground trace. Compared with the on-chip decoupling capacitor, the first capacitor 51 of the present application does not need to occupy resources on the bare chip, saving costs. Compared with the built-in decoupling capacitor in the package, the first capacitor 51 of the present application does not affect the trace of the package substrate 20, saving costs, and the first capacitor can be set at a high density; and the distance between the first capacitor 51 of the present application and the active area in the bare chip 10 is closer than the distance between the built-in decoupling capacitor in the package and the active area of ​​the bare chip 10. Therefore, the first capacitor 51 of the present application is more conducive to filtering out high-frequency noise. The distance between the first capacitor 51 of the present application and the active area of ​​the bare chip 10 is closer than the distance between the board-level decoupling capacitor and the active area of ​​the bare chip 10. Therefore, the first capacitor 51 of the present application is more conducive to filtering out high-frequency noise.

[0079] In addition, the bare chip 10 may further include a plurality of transistors and conductive wires 70 . The transistor includes a channel layer 61 , a source 62 , and a drain 63 .

[0080] Taking a transistor electrically connected between a power supply line and a ground line as an example, as shown in Figures 3a and 3b, if the first line 11 and the third line 22 are ground lines, and the second line 21 is a power supply line, then the drain 63 of the transistor is electrically connected to different conductive bumps respectively through the same ground line in the bare chip 10. Specifically, the ground line in the bare chip 10 is electrically connected to the ground line in the package substrate 20 through the conductive lead 70 and the second conductive bump 32, and the ground line in the bare chip 10 is also electrically connected to the power supply line in the package substrate 20 through the conductive lead 70, the first capacitor 51, and the first conductive bump 31. In this way, the first capacitor 51 is electrically connected between the power supply line and the ground line, and the drain 63 of the transistor is electrically connected to the ground line. In the embodiments of the present application, the power supply in the circuit diagrams all represents the power supply line.

[0081] On this basis, as shown in Figures 3a and 3b, the bare chip 10 further includes a fourth trace 22, which is a power trace. The plurality of conductive bumps further includes a third conductive bump 33. The source 62 of the transistor is electrically connected to the power trace in the package substrate 20 via the power trace in the bare chip 10, the conductive lead 70, and the third conductive bump 33. In this way, the source 62 of the transistor is electrically connected to the power trace. The power trace in the package substrate 20 electrically connected to the first conductive bump 31 and the trace in the package substrate 20 electrically connected to the third conductive bump 31 are the same second trace 21.

[0082] In some possible implementations, as shown in Figures 3a and 3b , the number of first conductive bump 31 and first capacitor 51 is one; alternatively, as shown in Figures 3c and 3d , the number of first conductive bump 31 and first capacitor 51 is multiple. For example, the number of first conductive bump 31 and first capacitor 51 is two, and the two first capacitors 51 are connected in parallel between the ground trace and the power trace. In this way, different capacitance requirements can be achieved by designing the capacitance values ​​of the two first capacitors 51 according to the parallel connection relationship of the two first capacitors 51.

[0083] Still taking the example of a transistor electrically connected between a power line and a ground line, as shown in Figures 4a and 4b, if the first line 11 and the third line 22 are power lines, and the second line 21 is a ground line, then the source 62 of the transistor is electrically connected to different conductive bumps respectively through the same power line in the bare chip 10. Specifically, the power line in the bare chip 10 is electrically connected to the power line in the package substrate 20 via the conductive lead 70 and the second conductive bump 32. The power line in the bare chip 10 is also electrically connected to the ground line in the package substrate 20 via the conductive lead 70, the first capacitor 51, and the first conductive bump 31. In this way, the first capacitor 51 is electrically connected between the power line and the ground line, and the source 62 of the transistor is electrically connected to the power line.

[0084] On this basis, as shown in Figures 4a and 4b, the bare chip 10 also includes a fourth trace 22, which is a ground trace. The plurality of conductive bumps also includes a third conductive bump 33. The drain of the transistor is electrically connected to the ground trace in the package substrate 20 via the ground trace, conductive lead 70, and third conductive bump 33 in the bare chip 10. In this way, the drain 63 of the transistor is electrically connected to the ground trace. The ground trace electrically connected to the first conductive bump 31 in the package substrate 20 and the ground trace electrically connected to the third conductive bump 31 in the package substrate 20 are the same second trace 21.

[0085] In some possible implementations, as shown in Figures 4a and 4b , the number of first conductive bump 31 and first capacitor 51 is one; alternatively, as shown in Figures 4c and 4d , the number of first conductive bump 31 and first capacitor 51 is multiple. For example, there may be two first conductive bumps 31 and two first capacitors 51, and the two first capacitors 51 are connected in parallel between the ground trace and the power trace. In this way, different capacitance requirements can be achieved by designing the capacitance values ​​of the two first capacitors 51 according to the parallel connection relationship of the two first capacitors 51.

[0086] The above example describes a transistor electrically connected between a power line and a ground line. Of course, other circuits may also be electrically connected between the power line and the ground line, and the embodiments of the present application are not limited to this.

[0087] In some embodiments, as shown in FIG4 a , the first capacitor 51 includes a first electrode 511, a first dielectric layer 512, and a second electrode 513. The first electrode 511, the first dielectric layer 512, and the second electrode 513 are stacked in this order, extending from the bare chip 10 toward the package substrate 20. Since both the second electrode 513 and the first conductive bump 31 comprise conductive material, the first conductive bump 31 can be reused as the second electrode 513.

[0088] The above description describes a case where the first capacitor 51 is disposed between the bare chip 10 and the first conductive bump 31. In other embodiments, as shown in Figures 5a and 5b, the chip package structure may further include a second capacitor 52. The second capacitor 52 is disposed between the first conductive bump 31 and the package substrate 20. Alternatively, the second capacitor 52 is part of the first conductive bump 31, and within the first conductive bump 31, the second capacitor 51 is closer to the package substrate 20. The first trace 11 is electrically connected to the second trace 21 via the first capacitor 51, the first conductive bump 31, and the second capacitor 52.

[0089] Compared to on-chip decoupling capacitors, the second capacitor 52 of the present application does not need to occupy resources on the bare chip, saving costs. Compared to packaged built-in decoupling capacitors, the second capacitor 52 of the present application does not affect the routing of the package substrate 20, saving costs, and the second capacitor 52 can be set at a high density; and the distance between the second capacitor 52 of the present application and the active area in the bare chip 10 is closer than the distance between the packaged built-in decoupling capacitor and the active area in the bare chip 10. Therefore, the second capacitor 52 of the present application is more conducive to filtering out high-frequency noise. The distance between the second capacitor 52 of the present application and the active area in the bare chip 10 is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip 10. Therefore, the second capacitor 52 of the present application is more conducive to filtering out high-frequency noise.

[0090] On this basis, different capacitance requirements can be achieved by designing the capacitance value of the first capacitor 51 and the capacitance value of the second capacitor 52 according to the series relationship between the first capacitor 51 and the second capacitor 52 .

[0091] Taking a transistor electrically connected between a power supply line and a ground line as an example, as shown in FIG5a , if the first line 11 and the third line 22 are ground lines, and the second line 21 is a power line, then the drain 63 of the transistor is electrically connected to different conductive bumps through the same ground line in the bare chip 10. Specifically, the ground line in the bare chip 10 is electrically connected to the ground line in the package substrate 20 via the conductive lead 70 and the second conductive bump 32. The ground line in the bare chip 10 is also electrically connected to the power supply line in the package substrate 20 via the conductive lead 70, the first capacitor 51, the first conductive bump 31, and the second capacitor 51. In this way, the first capacitor 51 is electrically connected between the power supply line and the ground line, and the drain 63 of the transistor is electrically connected to the ground line.

[0092] Still taking the example of a transistor electrically connected between a power line and a ground line, as shown in FIG5b , if the first line 11 and the third line 22 are power lines, and the second line 21 is a ground line, then the source 62 of the transistor is electrically connected to different conductive bumps respectively through the same power line in the bare chip 10. Specifically, the power line in the bare chip 10 is electrically connected to the power line in the package substrate 20 via the conductive lead 70 and the second conductive bump 32. The power line in the bare chip 10 is also electrically connected to the ground line in the package substrate 20 via the conductive lead 70, the first capacitor 51, the first conductive bump 31, and the second capacitor 52. In this way, the first capacitor 51 is electrically connected between the power line and the ground line, and the source 62 of the transistor is electrically connected to the power line.

[0093] In some possible implementations, the embodiments of the present application do not limit the specific structures of the first capacitor 51 and the second capacitor 52, as long as the first capacitor 51 includes a first electrode 511, a first dielectric layer 512, and a second electrode 513 stacked in sequence, and the second capacitor 52 includes a third electrode, a second dielectric layer, and a fourth electrode stacked in sequence.

[0094] Optionally, as shown in Figures 5a and 5b, the first electrode 511, the first dielectric layer 512, and the second electrode 513 are stacked in sequence along the direction from the bare chip 10 to the packaging substrate 20, the first electrode 511 and the first dielectric layer 512 are concave-shaped, and the second electrode 513 is located in the concave-shaped groove; the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 are stacked in sequence along the direction from the packaging substrate 20 to the bare chip 10, the third electrode 521 and the second dielectric layer 522 are concave-shaped, and the fourth electrode 523 is located in the concave-shaped groove.

[0095] Optionally, as shown in Figure 6a, the first electrode 511, the first dielectric layer 512, and the second electrode 513 are stacked in sequence along the direction from the bare chip 10 to the packaging substrate 20, and the first electrode 511, the first dielectric layer 512, and the second electrode 513 are all plate-shaped; the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 are stacked in sequence along the direction from the packaging substrate 20 to the bare chip 10, and the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 are all plate-shaped.

[0096] Optionally, as shown in Figure 6b, the first electrode 511, the first dielectric layer 512, and the second electrode 513 are stacked in sequence along the direction from the bare chip 10 to the packaging substrate 20, the first electrode 511 and the first dielectric layer 512 both include multiple grooves, and the second electrode 513 is located in the multiple grooves; the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 are stacked in sequence along the direction from the packaging substrate 20 to the bare chip 10, the third electrode 521 and the second dielectric layer 522 both include multiple grooves, and the fourth electrode 523 is located in the multiple grooves.

[0097] As shown in Figures 6c and 6d, along the direction from the second conductive bump 32 to the first conductive bump 31, the first electrode 511, the first dielectric layer 512, and the second electrode 513 are stacked in sequence and form a circular ring. Along the direction from the second conductive bump 32 to the first conductive bump 31, the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 are stacked in sequence and form a circular ring. In the first capacitor 51, the number of first electrodes 511, first dielectric layer 512, and second electrode 513 can be one or more; in the second capacitor 52, the number of third electrodes 521, second dielectric layer 522, and fourth electrode 523 can be one or more. If there are multiple first electrodes 511, the multiple first electrodes 511 are electrically connected. If there are multiple second electrodes 513, the multiple second electrodes 513 are electrically connected. If there are multiple third electrodes 521, the multiple third electrodes 521 are electrically connected. If there are multiple fourth electrodes 523, the multiple fourth electrodes 523 are electrically connected.

[0098] In some embodiments, if the material of the multiple conductive bumps can react with the material of the second connection pad of the redistribution layer 20 and the first connection pad of the bare chip 10 to form a metal layer reaction to form an intermetallic compound, the second connection pad of the redistribution layer 20 and the first connection pad of the bare chip 10 will cause a phase change, resulting in shrinkage and collapse problems, thereby greatly reducing the welding reliability of the multiple conductive bumps.

[0099] For example, the first connection pad and the second connection pad are made of copper (Cu), and the conductive bumps are made of tin (Sn). Copper and tin react to form a copper-tin intermetallic compound.

[0100] As shown in FIG7 , the chip packaging structure further includes a first seed layer 81 disposed between the bare chip 10 and the plurality of conductive protrusions, and a second seed layer 82 disposed between the packaging substrate 20 and the plurality of conductive protrusions. The first capacitor 51 is disposed between the first conductive bump 31 and the first seed layer 81, and the second capacitor 52 is disposed between the first conductive bump 31 and the second seed layer 82. In this manner, the first seed layer 81 and the second seed layer 82 can be used to prevent the materials of the plurality of conductive bumps from reacting with the first connection pad of the bare chip 10 and the second connection pad of the packaging substrate 20.

[0101] Furthermore, to ensure that the second connection pad of the package substrate 20 is electrically connected to the first connection pad of the bare chip 10, the materials of the first seed layer 81 and the second seed layer 82 both include conductive materials, so that the second connection pad of the package substrate 20 is electrically connected to the first connection pad of the bare chip 10 through the first seed layer 81, the plurality of conductive bumps, and the second seed layer 82. Optionally, the first seed layer 81 and the second seed layer 82 can be a stack of titanium (Ti) and Cu.

[0102] In some embodiments, as shown in FIG8 , the plurality of conductive bumps may include a stack of titanium (Ti) / titanium nitride (TiN) and copper (Cu), with the Cu layer being located on the side of the Ti / TiN layer facing away from the bare chip 10. Furthermore, the chip package structure may further include a tin (Sn) layer (or SnAg layer) 92, which is disposed on the side of the Cu layer facing away from the bare chip 10.

[0103] In order to prevent the diffusion of Cu in the Cu layer and to better bond the Sn layer 92 , the chip packaging structure may further include a nickel (Ni) layer 91 . The Ni layer 91 is located between the Cu layer and the Sn layer 92 .

[0104] In another embodiment, the present application provides a chip-to-package method, as shown in FIG9 , which can be implemented by the following steps:

[0105] S110, forming a first capacitor 51 and a plurality of first bumps in sequence on the bare chip 10 to obtain a first substrate; the bare chip 10 includes a first trace 11, and the plurality of first bumps include a first sub-bump and a second sub-bump; the first capacitor 51 is located between the bare chip 10 and the first sub-bump.

[0106] Specifically, as shown in FIG10a, before forming the first capacitor 51, a first seed layer 81 may be formed on the bare chip 10, and a first photoresist 101 may be formed on the first seed layer 81. As shown in FIG10b, the first photoresist 101 is exposed and developed to form a first photoresist pattern 102. The first photoresist pattern 102 exposes the area where the first sub-bump to be formed is located. Furthermore, the first photoresist pattern 102 covers the area where the second sub-bump to be formed is located.

[0107] Next, under the protection of the first photoresist pattern 102, the first capacitor 51 is formed on the first seed layer 81. Specifically, as shown in Figures 10c-10f, a first electrode 511, a first dielectric layer 512, and a second electrode 513 are sequentially formed on the first seed layer 81. As shown in Figure 10e, a portion of the second electrode 5131 can be first deposited using atomic layer deposition (ALD), and then, as shown in Figure 10f, another portion of the second electrode 5132 can be deposited using chemical vapor deposition (CVD). The second electrode 5131 and the second electrode 5132 together constitute the second electrode 513.

[0108] In some possible implementations, the second electrode 513 is reused as the first sub-bump 301 , and forming the second electrode 513 is equivalent to forming the first sub-bump 301 .

[0109] In some possible implementations, as shown in Figures 10e and 10f, when the second electrode 513 is reused as the first sub-bump 301, after forming the first dielectric layer 512 and before forming the second electrode 513, the first photoresist pattern 102 can be further exposed, and the developed first photoresist pattern 102 also exposes the area where the second sub-bump is to be formed. In this way, the second sub-bump 302 can be deposited simultaneously with the deposition of the second electrode 5131 and the second electrode 5132. Next, as shown in Figures 10g and 10h, a Ni layer 91 and a Sn layer (or SnAg layer) 92 can be sequentially formed on the plurality of first bumps.

[0110] S120 , forming a plurality of second bumps on the packaging substrate 20 to obtain a second substrate; the packaging substrate 20 includes a second trace 21 and a third trace 22 , and the plurality of second bumps include a third sub-bump and a fourth sub-bump.

[0111] Specifically, as shown in FIG11a, a second seed layer 82 may be formed on the bare chip 10, and a second photoresist 103 may be formed on the second seed layer 82. As shown in FIG11b, the second photoresist 103 is exposed and developed to obtain a second photoresist pattern 104, which exposes the area where the second bump is to be formed.

[0112] In some possible implementations, the packaging substrate 20 may be, for example, a silicon-based substrate or an interposer.

[0113] Next, as shown in FIG11 c , a plurality of second bumps are formed under the protection of the first photoresist pattern 102 , wherein the plurality of second bumps include a third sub-bump 303 and a fourth sub-bump 304 .

[0114] S130, referring to FIG3a, align the first substrate and the second substrate; the first sub-bump 301 and the third sub-bump 303 are arranged opposite each other, and the second sub-bump 302 and the fourth sub-bump 304 are arranged opposite each other; the first trace 11 is electrically connected to the second trace 21 through the first capacitor 51, the first sub-bump 301, and the third sub-bump 303; the first trace 11 is also electrically connected to the third trace 22 through the second sub-bump 302 and the fourth sub-bump 304. The first trace 11 and the third trace 22 are ground traces, and the second trace 21 is a power trace; alternatively, the first trace 11 and the third trace 22 are power traces, and the second trace 21 is a ground trace.

[0115] The third sub-bump 303 is aligned with the first sub-bump 301 to form a first conductive bump 31 ; the fourth sub-bump 304 is aligned with the second sub-bump 302 to form a second conductive bump 32 .

[0116] The above description describes a chip package structure including a first capacitor 51. In some embodiments, the chip package structure further includes a second capacitor 52. Specifically, as shown in FIG12a , after forming the second seed layer 82 and before step S120 , the second photoresist 103 is exposed and developed to form a second photoresist pattern 104. The second photoresist pattern 104 exposes the region where the third sub-bump is to be formed. Furthermore, the second photoresist pattern 104 covers the region where the fourth sub-bump is to be formed.

[0117] Next, under the protection of the second photoresist pattern 104, the first capacitor 51 is formed on the second seed layer 82. Specifically, as shown in Figures 12a to 10e, a third electrode 521, a second dielectric layer 522, and a fourth electrode 523 are sequentially formed on the second seed layer 82. As shown in Figure 12d, a portion of the fourth electrode 5231 can be first deposited using ALD, and then, as shown in Figure 12e, another portion of the fourth electrode 5232 can be deposited using CVD. The fourth electrode 5231 and the fourth electrode 5232 together constitute the fourth electrode 523.

[0118] In some possible implementations, the fourth electrode 523 is reused as the third sub-bump 303 , and forming the fourth electrode 523 is equivalent to forming the third sub-bump 303 .

[0119] In some possible implementations, as shown in FIG12d and FIG12e, when the fourth electrode 523 is reused as the third sub-bump 303, after forming the second dielectric layer 522 and before forming the fourth electrode 523, the second photoresist pattern 104 can be further exposed. After development, the second photoresist pattern 104 also exposes the area where the fourth sub-bump is to be formed. In this way, the fourth sub-bump 304 can be deposited simultaneously with the deposition of the fourth electrodes 5231 and 5232.

[0120] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as those of the previous embodiment and will not be repeated here.

[0121] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A chip packaging structure, characterized in that: It includes a bare chip, an electronic device, a plurality of conductive bumps, and a first capacitor; The bare chip includes a first routing line, and the electronic device includes a second routing line and a third routing line; The plurality of conductive bumps are disposed between the bare chip and the electronic device, and the plurality of conductive bumps include a first conductive bump and a second conductive bump; The first capacitor is disposed between the bare chip and the first conductive bump; the first routing line is electrically connected to the second routing line through the first capacitor and the first conductive bump; the first routing line is also electrically connected to the third routing line through the second conductive bump; The first routing line and the third routing line are ground routing lines, and the second routing line is a power routing line; or the first routing line and the third routing line are power routing lines, and the second routing line is a ground routing line.

2. The chip packaging structure according to claim 1, characterized in that: The bare chip further includes a fourth trace, and the plurality of conductive bumps further includes a third conductive bump; The fourth wiring is electrically connected to the second wiring through the third conductive bump; Wherein, the second routing line and the fourth routing line are both ground routing lines; or, the second routing line and the fourth routing line are both power routing lines.

3. The chip packaging structure according to claim 1 or 2, characterized in that: There are multiple first capacitors and multiple first conductive bumps, and multiple first capacitors are connected in parallel between the first wiring and the second wiring.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure also includes a second capacitor; The second capacitor is disposed between the first conductive bump and the electronic device, and the first wiring is electrically connected to the second wiring through the first capacitor, the first conductive bump, and the second capacitor.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The chip packaging structure further includes a first seed layer disposed between the bare chip and the plurality of conductive bumps, and a second seed layer disposed between the electronic device and the plurality of conductive bumps; The first capacitor is disposed between the first conductive bump and the first seed layer.

6. The chip packaging structure according to claim 4 or 5, characterized in that: Along the direction from the bare chip to the electronic device, the first capacitor includes a first electrode, a first dielectric layer, and a second electrode, and the first conductive bump is reused as the second electrode; Along the direction from the electronic device to the bare chip, the second capacitor includes a third electrode, a second dielectric layer, and a fourth electrode, and the first conductive bump is also reused as the fourth electrode.

7. The chip packaging structure according to any one of claims 1 to 6, characterized in that: The electronic device is a packaging substrate.

8. A chip flip packaging method, characterized in that: include: A first capacitor and a plurality of first bumps are sequentially formed on a bare chip to obtain a first substrate; the bare chip comprises a first trace, and the plurality of first bumps comprises a first sub-bump and a second sub-bump; the first capacitor is located between the bare chip and the first sub-bump; A plurality of second bumps are formed on the electronic device to obtain a second substrate; the electronic device includes a second routing line and a third routing line, and the plurality of second bumps include a third sub-bump and a fourth sub-bump; The first substrate and the second substrate are aligned; the first sub-bump and the third sub-bump are arranged one by one opposite to each other, and the second sub-bump and the fourth sub-bump are arranged one by one opposite to each other; the first routing is electrically connected to the second routing through the first capacitor, the first sub-bump, and the third sub-bump; the first routing is also electrically connected to the third routing through the second sub-bump and the fourth sub-bump; wherein the first routing and the third routing are ground routing, and the second routing is a power routing; or, the first routing and the third routing are power routing, and the second routing is a ground routing.

9. The chip flip packaging method according to claim 8, characterized in that: Before forming a plurality of second bumps on the electronic device, the chip flip packaging method further comprises: A second capacitor is formed on the electronic device; the second capacitor is located between the third sub-bump and the electronic device, and the first wiring is electrically connected to the second wiring through the first capacitor, the first sub-bump, the third sub-bump, and the second capacitor.

10. An electronic device, characterized in that: It comprises a circuit board, solder balls, and the chip packaging structure according to any one of claims 1 to 7, wherein the electronic device of the chip packaging structure is soldered on the circuit board through the solder balls.

Images