Array substrate, display panel and display device

Abstract

An array substrate, comprising a plurality of columns of pixel circuits, a plurality of data lines, a plurality of multiplexing circuits, a plurality of input signal lines, a plurality of output signal line groups, a plurality of first gate lines and a plurality of second gate line groups. One data line is connected to one column of pixel circuits. The plurality of multiplexing circuits are arranged in a plurality of columns in a first direction, each column comprising a plurality of multiplexing circuits arranged in a second direction. The input signal lines are located on the side of the multiplexing circuits away from a display area, and one input signal line is connected to one multiplexing circuit. Each output signal line group comprises a plurality of output signal lines, the plurality of output signal lines are connected to the same multiplexing circuit, and one output signal line is connected to one data line. The first gate lines are located on the side of the plurality of multiplexing circuits away from the display area. Each second gate line group comprises a plurality of second gate lines, one second gate line is connected to one first gate line, and the plurality of second gate lines in one second gate line group are connected to the plurality of multiplexing circuits in one column.

Description

Array substrate, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202311688644.X filed on December 8, 2023, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0003] With the continuous development of display technology, the requirements for display devices are becoming increasingly stringent. Among them, high pixel density and narrow borders are important development directions for display devices. How to improve the pixel density of display devices and reduce the width of their borders is a technical problem that needs to be solved urgently. Summary of the Invention

[0004] In one aspect, an array substrate is provided. The array substrate includes a substrate, multiple columns of pixel circuits, multiple data lines, multiple multiplexing circuits, multiple input signal lines, multiple output signal line groups, multiple first gate lines, and multiple second gate line groups. The substrate includes a display area and a fan-out area adjacent to the display area. The multiple columns of pixel circuits are disposed in the display area, arranged along a first direction, and each column of pixel circuits includes multiple pixel circuits arranged along a second direction, where the first direction intersects the second direction. The multiple data lines are at least partially disposed in the display area and arranged at intervals along the first direction. The multiple data lines each extend along the second direction, with one data line connected to one column of pixel circuits. The multiple multiplexing circuits are disposed in the fan-out area, arranged in multiple columns along the first direction, with each column including multiple multiplexing circuits arranged along the second direction. The multiple input signal lines are disposed in the fan-out area and located on a side of the multiplexing circuits away from the display area, with one input signal line connected to one multiplexing circuit. The plurality of output signal line groups are arranged in the fan-out area and are located on a side of the plurality of multiplexing circuits close to the display area, and one output signal line group includes a plurality of output signal lines. The plurality of output signal lines included in one output signal line group are connected to the same multiplexing circuit, and one output signal line is connected to a data line. The plurality of first gate lines are arranged in the fan-out area and are located on a side of the plurality of multiplexing circuits away from the display area. A second gate line group includes a plurality of second gate lines, and a second gate line is connected to a first gate line. The plurality of second gate lines included in one second gate line group are connected to a plurality of the multiplexing circuits in a column.

[0005] In some embodiments, any two adjacent multiplexing circuits in the same column are staggered in the first direction, and a multiplexing circuit close to the display area is offset toward the same side as a multiplexing circuit far from the display area.

[0006] In some embodiments, two adjacent columns of multiplexing circuits are symmetrically arranged along the first direction.

[0007] In some embodiments, an angle α between a line connecting geometric centers of outlines of orthographic projections of any two adjacent multiplexing circuits in the same column on the substrate and the second direction is 4°≤α≤30°.

[0008] In some embodiments, the distance between any two adjacent multiplexing circuits in the same column in the first direction is D1 and the distance between any two adjacent multiplexing circuits in the second direction is D2; wherein D1, D2 and α satisfy: tanα=D2 / D1.

[0009] In some embodiments, the outline of the orthographic projection of the multiplexing circuit on the substrate is rectangular in shape.

[0010] In some embodiments, the plurality of second gate lines belonging to a second gate line group include a plurality of first sub-lines and a plurality of second sub-lines. The multiplexing circuit includes a plurality of N-type transistors and a plurality of P-type transistors. The plurality of control electrodes of the plurality of N-type transistors are respectively connected to the plurality of first sub-lines, the plurality of first electrodes of the plurality of N-type transistors are all connected to the input signal line, and the plurality of second electrodes of the plurality of N-type transistors are respectively connected to the plurality of output signal lines of the output signal line group. The plurality of control electrodes of the plurality of P-type transistors are respectively connected to the plurality of second sub-lines, the plurality of first electrodes of the plurality of P-type transistors are all connected to the input signal line, and the plurality of second electrodes of the plurality of P-type transistors are respectively connected to the plurality of output signal lines of the output signal line group. An output signal line is connected to the second electrode of an N-type transistor and the second electrode of a P-type transistor.

[0011] In some embodiments, the N-type transistor and the P-type transistor connected to the same output signal line have the same conduction state.

[0012] In some embodiments, the size of the N-type transistor is the same as the size of the P-type transistor.

[0013] In some embodiments, the multiple N-type transistors and the multiple P-type transistors belonging to the same multiplexing circuit are spaced apart along the second direction, and along the first direction, both ends of the multiple N-type transistors and the multiple P-type transistors are aligned.

[0014] In some embodiments, any two adjacent multiplexing circuits in the same column have a gap in the first direction and a second gap in the second direction.

[0015] In some embodiments, two adjacent multiplexing circuits in the same column are spaced apart along the first direction, and at least portions of the two multiplexing circuits are disposed opposite to each other along the first direction.

[0016] In some embodiments, a plurality of N-type transistors and a plurality of P-type transistors that are closest to each other and belong to two adjacent multiplexing circuits in the same column are arranged opposite each other along the first direction. The plurality of N-type transistors in the two adjacent multiplexing circuits in the same column have a third interval in the second direction, and the plurality of P-type transistors in the two adjacent multiplexing circuits in the same column have a fourth interval in the second direction.

[0017] In some embodiments, the first sub-line includes a plurality of first extension segments and a plurality of second extension segments. The plurality of first extension segments all extend along the second direction, and at least one first extension segment is configured to form a gate of an N-type transistor. The plurality of second extension segments all extend along the first direction, and the two ends of the second extension segments are respectively connected to a first extension segment. The second sub-line includes a plurality of third extension segments and a plurality of fourth extension segments. The plurality of third extension segments all extend along the second direction, and at least one third extension segment is configured to form a gate of a P-type transistor. The plurality of fourth extension segments all extend along the first direction, and the two ends of the fourth extension segments are respectively connected to a third extension segment.

[0018] In some embodiments, an output signal line group includes three output signal lines, and the multiplexing circuit is connected to the three output signal lines. The multiplexing circuit includes a P-type semiconductor layer, an N-type semiconductor layer, a source pattern, and three drain patterns. The P-type semiconductor layer includes a first and a second semiconductor pattern spaced apart along the first direction. The N-type semiconductor layer includes a third and a fourth semiconductor pattern spaced apart along the first direction. The source pattern includes a first source electrode, a second source electrode, and a first connecting portion. The first and second source electrodes are spaced apart along the first direction and both extend along the second direction. The first connecting portion is connected to adjacent ends of the first and second source electrodes and is also connected to the input signal line. The first source electrode is connected to the first and third semiconductor patterns, respectively, and the second source electrode is connected to the second and fourth semiconductor patterns, respectively. The three drain patterns are spaced apart along the first direction and all extend along the second direction. Two drain patterns are located on either side of the first source electrode along the first direction and are both connected to the first and third semiconductor patterns. Another drain pattern is arranged side by side with the second source along the first direction and is connected to the second semiconductor pattern and the fourth semiconductor pattern; one drain pattern is connected to one output signal line.

[0019] In some embodiments, an output signal line group includes two output signal lines, and the multiplexing circuit is connected to the two output signal lines. The multiplexing circuit includes a P-type semiconductor layer and an N-type semiconductor layer. The P-type semiconductor layer includes a fifth semiconductor pattern. The N-type semiconductor layer includes a sixth semiconductor pattern. The source pattern extends along the second direction and is connected to the fifth semiconductor pattern, the sixth semiconductor pattern, and the input signal line. The two drain patterns are located on either side of the source pattern along the first direction, and both drain patterns are connected to the fifth semiconductor pattern and the sixth semiconductor pattern. One drain pattern is connected to one output signal line.

[0020] In some embodiments, the multiple N-type transistors and the multiple P-type transistors belonging to the same multiplexing circuit are arranged at intervals along the second direction, and the multiple N-type transistors and the multiple P-type transistors are staggered in the first direction.

[0021] In some embodiments, along the second direction, a portion of the plurality of N-type transistors and a portion of the plurality of P-type transistors of the same multiplexing circuit are arranged opposite to each other.

[0022] In some embodiments, portions of two adjacent multiplexing circuits in the same column are arranged opposite to each other along the second direction.

[0023] In some embodiments, two adjacent multiplexing circuits respectively belonging to the same column, and the multiple N-type transistors and multiple P-type transistors closest to each other are spaced apart along the first direction, and parts of the multiple N-type transistors of the two adjacent multiplexing circuits respectively belonging to the same column are relatively arranged along the second direction, and parts of the multiple P-type transistors of the two adjacent multiplexing circuits respectively belonging to the same column are relatively arranged along the second direction.

[0024] In some embodiments, the first sub-line includes a plurality of fifth extension segments and a plurality of sixth extension segments. The plurality of fifth extension segments all extend along the second direction, and one fifth extension segment is configured to form the gate of an N-type transistor. The plurality of sixth extension segments are angled with the first direction, and the two ends of one sixth extension segment are respectively connected to two fifth extension segments. The second sub-line includes a plurality of seventh extension segments and a plurality of eighth extension segments. The plurality of seventh extension segments all extend along the second direction, and one seventh extension segment is configured to form the gate of a P-type transistor. The plurality of eighth extension segments are angled with the first direction, and the two ends of one eighth extension segment are respectively connected to one seventh extension segment.

[0025] In some embodiments, an output signal line group includes four output signal lines, and the multiplexing circuit is connected to the four output signal lines. The multiplexing circuit also includes a P-type semiconductor layer, an N-type semiconductor layer, a source pattern, and four drain patterns. The P-type semiconductor layer includes a seventh semiconductor pattern and an eighth semiconductor pattern spaced apart along the first direction. The N-type semiconductor layer includes a ninth semiconductor pattern and a tenth semiconductor pattern spaced apart along the first direction.

[0026] The source pattern includes a third source electrode, a fourth source electrode, and a second connecting portion. The third source electrode and the fourth source electrode are spaced apart along the first direction. The second connecting portion is connected to mutually adjacent ends of the third source electrode and the fourth source electrode and is also connected to the input signal line. The third source electrode is connected to the seventh semiconductor pattern and the ninth semiconductor pattern, and the fourth source electrode is connected to the eighth semiconductor pattern and the tenth semiconductor pattern.

[0027] The four drain patterns are arranged at intervals along the first direction; two of the drain patterns are located on both sides of the third source along the first direction, and are both connected to the seventh semiconductor pattern and the ninth semiconductor pattern; the other two drain patterns are located on both sides of the fourth source along the first direction, and are connected to the eighth semiconductor pattern and the tenth semiconductor pattern; one drain pattern is connected to an output signal line.

[0028] In some embodiments, the channel length of the N-type transistor and the P-type transistor is L, and the source and drain width of the N-type transistor and the P-type transistor is W. SD One of the multiplexing circuits is connected to M output signal lines, and a column of multiplexing circuits includes N multiplexing circuits; the spacing between two adjacent pixel circuits along the first direction is P Pixel In the region where the multiplexing circuit is located, the width of the output signal line along the first direction is W data The interval between two adjacent output signal lines is S data Among them, L, W SD , M, N, P Pixel 、W data and S data Meets: 2MNP pixel =2[ML+(M+1)W SD ]+2MN(W data +S data )+R design Among them, R design is the design redundancy, R design The value range is ±5μm.

[0029] In some embodiments, the L, W SD , M, N, P Pixel 、W data and S data It also approximately satisfies:

[0030] In some embodiments, the width-to-length ratio W / L of the N-type transistor and the P-type transistor is ≥ 38 μm / 7 μm. And / or the source-drain width W of the N-type transistor and the P-type transistor is SD ≤5μm; and / or, the distance P between two adjacent pixel circuits along the first direction Pixel ≤7.2μm. And / or, the width W of the output signal line along the first direction data ≤2μm. And / or, the interval S between two adjacent output signal lines data ≤3.25μm.

[0031] In some embodiments, the width of the input signal line along the first direction is W1, where W1≤2.5 μm, and / or the interval between two adjacent input signal lines along the first direction is W2, where W2≤7.2 μm.

[0032] In some embodiments, two adjacent multiplexing circuits in the same column have two ends aligned along the first direction.

[0033] In some embodiments, one column includes two multiplexing circuits, one multiplexing circuit includes a plurality of transistors; the plurality of transistors are arranged into a plurality of rows along the second direction, and each row includes at least one transistor.

[0034] In some embodiments, one of the multiplexing circuits includes three transistors, wherein the three transistors are arranged in a first row and a second row in a direction close to the display area, the first row including two transistors and the second row including one transistor.

[0035] In some embodiments, one of the multiplexing circuits includes two transistors; the two transistors are arranged in two rows along the second direction, and each row includes one transistor.

[0036] In some embodiments, one multiplexing circuit is connected to M output signal lines, where M ≥ 2. The array substrate includes (Q×M) first gate lines, the (Q×M) first gate lines are divided into Q groups, each group including M first gate lines, where O ≥ 2. A second gate line group is connected to a group of first gate lines, and along the first direction, the plurality of second gate line groups are alternately connected to the Q groups of first gate lines.

[0037] In some embodiments, one multiplexing circuit is connected to M output signal lines, where M ≥ 2. The array substrate includes (Q × 2M) first gate lines, the (Q × 2M) first gate lines being divided into Q groups, each group including 2M first gate lines, and the 2M first gate lines in each group being divided into M subgroups, each subgroup including two first gate lines arranged in parallel, and one second gate line being connected to the two first gate lines in each subgroup; wherein O ≥ 2. One second gate line group is connected to one group of first gate lines, and along the first direction, the multiple second gate line groups are alternately connected to the Q groups of first gate lines.

[0038] In some embodiments, the array substrate further includes a plurality of third connection portions, the plurality of third connection portions being located between and connected to two first gate lines of a subgroup, and the second gate line being connected to the third connection portions.

[0039] In some embodiments, the number of the third connection portions is greater than the number of the second gate lines connected to two first gate lines of a subset.

[0040] In some embodiments, the multiplexing circuit includes a plurality of transistors, wherein a width-to-length ratio of a channel of the transistor is W / L, wherein W / L≥180 / 35.

[0041] In some embodiments, the array substrate further comprises a plurality of test signal lines, at least one third gate line, at least one fourth gate line, a plurality of signal transmission lines, a plurality of first test transistors, and a plurality of second test transistors. The plurality of test signal lines comprise at least one first test signal line and at least one second test signal line, wherein the first test signal line is farther away from the display area than the second test signal line. The third gate line is disposed on a side of the plurality of test signal lines away from the display area. The fourth gate line is disposed on a side of the plurality of test signal lines close to the display area. The plurality of signal transmission lines are arranged at intervals along the first direction, and one end of a signal transmission line is configured to be connected to a data line, and the other end is configured to be connected to a driver chip. The plurality of first test transistors are disposed between the plurality of test signal lines and the third gate line. Along the second direction, the plurality of first test transistors are arranged in two rows, one row including a plurality of first transistor groups arranged along the first direction, one first transistor group including at least one first test transistor, and the plurality of first transistor groups in the two rows are alternately arranged in the first direction; the gate of the first test transistor is connected to the third gate line, the first electrode is connected to a first test signal line, and the second electrode is connected to a signal transmission line. The plurality of second test transistors are disposed between the plurality of test signal lines and the fourth gate line. Along the second direction, the plurality of second test transistors are arranged in two rows, one row including a plurality of second transistor groups arranged along the first direction, one second transistor group including at least one second test transistor, and the plurality of second transistor groups in the two rows are alternately arranged in the first direction; the gate of the second test transistor is connected to the fourth gate line, the first electrode is connected to a second test signal line, and the second electrode is connected to a signal transmission line.

[0042] In some embodiments, the array substrate has four test signal lines. Two test signal lines away from the display area are first test signal lines, and two test signal lines close to the display area are second test signal lines. The first electrodes of the plurality of first test transistors are respectively connected to the two first test signal lines, and along the first direction, the first electrodes of the plurality of first test transistors are alternately connected to the two first test signal lines. The first electrodes of the plurality of second test transistors are respectively connected to the two second test signal lines, and along the first direction, the first electrodes of the plurality of second test transistors are alternately connected to the two second test signal lines.

[0043] In some embodiments, one of the first transistor groups includes two first test transistors; and / or one of the second transistor groups includes two second test transistors.

[0044] In some embodiments, the array substrate further comprises a plurality of test signal lines, a plurality of test transistors, two fifth gate lines, and a plurality of signal transmission lines. The plurality of test signal lines are arranged in the fan-out area. The plurality of test transistors are arranged on a side of the plurality of test signal lines close to the display area and are arranged in two rows along the second direction. Both rows include a plurality of test transistors spaced apart along the first direction, belonging to two adjacent test transistors in two rows, and staggered along the first direction. The two fifth gate lines are spaced apart along the second direction, and the orthographic projection of a fifth gate line on the substrate partially overlaps with the orthographic projection of a row of test transistors on the substrate, and is configured to form the gate of a row of test transistors. The plurality of signal transmission lines are spaced apart along the first direction, and one end of a signal transmission line is configured to be connected to a data line, and the other end is configured to be connected to a driver chip. The first electrode of the test transistor is connected to a test signal line, and the second electrode is connected to a signal transmission line.

[0045] In some embodiments, the multiple test transistors are arranged into multiple columns along the first direction, each column includes two test transistors arranged along the second direction; at least portions of the two test transistors in a column are arranged relative to each other along the second direction, and there is a gap between two adjacent columns of test transistors in the first direction.

[0046] In some embodiments, the plurality of test signal lines are divided into a plurality of groups, each group including two test signal lines, wherein two test transistors in a column are respectively connected to the two test signal lines in a group, and along the first direction, the columns of test transistors are alternately connected to the plurality of groups of test signal lines.

[0047] In some embodiments, the signal transmission line includes a first region, the first gate line includes a second region, and the orthographic projections of the first region and the second region on the substrate overlap. The first region is provided with a hollow pattern, and / or the second region is provided with a hollow pattern.

[0048] In another aspect, a display panel is provided. The display panel includes a package cover plate and an array substrate as described in any of the above embodiments. The package cover plate is disposed on a first side of the array substrate, where the first side is the side of the array substrate's pixel circuits away from the substrate.

[0049] In another aspect, a display device is provided. The display device includes a driving circuit board and the display panel described above. The driving circuit board is connected to an array substrate of the display panel and is configured to transmit a control signal to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0051] FIG1 is a schematic diagram of a planar structure of a display device according to some embodiments;

[0052] FIG2 is a block diagram of a display device according to some embodiments;

[0053] FIG3 is a schematic diagram of a stacked structure of a display device according to some embodiments;

[0054] FIG4 is a structural diagram of an array substrate according to some embodiments;

[0055] FIG5 is a partial enlarged view of area A in FIG4 ;

[0056] FIG6 is a partial enlarged view of area B in FIG5 ;

[0057] FIG7 is another partial enlarged view of the area A in FIG4 ;

[0058] FIG8 is a partial enlarged view of area C in FIG7 ;

[0059] FIG9 is another structural diagram of an array substrate according to some embodiments;

[0060] FIG10 is a partial enlarged view of area D in FIG9 ;

[0061] FIG11 is another structural diagram of an array substrate according to some embodiments;

[0062] FIG12 is another structural diagram of an array substrate according to some embodiments;

[0063] FIG13 is another structural diagram of an array substrate according to some embodiments;

[0064] FIG14 is another structural diagram of an array substrate according to some embodiments;

[0065] FIG15 is a structural diagram of a test circuit of an array substrate according to some embodiments;

[0066] FIG16 is another structural diagram of a test circuit of an array substrate according to some embodiments;

[0067] FIG. 17 is a structural diagram showing a first gate line overlapping a signal transmission line according to some embodiments. DETAILED DESCRIPTION

[0068] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0069] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example" or "some examples" and the like are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0070] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0071] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed, removable, or integrated; it can be directly connected or indirectly connected through an intermediary. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0072] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0073] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0074] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0075] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0076] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0077] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0078] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0079] 1 , an embodiment of the present disclosure provides a display device, wherein display device 1000 is a product having an image display function. For example, display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0080] Exemplarily, the display device 1000 can be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a camera view display (for example, a display of a rearview camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, an aircraft display, or any other product or component with a display function.

[0081] From the perspective of the light-emitting type of the display device 1000, the display device 1000 can be a liquid crystal display (LCD), or it can also be an organic light-emitting diode (OLED), a quantum dot electroluminescent display (QLED), or a mini / micro light-emitting diode (MLED). From the perspective of the form of the display device 1000, the display device 1000 can be a flat display, a curved display, or a foldable display. From the perspective of the shape of the display device 1000, the display device 1000 can be rectangular or circular. The embodiments of the present disclosure do not specifically limit this. The following uses a rectangular and flat liquid crystal display as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited to this, and any other display device can also be considered as long as the same technical concept is applied.

[0082] In some embodiments, referring to FIG2 , the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driving circuit board 1200 may also include other circuit structures, which are not listed here one by one. The driving circuit board 1200 is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition, which are not specifically limited here.

[0083] As shown in FIG2 , the display panel 1100 may include a plurality of sub-pixels P. The sub-pixel P may be understood as the smallest light-emitting unit in the display panel 1100. The sub-pixel P includes a pixel circuit 102. The plurality of sub-pixels P may be arranged in a plurality of rows and columns, wherein a plurality of sub-pixels arranged along a first direction X is referred to as a row of sub-pixels P, and a plurality of sub-pixels arranged along a second direction Y is referred to as a column of sub-pixels P. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular. The display panel 1100 may further include a gate driver on array (GOA) 103 and a source driver chip 104. The gate driver circuit 103 may be connected to the pixel circuits 102 of a row of sub-pixels P via scan signal lines GL. The source driver chip 104 may be connected to the pixel circuits 102 of a column of sub-pixels P via input signal lines DL, and transmit data signals to the pixel circuits 102 of the column of sub-pixels P.

[0084] In the case where the display device 1000 is a liquid crystal display device, referring to FIG3 , the display device 1000 may further include a backlight source 1300 disposed on the backlight side of the display panel 1100. For example, the backlight source 1300 may be a direct-lit backlight source or an edge-lit backlight source. The backlight source 1300 is configured to provide backlight for the display panel 1100, which is configured to adjust the amount of light passing through the display panel 1100 to display different grayscales.

[0085] Continuing to refer to FIG3 , the display panel 1100 is a liquid crystal display panel. In this case, the display panel 1100 may include an array substrate 100 and a package cover plate 200 (also referred to as a color filter substrate) arranged opposite to each other, and a liquid crystal layer 300 arranged between the array substrate 100 and the package cover plate 200. When the package cover plate 200 is a color filter substrate, the package cover plate 200 can provide packaging for the display panel 1100 and can also filter the light incident on the package cover plate 200 so that each sub-pixel emits light of a color (such as red, green, and blue), thereby enabling the display panel 1100 to achieve color display. Of course, the display panel 1100 may also include other structures. For example, the display panel 1100 may also include a first alignment film (not shown in the figure) arranged on the side of the array substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) arranged on the side of the package cover plate 200 close to the liquid crystal layer 300, etc. The embodiments of the present disclosure will not list them one by one.

[0086] It is understood that when the display device 1000 is an OLED display device or a QLED display device, the display panel may include an array substrate, a light-emitting device, and an encapsulation substrate that are stacked. In this case, the encapsulation substrate may be, for example, an encapsulation film. The type of display device and the structure of the display device disclosed herein are not limited thereto, and any other suitable display device may be considered.

[0087] In some embodiments, referring to FIG4 , the array substrate 100 may include a display area AA and a peripheral area BB arranged around the display area AA. The peripheral area BB includes a fan-out area (Fanout) BB1 located on one side of the display area AA and adjacent to the display area AA. That is, the fan-out area BB1 is an area in the peripheral area BB located on one side of the display area AA. The fan-out area BB1 is adjacent to one side edge of the display area AA, that is, the fan-out area BB1 is close to one side edge of the display area AA and coincides with the one side edge of the display area AA close to the fan-out area BB1. The fan-out area BB1 can be used to lead out signal lines (such as data lines, clock signal lines, power signal lines, etc.) of the display area and the peripheral area and bind them to a driving circuit board or a source driver chip. For example, as shown in FIG4 , the fan-out area BB1 is adjacent to the lower edge of the display area AA.

[0088] The source driver chip is used to transmit data signals to multiple data lines DL. To reduce the cost of the source driver IC, a multiplexer (MUX) circuit can be set in the fan-out area BB1 to reduce the number of output signals from the source driver chip, thereby reducing the cost of the source driver chip and the production cost of the display panel.

[0089] In the related art, an array substrate is provided, comprising a plurality of multiplexing circuits arranged along a first direction X. However, as the pixel density of a display panel 1100 increases, the pitch of the pixel circuits 102 in the first direction X becomes smaller and smaller. With the display area AA having the same size, the number of data lines DL included in the array substrate 100 increases, and the pitch between adjacent data lines DL becomes smaller and smaller. Limited by the wiring space of the multiplexing circuits, a single row of multiplexing circuits can no longer meet the demand for the increasing number of data lines DL.

[0090] To solve the above technical problems, an embodiment of the present disclosure provides an array substrate 100, as shown in FIG4 , wherein the array substrate 100 further includes a substrate 101 and a plurality of pixel circuits 102, a plurality of data lines DL, a plurality of multiplexing circuits 10, a plurality of input signal lines 20, a plurality of output signal line groups 30, a plurality of first gate lines 40, and a plurality of second gate line groups 50 disposed on the substrate 101. FIG4 only exemplarily illustrates a few pixel circuits 102.

[0091] A plurality of pixel circuits 102 are disposed in the display area AA. Furthermore, the plurality of pixel circuits 102 are arranged in a plurality of columns. The plurality of pixel circuits 102 are arranged along a first direction X. Each of the plurality of pixel circuits 102 includes a plurality of pixel circuits 102 arranged along a second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X and the second direction Y are perpendicular to each other.

[0092] The pixel circuit 102 includes multiple thin film transistors (TFTs) and at least one capacitor Cst. For example, the pixel circuit 102 can be a "3T1C" circuit, a "5T1C" circuit, or the like. The embodiments of the present disclosure are not limited thereto, and any other pixel circuits can also be considered, as long as the same technical concept is applied. "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to capacitor Cst, and the number before "C" refers to the number of capacitors Cst.

[0093] At least a portion of the plurality of data lines DL is disposed in the display area AA, and the plurality of data lines DL are arranged at intervals along the first direction X. The plurality of data lines DL extend along the second direction Y. One data line DL is connected to a column of pixel circuits 102 to transmit a data signal to the column of pixel circuits 102 connected to the data line DL.

[0094] Multiple multiplexing circuits 10 are provided in the fan-out area BB1. The multiplexing circuits 10 are arranged in multiple columns along a first direction X. In FIG4 , two multiplexing circuits 10 in a column are labeled 11. A column of multiplexing circuits 10 includes multiple multiplexing circuits 10 arranged along a second direction Y. As shown in FIG4 , the arrangement direction of the multiple multiplexing circuits 10 in a column can have a certain angle with the second direction. The multiplexing circuits 10 are further arranged in multiple rows along the second direction Y, with each row including multiple multiplexing circuits 10 arranged along the first direction X. Based on this, multiple rows of multiplexing circuits 10 can be provided within the fan-out area BB1, which helps increase the number of multiplexing circuits 10 within the fan-out area BB1, thereby increasing the number of input signal lines 20 and output signal lines 31, and increasing the number of data lines DL. This reduces the spacing between the data lines DL, thereby increasing the density of pixel circuits in the array substrate 100 and the pixel density of the display panel, thereby achieving a high pixel density of the display panel.

[0095] For example, a column may include 2, 3, 4, 8, or any other number of multiplexing circuits 10 arranged along the second direction Y. For example, as shown in FIG4 , a column may include 4 multiplexing circuits 10. Of course, the embodiments of the present disclosure are not limited thereto, as long as the same technical concept is adopted.

[0096] Multiple input signal lines 20 are disposed in the fan-out area BB1 and are located on a side of the multiplexing circuits 10 away from the display area AA. One input signal line 20 is connected to one multiplexing circuit 10. Exemplarily, the multiple input signal lines 20 are spaced apart along a first direction X and extend along a second direction Y. The input signal lines 20 are configured to transmit data signals required by the data lines DL.

[0097] Multiple output signal line groups 30 are provided in the fan-out area BB1, and the multiple output signal line groups 30 are located on a side of the multiplexing circuits 10 close to the display area AA. Each output signal line group 30 includes multiple output signal lines 31. The multiple output signal lines 31 included in one output signal line group 30 are connected to the same multiplexing circuit 10, and one output signal line 31 is connected to one data line DL. FIG. 4 illustrates an output signal line group 30 including two output signal lines 31, which should not be construed as limiting the present application. For example, an output signal line group 30 may also include three, four, or any other number of output signal lines 31.

[0098] A plurality of first gate lines 40 are arranged at fan-out area BB1, and are positioned at a side of a plurality of multiplexing circuits 10 away from display area AA.Each second gate line group 50 in a plurality of second gate line groups 50 all comprises a plurality of second gate lines 51, and a second gate line 51 is connected with a first gate line 40.A plurality of second gate lines 51 that a second gate line group 50 comprises are connected with a plurality of multiplexing circuits 10 of a row, and each multiplexing circuit 10 all is connected with a plurality of second gate lines 51 that a second gate line group 50 comprises.In other words, a plurality of multiplexing circuits 10 of a row share a plurality of second gate lines 51 of a second gate line group 50, and share a plurality of first gate lines 40 by the second gate line group 50. Based on this, there is no need to separately set a first gate line extending along the first direction X for each row of multiplexing circuits 10. This is beneficial to reducing the interval between two adjacent multiplexing circuits 10 along the second direction Y, and further beneficial to reducing the width of the fan-out area BB1 along the second direction, that is, it is beneficial to achieve a narrow frame for the array substrate 100.

[0099] As shown in Figure 4, the multiplexing circuit 10 is connected to an input signal line 20, multiple output signal lines 31 of an output signal line group 30, and multiple second gate lines 51 of a second gate line group 50, and an output signal line 31 can correspond to at least one second gate line 51. The multiplexing circuit 10 is configured to, under the control of a control signal from at least one second gate line 51 corresponding to an output signal line 31 in the multiple second gate lines 51, transfer the data signal from the input signal line 20 to the output signal line 31, and transfer it to the data line DL through the output signal line 31, and then transfer the data signal to a column of pixel circuits 102 connected to the data line DL. Exemplarily, an output signal line 31 can correspond to a second gate line 51, or an output signal line 31 can also correspond to two second gate lines 51.

[0100] In some embodiments, referring to FIG. 4 , any two adjacent multiplexing circuits 10 in the same column are staggered in the first direction X. That is, the two adjacent multiplexing circuits 10 are offset from each other in the first direction X. In this way, the multiple input signal lines 20 and the multiple output signal line groups 30 connected to the multiple multiplexing circuits 10 in the same column can have relatively sufficient wiring space in the first direction X, which is conducive to the wiring arrangement of the multiple input signal lines 20 and the multiple output signal line groups 30.

[0101] For example, two adjacent multiplexing circuits 10 may be partially staggered in the first direction X, that is, portions of the adjacent multiplexing circuits 10 are arranged relative to each other in the second direction Y (as shown in FIG4 ). Alternatively, two adjacent multiplexing circuits 10 may be completely staggered in the first direction X, that is, the projections of the adjacent multiplexing circuits 10 along the second direction Y do not overlap.

[0102] Among them, among any two adjacent multiplexing circuits 10 belonging to the same column, the multiplexing circuit 10 closer to the display area AA is offset toward the same side along the first direction X as the multiplexing circuit 10 farther away from the display area AA. In other words, the arrangement direction of the multiple multiplexing circuits 10 in a column has an angle with the second direction Y, and along the second direction Y, the multiple multiplexing circuits 10 in a column are tilted toward the same side of the first direction X in sequence. In this way, the multiple output signal line groups 30 connected to the multiple multiplexing circuits 10 in the same column can be arranged in sequence in the first direction X, and the spaces occupied by each of them will not overlap, which can effectively avoid wiring interference between the multiple output signal line groups 30 and is conducive to the uniform arrangement of the multiple output signal lines 31 included in the multiple output signal line groups 30 in the first direction X. In other words, it is conducive to the wiring arrangement of the multiple input signal lines 20 and the multiple output signal line groups 30.

[0103] For example, as shown in FIG4 , along the first direction X from left to right, there are a first column of multiplexing circuits 10, and among any two adjacent multiplexing circuits 10, the multiplexing circuit 10 closer to the display area AA is offset to the right along the first direction X compared to the multiplexing circuit 10 farther from the display area AA.

[0104] In some embodiments, as shown in FIG4 , two adjacent columns of multiplexing circuits 10 are symmetrically arranged along the first direction X. That is, among the multiple multiplexing circuits 10 belonging to two adjacent columns, a multiplexing circuit close to the display area AA is offset in the opposite direction along the first direction X compared to a multiplexing circuit far from the display area AA. This facilitates the wiring arrangement of the multiple input signal lines 20.

[0105] Exemplarily, from left to right along the first direction X, among any two adjacent multiplexing circuits 10 in the odd-numbered columns of multiplexing circuits 10, the multiplexing circuit 10 closer to the display area AA is offset to the right compared to the multiplexing circuit 10 farther from the display area AA; and among any two adjacent multiplexing circuits 10 in the even-numbered columns of multiplexing circuits 10, the multiplexing circuit 10 closer to the display area AA is offset to the left compared to the multiplexing circuit 10 farther from the display area AA. Alternatively, among any two adjacent multiplexing circuits 10 in the even-numbered columns of multiplexing circuits 10, the multiplexing circuit 10 closer to the display area AA is offset to the right compared to the multiplexing circuit 10 farther from the display area AA; and among any two adjacent multiplexing circuits 10 in the odd-numbered columns of multiplexing circuits 10, the multiplexing circuit 10 closer to the display area AA is offset to the left compared to the multiplexing circuit 10 farther from the display area AA.

[0106] For example, as shown in FIG4 , along the first direction X from left to right, among any two adjacent multiplexing circuits 10 in the first and third columns of multiplexing circuits 10, the multiplexing circuit 10 closer to the display area AA is offset to the right compared to the multiplexing circuit 10 farther from the display area AA; and among any two adjacent multiplexing circuits 10 in the second and fourth columns of multiplexing circuits 10, the multiplexing circuit 10 closer to the display area AA is offset to the left compared to the multiplexing circuit 10 farther from the display area AA.

[0107] In some embodiments, as shown in FIG4 , the angle α between the line L1 connecting the geometric centers of the orthographic projections of any two adjacent multiplexing circuits 10 in the same column on the substrate and the second direction Y is 4°≤α≤30°. This helps reduce the spacing between the two adjacent multiplexing circuits 10 in the first direction X, thereby maximizing the number of multiplexing circuits 10 within the fan-out area BB1, increasing the number of input signal lines 20 and output signal lines 31, and increasing the number of data lines DL to reduce the spacing between the data lines DL, thereby increasing the density of pixel circuits on the array substrate 100 and the pixel density of the display panel, thereby achieving a high pixel density of the display panel. For example, α can be 4°, 5°, 10°, 20°, 25°, or 30°, etc., which are not listed here.

[0108] In some embodiments, referring to FIG. 4 , the outline of the orthographic projection of the multiplexing circuit 10 on the substrate may be in the shape of a rectangle.

[0109] In some embodiments, as shown in FIG4 , any two adjacent multiplexing circuits 10 belonging to the same column have a spacing of D1 in the first direction X and a spacing of D2 in the second direction Y. The spacing between the two multiplexing circuits 10 in the first direction X can be understood as the spacing between the geometric centers of the orthographic projections of the two multiplexing circuits 10 on the substrate 101 in the first direction X. The spacing between the two multiplexing circuits 10 in the second direction Y can be understood as the spacing between the geometric centers of the orthographic projections of the two multiplexing circuits 10 on the substrate 101 in the second direction X. Wherein, D1, D2, and α satisfy: tanα=D2 / D1

[0110] In some embodiments, referring to FIG. 5 , a plurality of second gate lines 51 belonging to a second gate line group 50 include a plurality of first sub-lines 52 and a plurality of second sub-lines 53. The multiplexing circuit 10 includes a plurality of N-type transistors 11 and a plurality of P-type transistors 12. In this case, one output signal line 31 corresponds to two second gate lines 51. Under the control of one second gate line 51, one N-type transistor and one P-type transistor 12 transmit data signals from the input signal line to one output signal line 31.

[0111] The control electrodes of the plurality of N-type transistors 11 are respectively connected to the plurality of first sub-lines 52, the first electrodes of the plurality of N-type transistors 11 are respectively connected to the input signal line 20, and the second electrodes of the plurality of N-type transistors 11 are respectively connected to the plurality of output signal lines 31 of the output signal line group 30. Under the control of the first sub-line 52 connected to the control electrode of the N-type transistor 11, each N-type transistor 11 is configured to transmit a data signal from the input signal line 20 to the output signal line 31 connected to the N-type transistor 11, and further to the data line DL connected to the output signal line.

[0112] The control electrodes of the plurality of P-type transistors 12 are respectively connected to the plurality of second sub-lines 53, the first electrodes of the plurality of P-type transistors 12 are respectively connected to the input signal line 20, and the second electrodes of the plurality of P-type transistors 12 are respectively connected to the plurality of output signal lines 31 of the output signal line group 30. Under the control of the second sub-line 53 connected to the control electrode of the P-type transistor, each P-type transistor 12 is configured to transmit a data signal from the input signal line 20 to the output signal line 31 connected to the P-type transistor 12, and further to the data line DL connected to the output signal line.

[0113] The input signal line 20 connected to the multiplexing circuit 10 is simultaneously connected to the first electrodes of multiple N-type transistors 11 and multiple P-type transistors 12, and an output signal line 31 is simultaneously electrically connected to an N-type transistor 11 and a P-type transistor 12. In other words, the output signal line 31 is electrically connected to the output signal line 31 through an N-type transistor 11 and a P-type transistor 12, respectively. In this way, the N-type transistor 11 and the P-type transistor 12 connected to the same output signal line 31 are connected in parallel to form a complementary metal oxide semiconductor (CMOS) transmission gate. The CMOS transmission gate has a low on-resistance (several hundred ohms) and a high off-resistance (greater than 10 9 In this case, the CMOS transmission gate formed by the N-type transistor 11 and the P-type transistor 12 facilitates the transmission of data signals. For example, when the CMOS transmission gate is on, the data signal transmitted by the input signal line 20 can be transmitted to the output signal line 31 with minimal signal transmission loss. When the CMOS transmission gate is off, the off-resistance between the input signal line 20 and the output signal line 31 is extremely large, thereby preventing leakage current.

[0114] In some embodiments, the N-type transistor 11 and the P-type transistor 12 connected to the same output signal line 31 have the same conduction state, that is, the N-type transistor 11 and the P-type transistor 12 connected to the same output signal line 31 are turned on or turned off at the same time. It should be noted that the N-type transistor 11 and the P-type transistor 12 having the same conduction state does not mean that their on-resistance is the same, but rather that both are in the on or off state.

[0115] For example, when a data signal needs to be transmitted to the output signal line 31, the first sub-line 52 connected to the N-type transistor 11 transmits a high voltage signal to turn on the N-type transistor 11, and the second sub-line 53 connected to the P-type transistor 12 transmits a low voltage signal to turn on the P-type transistor 12. At this time, the data signal on the input signal line 20 is transmitted to the output signal line 31. When a data signal does not need to be transmitted to the output signal line 31, the first sub-line 52 connected to the N-type transistor 11 transmits a low voltage signal to turn off the N-type transistor 11, and the second sub-line 53 connected to the P-type transistor 12 transmits a high voltage signal to turn off the P-type transistor 12.

[0116] Of course, in some other examples, the conduction states of the N-type transistor 11 and the P-type transistor 12 connected to the same output signal line 31 may also be different. For example, in two adjacent frame periods, the N-type transistor 11 and the P-type transistor 12 connected to the same output signal line 31 are each turned on once. Of course, the control timing of the N-type transistor 11 and the P-type transistor 12 is not limited to this, and the embodiments of the present disclosure will not be listed one by one.

[0117] Exemplarily, the number of first sub-lines 52 included in a second gate line group 50, the number of N-type transistors 11 included in a multiplexing circuit 10, the number of P-type transistors 12 included in a multiplexing circuit 10, and the number of output signal lines 31 included in an output signal line group 30 are all equal. For example, as shown in FIG5 , the multiplexing circuit 10 includes three N-type transistors 11 and three P-type transistors 12. In this case, a second gate line group 50 includes three first sub-lines 52 and three second sub-lines 53, and an output signal line group 30 includes three output signal lines 31.

[0118] In some embodiments, referring to Figures 5 and 6 , an output signal line group 30 includes three output signal lines 31, and the multiplexing circuit 10 is connected to the three output signal lines 31. In this case, the multiplexing circuit 10 may include three N-type transistors 11 and three P-type transistors 12. The multiplexing circuit 10 also includes a P-type semiconductor layer 14, an N-type semiconductor layer 13, a source pattern 15, and three drain patterns 16.

[0119] The P-type semiconductor layer 14 includes a first semiconductor pattern 141 and a second semiconductor pattern 142 spaced apart along a first direction X. One of the first semiconductor pattern 141 and the second semiconductor pattern 142 is used to form a channel structure for one P-type transistor 12, and the other is used to form a channel structure for two P-type transistors 12. The following describes embodiments of the present disclosure using the example of the first semiconductor pattern 141 forming a channel structure for two P-type transistors 12 and the second semiconductor pattern 142 forming a channel structure for one P-type transistor 12.

[0120] The N-type semiconductor layer 13 includes a third semiconductor pattern 131 and a fourth semiconductor pattern 132 spaced apart along the first direction X. One of the third semiconductor pattern 131 and the fourth semiconductor pattern 132 is used to form a channel structure for one N-type transistor 11, and the other is used to form a channel structure for two N-type transistors 11. The following describes embodiments of the present disclosure using the example of the third semiconductor pattern 131 forming the channel structure for two N-type transistors 11 and the fourth semiconductor pattern 132 forming the channel structure for one N-type transistor 11.

[0121] The source pattern 15 includes a first source electrode 151, a second source electrode 152, and a first connecting portion 153. The first source electrode 151 and the second source electrode 152 are spaced apart along the first direction X and both extend along the second direction Y. The first source electrode 151 is connected to the first semiconductor pattern 141 and the third semiconductor pattern 131 to form the first electrodes (e.g., sources) of the two P-type transistors 12 and the two N-type transistors 11. The second source electrode 152 is connected to the second semiconductor pattern 142 and the fourth semiconductor pattern 132 to form the first electrodes of the one P-type transistor 12 and the one N-type transistor 11.

[0122] The first connecting portion 153 is connected to the mutually adjacent ends of the first source 151 and the second source 152 (ends close to the input signal line 20), and is also connected to the input signal line 20. The first connecting portion 153 is used to connect the first source 151 and the second source 152 to each other, and to connect the first source 151 and the second source 152 to the input signal line 20. In other words, the first electrodes of the three P-type transistors 12 and the three N-type transistors 11 included in the multiplexing circuit 10 are connected to each other, that is, the three P-type transistors 12 and the three N-type transistors 11 have a common source.

[0123] Three drain patterns 16 are spaced apart along the first direction X and extend along the second direction Y. Two of the drain patterns 16 are located on either side of the first source 151 along the first direction X and are connected to the first semiconductor pattern 141 and the third semiconductor pattern 131. Another drain pattern 16 is arranged side by side with the second source 152 along the first direction X and is connected to the second semiconductor pattern 142 and the fourth semiconductor pattern 132. A P-type transistor 12 and an N-type transistor 11 share one drain pattern 16, and one drain pattern 16 is connected to one output signal line 31. Each drain pattern 16 is used to form the second electrode (e.g., drain) of one P-type transistor 12 and one N-type transistor 11. Compared to arranging the three P-type transistors 12 and the three N-type transistors 11 at intervals along the first direction X, the above-mentioned embodiment of the present disclosure provides that the three P-type transistors 12 and the three N-type transistors 11 are arranged at intervals along the second direction Y, which is beneficial for reducing the sizes of the three P-type transistors 12 and the three N-type transistors 11 along the first direction X. As a result, as many multiplexing circuits 10 as possible can be arranged within the fan-out area BB1, thereby improving the density of the pixel circuits of the array substrate 100 and the pixel density of the display panel, thereby achieving a high pixel density of the display panel.

[0124] In Figures 5 and 6, different fill patterns are used only to represent different structures and are not used to define the film layers in which the corresponding structures are located. For example, the P-type semiconductor layer 14 and the N-type semiconductor layer 13 are located in different film layers, the input signal line and the second gate line group 50 are located in a film layer (such as a gate conductive layer), and the first gate line 40, the output signal line 31, the source pattern 15, and the drain pattern 16 are located in a film layer (such as a source-drain conductive layer).

[0125] In some embodiments, as shown in Figures 5 and 6, the size of the N-type transistor 11 is the same as the size of the P-type transistor 12, or in other words, the width-to-length ratio of the N-type transistor 11 is the same as the width-to-length ratio of the P-type transistor 12, so that the on-resistance and off-resistance of the N-type transistor 11 and the P-type transistor 12 are respectively equal or approximately equal.

[0126] Continuing with FIG. 5 , the multiple N-type transistors 11 and the multiple P-type transistors 12 belonging to the same multiplexing circuit 10 are arranged at intervals along the second direction Y. Furthermore, along the first direction X, the ends of the multiple N-type transistors 11 and the multiple P-type transistors 12 are aligned. That is, the orthographic projections of the multiple N-type transistors 11 and the multiple P-type transistors 12 of the same multiplexing circuit 10 along the second direction Y overlap. For example, the multiple N-type transistors 11 of the same multiplexing circuit 10 are further away from the display area AA than the multiple P-type transistors 12. This helps reduce the size of a single multiplexing circuit 10 in the first direction X, facilitates the placement of as many multiplexing circuits 10 as possible within the fan-out area BB1, increases the number of input signal lines 20 and output signal lines 31, and increases the number of data lines DL to reduce the spacing between the data lines DL. This increases the density of the pixel circuits on the array substrate 100, thereby improving the pixel density of the display panel and achieving a high pixel density.

[0127] In some embodiments, as shown in FIG5 , any two adjacent multiplexing circuits 10 belonging to the same column are spaced apart in the first direction X and in the second direction Y. In other words, the transistors (N-type transistors and P-type transistors) included in the two multiplexing circuits 10 are spaced apart in the first direction X and the second direction Y. This avoids the risk of interference between adjacent multiplexing circuits 10 and helps increase the wiring space for multiple multiplexing circuits 10 in a column, increases the spacing between adjacent signal lines (input signal lines and output signal lines, etc.), and reduces the risk of signal interference between adjacent signal lines.

[0128] In other embodiments, referring to FIG. 7 , two adjacent multiplexing circuits 10 in the same column are spaced apart along the first direction X, and at least portions of the two adjacent multiplexing circuits 10 in the same column are arranged relative to each other along the first direction X. In this way, portions of the two multiplexing circuits 10 share a space in the second direction Y, which is beneficial for reducing the size of the multiple multiplexing circuits 10 in a column in the second direction Y, and is beneficial for reducing the size of the fan-out area BB1 in the second direction Y, which is beneficial for achieving a narrow frame of the array substrate 100.

[0129] Continuing with FIG7 and FIG8 , the plurality of N-type transistors 11 and the plurality of P-type transistors 12 in two adjacent multiplexing circuits 10 in the same column and closest to each other are arranged opposite each other along the first direction X. The N-type transistors 11 in the two adjacent multiplexing circuits 10 in the same column have a third interval D3 in the second direction Y, and the plurality of P-type transistors in the two adjacent multiplexing circuits 10 in the same column have a fourth interval D4 in the second direction Y. In this way, the first sub-line 52 can be arranged within the third interval D3, and the second sub-line 53 can be arranged within the fourth interval D4, which facilitates the arrangement of the first sub-line 52 and the second sub-line 53.

[0130] Exemplarily, the third interval D3 may be equal to the fourth interval D4.

[0131] For example, as shown in Figures 7 and 8, when the multiple N-type transistors 11 included in the multiplexing circuit 10 are farther away from the display area than the multiple P-type transistors, in two adjacent multiplexing circuits 10 in the same column, the P-type transistor 12 included in the multiplexing circuit 10 away from the display area AA is arranged opposite to the N-type transistor 11 included in the multiplexing circuit 10 close to the display area AA in the first direction X.

[0132] In some embodiments, referring to FIG5 and FIG7 , the first sub-line 52 includes a plurality of first extension segments 521 and a plurality of second extension segments 522. The plurality of first extension segments 521 extend along the second direction Y, and at least one first extension segment 521 is configured to form the gate of an N-type transistor. The plurality of second extension segments 522 extend along the first direction X, and along the second direction X, the two ends of the second extension segments 522 are respectively connected to a first extension segment 521. In other words, the first sub-line 52 includes zigzag segments, and the first sub-line 52 includes alternating first extension segments 521 and second extension segments 522. The first extension segments 521 extend along the second direction Y and are configured to form the gate of the N-type transistor 11. The second extension segments 522 extend along the first direction X and are used to connect adjacent first extension segments 521. Illustratively, the orthographic projection of the second extension section 522 on the substrate 101 is located within the interval between the orthographic projections of the adjacent N-type transistor 11 and P-type transistor 12 on the substrate. In this way, the influence of the second extension section 522 on the N-type transistor 11 and the P-type transistor 12 can be reduced.

[0133] Continuing with reference to Figures 5 and 7, similar to the first sub-line 52, the second sub-line 53 includes a plurality of third extension segments 531 and a plurality of fourth extension segments 532. The plurality of third extension segments 531 all extend along the second direction Y, and at least one third extension segment 531 is configured to form the gate of the P-type transistor 12. The plurality of fourth extension segments 532 all extend along the first direction X, and along the second direction Y, the ends of the fourth extension segments 532 are respectively connected to a third extension segment 531. In other words, the second sub-line 53 is a zigzag line, and the second sub-line 53 includes alternating third extension segments 531 and fourth extension segments 532. The third extension segments 531 extend along the second direction Y and are configured to form the gate of the P-type transistor 12. The fourth extension segments 532 extend along the first direction X and are used to connect adjacent third extension segments 531. Illustratively, the orthographic projection of the fourth extension section 532 on the substrate 101 is located within the gap between the adjacent N-type transistor 11 and the P-type transistor 12, thereby reducing the impact of the fourth extension section 532 on the N-type transistor 11 and the P-type transistor 12. Illustratively, the orthographic projection of the fourth extension section 532 on the substrate 101 is located within the gap between the orthographic projections of the adjacent N-type transistor 11 and the P-type transistor 12 on the substrate, thereby reducing the impact of the fourth extension section 532 on the N-type transistor 11 and the P-type transistor 12.

[0134] 7 and 8 , in some embodiments, an output signal line group 30 includes two output signal lines 31, and the multiplexing circuit 10 is connected to the two output signal lines 31. In this case, the multiplexing circuit 10 may include two N-type transistors 11 and two P-type transistors 12. The multiplexing circuit 10 includes an N-type semiconductor layer 13, a P-type semiconductor layer 14, a source pattern 15, and three drain patterns 16.

[0135] The N-type semiconductor layer 13 includes a sixth semiconductor pattern 133. The P-type semiconductor layer 14 includes a fifth semiconductor pattern 143. The sixth semiconductor pattern 133 and the fifth semiconductor pattern 143 are arranged along a second square Y. The fifth semiconductor pattern 143 is used to form a channel structure for the two P-type transistors 12, and the sixth semiconductor pattern 133 is used to form a channel structure for the two N-type transistors 11.

[0136] The source pattern 15 extends along the second direction Y and is connected to the fifth semiconductor pattern 143, the sixth semiconductor pattern 133, and the input signal line 20. For example, at least one source pattern 15 may include a main portion 154 and a fourth connecting portion 155. The main portion 154 extends along the second direction Y and is connected to the fifth semiconductor pattern 143 and the sixth semiconductor pattern 133 to form the first electrodes (e.g., sources) of the two P-type transistors 12 and the two N-type transistors 11. The fourth connecting portion 155 may extend along the first direction X, with one end connected to the main portion 154 and the other end connected to the input signal line 20.

[0137] The two drain patterns 16 are respectively located on both sides of the source pattern 15 along the first direction X, and the two drain patterns 16 are both connected to the fifth semiconductor pattern 143 and the sixth semiconductor pattern 133. One drain pattern 16 is used to form the drain of a P-type transistor 12 and an N-type transistor 11, and one drain pattern 16 is connected to an output signal line 31.

[0138] In some embodiments, referring to FIG9 , multiple N-type transistors 11 and multiple P-type transistors 12 belonging to the same multiplexing circuit 10 are arranged in an alternating manner along a second direction Y. The multiple N-type transistors 11 and the multiple P-type transistors 12 of the multiplexing circuit 10 are staggered in a first direction X. That is, the orthographic projections of the multiple N-type transistors 11 and the multiple P-type transistors 12 of the same multiplexing circuit 10 along the second direction Y overlap. In other words, along the second direction Y, portions of the multiple N-type transistors 11 and portions of the multiple P-type transistors 12 of the same multiplexing circuit 10 are arranged opposite each other. For example, as shown in FIG9 and FIG10 , along the first direction X, the left sides of the multiple N-type transistors 11 extend beyond the left sides of the multiple P-type transistors 12, and the right sides of the multiple P-type transistors 12 extend beyond the right sides of the multiple N-type transistors 11.

[0139] Continuing with FIG. 9 , along the second direction Y, portions of the multiple N-type transistors 11 and portions of the multiple P-type transistors 12 of the same multiplexing circuit 10 are arranged opposite each other. This helps reduce the size of a single multiplexing circuit 10 in the first direction X, facilitates disposing as many multiplexing circuits 10 as possible within the fan-out area BB1, increases the density of pixel circuits on the array substrate 100, and improves the pixel density of the display panel, thereby achieving a high pixel density for the display panel.

[0140] As shown in FIG9 , portions of two adjacent multiplexing circuits 10 in the same column are arranged relative to each other along the second direction Y. In other words, the orthographic projections of the two adjacent multiplexing circuits 10 along the second direction Y overlap. This helps reduce the overall size of the multiplexing circuits 10 in a column in the first direction X, facilitates the placement of as many multiplexing circuits 10 as possible within the fan-out area BB1, increases the density of pixel circuits on the array substrate 100, and improves the pixel density of the display panel, enabling the display panel to achieve a high pixel density.

[0141] Continuing with FIG. 9 , two adjacent multiplexing circuits 10 belonging to the same column have a plurality of N-type transistors 11 and a plurality of P-type transistors 12 that are closest to each other separated along a first direction X. For example, the plurality of P-type transistors 12 included in a multiplexing circuit 10 located farther from the display area AA are separated from the plurality of N-type transistors 11 included in the multiplexing circuit 10 located closer to the display area AA in the first direction X. Portions of the plurality of N-type transistors 11 of the two adjacent multiplexing circuits 10 belonging to the same column are arranged opposite each other along a second direction Y, and the plurality of P-type transistors 12 of the two adjacent multiplexing circuits 10 belonging to the same column partially overlap along the second direction Y. In this way, the first sub-line 52 is advantageously kept away from multiple P-type transistors 12, and the second sub-line 53 is advantageously kept away from multiple N-type transistors 11. That is, the above design is advantageous for the wiring arrangement of multiple second gate lines 50, and can reduce the size of multiple multiplexing circuits 10 in a column in the first direction X, which is advantageous for arranging as many multiplexing circuits 10 as possible in the fan-out area BB1, thereby increasing the density of the pixel circuits of the array substrate 100, and increasing the pixel density of the display panel, so that the display panel can achieve a high pixel density.

[0142] In some embodiments, as shown in FIG9 , the first sub-line 52 includes multiple fifth extension segments 523 and multiple sixth extension segments 524. Each of the multiple fifth extension segments 523 extends along the second direction Y, with each fifth extension segment 523 forming the gate of an N-type transistor. The multiple sixth extension segments 524 form an angle with the first direction X, with each end of the sixth extension segment 524 connected to two fifth extension segments 523, respectively. In other words, the first sub-line 52 includes a zigzag segment and includes multiple fifth extension segments 523 and multiple sixth extension segments 524 alternately connected. The fifth extension segments 523 extend along the second direction Y and form the gates of the N-type transistor 11. The sixth extension segment 524 forms an angle with the first direction X and connects adjacent fifth extension segments 523. For example, the orthographic projection of the sixth extension segment 524 on the substrate 101 is located within the gap between the adjacent N-type transistor 11 and the adjacent P-type transistor 12, thereby reducing the impact of the sixth extension segment 524 on the N-type transistor 11 and the adjacent P-type transistor 12.

[0143] Continuing with FIG9 , similar to the first sub-line 52 , the second sub-line 53 includes a plurality of seventh extension segments 533 and a plurality of eighth extension segments 534 . The plurality of seventh extension segments 534 extend along the second direction Y, and each seventh extension segment 534 forms the gate of a P-type transistor 12 . The plurality of eighth extension segments 534 form an angle with the first direction X, and the two ends of an eighth extension segment 534 are respectively connected to a seventh extension segment 533 . In other words, the second sub-line 53 includes folded line segments, and the second folded line 53 includes a plurality of seventh extension segments 533 and a plurality of eighth extension segments 534 that are alternately connected. The seventh extension segments 533 extend along the second direction Y and form the gate of the P-type transistor 12. The eighth extension segments 534 form an angle with the first direction X and are used to connect adjacent seventh extension segments 533 . Illustratively, the orthographic projection of the eighth extension segment 534 on the substrate 101 is located in the interval between the adjacent N-type transistor 11 and P-type transistor 12 , which can reduce the impact of the sixth extension segment 524 on the N-type transistor 11 and the P-type transistor 12 .

[0144] As shown in Figures 9 and 10, one output signal line group 30 includes four output signal lines 31, and the multiplexing circuit 10 is connected to the four output signal lines 31. In this case, the multiplexing circuit 10 may include four N-type transistors 11 and four P-type transistors 12. The multiplexing circuit 10 includes a P-type semiconductor layer 14, an N-type semiconductor layer 13, a source pattern 15, and four drain patterns 16.

[0145] The P-type semiconductor layer 14 includes a seventh semiconductor pattern 144 and an eighth semiconductor pattern 145 spaced apart along the first direction X. The seventh semiconductor pattern 144 and the eighth semiconductor pattern 145 are each configured to form a channel structure for two P-type transistors 12. The N-type semiconductor layer 13 includes a ninth semiconductor pattern 134 and a tenth semiconductor pattern 135 spaced apart along the first direction X. The ninth semiconductor pattern 134 and the tenth semiconductor pattern 135 are each configured to form a channel structure for two N-type transistors 11. Exemplarily, the seventh semiconductor pattern 144 and the eighth semiconductor pattern 145 have the same size and shape, and the ninth semiconductor pattern 134 and the tenth semiconductor pattern 135 have the same size and shape.

[0146] The source pattern 15 includes a third source electrode 156, a fourth source electrode 157, and a second connecting portion 158. The third source electrode 156 and the fourth source electrode 157 are spaced apart along the first direction X. The third source electrode 156 is connected to the seventh semiconductor pattern 144 and the ninth semiconductor pattern 135, and the fourth source electrode 157 is connected to the eighth semiconductor pattern 144 and the tenth semiconductor pattern 135. The third source electrode 156 and the fourth source electrode 157 are used to form the first electrodes (e.g., sources) of the P-type transistor 12 and the N-type transistor. The second connecting portion 158 is connected to the adjacent ends (the upper ends in FIG. 7 ) of the third source electrode 156 and the fourth source electrode 157 and is connected to the input signal line 20. The third source electrode 156 and the fourth source electrode 157 are connected as a whole by the second connecting portion 158 and are both connected to the input signal line 20. The source pattern 15 is used to form a common source for the four P-type transistors 12 and the four N-type transistors 11.

[0147] Four drain patterns 16 are arranged at intervals along the first direction X. Two drain patterns 16 are located on either side of the third source 156 along the first direction X and are connected to the seventh semiconductor pattern 144 and the ninth semiconductor pattern 134. The other two drain patterns 16 are located on either side of the fourth source 157 along the first direction X and are connected to the eighth semiconductor pattern 145 and the tenth semiconductor pattern 135. One drain pattern 16 is used to form the drain of one P-type transistor 12 and one N-type transistor 11, and is connected to one output signal line 31.

[0148] In some embodiments, the channel length (dimension along the second direction Y) of the N-type transistor 11 and the P-type transistor 12 is L. The source and drain width (dimension along the first direction X) of the N-type transistor 11 and the P-type transistor 12 is W. SD A multiplexing circuit 10 is connected to M output signal lines 31, and a column of multiplexing circuits 10 includes N multiplexing circuits 10. The distance between two adjacent pixel circuits 102 along the first direction X is P. Pixel The distance between two adjacent pixel circuits 102 in the display area AA along the first direction X can also be understood as the distance between adjacent sub-pixels P, and the distance between two adjacent data lines DL. In the area where the multiplexing circuit 10 is located in the fan-out area BB1 (hereinafter referred to as: MUX area), the width of the output signal line 31 in the first direction X is W data The interval between two adjacent output signal lines 31 is S data Among them, L, W SD , M, N, P Pixel 、W data and S data Meets: 2MNP pixel =2[ML+(M+1)W SD ]+2MN(W data+S data )+R design (Formula 1)

[0149] In the above formula 1, R design is the design redundancy, R design The value range is ±5μm. design It reflects the width of the multiplexing circuit 10 along the first direction X and the distance between the transistor (P-type transistor or N-type transistor) and the output signal line 31 in the first direction X, as well as the pitch between the data lines DL in the display area AA and the difference between the pitch between the output signal lines 31 in the area where the multiplexing circuit 10 is set.

[0150] It should be noted that the spacing between adjacent data lines DL in the display area AA is generally equal to the spacing between the pixel circuits 102 along the first direction X, and is generally greater than the spacing between the output signal lines 31 in the area where the multiplexing circuit 10 is set (hereinafter referred to as the MUX area). Moreover, the spacing of the pixel circuits 102 depends on the pixel density (Pixels Per Inch, abbreviated as: PPI) of the display panel. Currently, in liquid crystal display devices, the spacing of sub-pixels is generally greater than or equal to 3μm. In the fan-out area BB1, the width and spacing of the output signal lines 31 can reach the current process limit of 2μm to 3μm. Based on this, the above-mentioned design redundancy R design It is the difference between the spacing of the pixel circuits 102 in the display area AA and the spacing of the output signal lines 31 in the MUX area, minus the redundant part after designing the transistors and the spacing between the transistors of the multiplexer circuit 10, that is, the following formula 2. design =2MNP pixel -2MN(W data +S data )-2[ML+(M+1)W SD ] (Formula 2)

[0151] By transforming the above formula 1 and formula 2, we can get:

[0152] The above formula 3 can be approximately obtained:

[0153] The above formula 4 can be transformed into:

[0154] Since the pitch P of the sub-pixels P in the display area pixel (the spacing between pixel circuits in the first direction X) will not be less than the spacing (W data +S data ). (L+(1+1 / M)W SD) is the average length of a transistor in the multiplexing circuit 10. The resolution of the display panel As can be seen from the above, in a high PPI display device, the pitch P of the sub-pixels P pixel Based on this, in the fan-out area BB1, the line width and spacing of the output signal line 31 need to be made smaller (even approaching the process limit) to meet the demand for high pixel density.

[0155] The above formula 5 can also be obtained:

[0156] In the above formula 6, A is the number of sources included in a multiplexing circuit 10. For example, when the value of M is 2, the value of A is 1. When the value of M is 3 or 4, the value of A is 2 (at least two transistors share a common source). Based on this, In general, the channel length L of the transistor of the multiplexing circuit 10 is equal to the source-drain width W of the transistor. SD 1.5 to 1.6 times, that is, L = (1.5 to 1.6) W SD Based on this, we can approximate:

[0157] as well as:

[0158] And by the above formula 8 and It can be approximated as follows:

[0159] The above formula 9 can be used to derive the approximate relationship between the number of multiplexer circuits 10 included in a column of multiplexer circuits 10 and the resolution of the display panel, and the number of rows of the multiplexer circuits 10 can be designed based on the above formula 9.

[0160] In some embodiments of the present disclosure, the width-to-length ratio of the N-type transistor 11 and the P-type transistor 12 is W / L, where W / L is ≥ 38 / 7, to improve the charging capability of the N-type transistor 11 and the P-type transistor 12 and reduce the delay of signal transmission in the multiplexing circuit 10. Exemplarily, the width-to-length ratio W / L of the N-type transistor 11 and the P-type transistor 12 is 38 μm / 7 μm.

[0161] The source-drain width W of the N-type transistor 11 and the P-type transistor 12 SD ≤5μm, illustratively, the source-drain width W of the N-type transistor 11 and the P-type transistor 12 SD It can be 5 μm, 4.5 μm, 4 μm or 3 μm, etc., which are not listed here one by one. In this way, it is beneficial to reduce the size of the multiplexing circuit 10 along the first direction X, and to improve the pixel density of the display panel.

[0162] The distance between two adjacent pixel circuits 102 along the first direction X is P Pixel ≤7.2μm, that is, the pitch of the sub-pixels of the display panel is ≤7.2μm, and in the display area, the pitch between adjacent data lines DL is ≤7.2μm. For example, the pitch P between two adjacent pixel circuits 102 along the first direction X is Pixel It can be 7.2 μm, 7 μm, 5 μm or 3 μm, etc., and the embodiments of the present disclosure do not specifically limit this.

[0163] In the fan-out area BB1, the line width W of the output signal line 31 is data ≤2μm, illustratively, the line width W of the output signal line 31 data The spacing S between adjacent output signal lines 31 is 2 μm, 1.9 μm or 1.8 μm, etc., which is not specifically limited in the embodiments of the present disclosure. data ≤3.25 μm, illustratively, the interval S between adjacent output signal lines 31 data It can be 3.25μm, 3μm or 2.5μm, etc., which are not listed here one by one.

[0164] In some embodiments, the width of the input signal line 20 along the first direction X is W1, where W1 is ≤ 2.5 μm; and / or the interval between two adjacent input signal lines 20 along the first direction X is W2, where W2 is ≤ 7.2 μm. For example, the width W1 of the input signal line 20 along the first direction X can be 2.5 μm, 2.3 μm, 2 μm, or 1.5 μm, and the interval W2 between two adjacent input signal lines 20 along the first direction X can be 7.2 μm, 7 μm, 6.5 μm, or 5 μm, etc.

[0165] In other embodiments, referring to FIG. 11 , two adjacent multiplexing circuits 10 in the same column are aligned at both ends along the first direction X. That is, the two adjacent multiplexing circuits 10 are arranged along the second direction Y, and their projections along the second direction Y overlap. This helps further reduce the size of the multiple multiplexing circuits 10 in a column along the first direction X, thereby allowing for as many multiplexing circuits 10 as possible to be arranged within the fan-out area BB1. This helps improve the pixel density of the display panel, enabling the display panel to achieve a high pixel density. For example, the display panel can achieve a pixel density greater than 1000 PPI.

[0166] In some embodiments, as shown in FIG11 , a column includes two multiplexing circuits 10, and one multiplexing circuit 10 includes a plurality of transistors T10. The plurality of transistors T10 may be P-type transistors or N-type transistors, and the plurality of transistors T10 may be transistors of the same type, so as to simplify the preparation process of the array substrate. The plurality of transistors T10 included in the multiplexing circuit 10 are arranged in a plurality of rows along the second direction Y, and each row includes at least one transistor T10. In this way, the size of the multiplexing circuit 10 in the first direction X can be further reduced, and then as many multiplexing circuits 10 as possible can be set in the fan-out area BB1, which is conducive to improving the pixel density of the display panel and enabling the display panel to achieve a high pixel density. For example, the display panel can achieve a pixel density greater than 1200 PPI.

[0167] Exemplarily, the number of transistors T10 included in the multiplexing circuit 10 is the same as the number of output signal lines 31 connected to the multiplexing circuit 10. For example, as shown in FIG11 , one multiplexing circuit 10 includes three transistors, and one multiplexing circuit 10 is connected to three output signal lines 31. The three transistors may all be P-type transistors or may all be N-type transistors.

[0168] In some embodiments, referring to FIG11 , an output signal line group 30 includes three output signal lines 31, a multiplexing circuit 10 is connected to the three output signal lines 31, and the multiplexing circuit 10 includes three transistors T10. The three transistors T10 are arranged in a first row and a second row along a second direction Y and near the display area AA (from top to bottom in FIG11 ), with the first row including two transistors T10 and the second row including one transistor T10. In this way, signal lines (such as the input signal line 20, the second gate line 51, and the output signal line 31) can be arranged on one side of a transistor T10 in the second row. This helps reduce the space occupied by the signal lines in the first direction X, improves the space utilization of the fan-out area BB1, and further reduces the size of the multiplexing circuit 10 in the first direction X. This allows for as many multiplexing circuits 10 as possible to be arranged within the fan-out area BB1, which helps improve the pixel density of the display panel and achieves a high pixel density. For example, the display panel can achieve a pixel density greater than 1200 PPI.

[0169] For example, as shown in FIG11 , the three transistors T10 included in the multiplexing circuit 10 of the first row are a first transistor T11, a second transistor T12, and a third transistor T13, and the three transistors T10 included in the multiplexing circuit 10 of the second row are a fourth transistor T14, a fifth transistor T15, and a sixth transistor T16. The gates of the first transistor T11 and the fourth transistor T14 are connected to the same second gate line 51, the gates of the second transistor T12 and the fifth transistor T15 are connected to the same second gate line 51, and the gates of the third transistor T13 and the sixth transistor T16 are connected to the same second gate line 51. The first electrode (e.g., source) of the first transistor T11, the second transistor T12, and the third transistor T13 are shared, and the second electrodes (e.g., drains) of the first transistor T11, the second transistor T12, and the third transistor T13 are respectively connected to an output signal line 31. The first electrodes of the fourth transistor T14 , the fifth transistor T15 and the sixth transistor T16 are shared, and the second electrodes of the fourth transistor T14 , the fifth transistor T15 and the sixth transistor T16 are respectively connected to one output signal line 31 .

[0170] Continuing with FIG11 , the six data lines DL connected to the two multiplexing circuits 10 in the same column are divided, from left to right, into: a first data line DL1, a second data line DL2, ..., a fifth data line DL5, and a sixth data line DL6. In one example, as shown in FIG11 , the first transistor T11 can be connected to the first data line DL1 via an output signal line 31, the second transistor T12 can be connected to the fifth data line DL5 via an output signal line 31, and the third transistor T13 can be connected to the third data line DL3 via an output signal line 31. The fourth transistor T14 can be connected to the fourth data line DL4 via an output signal line 31, the fifth transistor T15 can be connected to the second data line DL2 via an output signal line 31, and the sixth transistor T16 can be connected to the sixth data line DL6 via an output signal line 31. Of course, the multiplexing circuit 10 can also be connected to the six data lines DL in other ways, and the embodiments of the present disclosure are not specifically limited thereto, as long as the same technical principles are adopted.

[0171] It should be noted that, as shown in FIG11 , the input signal line 20, the output signal line 31, and the second gate line 51, etc., can be set in different conductive layers. That is, for any signal line, its routing can cross different conductive layers. This is beneficial to the spatial arrangement of the signal lines and can avoid signal interference between signal lines. For example, in FIG11 , different fill patterns can mean different conductive layers. Of course, the embodiments of the present disclosure are not limited to the wiring method shown in FIG11 , and any other suitable wiring method can be considered, as long as the same technical ideas are adopted.

[0172] In some embodiments, the number of first gate lines 40 included in the array substrate 100 is the same as the number of transistors T10 included in one multiplexing circuit 10. For example, as shown in FIG11 , when the multiplexing circuit 10 includes three transistors T10, the array substrate 100 may include three first gate lines 40, the gate of each transistor T10 (each second gate line 51) is connected to one first gate line 40, and the multiplexing circuits 10 in different columns are all connected to the three first gate lines 40.

[0173] In other embodiments, referring to FIG12 , a multiplexing circuit 10 is connected to M output signal lines 31, that is, the multiplexing circuit 10 includes M transistors T10 for transmitting data signals to M data lines DL. Wherein, M≥2, illustratively, the value of M can be 2, 3 or 4, of course, M can also have other values, and the embodiments of the present disclosure are no longer listed one by one. The array substrate 100 includes (Q×M) first gate lines 40, and the (Q×M) first gate lines 40 are divided into Q groups, one group includes M first gate lines 40, and O≥2. Exemplarily, the value of Q can be 2 or 3, of course, M can also have other values, and the embodiments of the present disclosure are no longer listed one by one.

[0174] One second gate line group 50 is connected to a group of first gate lines 40, and along the first direction X, multiple second gate line groups 50 are alternately connected to Q groups of first gate lines 40. As the pixel density of the display panel increases, the number of multiplexing circuits 10 required to drive the first gate lines 40 also increases. The multiple second gate line groups 50 are alternately connected to Q groups of first gate lines 40, which helps to reduce the number of multiplexing circuits 10 driven by each first gate line 40, that is, reduces the load of the first gate line 40 and reduces the voltage drop of the first gate line 40.

[0175] For example, referring to FIG. 12 , M is 3, meaning the multiplexing circuit 10 is connected to three output signal lines 31 and includes three transistors T10. Q is 2, so the array substrate 100 includes (Q×M) first gate lines 40, meaning the array substrate 100 includes 2×3=6 first gate lines 40. Three first gate lines 40 form a group, with the three first gate lines 40 closest to the multiplexing circuit 10 forming a group, and the three first gate lines 40 farther from the multiplexing circuit 10 forming a group. The two second gate line groups 50 connected to the multiplexing circuits 10 in adjacent columns are connected to the two groups of first gate lines 40, respectively. For example, the three first gate lines 40 close to the multiplexing circuit 10 are marked as the first group 401, and the three first gate lines 40 far away from the multiplexing circuit 10 are marked as the second group 402. The second gate lines 51 included in the second gate line group 50 connected to the odd-numbered column multiplexing circuit 10 are all connected to the three first gate lines 40 of the first group 401, and the second gate lines 51 included in the second gate line group 50 connected to the even-numbered column multiplexing circuit 10 are all connected to the three first gate lines 40 of the second group 402. Of course, the embodiments of the present disclosure are not limited to this. For example, the values ​​of M and Q can also be other values, and multiple second gate line groups 50 can also be connected to multiple groups of first gate lines 40 in other corresponding ways, as long as the same technical ideas are adopted.

[0176] In other embodiments, referring to FIG. 13 , a multiplexing circuit 10 is connected to two output signal lines 31 , and the multiplexing circuit 10 includes two transistors T10 . The two transistors are arranged in two rows along the second direction Y, with each row including one transistor T10 . In this way, the transistors T10 and the signal lines (the signal lines for driving the two multiplexing circuits 10 in a column) can be arranged side by side in the first direction X, which can further improve the space utilization of the fan-out area BB and reduce the size of the two multiplexing circuits 10 in a column in the first direction X. This facilitates the arrangement of as many multiplexing circuits 10 as possible within the fan-out area BB1, thereby improving the pixel density of the display panel and enabling the display panel to achieve a high pixel density. For example, the display panel can achieve a pixel density greater than 1500 PPI.

[0177] In some embodiments, referring to FIG13 , a multiplexing circuit 10 is connected to M output signal lines 31, that is, the multiplexing circuit 10 includes M transistors T10 for transmitting data signals to M data lines DL. Wherein, M ≥ 2. For example, the value of M can be 2, 3, or 4. Of course, M can also have other values, which are not listed in the embodiments of the present disclosure. The array substrate 100 includes (Q×2M) first gate lines 40, where O ≥ 2. For example, the value of Q can be 2 or 3. Of course, M can also have other values, which are not listed in the embodiments of the present disclosure.

[0178] The (Q×2M) first gate lines 40 are divided into Q groups, where one group includes 2M first gate lines 40. The 2M first gate lines 40 in one group are divided into M subgroups, where one subgroup includes two first gate lines 40 arranged in parallel. One second gate line 51 is connected to the two first gate lines 40 of one subgroup. One second gate line group 50 is connected to one group of first gate lines 40, and along the first direction X, multiple second gate line groups 50 are alternately connected to the Q groups of first gate lines 40. As the pixel density of the display panel increases, the number of multiplexing circuits 10 required to drive the first gate lines 40 also increases. One second gate line 51 is connected to the two first gate lines 40 of one subgroup, and multiple second gate line groups 50 are alternately connected to the Q groups of first gate lines 40. This not only helps to reduce the number of multiplexing circuits 10 driven by each first gate line 40, that is, reduces the load of the first gate line 40 and reduces the voltage drop of the first gate line 40, but also reduces the resistance of the first gate line 40.

[0179] Exemplarily, referring to FIG13 , the value of M is 2, and the value of Q is 2. That is, the multiplexing circuit 10 includes two transistors T10, and the multiplexing circuit 10 is connected to two output signal lines 31; the array substrate 100 includes eight first gate lines 40, and the eight first gate lines 40 are divided into two groups, one group of four first gate lines 40, and the four first gate lines 40 in one group include two subgroups, each subgroup including two first gate lines 40 arranged in parallel. A second gate line 51 is connected to the two first gate lines 40 in one subgroup, and a second gate line group 50 is connected to the four first gate lines 40 in one group. Wherein, along the second direction Y, two adjacent first gate lines 40 are arranged in parallel to form a subgroup, and two adjacent subgroups form a group of first gate lines 40. The two second gate line groups 50 connected to the multiplexing circuits 10 in adjacent columns are respectively connected to the two groups of first gate lines 40.

[0180] For example, as shown in FIG13 , two first gate lines 40 of a subgroup are labeled 403, and the group of the two groups of first gate lines 40 that is close to the multiplexing circuit 10 is labeled as the first group 401, and the group that is far from the multiplexing circuit 10 is labeled as the second group 402. Along the first direction X and from left to right, of the two second gate lines 51 included in the second gate line group 50 connected to the multiplexing circuits 10 of the odd-numbered columns (e.g., the first column and the third column), one second gate line 51 is connected to the two first gate lines 40 included in a subgroup 403 of the first group 401 that is close to the multiplexing circuit 10, and the other second gate line 51 is connected to the two first gate lines 40 included in a subgroup 403 of the first group 401 that is far from the multiplexing circuit 10. Of the two second gate lines 51 included in the second gate line group 50 connected to the multiplexing circuit 10 of the even columns (for example, the second column and the fourth column), one second gate line 51 is connected to the two first gate lines 40 included in a subgroup 403 of the second group 402 close to the multiplexing circuit 10, and the other is connected to the two first gate lines 40 included in a subgroup 403 of the second group 402 far from the multiplexing circuit 10.

[0181] As shown in FIG13 , in some embodiments, the array substrate may include a semiconductor layer (not shown in the figure), a gate conductive layer (not shown in the figure), a first source-drain conductive layer (not shown in the figure), and a second source-drain conductive layer (not shown in the figure) stacked in a direction away from the substrate, wherein the active layer of the plurality of transistors T10 may be located in the semiconductor layer, and the gate of the transistor T10 may be located in the gate conductive layer, the first gate line 40, the first electrode (such as the source) and the second electrode (such as the drain) of the transistor T10, and the data line DL may be located in the first source-drain conductive layer, and the input signal line 20 and the second gate line 51 may be located in the second source-drain conductive layer. Furthermore, as shown in FIG13 , a patch cord having the same filler as the input signal line 20 and the second gate line 51 may be located in the second source-drain conductive layer. Of course, the embodiments of the present disclosure are not limited thereto, and the array substrate may also include other conductive layers, and the above-mentioned signal lines or transistors may be considered to be arranged in other suitable conductive layers, as long as the same technical concept is adopted.

[0182] Continuing with FIG13 , when two adjacent first gate lines 40 are arranged in parallel to form a subgroup 403, the array substrate 100 further includes a plurality of third connecting portions 41. The plurality of third connecting portions 41 are located between the two first gate lines 40 of a subgroup and are connected to the two first gate lines 40 of a subgroup. Exemplarily, each subgroup includes third connecting portions 41 spaced apart along the first direction X between the two first gate lines 40.

[0183] The second gate line 51 includes a first end 511, which is connected to the third connecting portion 41. The two first gate lines 40 of a subgroup are connected at the third connecting portion 41. The two first gate lines 40 and the third connecting portion 41 together form a pattern with a larger area. The first end 511 is connected to the two first gate lines 40 at the third connecting portion 41, which is beneficial to increasing the process window of the second gate line 51, that is, it is beneficial to increase the contact area between the first end 511 and the connecting portion and the two first gate lines 40, thereby reducing the difficulty of preparing the first end 511.

[0184] In some embodiments, as shown in Figure 13, the number of third connecting portions 41 between two first gate lines 40 of a subgroup can be equal to the number of second gate lines 51 connected to two first gate lines 40 of a subgroup, so that one second gate line 51 corresponds to one third connecting portion 41, and one second gate line 51 is connected to one third connecting portion 41.

[0185] In other embodiments, referring to FIG. 14 , the number of third connecting portions 41 between two first gate lines 40 of a subgroup 403 can be greater than the number of second gate lines 51 connected to the two first gate lines 40 of a subgroup 403. In this way, at least two second gate lines 51 connected to at least two first gate lines 40 of a subgroup include a third connecting portion 41. This helps improve the connection reliability between the two first gate lines 40 of a subgroup and helps further reduce the resistance of the two first gate lines 40 of a subgroup. Of course, the embodiments of the present disclosure are not limited to this, as long as the same technical concept is adopted.

[0186] In some of the aforementioned embodiments of the present disclosure, such as the embodiments corresponding to Figures 11 to 14 , the multiplexing circuit 10 includes a plurality of transistors T10. The width-to-length ratio of the channels of the transistors T10 is W / L, where W / L is ≥ 180 μm / 35 μm. This facilitates further improving the width-to-length ratio of the transistors T10, thereby enhancing the charging capability of the transistors T10 and reducing the delay in signal transmission by the multiplexing circuit 10.

[0187] In some embodiments, referring to Figures 15 and 16 , the array substrate 100 further includes a plurality of test transistors T20 . The plurality of test transistors T20 are arranged in a plurality of rows along the second direction Y. Each of the plurality of rows of test transistors T20 includes a plurality of test transistors T20 spaced apart along the first direction X. This facilitates increasing the number of test transistors T20 provided within the fan-out area BB1 , thereby adapting to high-PPI array substrates and facilitating high resolution for the array substrate. Two adjacent test transistors T20 belonging to two adjacent rows are staggered in the first direction X. This facilitates wiring within the spaces between the test transistors T20 .

[0188] Illustratively, the two test transistors T20 are completely staggered in the first direction X, that is, the orthographic projections of the two test transistors T20 along the second direction Y do not overlap; or, the two test transistors T20 are partially staggered in the first direction X, that is, portions of the two adjacent test transistors T20 are arranged opposite to each other along the second direction Y.

[0189] 15 , the array substrate 100 further includes a plurality of test signal lines 61, at least one third gate line 62, at least one fourth gate line 63, and a plurality of signal transmission lines 64. The plurality of test transistors T20 include a plurality of first test transistors T21 and a plurality of second test transistors T22.

[0190] The plurality of test signal lines 61 include at least one first test signal line 61 and at least one second test signal line 612. The first test signal line 611 is further away from the display area AA than the second test signal line 612. The third gate line 62 is disposed on a side of the plurality of test signal lines 61 that is further away from the display area AA, and the fourth gate line 63 is disposed on a side of the plurality of test signal lines 61 that is closer to the display area AA. The plurality of signal transmission lines 64 are arranged at intervals along the first direction X. One end of each signal transmission line 64 is configured to be connected to a data line DL, and the other end is configured to be connected to a driver chip (e.g., a source driver chip).

[0191] Multiple first test transistors T21 are disposed between multiple test signal lines 61 and a third gate line 62. The multiple first test transistors T21 are arranged in two rows along the second direction Y. Two adjacent first test transistors T21 in each row are staggered, for example, completely staggered, in the first direction X. The gate of each first test transistor T21 is connected to the third gate line 62, the first electrode is connected to a first test signal line 611, and the second electrode is connected to a signal transmission line 64.

[0192] For example, referring to FIG. 15 , along the first direction X, two first test transistors T21 are alternately arranged in two rows. In other words, two adjacent first test transistors T21 in the same row are defined as a first transistor group 601, and the first transistor groups 601 belonging to the two rows are alternately arranged in the first direction X. Alternatively, along the first direction X, one first test transistor T21 may be alternately arranged in two rows (not shown in the figure). In other words, the first test transistors T21 belonging to the two rows are alternately arranged in the first direction X.

[0193] Multiple second test transistors T22 are disposed between multiple test signal lines 61 and a fourth gate line 63. The multiple second test transistors T22 are arranged in two rows along the second direction Y. Adjacent second test transistors T22 in the two rows are staggered, for example, completely staggered, in the first direction X. The gates of the second test transistors T22 are connected to the fourth gate line 63, the first electrodes are connected to a second test signal line 612, and the second electrodes are connected to a signal transmission line 64.

[0194] For example, referring to FIG. 15 , along the first direction X, two second test transistors T22 are alternately arranged in two rows. In other words, two adjacent second test transistors T22 in the same row are defined as a second transistor group 602 , and the second transistor groups 602 belonging to the two rows are alternately arranged in the first direction X. Alternatively, along the first direction X, one second test transistor T22 (not shown) may be alternately arranged in two rows. In other words, the second transistors T21 belonging to the two rows are alternately arranged in the first direction X.

[0195] The configuration of the test unit provided in the embodiments of the present disclosure facilitates the placement of a greater number of first test transistors T21 and second test transistors T22 within the fan-out region BB1, thereby improving the pixel density of the display panel. Furthermore, signal routing can be provided between adjacent test transistors T20, thereby optimizing the routing space for the test signal line 61, the third gate line 62, the fourth gate line 63, and the plurality of signal transmission lines 64. This in turn reduces the size of the fan-out region BB1 in the second direction Y, thereby facilitating a reduction in the border width of the array substrate.

[0196] 15 , the array substrate 100 includes four test signal lines 61 , wherein two test signal lines 61 away from the display area AA are first test signal lines 611 , and two test signal lines 61 close to the display area AA are second test signal lines 612 .

[0197] The first electrodes of the plurality of first test transistors T21 are respectively connected to the two first test signal lines 611, and the first electrodes of the plurality of first test transistors T21 are alternately connected to the two first test signal lines 611 along the first direction X. The first electrodes of the plurality of second test transistors T22 are respectively connected to the two second test signal lines 612, and the first electrodes of the plurality of second test transistors T22 are alternately connected to the two second test signal lines along the first direction X. This helps reduce the load on the first test signal lines 611 and the second test signal lines 612.

[0198] 15 , the interval between the two second test transistors T22 of the second transistor group 602 in the first direction X is greater than the interval between the two first test transistors T21 of the first transistor group 601 in the first direction X. This facilitates the wiring arrangement of the signal lines.

[0199] In some other embodiments, referring to FIG. 16 , the array substrate 100 includes a plurality of test signal lines 61 , a plurality of test transistors T20 , two fifth gate lines 65 , and a plurality of signal transmission lines 64 .

[0200] A plurality of test signal lines 61 are disposed in the fan-out area BB1. A plurality of test transistors T20 are disposed on a side of the test signal lines 61 that is close to the display area AA. The plurality of test transistors T20 are arranged in two rows along the second direction Y. Both rows include a plurality of test transistors T20 spaced apart along the first direction X. Two adjacent test transistors T20 belonging to each row are staggered along the first direction X. That is, the two adjacent test transistors T20 are offset from each other in the first direction X. This helps reduce the spacing between two adjacent test transistors T20 and the space occupied by the test transistors T20 in the first direction X. This allows for a greater number of test transistors T20 to be arranged in the fan-out area BB1, thereby improving the pixel density of the display panel and achieving a high pixel density.

[0201] Two fifth gate lines 65 are spaced apart along the second direction Y. The orthographic projection of one fifth gate line 65 on the substrate partially overlaps the orthographic projection of a row of test transistors T20 on the substrate and is configured to form the gate of a row of test transistors T20. A plurality of signal transmission lines 64 are spaced apart along the first direction X. One end of each signal transmission line 64 is configured to be connected to a data line DL and the other end is configured to be connected to the driver chip. A signal transmission line 64 is also configured to be connected to the first electrode of the test transistor T20. The second electrode of the test transistor T20 is connected to a test signal line 61.

[0202] Continuing with FIG. 16 , multiple test signal lines 61 are divided into multiple groups 603 , each group 603 including two test signal lines 61 . Multiple test transistors T20 are arranged in multiple columns 201 along a first direction X, with each column 201 including two test transistors T20 arranged along a second direction Y. Portions of the two test transistors T20 in a column are arranged relative to each other along the second direction Y. This helps reduce the size of the two test transistors T20 in a column in the first direction X, thereby allowing for a greater number of test transistors T20 to be provided within the fan-out area BB1. This increases the number of data lines on the array substrate, thereby improving the pixel density of the display panel and achieving a high PPI. Adjacent columns of test transistors T20 are spaced apart in the first direction X, facilitating the provision of a signal line (such as a signal transmission line 64) between the two adjacent columns of test transistors T20. This reduces the width of the fan-out area BB1 of the array substrate along the second direction Y, thereby achieving a narrow bezel on the display panel.

[0203] As shown in FIG16 , the plurality of test signal lines 61 can be divided into a plurality of groups, each group including two test signal lines 61. The two test transistors T20 in a column are respectively connected to the two test signal lines 61 in a group. Furthermore, along a first direction X, the columns of test transistors T20 are alternately connected to the plurality of groups of test signal lines 61. This helps reduce the load on the test signal lines 61.

[0204] For example, as shown in FIG16 , the array substrate 100 includes six test signal lines 61, which are divided into three groups. Along the first direction X and from left to right, the test transistors T20 in the first, fourth, ..., (3K+1)th columns are connected to a group of test signal lines 61 closest to the test transistors T20 along the second direction Y. The test transistors T20 in the second, fifth, ..., (3K+2)th columns are connected to a group of test signal lines 61 located in the middle along the second direction Y. The test transistors T20 in the third, sixth, ..., (3K)th columns are connected to a group of test signal lines 61 farthest from the test transistors T20 along the second direction Y. The value of K can be 0 or any positive integer.

[0205] In some embodiments, as shown in FIG17 , the signal transmission line 64 includes a first region 641, and the first gate line 40 includes a second region 42. The orthographic projections of the first region 641 and the second region 42 on the substrate overlap, that is, the first region 641 and the second region 42 are respectively the overlapping portions of the projections of the signal transmission line 64 and the first gate line 40. The first region 641 is provided with a hollow pattern, and / or the second region 42 is provided with a hollow pattern. In this way, the facing area between the first region 641 and the second region 42 can be reduced, and the facing area between the signal transmission line 64 and the first gate line 40 can be reduced, thereby reducing the parasitic capacitance between the transmission line 64 and the first gate line 40, and the signal delay on the transmission line 64 and the first gate line 40. The specific pattern type of the hollow pattern can be designed as needed, and the embodiments of the present disclosure are not limited to this. For example, the first region 641 and the second region 42 can be a grid structure, or the first region 641 and the second region 42 can include through holes arranged in an array. Of course, the embodiments of the present disclosure are not limited to this, as long as the same technical ideas are adopted. The number of first gate lines 40 and the number of signal transmission lines 64 included in the array substrate 100 can be adjusted as needed. Figure 17 is only exemplary, and the embodiments of the present disclosure are not limited thereto, as long as the same technical concept is adopted.

[0206] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising a substrate, wherein the substrate comprises a display area and a fan-out area adjacent to the display area; wherein: The array substrate further includes: A plurality of columns of pixel circuits are arranged in the display area, the plurality of columns of pixel circuits are arranged along a first direction, and the plurality of columns of pixel circuits each include a plurality of pixel circuits arranged along a second direction, and the first direction intersects with the second direction; a plurality of data lines, at least partially disposed in the display area and arranged at intervals along the first direction, the plurality of data lines all extending along the second direction, and one data line connected to one column of pixel circuits; A plurality of multiplexing circuits are arranged in the fan-out area, the plurality of multiplexing circuits are arranged in a plurality of columns along the first direction, and one column includes a plurality of multiplexing circuits arranged along the second direction; A plurality of input signal lines are arranged in the fan-out area and located at a side of the plurality of multiplexing circuits away from the display area, and one input signal line is connected to one multiplexing circuit; A plurality of output signal line groups are arranged in the fan-out area and located on a side of the plurality of multiplexing circuits close to the display area, wherein one output signal line group includes a plurality of output signal lines; the plurality of output signal lines included in one output signal line group are connected to the same multiplexing circuit, and one output signal line is connected to one data line; A plurality of first gate lines are arranged in the fan-out area and located at a side of the plurality of multiplexing circuits away from the display area; A plurality of second gate line groups, one second gate line group includes a plurality of second gate lines, one second gate line is connected to one first gate line; the plurality of second gate lines included in one second gate line group are connected to a plurality of the multiplexing circuits in one column.

2. The array substrate according to claim 1, wherein: Any two adjacent multiplexing circuits in the same column are staggered in the first direction, and a multiplexing circuit close to the display area is offset toward the same side as a multiplexing circuit far from the display area.

3. The array substrate according to claim 2, wherein: Two adjacent columns of multiplexing circuits are symmetrically arranged along the first direction.

4. The array substrate according to claim 2 or 3, wherein: The angle between the line connecting the geometric centers of the outlines of the orthographic projections of any two adjacent multiplexing circuits in the same column on the substrate and the second direction is α; 4°≤α≤30°.

5. The array substrate according to claim 4, wherein: The spacing between any two adjacent multiplexing circuits in the same column in the first direction is D1, and the spacing in the second direction is D2; wherein D1, D2 and α satisfy: tanα=D2 / D1.

6. The array substrate according to claim 4 or 5, wherein: The multiplexing circuit has a rectangular outline as an orthographic projection on the substrate.

7. The array substrate according to any one of claims 1 to 6, wherein: The plurality of second gate lines belonging to a second gate line group include a plurality of first sub-lines and a plurality of second sub-lines; The multiplexing circuit comprises: a plurality of N-type transistors, wherein a plurality of control electrodes of the plurality of N-type transistors are respectively connected to a plurality of first sub-lines, a plurality of first electrodes of the plurality of N-type transistors are all connected to the input signal line, and a plurality of second electrodes of the plurality of N-type transistors are respectively connected to a plurality of output signal lines of the output signal line group; a plurality of P-type transistors, wherein a plurality of control electrodes of the plurality of P-type transistors are respectively connected to a plurality of second sub-lines, a plurality of first electrodes of the plurality of P-type transistors are all connected to the input signal line, and a plurality of second electrodes of the plurality of P-type transistors are respectively connected to a plurality of output signal lines of the output signal line group; Wherein, an output signal line is connected to a second electrode of an N-type transistor and a second electrode of a P-type transistor.

8. The array substrate according to claim 7, wherein: The conduction states of the N-type transistor and the P-type transistor connected to the same output signal line are the same.

9. The array substrate according to claim 7 or 8, wherein: The size of the N-type transistor is the same as the size of the P-type transistor.

10. The array substrate according to any one of claims 7 to 9, wherein: The multiple N-type transistors and the multiple P-type transistors belonging to the same multiplexing circuit are arranged at intervals along the second direction, and along the first direction, two ends of the multiple N-type transistors and the multiple P-type transistors are respectively flush.

11. The array substrate according to claim 10, wherein: Any two adjacent multiplexing circuits in the same column are spaced apart in the first direction and are spaced apart in the second direction.

12. The array substrate according to claim 10, wherein: Two adjacent multiplexing circuits in the same column are spaced apart along the first direction, and at least parts of the two multiplexing circuits are arranged opposite to each other along the first direction.

13. The array substrate according to claim 12, wherein: Multiple N-type transistors and multiple P-type transistors that belong to two adjacent multiplexing circuits in the same column and are closest to each other are relatively arranged along the first direction, and the multiple N-type transistors that belong to two adjacent multiplexing circuits in the same column have a third interval in the second direction, and the multiple P-type transistors that belong to two adjacent multiplexing circuits in the same column have a fourth interval in the second direction.

14. The array substrate according to any one of claims 7 to 13, wherein: The first sub-line comprises: a plurality of first extension segments, each of which extends along the second direction, and at least one of which is configured to form a gate of an N-type transistor; A plurality of second extension segments, each of which extends along the first direction, and two ends of each second extension segment are respectively connected to a first extension segment; The second sub-line comprises: a plurality of third extension segments, each of which extends along the second direction, and at least one of which is configured to form a gate of a P-type transistor; A plurality of fourth extension segments are provided, wherein the plurality of fourth extension segments extend along the first direction, and two ends of the fourth extension segments are respectively connected to a third extension segment.

15. The array substrate according to any one of claims 7 to 13, wherein: An output signal line group includes three output signal lines, and the multiplexing circuit is connected to the three output signal lines; The multiplexing circuit comprises: The P-type semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern spaced apart along the first direction; The N-type semiconductor layer includes a third semiconductor pattern and a fourth semiconductor pattern spaced apart along the first direction; a source pattern, comprising a first source, a second source and a first connection portion, wherein the first source and the second source are spaced apart along the first direction and both extend along the second direction, the first connection portion is connected to the mutually adjacent ends of the first source and the second source, and is connected to the input signal line; the first source is respectively connected to the first semiconductor pattern and the third semiconductor pattern, and the second source is respectively connected to the second semiconductor pattern and the fourth semiconductor pattern; Three drain patterns, the three drain patterns are arranged at intervals along the first direction and all extend along the second direction; two of the drain patterns are located on both sides of the first source along the first direction and are both connected to the first semiconductor pattern and the third semiconductor pattern, another drain pattern is arranged side by side with the second source along the first direction and is connected to the second semiconductor pattern and the fourth semiconductor pattern; one drain pattern is connected to an output signal line.

16. The array substrate according to any one of claims 7 to 13, wherein: An output signal line group includes two output signal lines, and the multiplexing circuit is connected to the two output signal lines; The multiplexing circuit comprises: The P-type semiconductor layer includes a fifth semiconductor pattern; The N-type semiconductor layer includes a sixth semiconductor pattern; a source pattern extending along the second direction and connected to the fifth semiconductor pattern, the sixth semiconductor pattern and the input signal line; Two drain patterns, the two drain patterns are respectively located at two sides of the source pattern along the first direction, and the two drain patterns are both connected to the fifth semiconductor pattern and the sixth semiconductor pattern, and one drain pattern is connected to an output signal line.

17. The array substrate according to any one of claims 7 to 13, wherein: The multiple N-type transistors and the multiple P-type transistors belonging to the same multiplexing circuit are arranged at intervals along the second direction, and the multiple N-type transistors and the multiple P-type transistors are staggered in the first direction.

18. The array substrate according to claim 17, wherein: Along the second direction, a portion of the plurality of N-type transistors and a portion of the plurality of P-type transistors of the same multiplexing circuit are arranged opposite to each other.

19. The array substrate according to claim 17 or 18, wherein: Parts of two adjacent multiplexing circuits in the same column are arranged opposite to each other along the second direction.

20. The array substrate according to any one of claims 17 to 19, wherein: Two adjacent multiplexing circuits respectively belong to the same column, and the multiple N-type transistors and multiple P-type transistors that are closest to each other are spaced apart along the first direction, and parts of the multiple N-type transistors of the two adjacent multiplexing circuits respectively belong to the same column are relatively arranged along the second direction, and parts of the multiple P-type transistors of the two adjacent multiplexing circuits respectively belong to the same column are relatively arranged along the second direction.

21. The array substrate according to any one of claims 17 to 20, wherein: The first sub-line comprises: a plurality of fifth extension segments, each of which extends along the second direction, and a fifth extension segment is configured to form a gate of an N-type transistor; A plurality of sixth extension segments, wherein the plurality of sixth extension segments form an angle with the first direction, and two ends of a sixth extension segment are respectively connected to two fifth extension segments; The second sub-line comprises: a plurality of seventh extension segments, each of which extends along the second direction, and one seventh extension segment forms a gate of a P-type transistor; A plurality of eighth extension segments, wherein the plurality of eighth extension segments form an angle with the first direction, and two ends of one of the eighth extension segments are respectively connected to one of the seventh extension segments.

22. The array substrate according to any one of claims 17 to 21, wherein: An output signal line group includes four output signal lines, and the multiplexing circuit is connected to the four output signal lines; The multiplexing circuit also includes: The P-type semiconductor layer includes a seventh semiconductor pattern and an eighth semiconductor pattern spaced apart along the first direction; The N-type semiconductor layer includes a ninth semiconductor pattern and a tenth semiconductor pattern spaced apart along the first direction; a source pattern, comprising a third source, a fourth source, and a second connection portion, wherein the third source and the fourth source are spaced apart along the first direction, the second connection portion is connected to the ends of the third source and the fourth source that are close to each other, and is connected to the input signal line; the third source is connected to the seventh semiconductor pattern and the ninth semiconductor pattern, and the fourth source is connected to the eighth semiconductor pattern and the tenth semiconductor pattern; Four drain patterns are arranged at intervals along the first direction; two of the drain patterns are located on both sides of the third source along the first direction, and are connected to the seventh semiconductor pattern and the ninth semiconductor pattern, and the other two drain patterns are located on both sides of the fourth source along the first direction, and are connected to the eighth semiconductor pattern and the tenth semiconductor pattern; one drain pattern is connected to an output signal line.

23. The array substrate according to any one of claims 7 to 22, wherein: The channel length of the N-type transistor and the P-type transistor is L, and the source-drain width of the N-type transistor and the P-type transistor is W. SD ; One of the multiplexing circuits is connected to M output signal lines, and a column of multiplexing circuits includes N multiplexing circuits; the spacing between two adjacent pixel circuits along the first direction is P Pixel In the region where the multiplexing circuit is located, the width of the output signal line along the first direction is W data The interval between two adjacent output signal lines is S data ; Among them, L, W SD , M, N, P Pixel , W data and S data satisfy: 2MNP pixel =2[ML+(M+1)W SD ]+2MN(W data +S data )+R design R design is the design redundancy, R design The value range is ±5μm.

24. The array substrate according to claim 23, wherein: The L, W SD , M, N, P Pixel , W data and S data It also approximately satisfies:

25. The array substrate according to claim 23 or 24, wherein: The width-to-length ratio W / L of the N-type transistor and the P-type transistor is ≥ 38 μm / 7 μm; and / or, The source-drain width W of the N-type transistor and the P-type transistor SD ≤5μm; and / or, The distance P between two adjacent pixel circuits along the first direction is Pixel ≤7.2μm; and / or, The width W of the output signal line along the first direction data ≤2μm; and / or, The interval S between two adjacent output signal lines data ≤3.25μm.

26. The array substrate according to any one of claims 1 to 25, wherein: The width of the input signal line along the first direction is W1, wherein W1≤2.5 μm; and / or, The interval between two adjacent input signal lines along the first direction is W2, where W2≤7.2 μm.

27. The array substrate according to claim 1, wherein: Two adjacent multiplexing circuits in the same column have two ends aligned along the first direction.

28. The array substrate according to claim 27, wherein: One column includes two multiplexing circuits, and one multiplexing circuit includes a plurality of transistors; the plurality of transistors are arranged in a plurality of rows along the second direction, and each row includes at least one transistor.

29. The array substrate according to claim 28, wherein: One of the multiplexing circuits includes three transistors; wherein, along a direction close to the display area, the three transistors are arranged into a first row and a second row, the first row includes two transistors, and the second row includes one transistor.

30. The array substrate according to claim 28, wherein: One of the multiplexing circuits includes two transistors; the two transistors are arranged in two rows along the second direction, and each row includes one transistor.

31. The array substrate according to any one of claims 27 to 30, wherein: One of the multiplexing circuits is connected to M output signal lines, M≥2; The array substrate includes (Q×M) first gate lines, the (Q×M) first gate lines are divided into Q groups, one group includes M first gate lines, O≥2; A second gate line group is connected to a group of first gate lines, and along the first direction, the plurality of second gate line groups are alternately connected to Q groups of the first gate lines.

32. The array substrate according to any one of claims 27 to 30, wherein: One of the multiplexing circuits is connected to M output signal lines, M≥2; The array substrate includes (Q×2M) first gate lines, the (Q×2M) first gate lines are divided into Q groups, one group includes 2M first gate lines, and the 2M first gate lines of the group are divided into M subgroups, one subgroup includes two first gate lines arranged in parallel, and one second gate line is connected to the two first gate lines of one subgroup; wherein O≥2; A second gate line group is connected to a group of first gate lines, and along the first direction, the plurality of second gate line groups are alternately connected to Q groups of the first gate lines.

33. The array substrate according to claim 32, wherein: The array substrate further includes a plurality of third connection portions, which are located between two first gate lines of a subgroup and connected to the two first gate lines of a subgroup; and the second gate lines are connected to the third connection portions.

34. The array substrate according to claim 33, wherein: The number of the third connection parts is greater than the number of the second gate lines connected to two first gate lines of one subgroup.

35. The array substrate according to any one of claims 27 to 34, wherein: The multiplexing circuit includes a plurality of transistors; the width-to-length ratio of the channels of the transistors is W / L, wherein W / L≥180 / 35.

36. The array substrate according to any one of claims 1 to 35, wherein: The array substrate further includes: A plurality of test signal lines, including at least one first test signal line and at least one second test signal line, wherein the first test signal line is farther away from the display area than the second test signal line; at least one third gate line, disposed on a side of the plurality of test signal lines away from the display area; at least one fourth gate line, disposed on a side of the plurality of test signal lines close to the display area; A plurality of signal transmission lines are arranged at intervals along the first direction, one end of a signal transmission line is configured to be connected to a data line, and the other end of a signal transmission line is configured to be connected to a driving chip; A plurality of first test transistors are arranged between the plurality of test signal lines and the third gate line, and along the second direction, the plurality of first test transistors are arranged in two rows, and two adjacent first test transistors belonging to the two rows are staggered in the first direction; a gate of the first test transistor is connected to the third gate line, a first electrode is connected to a first test signal line, and a second electrode is connected to a signal transmission line; A plurality of second test transistors are arranged between the plurality of test signal lines and the fourth gate line. Along the second direction, the plurality of second test transistors are arranged in two rows, and two adjacent second test transistors belonging to the two rows are staggered in the first direction; a gate of the second test transistor is connected to the fourth gate line, a first electrode is connected to a second test signal line, and a second electrode is connected to a signal transmission line.

37. The array substrate according to claim 36, wherein: The array substrate has four test signal lines; two test signal lines away from the display area are first test signal lines, and two test signal lines close to the display area are second test signal lines; The first electrodes of the plurality of first test transistors are respectively connected to the two first test signal lines, and along the first direction, the first electrodes of the plurality of first test transistors are alternately connected to the two first test signal lines; The first electrodes of the plurality of second test transistors are respectively connected to two of the second test signal lines, and along the first direction, the first electrodes of the plurality of second test transistors are alternately connected to the two second test signal lines.

38. The array substrate according to claim 1, wherein: The array substrate further includes: A plurality of test signal lines are arranged in the fan-out area; A plurality of test transistors are arranged on one side of the plurality of test signal lines close to the display area and arranged in two rows along the second direction, wherein the two rows each include a plurality of test transistors spaced apart along the first direction, and two adjacent test transistors belonging to two rows are staggered along the first direction; Two fifth gate lines are arranged at intervals along the second direction, an orthographic projection of one fifth gate line on the substrate partially overlaps with an orthographic projection of a row of test transistors on the substrate, and are configured to form gates of a row of test transistors; A plurality of signal transmission lines are arranged at intervals along the first direction, one end of a signal transmission line is configured to be connected to a data line, and the other end of a signal transmission line is configured to be connected to a driving chip; Wherein, the first electrode of the test transistor is connected to a test signal line, and the second electrode is connected to a signal transmission line.

39. The array substrate according to claim 38, wherein: The multiple test transistors are arranged into multiple columns along the first direction, each column includes two test transistors arranged along the second direction; at least parts of the two test transistors in one column are arranged opposite to each other along the second direction, and there is a gap between two adjacent columns of test transistors in the first direction.

40. The array substrate according to claim 38 or 39, wherein: The multiple test signal lines are divided into multiple groups, each group includes two test signal lines; wherein two test transistors in one column are respectively connected to two test signal lines in one group, and along the first direction, multiple columns of test transistors are alternately connected to multiple groups of test signal lines.

41. The array substrate according to any one of claims 36 to 40, wherein: The signal transmission line includes a first region, the first gate line includes a second region, and the orthographic projections of the first region and the second region on the substrate overlap; Wherein, the first area is provided with a hollow pattern, and / or the second area is provided with a hollow pattern.

42. A display panel comprising: The array substrate according to any one of claims 1 to 41; The packaging cover plate is disposed on the first side of the array substrate, where the first side is a side of the pixel circuit of the array substrate away from the substrate.

43. A display device comprising: The display panel as claimed in claim 42; The driving circuit board is connected to the array substrate of the display panel and is configured to transmit a control signal to the array substrate.

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