Circuit arrangement

Abstract

The invention relates to a circuit arrangement comprising a printed circuit board (10), which has a first conductor layer (11) in which a first conductor region (21) is formed, a second conductor layer (12) in which a second conductor region (22) is formed, and a first insulation layer (31) arranged between the first conductor layer (11) and the second conductor layer (12). The circuit arrangement also comprises a series resonance circuit (3), which has a series connection consisting of a resistor (R), an inductor (L) and a capacitor (C), and which is electrically connected between a signal region (25) and the second conductor region (22). The first conductor region (21) and the second conductor region (22) are arranged directly opposite each other and form the capacitor (C) of the series resonance circuit (3).

Description

[0001] Circuit arrangement

[0002] Description:

[0003] The invention relates to a circuit arrangement comprising a printed circuit board having a first conductor layer in which a first conductor region is formed, a second conductor layer in which a second conductor region is formed, and a first insulation layer arranged between the first conductor layer and the second conductor layer.

[0004] Printed circuit boards are used to accommodate electrical components such as resistors, capacitors, transistors, and power semiconductors. Multilayer printed circuit boards are known, which comprise a plurality of electrically conductive layers. The electrically conductive layers comprise conductor tracks for interconnecting the electrical components. Insulating layers are provided between the electrically conductive layers, which electrically insulate the electrically conductive layers from one another. Through-hole connections, also known as vias, are used to electrically connect electrical components and conductor tracks in different electrically conductive layers.

[0005] DE 10 2021 004 458 A1 discloses a printed circuit board and a circuit arrangement. The printed circuit board comprises a top surface for accommodating electrical components, a bottom surface for accommodating a heat sink, a plurality of electrically conductive layers, and a plurality of electrically insulating layers.

[0006] DE 10 2017 005 928 A1 discloses a converter system comprising a DC / DC converter and two inverters. The converter provides an output voltage to power a three-phase motor in motor mode. When the motor is operating in generator mode, the converter feeds energy into a power grid.

[0007] DE 39 38 238 A1 discloses a resonant circuit absorber for electromagnetic waves. The absorber comprises a coil, a capacitor, and a resistor, which are electrically connected in series.

[0008] US 2005 / 0200431 A1 discloses a low-pass filter formed in a multilayer circuit board. US 2021 / 0058053 A1 discloses a noise filter comprising two capacitors.

[0009] US 2020 / 0382152 A1 discloses a multilayer circuit board comprising a plurality of electrodes and a dielectric substrate. The electrodes are arranged opposite one another and, together with the substrate, form a plurality of capacitors.

[0010] From US 2004 / 0136169 A1 a printed circuit board is known which has several layers that are electrically connected by means of vias.

[0011] DE 100 13 936 A1 discloses a filter arrangement for separating RF energy and signal energy in a signal line. The signal line runs in a first layer of a multilayer printed circuit board.

[0012] Circuit boards of such converters or similar devices exhibit certain resonance frequencies due to their geometry. High-frequency interference signals with these

[0013] Resonant frequencies are radiated via the device or connected cables. This can cause permissible EMC limits to be exceeded. Furthermore, such a device is sensitive to interference at these resonant frequencies.

[0014] The invention is based on the object of developing a circuit arrangement, in particular increasing the electromagnetic compatibility.

[0015] The object is achieved according to the invention by a circuit arrangement having the features specified in claim 1. Advantageous embodiments and further developments are the subject of the subclaims.

[0016] A circuit arrangement according to the invention comprises a printed circuit board having a first conductor layer in which a first conductor region is formed, a second conductor layer in which a second conductor region is formed, and a first insulation layer arranged between the first conductor layer and the second conductor layer. The circuit arrangement also comprises a resonant circuit having a series circuit comprising a resistor, an inductor, and a capacitor, and which is electrically connected between a signal region and the second conductor region. The first conductor region and the second conductor region are arranged directly opposite one another and form the capacitor of the resonant circuit.

[0017] The absorption circuit enables targeted damping of specific resonant frequencies by tuning the individual components. The capacitance of the absorption circuit is designed as a plate capacitor, with the first conductor region and the second conductor region forming the plates, between which the first insulating layer is arranged as a dielectric. This capacitance design is more cost-effective than using a capacitor as a discrete component. Furthermore, capacitors as discrete components exhibit undesirable self-inductance, which is caused by their connecting legs and their internal design.

[0018] According to an advantageous embodiment of the invention, a series circuit comprising the resistor and the inductor is electrically connected between the signal region and the first conductor region. The capacitor is electrically connected between the first conductor region and the second conductor region. Thus, the absorption circuit is electrically connected between the signal region and the second conductor region.

[0019] According to an advantageous embodiment of the invention, the resistor is designed as a discrete component. In particular, the resistor is implemented as an SMD resistor and soldered to the circuit board. The size of the resistor can be selected almost freely, and the space requirement is minimal. Due to its design, an SMD resistor has a self-inductance, which also forms part of the inductance of the absorption circuit.

[0020] According to an advantageous embodiment of the invention, the signal region is formed in the first conductor layer. The signal region and the first conductor region are thus located in one layer of the circuit board. The circuit board thus requires only two conductive layers, namely the first conductor layer and the second conductor layer. Additional conductive layers are not required, thus keeping the costs of the circuit board low.

[0021] According to an advantageous embodiment of the invention, a connecting conductor is formed in the first conductor layer, which essentially forms the inductance. The absorption circuit is thus largely integrated into the circuit board and thus requires little space. The inductance of the absorption circuit is essentially determined by the length of the connecting conductor.

[0022] According to an advantageous embodiment of the invention, the circuit board has a third conductor layer and a second insulation layer arranged between the second conductor layer and the third conductor layer. The signal area is formed in the third conductor layer. The circuit board is thus designed as a multilayer board and allows for flexible wiring of the components.

[0023] According to an advantageous embodiment of the invention, an electrically conductive via is introduced into the circuit board, extending from the first conductor layer to the third conductor layer. The via has self-inductance and is integrated into the circuit board. The absorption circuit is thus largely integrated into the circuit board and thus requires minimal space.

[0024] According to an advantageous embodiment of the invention, the resistor is electrically connected between the signal region and the via, or the resistor is electrically connected between the first conductor region and the via.

[0025] According to an advantageous embodiment of the invention, the via is electrically connected directly to the first conductor region, or the via is electrically connected directly to the signal region. In this case, the via essentially forms the inductance. The inductance of the absorption circuit is essentially determined by the length of the via.

[0026] It is also conceivable to connect several vias in parallel. The self-inductance of a parallel connection of several vias is lower than the self-inductance of a single via. By connecting several vias in parallel, the inductance of the absorption circuit can be reduced.

[0027] According to an advantageous embodiment of the invention, a connecting conductor is formed in the first conductor layer, or a connecting conductor is formed in the third conductor layer. The via is electrically connected directly to the connecting conductor, and the via and the connecting conductor essentially form the inductance. The inductance of the absorption circuit is essentially determined by the length of the via and the length of the connecting conductor.

[0028] According to an advantageous embodiment of the invention, the connecting conductor is completely surrounded by the first conductor region, or the connecting conductor is completely surrounded by the signal region.

[0029] According to an advantageous embodiment of the invention, the connecting conductor is linear. As a result, the connecting conductor has a relatively low self-inductance.

[0030] According to an advantageous embodiment of the invention, the connecting conductor is spiral-shaped. As a result, the connecting conductor has a higher self-inductance than a straight one.

[0031] The invention is not limited to the combination of features in the claims. Further possible combinations of claims and / or individual claim features and / or features of the description and / or the figures will become apparent to those skilled in the art, particularly from the problem and / or the problem posed by comparison with the prior art.

[0032] The invention will now be explained in more detail with reference to the accompanying drawings. The invention is not limited to the exemplary embodiments shown in the drawings. The drawings only represent the subject matter of the invention schematically. They show:

[0033] Figure 1 : an electrical circuit diagram of a circuit arrangement,

[0034] Figure 2: a schematic representation of a circuit arrangement according to a first embodiment,

[0035] Figure 3: a schematic representation of a circuit arrangement according to a second embodiment,

[0036] Figure 4: a plan view of a third conductor layer of a printed circuit board of the circuit arrangement according to the second embodiment,

[0037] Figure 5: a plan view of a first conductor layer of a printed circuit board of the circuit arrangement according to the second embodiment,

[0038] Figure 6: a plan view of a first conductor layer of a printed circuit board of a circuit arrangement according to a third embodiment and

[0039] Figure 7: a plan view of a first conductor layer of a printed circuit board of a circuit arrangement according to a fourth embodiment.

[0040] Figure 1 shows an electrical circuit diagram of a circuit arrangement. The circuit arrangement is part of an electrical device, for example, a converter, which provides an output voltage to power a three-phase motor. The circuit arrangement includes a resonant circuit 3. The resonant circuit 3 has a series circuit consisting of a resistor R, an inductance L, and a capacitor C.

[0041] The absorption circuit 3 is electrically connected between a signal region 25 and a second conductor region 22. The second conductor region 22 is electrically connected to a reference ground. A series circuit consisting of the resistor R and the inductance L of the absorption circuit 3 is electrically connected between the signal region 25 and a first conductor region 21. The capacitance C of the absorption circuit 3 is electrically connected between the first conductor region 21 and the second conductor region 22.

[0042] The circuit arrangement also includes a parasitic resonant circuit 2, which has a resonant frequency. The parasitic resonant circuit 2 is also electrically connected between the signal region 25 and the second conductor region 22. The parasitic resonant circuit 2 amplifies and boosts interference signals in a frequency range around the resonant frequency.

[0043] An interference source 1 couples an interference signal with the resonant frequency between the signal region 25 and the second conductor region 22. The interference signal is thus present at the parasitic resonant circuit 2 and the absorption circuit 3. The absorption circuit 3 is specifically tuned to the resonant frequency of the parasitic resonant circuit 2 and thus effects a targeted attenuation of the interference signal with the resonant frequency.

[0044] The resonance frequency F of the absorption circuit 3 is essentially determined by the inductance L and the capacitance C. The resonance frequency F of the absorption circuit 3 is calculated as follows:

[0045] 1 F = -

[0046] 2TI LC

[0047] The resistance R of absorption circuit 3 influences the quality factor of absorption circuit 3. The quality factor should be selected so that absorption circuit 3 does not generate any additional disturbing resonant frequencies in the circuit arrangement, while maintaining a sufficiently large main effect. Ideal quality factors lie in a range between 1 and 5. The quality factor G of absorption circuit 3 is calculated as follows:

[0048] With an inductance L of, for example, 1 nH, a capacitance C of, for example, 1 nF and a resistance R of, for example, 1 Q, this results in a resonance frequency F of approximately 160 MHz and a quality factor of approximately 1.

[0049] Figure 2 shows a schematic representation of a circuit arrangement according to a first embodiment. The circuit arrangement comprises a printed circuit board 10, which has a first conductor layer 11, a second conductor layer 12, and a first insulation layer 31. The first insulation layer 31 is arranged between the first conductor layer 11 and the second conductor layer 12.

[0050] The first conductor region 21 is formed in the first conductor layer 11. The first conductor region 11 has a first surface made of a metallic material, in particular copper. The second conductor region 22 is formed in the second conductor layer 12. The second conductor region 12 has a second surface made of a metallic material, in particular copper.

[0051] The first conductor region 21 and the second conductor region 22 are arranged directly opposite one another. The first conductor region 21 and the second conductor region 22 represent plates of a plate capacitor, between which the first insulation layer 31 is arranged as a dielectric. The first conductor region 21 and the second conductor region 22 form the capacitance C of the absorption circuit 3.

[0052] The first conductor region 21 and the second conductor region 22 overlap on an area A. The insulation layer 31 as a dielectric has a thickness d and a permittivity E. The capacitance C of the absorption circuit is calculated as:

[0053] The signal region 25 is also formed in the first conductor layer 11. The signal region 25 is made of a metallic material, in particular copper. A connecting conductor 45 made of the same metallic material is also formed in the first conductor layer 11. The connecting conductor 45 is connected to the signal region 25 in this case. The connecting conductor 45 forms the inductance L of the absorption circuit 3.

[0054] The resistor R is designed as a discrete component, particularly in the form of an SMD resistor. The resistor R is arranged on the first conductor layer 11 and connected to the first conductor region 21 and to the connecting conductor 45. The series circuit comprising the resistor R and the inductance L of the absorption circuit 3 is thus electrically connected between the signal region 25 and the first conductor region 21.

[0055] Alternatively, the connecting conductor 45 is connected to the first conductor region 21, and the resistor R is connected to the signal region 25. The series circuit comprising the resistor R and the inductance L of the absorption circuit 3 is also electrically connected between the signal region 25 and the first conductor region 21 in this case.

[0056] Figure 3 shows a schematic representation of a circuit arrangement according to a second embodiment. The circuit arrangement comprises a printed circuit board 10, which has a first conductor layer 11, a second conductor layer 12, and a first insulation layer 31. The first insulation layer 31 is arranged between the first conductor layer 11 and the second conductor layer 12.

[0057] The circuit board 10 further comprises a third conductor layer 13 and a second insulation layer 32. The second insulation layer 32 is arranged between the second conductor layer 12 and the third conductor layer 13. The circuit board 10 is thus designed as a multilayer board, with the second conductor layer 12 arranged internally.

[0058] The first conductor region 21 is formed in the first conductor layer 11. The first conductor region 11 has a first surface made of a metallic material, in particular copper. The second conductor region 22 is formed in the second conductor layer 12. The second conductor region 12 has a second surface made of a metallic material, in particular copper. The signal region 25 is formed in the third conductor layer 13. The signal region 25 is made of a metallic material, in particular copper.

[0059] The first conductor region 21 and the second conductor region 22 are arranged directly opposite one another. The first conductor region 21 and the second conductor region 22 represent plates of a plate capacitor, between which the first insulation layer 31 is arranged as a dielectric. The first conductor region 21 and the second conductor region 22 form the capacitance C of the absorption circuit 3.

[0060] The first conductor region 21 and the second conductor region 22 overlap on an area A. The insulation layer 31 as a dielectric has a thickness d and a permittivity E. The capacitance C of the absorption circuit is calculated as: An electrically conductive via 40 is introduced into the circuit board 10. The via 40 extends from the first conductor layer 11 to the third conductor layer 13. The via 40 has a self-inductance.

[0061] The resistor R is designed as a discrete component, in particular in the form of an SMD resistor. In this case, the resistor R is arranged on the third conductor layer 13 and connected to the signal region 25.

[0062] Figure 4 shows a top view of the third conductor layer 13 of the circuit board 10 of the circuit arrangement according to the second embodiment. In this case, the resistor R is electrically connected between the signal region 25 and the via 40.

[0063] Figure 5 shows a top view of the first conductor layer 11 of the circuit board 10 of the circuit arrangement according to the second embodiment. The via 40 is electrically connected directly to the first conductor region 21. The via 40 forms the inductance L of the absorption circuit 3.

[0064] The series circuit consisting of the resistor R and the inductance L of the absorption circuit 3 is thus electrically connected between the signal area 25 and the first conductor area 21.

[0065] Alternatively, the resistor R is electrically connected between the first conductor region 21 and the via 40, and the via 40 is directly electrically connected to the signal region 25. In this case, the series circuit comprising the resistor R and the inductance L of the absorption circuit 3 is also electrically connected between the signal region 25 and the first conductor region 21.

[0066] Figure 6 shows a plan view of a first conductor layer 11 of a printed circuit board 10 of a circuit arrangement according to a third embodiment. The circuit arrangement according to the third embodiment largely corresponds to the circuit arrangement according to the second embodiment.

[0067] In contrast to the circuit arrangement according to the second embodiment, a connecting conductor 45 having self-inductance is formed in the first conductor layer 11. The connecting conductor 45 is connected to the first conductor region 21 and is linear. The through-hole 40 is electrically connected directly to the connecting conductor 45. The through-hole 40 and the connecting conductor 45 together form the inductance L of the absorption circuit 3.

[0068] The series circuit consisting of the resistor R and the inductance L of the absorption circuit 3 is thus electrically connected between the signal area 25 and the first conductor area 21.

[0069] Alternatively, the resistor R is electrically connected between the first conductor region 21 and the via 40, and the connecting conductor 45 is formed in the third conductor layer 13. The connecting conductor 45 is connected to the first signal region 25, and the via 40 is directly electrically connected to the connecting conductor 45. The series circuit comprising the resistor R and the inductance L of the absorption circuit 3 is also electrically connected between the signal region 25 and the first conductor region 21 in this case.

[0070] Figure 7 shows a plan view of a first conductor layer 11 of a printed circuit board 10 of a circuit arrangement according to a fourth embodiment. The circuit arrangement according to the fourth embodiment largely corresponds to the circuit arrangement according to the third embodiment.

[0071] In contrast to the circuit arrangement according to the third embodiment, the connecting conductor 45 is spiral-shaped and placed around the via 40. The spiral-shaped connecting conductor 45 has a higher self-inductance than in a straight configuration. As a result, the inductance L of the absorption circuit 3 is increased compared to the circuit arrangement according to the third embodiment.

[0072] List of reference symbols

[0073] 1 source of interference

[0074] 2 parasitic resonance circuit

[0075] 3 Suction circuit

[0076] 10 circuit board

[0077] 11 first conductor layer

[0078] 12 second conductor layer

[0079] 13 third conductor layer

[0080] 21 first ladder area

[0081] 22 second ladder area

[0082] 25 signal range

[0083] 31 first insulation layer

[0084] 32 second insulation layer

[0085] 40 vias

[0086] 45 connecting conductors

[0087] R resistance

[0088] L Inductance

[0089] C capacity

Claims

Patent claims:

1. Circuit arrangement, comprising a printed circuit board (10) which has a first conductor layer (11) in which a first conductor region (21) is formed, a second conductor layer (12) in which a second conductor region (22) is formed, and a first insulation layer (31) arranged between the first conductor layer (11) and the second conductor layer (12), characterized in that the circuit arrangement comprises a suction circuit (3) which has a series circuit of a resistor (R), an inductance (L) and a capacitor (C) and which is electrically connected between a signal region (25) and the second conductor region (22), and in that the first conductor region (21) and the second conductor region (22) are arranged directly opposite one another and form the capacitor (C) of the suction circuit (3).

2. Circuit arrangement (10) according to claim 1, characterized in that a series circuit comprising the resistor (R) and the inductance (L) is electrically connected between the signal region (25) and the first conductor region (21).

3. Circuit arrangement according to one of the preceding claims, characterized in that the resistor (R) is designed as a discrete component.

4. Circuit arrangement according to one of the preceding claims, characterized in that the signal region (25) is formed in the first conductor layer (11).

5. Circuit arrangement (10) according to claim 4, characterized in that a connecting conductor (45) is formed in the first conductor layer (11), which forms the inductance (L).

6. Circuit arrangement according to one of claims 1 to 3, characterized in that the printed circuit board (10) has a third conductor layer (13) and a second insulation layer (32) arranged between the second conductor layer (12) and the third conductor layer (13), and in that the signal region (25) is formed in the third conductor layer (13).

7. Circuit arrangement (10) according to claim 6, characterized in that an electrically conductive through-contact (40) is introduced into the printed circuit board (10), which extends from the first conductor layer (11) to the third conductor layer (13).

8. Circuit arrangement (10) according to claim 7, characterized in that the resistor (R) is electrically connected between the signal region (25) and the through-contact (40), or that the resistor (R) is electrically connected between the first conductor region (21) and the through-contact (40).

9. Circuit arrangement according to one of claims 7 to 8, characterized in that the through-contact (40) is electrically connected directly to the first conductor region (21), or that the through-contact (40) is electrically connected directly to the signal region (25), and that the through-contact (40) forms the inductance (L).

10. Circuit arrangement according to one of claims 7 to 9, characterized in that a connecting conductor (45) is formed in the first conductor layer (11), or that a connecting conductor (45) is formed in the third conductor layer (13), and that the through-plating (40) is electrically connected directly to the connecting conductor (45), and that the through-plating (40) and the connecting conductor (45) form the inductance (L).

11. Circuit arrangement (10) according to claim 10, characterized in that the connecting conductor (45) is completely surrounded by the first conductor region (21), or that the connecting conductor (45) is completely surrounded by the signal region (25).

12. Circuit arrangement (10) according to one of claims 5 or 10 to 11, characterized in that the connecting conductor (45) is of straight design.

13. Circuit arrangement (10) according to one of claims 5 or 10 to 11, characterized in that the connecting conductor (45) is spiral-shaped.

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