Method for manufacturing semiconductor device

Abstract

One example of the present invention pertains to hybrid bonding in CoW (chip-on-wafer), which is a technique for the three-dimensional integration of semiconductors. In this manufacturing method, semiconductor wafers 100, 200 are prepared. During this preparation, an organic insulation material M is applied so as to cover rewiring on substrate bodies 101, 201 such as silicon wafers, and organic insulation layers 102, 202 are thereby formed. The semiconductor wafer 100 is heated within a heating device H so that the curing rate of the organic insulation layer 102 of the semiconductor wafer 100 is brought to at least 30%. The curing rate of the semiconductor wafer 200 is kept to 85% or less. The cured semiconductor wafer 100 is singulated to acquire semiconductor chips 10. The semiconductor chips 10 are mounted on the semiconductor wafer 200 by a chip bonder CB. A resulting joined body S is re-heated by the heating device H to fully cure the organic insulation layer. This manufacturing method makes it possible to increase shear strength in hybrid bonding that uses organic insulation layers.

Description

Semiconductor device manufacturing method

[0001] The present disclosure relates to a method for manufacturing a semiconductor device.

[0002] In recent years, three-dimensional integration techniques have been studied to improve the integration degree of LSIs. Non-Patent Document 1 discloses an example of three-dimensional integration techniques for semiconductor chips.

[0003] FC Chen et al., “System on Integrated Chips(SoIC TM) for 3D Heterogeneous Integration”, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), p.594-599(2019)

[0004] As a three-dimensional semiconductor integration technology, hybrid bonding is being considered for wafer-to-wafer (W2W) bonding or chip-on-wafer (CoW) bonding. In hybrid bonding, organic insulating materials are sometimes used for the insulating layer on the bonding surface as a countermeasure against foreign matter. It is desirable to increase the bonding strength between such organic insulating layers.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can increase the bonding strength between organic insulating layers.

[0006] [1] One aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes the steps of: preparing a first semiconductor substrate having a first substrate body, a first organic insulating layer provided on one surface of the first substrate body, and at least one first electrode provided on one surface of the first substrate body; preparing a second semiconductor substrate having a second substrate body, a second organic insulating layer provided on one surface of the second substrate body, and at least one second electrode provided on one surface of the second substrate body; heating at least one of the first semiconductor substrate and the second semiconductor substrate to harden at least one of the first organic insulating layer and the second organic insulating layer; and, after the heating step, bonding the first organic insulating layer and the second organic insulating layer to each other and bonding the first electrode to each other. The first organic insulating layer and the second organic insulating layer contain a curable resin and a thermal crosslinking agent. In this method for manufacturing a semiconductor device, after the heating step, the first organic insulating layer is subjected to the bonding step with a cure rate of 30% or more, and after the heating step, the second organic insulating layer is subjected to the bonding step with a cure rate of 85% or less.

[0007] In this semiconductor device manufacturing method, the cure rate of the first organic insulating layer used in the bonding process is set to 30% or more, while the cure rate of the second organic insulating layer used in the bonding process is suppressed to 85% or less. The inventors' studies have shown that this increases the bonding strength between the first organic insulating layer and the second organic insulating layer. For example, when bonding the first organic insulating layer and the second organic insulating layer, by setting the cure rate of the first organic insulating layer to 30% or more and the cure rate of the second organic insulating layer to 85% or less, the shear strength between the organic insulating layers can be increased to 5 MPa or more, which is required for hybrid bonding.

[0008] [2] In the method for manufacturing a semiconductor device according to [1] above, it is preferable that the first semiconductor substrate is a semiconductor chip and the second semiconductor substrate is a semiconductor wafer. In this case, in the heating step, the first semiconductor substrate may be heated as part of a large-sized semiconductor wafer, or the large-sized semiconductor wafer may be singulated to form semiconductor chips after the heating step and before the bonding step. In the bonding step, the first semiconductor substrate, which is a semiconductor chip, is bonded to the second semiconductor substrate, which is a semiconductor wafer. This method for manufacturing a semiconductor device makes it possible to easily increase bonding strength in the fabrication of a chip-on-wafer (CoW) type semiconductor device in which one or more singulated semiconductor chips are mounted on a semiconductor wafer.

[0009] [3] In the method for manufacturing a semiconductor device according to [1] or [2] above, the heating step preferably heats the first semiconductor substrate so that the cure rate of the first organic insulating layer is 70% or more. In this case, lateral misalignment can be suppressed when bonding the organic insulating layers together. Furthermore, if the first semiconductor substrate is to be diced into semiconductor chips, having such a cure rate can suppress peeling of portions of the organic insulating layer when dicing from a large semiconductor wafer.

[0010] [4] In the semiconductor device manufacturing method of [1] or [2] above, the heating step preferably heats the first semiconductor substrate so that the cure rate of the first organic insulating layer is 90% or more. In this case, lateral misalignment can be suppressed when bonding the organic insulating layers together. Furthermore, in this case, if the first semiconductor substrate is to be diced into semiconductor chips, having such a cure rate can more reliably suppress peeling of portions of the organic insulating layer when diced from a large-sized semiconductor wafer. Furthermore, in this case, if the cure rate of the second organic insulating layer is 10% or less (including a 0% cure rate, i.e., uncured), the bonding strength between the organic insulating layers can be further increased. For example, the shear strength between the organic insulating layers can be 20 MPa or more.

[0011] [5] In the method for manufacturing a semiconductor device according to any one of [1] to [4] above, in the heating step, the second semiconductor substrate may be heated so that the cure rate of the second organic insulating layer is 60% or less. In this case, by suppressing the cure rate of the second organic insulating layer on the side receiving the first organic insulating layer to 60% or less, the bonding strength between the organic insulating layers can be increased.

[0012] [6] In the method for manufacturing a semiconductor device according to any one of the above [1] to [5], when the first organic insulating layer and the second organic insulating layer are bonded together, the cure rate of the second organic insulating layer may be 10% or less. In this case, by suppressing the cure rate of the second organic insulating layer that receives the first organic insulating layer to 10% or less, the bonding strength between the organic insulating layers can be further increased.

[0013] [7] In the method for manufacturing a semiconductor device according to [6] above, when the first organic insulating layer and the second organic insulating layer are bonded together, the second organic insulating layer is preferably in an uncured state. In this case, by leaving the second organic insulating layer on the side receiving the first organic insulating layer uncured, it is possible to further increase the bonding strength between the organic insulating layers.

[0014] [8] Preferably, the method for manufacturing a semiconductor device according to any one of [1] to [7] above further comprises a step of reheating the bonded body of the first semiconductor substrate and the second semiconductor substrate after the bonding step. The reheating temperature in the step of reheating the bonded body is preferably higher than the heating temperature in the step of heating at least one of the first semiconductor substrate and the second semiconductor substrate. In this case, reheating at a high temperature after bonding promotes hardening of the organic insulating layer, thereby strengthening the bond between the organic insulating layers.

[0015] [9] In any of the semiconductor device manufacturing methods described above in [1] to [8], the first organic insulating layer and the second organic insulating layer may contain a photosensitive resin composition. This photosensitive resin composition may contain the curable resin. By forming each organic insulating layer containing a photosensitive resin composition, it becomes possible to manufacture the layers using a damascene process when combining them with electrodes. Furthermore, in this case, the same materials as those used in the rewiring and passivation processes that have already been put into practical use can be used, making it easier to put the method into practical use.

[0016]

[10] In the method for manufacturing a semiconductor device according to [9] above, the photosensitive resin composition preferably contains an alkali-soluble resin having a phenolic hydroxyl group, a compound that generates an acid when exposed to light, a thermal crosslinking agent, and an acrylic resin. In this case, the photosensitive resin composition can be cured at a low temperature, efficiently increasing the curing rate of the organic insulating layer. Furthermore, the composition can have improved adhesion and good thermal shock resistance, thereby improving its function as an insulating layer.

[0017]

[11] In the method for manufacturing a semiconductor device according to any one of [1] to [9] above, the first organic insulating layer and the second organic insulating layer may contain a polyimide resin. In this case, a semiconductor device having excellent heat resistance can be manufactured.

[0018]

[12] In the method for manufacturing a semiconductor device according to any one of [1] to

[11] above, the first organic insulating layer and the second organic insulating layer may be formed from the same type of resin material, and the step of heating at least one of the first semiconductor substrate and the second semiconductor substrate may include a step of heating the first semiconductor substrate at a first temperature and a step of heating the second semiconductor substrate at a second temperature, and the first temperature may be higher than the second temperature. In this case, the cure rates of the first organic insulating layer and the second organic insulating layer can be easily adjusted to desired values.

[0019] According to the present disclosure, it is possible to provide a method for manufacturing a semiconductor device that increases the bonding strength between organic insulating layers.

[0020] Fig. 1 is a perspective view schematically showing an example of a semiconductor device manufactured by a semiconductor device manufacturing method according to an embodiment of the present disclosure. Fig. 2(a) to (e) are schematic views sequentially showing a method for manufacturing the semiconductor device shown in Fig. 1. Fig. 3(a) to (d) are schematic cross-sectional views sequentially showing a method for manufacturing the semiconductor device shown in Fig. 1. Fig. 4(a) and (b) are schematic cross-sectional views showing a method for manufacturing the semiconductor device shown in Fig. 1. Fig. 5 is a schematic cross-sectional view showing a method for measuring the bond strength (shear strength) between organic insulating layers.

[0021] Hereinafter, several embodiments of the present disclosure will be described in detail, with reference to the drawings as necessary. In the following description, identical or equivalent parts will be designated by the same reference numerals, and duplicate explanations will be omitted. Furthermore, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings unless otherwise specified. When terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "lower" are used in the description and claims of this specification, these are intended for explanatory purposes and do not necessarily mean that these relative positions will always be the same. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0022] In this specification, the term "layer" encompasses not only a structure with a shape formed over the entire surface when observed in a plan view, but also a structure with a shape formed on a portion of the surface. In this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes, as long as the intended effect of the process is achieved. A numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively.

[0023] (Configuration of Semiconductor Device) FIG. 1 is a perspective view schematically illustrating an example of a semiconductor device manufactured by the semiconductor device manufacturing method according to this embodiment. As shown in FIG. 1, the semiconductor device 1 is, for example, an example of a semiconductor package. The semiconductor device 1 includes multiple semiconductor chips 10 (first semiconductor substrate) and a semiconductor wafer 20 (second semiconductor substrate), and has a chip-on-wafer (CoW) structure. The multiple semiconductor chips 10 are fabricated by dicing a first semiconductor substrate 100 (described later) into individual pieces. The multiple semiconductor chips 10 are mounted on the semiconductor wafer 20 to form a three-dimensional mounting structure. The semiconductor wafer 20 may be a substrate on which multiple semiconductor chips, such as LSI (Large Scale Integrated Circuit) chips or CMOS (Complementary Metal Oxide Semiconductor) sensors, are formed in locations corresponding to the semiconductor chips 10. Each semiconductor chip 10 may be a semiconductor chip such as an LSI or memory. The multiple semiconductor chips 10 and the semiconductor wafer 20 are finely bonded to each other by hybrid bonding (described later) to firmly and without misalignment, with their respective terminal electrodes and the organic insulating layers surrounding them. The semiconductor device 1 may be further singulated into individual semiconductor devices (semiconductor devices) each comprising one semiconductor chip 10 that has been further singulated from the configuration shown in FIG. 1 and a substrate portion that is part of the semiconductor wafer 20 corresponding to the one semiconductor chip 10.

[0024] (Method for Manufacturing Semiconductor Device) Next, a method for manufacturing the semiconductor device 1 will be described with reference to Fig. 2 and Fig. 3. Fig. 2(a) to (e) and Fig. 3(a) to (d) are schematic diagrams sequentially illustrating a method for manufacturing the semiconductor device 1 shown in Fig. 1.

[0025] The semiconductor device 1 can be manufactured, for example, through the following steps (a) to (f): (a) preparing a first semiconductor substrate having a first substrate body, a first organic insulating layer provided on one surface of the first substrate body, and at least one first electrode provided on one surface of the first substrate body; (b) preparing a second semiconductor substrate having a second substrate body, a second organic insulating layer provided on one surface of the second substrate body, and at least one second electrode provided on one surface of the second substrate body; (c) heating at least one of the first semiconductor substrate and the second semiconductor substrate, whereby at least one of the first organic insulating layer and the second organic insulating layer is cured by the heating; (d) singulating the large-sized first semiconductor substrate after the heating step of step (c) and before the bonding step of step (e); and (e) bonding the first organic insulating layer and the second organic insulating layer to each other and the first electrode to each other after the heating step. (f) A step of reheating the bonded assembly of the first semiconductor substrate (semiconductor chip after separation) and the second semiconductor substrate after the bonding step (e).

[0026] [Step (a)] Step (a) is a step of preparing a first semiconductor substrate 100, which is a silicon substrate on which an integrated circuit consisting of semiconductor elements and interconnections is formed. The first semiconductor substrate 100 corresponds to the semiconductor chip 10 of the semiconductor device 1 shown in FIG. 1. In step (a), as shown in FIG. 2A, a liquid organic insulating material M is applied to a substrate body 101 (first substrate body) made of silicon or the like, on one side of which rewiring is provided, and spin-coated. The applied organic insulating material is then subjected to a mild heat treatment to volatilize the solvent in the coating liquid and form a film. As a result, a first semiconductor substrate 100 is prepared, which includes the substrate body 101, an organic insulating layer 102 (first organic insulating layer) provided on one side 101a of the substrate body 101, and rewiring portions 103 (first electrodes) provided on the one side 101a of the substrate body 101, as shown in FIG. 3A. A rewiring layer (RDL layer) is formed from the organic insulating layer 102 and each rewiring portion 103. Each rewiring portion 103 is formed to include a plurality of terminal electrodes and wirings made of copper, aluminum, or the like, and is provided at predetermined intervals. The rewiring portions 103 are configured to penetrate the organic insulating layer 102 and expose integrated circuits and the like formed on the first semiconductor substrate 100 to the outside. The thickness of the organic insulating layer 102 may be, for example, 1 μm to 10 μm, or may be 5 μm or less. Note that, although the above description illustrates a method in which the rewiring portions 103 are provided on the substrate main body 101 and then the organic insulating layer 102 is provided, this is not limiting, and the rewiring portions 103 may be provided after the organic insulating layer 102 is provided.

[0027] [Step (b)] Step (b) is similar to step (a) and involves preparing a second semiconductor substrate 200, which is a silicon substrate on which an integrated circuit consisting of semiconductor elements and interconnections connecting them is formed. The second semiconductor substrate 200 corresponds to the semiconductor wafer 20 of the semiconductor device 1 shown in FIG. 1. In step (b), as shown in FIGS. 2A and 3A, a liquid organic insulating material is applied to a substrate body 201 (second substrate body) made of silicon or the like, on one side of which rewiring is provided, and spin-coated. The applied organic insulating material is then subjected to a mild heat treatment to volatilize the solvent in the coating liquid and form a film. As a result, a second semiconductor substrate 200 is prepared, which includes the substrate body 201, an organic insulating layer 202 (second organic insulating layer) provided on one side 201a of the substrate body 201, and rewiring portions 203 (second electrodes) provided on the one side 201a of the substrate body 201, as shown in FIG. 3A. The organic insulating layer 202 and each rewiring portion 203 form a rewiring layer (RDL layer). Each rewiring portion 203 is formed to include a plurality of terminal electrodes and wirings made of copper, aluminum, or the like, and is provided at predetermined intervals. The rewiring portions 203 are configured to penetrate the organic insulating layer 202 and expose the integrated circuits and the like formed on the second semiconductor substrate 200 to the outside. The thickness of the organic insulating layer 202 may be, for example, 1 μm to 10 μm, or may be 5 μm or less. Note that, although the above description illustrates a method in which the rewiring portions 203 are provided on the substrate main body 201 and then the organic insulating layer 202 is provided, this is not limited thereto, and the rewiring portions 103 may be provided after the organic insulating layer 202 is provided. The organic insulating material constituting the organic insulating layer 202 may be the same type of organic insulating material as the organic insulating material constituting the organic insulating layer 102 described above, or may be a different organic insulating material.

[0028] In steps (a) and (b), polishing may be performed to flatten the surfaces of the organic insulating layers 102, 202 and the rewiring portions 103, 203. The surface roughness Ra of the organic insulating layers 102, 202 and the rewiring portions 103, 203 after polishing may be 1 nm or less. This polishing process may also be performed after the heating step in step (c), which will be described in detail later.

[0029] The resin composition constituting the organic insulating material M used to form the organic insulating layers 102, 202 in steps (a) and (b) is not particularly limited, but may be composed of a curable resin or may contain a photosensitive resin composition. Such a photosensitive resin composition may contain, for example, (A) an alkali-soluble resin having a phenolic hydroxyl group, (B) a compound that generates an acid when exposed to light, (C) a thermal crosslinking agent, and (D) an acrylic resin.

[0030] <Component (A)> Component (A): Alkali-Soluble Resin Having a Phenolic Hydroxyl Group Component (A) is a resin that has a phenolic hydroxyl group in its molecule and is soluble in an alkaline developer. Examples of the alkali-soluble resin having a phenolic hydroxyl group of component (A) include hydroxystyrene-based resins such as polyhydroxystyrene and copolymers containing hydroxystyrene as a monomer unit, phenolic resins, polybenzoxazole precursors such as poly(hydroxyamide), poly(hydroxyphenylene) ether, and polynaphthol. Component (A) may be composed of only one of these resins, or may be composed of two or more of them.

[0031] Among these, component (A) is preferably a phenolic resin, and particularly preferably a novolac phenolic resin, because of its low cost, high contrast, and small volumetric shrinkage upon curing. Component (A) may also be a hydroxystyrene-based resin, because of its excellent electrical properties (insulating properties) and small volumetric shrinkage upon curing.

[0032] Phenolic resins are polycondensation products of phenol or its derivatives with aldehydes. Polycondensation is carried out in the presence of a catalyst such as an acid or a base. Phenolic resins obtained using an acid catalyst are particularly called novolak-type phenolic resins. Specific examples of novolak resins include phenol / formaldehyde novolak resin, cresol / formaldehyde novolak resin, xylylenol / formaldehyde novolak resin, resorcinol / formaldehyde novolak resin, and phenol-naphthol / formaldehyde novolak resin.

[0033] <Component (B)> The component (B), a compound that generates an acid when exposed to light, is used as a photosensitizer. Such a component (B) generates an acid when exposed to light, and has the function of increasing the solubility of the exposed area in an alkaline aqueous solution. Compounds generally referred to as photoacid generators can be used as the component (B). Specific examples of the component (B) include o-quinonediazide compounds, aryldiazonium salts, diaryliodonium salts, and triarylsulfonium salts. Among these, it is preferable to use an o-quinonediazide compound as the component (B) because of its high sensitivity.

[0034] The blend amount of component (B) is preferably 3 to 100 parts by mass, more preferably 5 to 50 parts by mass, and particularly preferably 5 to 30 parts by mass per 100 parts by mass of component (A), in terms of the difference in dissolution rate between exposed and unexposed areas and the tolerance range of sensitivity.

[0035] <Component (C)> By including the thermal crosslinking agent (Component (C)), when the photosensitive resin layer after application is heated and cured, Component (C) reacts with Component (A) to form a crosslinked structure. This enables curing at low temperatures and prevents the insulating layer from becoming brittle and melting. Specific examples of the component (C) that can be preferably used are compounds having a phenolic hydroxyl group, compounds having a hydroxymethylamino group, and compounds having an epoxy group.

[0036] Note that the "compound having a phenolic hydroxyl group" referred to here does not include (A) an alkali-soluble resin having a phenolic hydroxyl group. A compound having a phenolic hydroxyl group as a thermal crosslinking agent not only functions as a thermal crosslinking agent, but also increases the dissolution rate of exposed areas during development in an alkaline aqueous solution, thereby improving sensitivity. The molecular weight of such a compound having a phenolic hydroxyl group is preferably 2000 or less. In consideration of solubility in an alkaline aqueous solution and the balance between photosensitive properties and mechanical properties, the number average molecular weight is preferably 94 to 2000, more preferably 108 to 2000, and particularly preferably 108 to 1500. Note that conventionally known compounds having a phenolic hydroxyl group can be used.

[0037] <Component (D)> By including an acrylic resin as component (D), it is possible to improve thermal shock resistance while maintaining good photosensitive properties. The acrylic resin is preferably an acrylic resin having one or more structural units represented by the following general formulas (1) to (3).

[0038] [In general formulas (1) to (3), R １ represents a hydrogen atom or a methyl group, R ２ represents an alkyl group having 4 to 20 carbon atoms, and R ３ represents a monovalent organic group having a primary, secondary, or tertiary amino group.] In particular, by containing an acrylic resin having a structural unit represented by the general formula (1) and a structural unit represented by the general formula (2), it is possible to improve thermal shock resistance while maintaining good photosensitive properties. Furthermore, from the viewpoint of further improving compatibility with component (A), adhesion of the organic insulating layer to the substrate, mechanical properties, and thermal shock resistance, it is more preferable to contain an acrylic resin having a structural unit represented by the general formula (1), a structural unit represented by the general formula (2), and a structural unit represented by the general formula (3). Component (D) may consist of only one of the above acrylic resins, or may contain two or more of them.

[0039] From the viewpoints of adhesion, mechanical properties, thermal shock resistance, and photosensitive properties, the blending amount of component (D) is preferably 1 to 50 parts by mass, more preferably 3 to 30 parts by mass, and particularly preferably 5 to 20 parts by mass, per 100 parts by mass of the total amount of component (A).

[0040] The photosensitive resin composition may contain other components such as a compound that generates an acid upon heating, an elastomer, a dissolution promoter, a dissolution inhibitor, a coupling agent, and a surfactant or leveling agent. Specific examples of the compound that generates an acid upon heating are compounds different from the compound that generates an acid upon heating (component (B)) upon light exposure, such as salts formed from a strong acid and a base, such as onium salts, which have the function of generating an acid upon heating, and imide sulfonates. Conventional elastomers can be used as the elastomer, but it is preferable that the polymer constituting the elastomer has a glass transition temperature (Tg) of 20°C or lower. Examples of such elastomers include styrene-based elastomers, olefin-based elastomers, urethane-based elastomers, polyester-based elastomers, polyamide-based elastomers, and silicone-based elastomers.

[0041] A solvent can be used in the photosensitive resin composition described above. By including a solvent in the photosensitive resin composition, it is possible to facilitate application to a substrate and form a coating film of uniform thickness. Examples of solvents include γ-butyrolactone, ethyl lactate, propylene glycol monomethyl ether acetate, benzyl acetate, n-butyl acetate, ethoxyethyl propionate, 3-methylmethoxypropionate, N-methyl-2-pyrrolidone, N,N-dimethylformamide, N,N-dimethylacetamide, dimethyl sulfoxide, hexamethylphosphorylamide, tetramethylene sulfone, diethyl ketone, diisobutyl ketone, methyl amyl ketone, cyclohexanone, propylene glycol monomethyl ether, propylene glycol monopropyl ether, propylene glycol monobutyl ether, and dipropylene glycol monomethyl ether. These solvents can be used alone or in combination of two or more. When a solvent is used, the content thereof is not particularly limited, but it is preferable to adjust the ratio of the solvent in the photosensitive resin composition to 20 to 90 mass %.

[0042] In steps (a) and (b), when an organic insulating layer is formed by applying an organic insulating material M made of the above-mentioned photosensitive resin composition, the layer may be exposed to light of a predetermined wavelength using a semiconductor laser or the like to form a predetermined pattern.

[0043] The organic insulating material used for the organic insulating layers 102 and 202 in steps (a) and (b) is not limited to the above-mentioned photosensitive resin composition, and may include, for example, a polyimide resin, a polyimide precursor (e.g., a polyimide ester or a polyamic acid), a polyamide-imide resin, a bismaleimide resin, a benzocyclobutene (BCB) resin, a polybenzoxazole (PBO) resin, or a PBO precursor.

[0044] The organic insulating layers 102 and 202 in steps (a) and (b) are mainly made of an organic insulating material, but may partially contain an inorganic insulating material or an inorganic insulating layer.

[0045] 2B, at least one of the first semiconductor substrate 100 and the second semiconductor substrate 200 is heated to harden at least one of the organic insulating layer 102 and the organic insulating layer 202. This heat hardening results in a hardening rate of 30% or more of the organic insulating layer 102 of the first semiconductor substrate 100, and a hardening rate of 85% or less of the organic insulating layer 202 of the second semiconductor substrate 200. In step (c), each semiconductor substrate is placed in a heating device H and heated to 100°C to 200°C, and heating is continued for a predetermined time (e.g., 30 minutes), thereby performing a hardening process.

[0046] The "curing rate" referred to here can be determined using a Fourier transform infrared spectrophotometer (FT-IR). Specifically, the curing rate can be determined according to the following procedure: (i) The FT-IR spectrum of the organic insulating layer before the curing treatment in step (c) is measured, and the peak area S of the peak attributable to the structure X involved in the curing reaction among the chemical structures of the thermal crosslinking agent is calculated. Ａ１ and the peak area S of the peak attributable to structure Y, which is not involved in the curing reaction among the chemical structures of the curable resin. Ｂ１ Ratio AＮ１ (=S Ａ１ / S Ｂ１ (ii) The FT-IR spectrum of the organic insulating layer after the curing treatment in the step (c) is measured, and the peak area S of the peak attributed to the structure X of the thermal crosslinking agent is calculated. Ａ２ and the peak area S of the peak attributed to the structure Y of the curable resin Ｂ２ Ratio A Ｎ２ (=S Ａ２ / S Ｂ２ (iii) A obtained in (i) and (ii) above is calculated. Ｎ１ , A Ｎ２ The curing rate is calculated according to the following formula (4): Curing rate (%) = {(A Ｎ１ -A Ｎ２ ) / A Ｎ１}×100 (4) For example, when the organic insulating layer contains a compound having a methoxy group at the end as a thermal crosslinking agent and an alkali-soluble resin having a phenolic hydroxyl group as a curable resin, S Ａ１ and S Ａ２ The wave number is 1080 cm －１ The peak area of ​​the peak at (attributed to the methoxy group (C—O) of the thermal crosslinking agent) is expressed as S Ｂ１ and S Ｂ２ as 700 cm －１ The peak areas of the peaks at (attributable to the phenyl group (C—H) of the curable resin) can be used.

[0047] In step (c), the first semiconductor substrate 100 to be singulated in a subsequent step may be heated so that the organic insulating layer 102 has a cure rate of 50% or more, so that the organic insulating layer 102 has a cure rate of 70% or more, or so that the organic insulating layer 102 has a cure rate of 90% or more. By sufficiently curing the organic insulating layer 102 in the first semiconductor substrate 100 to be singulated, peeling of the resin during singulation by dicing or the like is suppressed. The temperature in the heating step for the first semiconductor substrate 100 may be, for example, 140°C to 200°C, and may be higher than the temperature in the heating step for the second semiconductor substrate 200. In other words, the organic insulating layer 102 of the first semiconductor substrate 100 may be more hardened than the organic insulating layer 202 of the second semiconductor substrate 200. The curing may be accelerated not only by increasing the heating temperature but also by increasing the heating time.

[0048] In step (c), the second semiconductor substrate 200, which will not be singulated in a subsequent step, may be heated in the same manner as the first semiconductor substrate 100, but heating is not required. If the second semiconductor substrate 200 is not heated in step (c) or if the heating temperature is low, the organic insulating layer 202 of the second semiconductor substrate 200 remains uncured. On the other hand, if the second semiconductor substrate 200 is heated, the second semiconductor substrate 200 may be heated so that the cure rate of the organic insulating layer 202 is 60% or less, or the second semiconductor substrate 200 may be heated so that the cure rate of the organic insulating layer 202 is 10% or less. Because the second semiconductor substrate 200 will not be singulated in step (d), it does not need to be cured to a high cure rate from the beginning, as with the organic insulating layer 102 of the first semiconductor substrate 100. The temperature in the heating step for the second semiconductor substrate 200 may be, for example, 120°C to 170°C, and may be lower than the heating temperature for the first semiconductor substrate 100. That is, it is preferable that the organic insulating layer 202 of the second semiconductor substrate 200 is not cured as much as the organic insulating layer 102 of the first semiconductor substrate 100. Note that curing can be suppressed not only by reducing the heating temperature but also by shortening the heating time.

[0049] [Step (d)] Step (d) is a step performed after the heating step of step (c) and before the bonding step of step (e), which will be described later, in which a large (wafer-shaped) first semiconductor substrate 100 is diced to obtain multiple semiconductor chips 10 (first semiconductor substrates). In step (d), as shown in FIGS. 2(c) and 3(b), the first semiconductor substrate 100 is attached to a dicing tape DCT. The first semiconductor substrate 100 is then diced into multiple semiconductor chips 10 using a cutting tool such as a dicing blade D (dicer). The layered structure of the diced semiconductor chips 10 is the same as that of the first semiconductor substrate 100. In step (d), the substrate body 101 and organic insulating layer 102 of the first semiconductor substrate 100 are divided into substrate bodies 101b and organic insulating layers 102b corresponding to each semiconductor chip 10, as shown in FIG. 3(b). As a dicing method for dividing the first semiconductor substrate 100 into individual pieces, for example, it is preferable to use a dicer equipped with a dicing blade D, but stealth dicing or laser dicing may also be used.

[0050] [Step (e)] Step (e) is a step of bonding the organic insulating layer 102b and the organic insulating layer 202 together after the singulation step of step (d), and bonding the electrodes of the rewiring portion 103 and the electrodes of the rewiring portion 203 together. In step (e), as shown in (d) of FIG. 2 and (c) of FIG. 3, the singulated semiconductor chip 10 is picked up by a chip bonder CB, and the semiconductor chip 10 is mounted in a predetermined position on the second semiconductor substrate 200. For example, the chip bonding temperature may be 230°C, the bonding pressure may be 1.5 MPa, and the bonding time may be 10 to 20 seconds. During this chip bonding, the organic insulating layer 102b and the organic insulating layer 202 face each other, and the electrodes of the rewiring portion 103 and the electrodes of the rewiring portion 203 are aligned and bonded. 4A and 4B are enlarged views showing the state in which the semiconductor chip 10 and the second semiconductor substrate 200 are bonded together.

[0051] [Step (f)] Step (f) is a step of reheating the bonded assembly of the first semiconductor substrate 100 (semiconductor chip 10 after singulation) and the second semiconductor substrate 200 after the bonding step of step (e). In step (f), as shown in FIGS. 2(e) and 3(d), the bonded assembly S of the semiconductor chip 10 and the second semiconductor substrate 200 bonded by chip bonding in the bonding step of step (e) is placed in a heating device H and heated to 200°C or higher. Heating is continued for a predetermined time (e.g., 2 hours), thereby performing thermal curing. This fully hardens the organic insulating layer 102b of the semiconductor chip 10 corresponding to the first semiconductor substrate 100 and the organic insulating layer 202 of the second semiconductor substrate 200. This fully hardens the organic insulating layer 102b and the organic insulating layer 202, for example, to 97% or higher, essentially 100%. It is preferable that the curing rate of the organic insulating layer be 97% or more or substantially 100% by reheating, but the curing rate does not have to be 100% as long as the bonding strength (shear strength) between the organic insulating layer 102b and the organic insulating layer 202 is a predetermined value of 5 MPa or more.

[0052] The heating in step (f) may strengthen the bond at the bonded portion between the rewiring portion 103 of the semiconductor chip 10 corresponding to the first semiconductor substrate 100 and the rewiring portion 203 of the second semiconductor substrate 200 .

[0053] In this way, the semiconductor device 1 shown in Fig. 1 is obtained. The semiconductor device 1 may be further divided into individual pieces to produce a plurality of semiconductor devices.

[0054] As described above, in the method for manufacturing a semiconductor device according to this embodiment, when bonding the organic insulating layers 102b and 202 to each other, the cure rate of the organic insulating layer 102b is set to 30% or more, while the cure rate of the organic insulating layer 202 is suppressed to 85% or less. This increases the bonding strength between the organic insulating layer 102b and the organic insulating layer 202. As an example, when bonding the organic insulating layer 102b to the organic insulating layer 202, by setting the cure rate of the organic insulating layer 102b to 30% or more and the cure rate of the organic insulating layer 202 to 85% or less, the shear strength between the organic insulating layers can be set to 5 MPa or more, which is required for hybrid bonding.

[0055] Here, with reference to FIG. 5 , a method for measuring the bonding strength between the semiconductor chip 10 and the second semiconductor substrate 200 will be described. The bonding strength here refers to shear strength. First, a bonded structure S consisting of the semiconductor chip 10 and the second semiconductor substrate 200, with their organic insulating layers bonded together, is prepared on the stage 300. Then, a tool T is moved in the direction of the arrow from the side of the semiconductor chip 10 of the bonded structure S to measure the strength when the semiconductor chip 10 peels off. The height of the tool T from the top surface of the second semiconductor substrate 200 is 20 μm, the movement speed of the tool T is 20 μm / s, and the width of the tool T is 5 mm. In measuring the shear strength, n=5 shear strength measurements are performed on each test body (each sample of the bonded structure S), and the average of the three values ​​excluding the maximum and minimum values ​​can be used as the shear strength.

[0056] In the manufacturing method of a semiconductor device according to this embodiment, the first semiconductor substrate 100 is singulated into semiconductor chips 10, and the second semiconductor substrate 200 is a semiconductor wafer. Then, after the heating step and before the bonding step, the large-sized semiconductor wafer is singulated to form the semiconductor chips 10. In the bonding step, the semiconductor chips 10 are bonded to the second semiconductor substrate 200, which is also a semiconductor wafer. This manufacturing method makes it possible to easily increase the bonding strength in the fabrication of a chip-on-wafer (CoW) type semiconductor device in which one or more singulated semiconductor chips are mounted on a semiconductor wafer.

[0057] In the method for manufacturing a semiconductor device according to this embodiment, in step (c), the first semiconductor substrate 100 may be heated so that the cure rate of the organic insulating layer 102 is 70% or more. In this case, lateral misalignment can be suppressed when bonding the organic insulating layers together. Furthermore, by achieving such a cure rate, peeling of the organic insulating layers 102, 102b can be suppressed when a large-sized semiconductor wafer is diced into individual pieces.

[0058] In the semiconductor device manufacturing method according to this embodiment, in step (c), the first semiconductor substrate 100 is preferably heated so that the cure rate of the organic insulating layers 102, 102b is 90% or higher. This reduces lateral misalignment when bonding the organic insulating layers together. Furthermore, by achieving such a cure rate, peeling of the organic insulating layers 102, 102b can be more reliably prevented when the large-sized semiconductor wafer is diced into individual pieces. Furthermore, in this case, if the cure rate of the mating organic insulating layer 202 is 10% or lower (including a 0% cure rate, i.e., uncured), the bonding strength between the organic insulating layers can be further increased. For example, the shear strength between the organic insulating layers can be increased to 20 MPa or higher.

[0059] In the method for manufacturing a semiconductor device according to this embodiment, in step (c), the second semiconductor substrate 200 may be heated so that the cure rate of the organic insulating layer 202 is 60% or less. In this case, by suppressing the cure rate of the organic insulating layer 202 on the side that receives the organic insulating layer 102b to 60% or less, it is possible to increase the bonding strength between the organic insulating layers.

[0060] In the method for manufacturing a semiconductor device according to this embodiment, the cure rate of the organic insulating layer 202 may be 10% or less when bonding the organic insulating layer 102b and the organic insulating layer 202. In this case, by suppressing the cure rate of the organic insulating layer 202 on the side that receives the organic insulating layer 102b to 10% or less, it is possible to further increase the bonding strength between the organic insulating layers.

[0061] In the method for manufacturing a semiconductor device according to this embodiment, it is preferable that the organic insulating layer 202 is in an uncured state when bonding the organic insulating layer 102b to the organic insulating layer 202. In this case, by leaving the organic insulating layer 202 on the side that receives the organic insulating layer 102b uncured, it is possible to further increase the bonding strength between the organic insulating layers.

[0062] The method for manufacturing a semiconductor device according to this embodiment further includes a step (f) of reheating the bonded body S of the first semiconductor substrate (semiconductor chip 10) and the second semiconductor substrate 200 after step (d). The reheating temperature in step (f) of reheating the bonded body S is preferably higher than the heating temperature in step (c) of heating at least one of the first semiconductor substrate 100 and the second semiconductor substrate 200. In this case, reheating at a high temperature after bonding promotes hardening of the organic insulating layer, thereby strengthening the bond between the organic insulating layers. Furthermore, the electrode material at the bonding surfaces of the bonded electrodes is remelted, thereby strengthening the bond between the electrodes.

[0063] In the semiconductor device manufacturing method according to this embodiment, the organic insulating layers 102, 102b and the organic insulating layer 202 may contain a photosensitive resin composition. The photosensitive resin composition may contain the curable resin. Because the organic insulating layers 102, 102b and the organic insulating layer 202 are formed from a photosensitive resin composition, they can be fabricated using a damascene process when combined with an electrode. In this case, the same materials as those used in the rewiring and passivation processes that are already in practical use can be used, facilitating practical application.

[0064] In the semiconductor device manufacturing method according to this embodiment, the photosensitive resin composition preferably contains an alkali-soluble resin having a phenolic hydroxyl group, a compound that generates an acid when exposed to light, a thermal crosslinking agent, and an acrylic resin. In this case, the photosensitive resin composition can be cured at low temperatures, efficiently increasing the curing rate of the organic insulating layer. Furthermore, the composition can have improved adhesion and good thermal shock resistance, thereby improving its function as an insulating layer.

[0065] In the semiconductor device manufacturing method according to this embodiment, the organic insulating layers 102, 102b and the organic insulating layer 202 may be formed from the same type of resin material. In this case, in the step (c) of heating at least one of the first semiconductor substrate 100 and the second semiconductor substrate 200, the first semiconductor substrate 100 may be heated at a first temperature, and the second semiconductor substrate 200 may be heated at a second temperature. Here, the first temperature may be higher than the second temperature. In this case, the curing rates of the organic insulating layers 102, 102b and the organic insulating layer 202 can be easily adjusted to desired values.

[0066] Although the embodiments of the semiconductor device manufacturing method according to the present disclosure have been described in detail above, the present invention is not limited to the above embodiments and can be applied to various embodiments or examples. For example, the above description shows a case where the present invention is applied to CoW bonding in which the first semiconductor substrate 100 is singulated into semiconductor chips 10 and then bonded. However, the present invention may also be applied to Wafer-to-Wafer (W2W) bonding in which the first semiconductor substrate 100 is bonded to the second semiconductor substrate 200 as a semiconductor wafer without being singulated. Even in such a case, the desired bonding strength (shear strength) can be easily obtained.

[0067] The present invention will be described in more detail below with reference to examples, but the present invention is not limited to these examples.

[0068] Example 1 A 12-inch silicon wafer (substrate body 101, 201) was prepared to correspond to the first semiconductor substrate 100 and the second semiconductor substrate 200 in the above-described embodiment. Rewiring portions 103, 203 were formed on the silicon wafer. An organic insulating material was then applied and spin-coated onto the silicon wafer on which the rewiring portions 103, 203 were formed, and then heated to volatilize the solvent in the coating liquid, forming a film, thereby forming organic insulating layers 102, 202 with a thickness of 5 μm, respectively. The organic insulating material used here was the following photosensitive resin composition. In this way, the first semiconductor substrate 100 and the second semiconductor substrate 200 were prepared.

[0069] [Photosensitive Resin Composition] 100 g of the following component (A), 15 g of the component (B), 15 g of the component (C), 10 g of the component (D), 120 g of ethyl lactate as a solvent, and 2 g of a 50% methanol solution of ureapropyltriethoxysilane as a coupling agent were blended, and the mixture was filtered under pressure using a Teflon (registered trademark) filter with 3 μm pores to prepare a positive photosensitive resin composition of Example 1.

[0070] (A) Component: 4-hydroxystyrene / methyl methacrylate = 50 / 50 (molar ratio) copolymer (weight average molecular weight in terms of polystyrene = 10,000, manufactured by Maruzen Petrochemical Co., Ltd., trade name "Marukalinker CMM") (B) Component: 1-naphthoquinone-2-diazide-5-sulfonic acid ester of 1,1-bis(4-hydroxyphenyl)-1-[4-{1-(4-hydroxyphenyl)-1-methylethyl}phenyl]ethane (esterification rate approximately 90%, manufactured by AZ Electronic Materials Co., Ltd., trade name "TPPA528") (C) Component: hexakis(methoxymethyl)melamine (manufactured by Sanwa Chemical Co., Ltd., trade name "Nikarac MW-30HM", compound represented by the following structural formula) Component (D): Acrylic Resin The acrylic resin used as component (D) was synthesized as follows. 75 g of toluene and 75 g of isopropanol (IPA) were weighed into a 500 ml three-neck flask equipped with a stirrer, a nitrogen inlet tube, and a thermometer. Separately weighed polymerizable monomers of 85 g of butyl acrylate (BA), 24 g of lauryl acrylate (DDA), 14 g of acrylic acid (AA), and 7.9 g of 1,2,2,6,6-pentamethylpiperidin-4-yl methacrylate (trade name: FA-711MM, manufactured by Resonac Co., Ltd.), as well as 0.13 g of azobisisobutyronitrile (AIBN), were added. While stirring at a rotation speed of approximately 270 rpm at room temperature, nitrogen gas was passed through at a flow rate of 400 ml / min for 30 minutes to remove dissolved oxygen. Thereafter, the flow of nitrogen gas was stopped, the flask was sealed, and the temperature was raised to 65°C in about 25 minutes in a thermostatic water bath. The same temperature was maintained for 14 hours to carry out a polymerization reaction, yielding acrylic resin D. The conversion rate was 98%. The weight average molecular weight (Mw) of this acrylic resin D, calculated as standard polystyrene by the GPC method, was about 36,000.

[0071] Next, the prepared first semiconductor substrate 100 and second semiconductor substrate 200 were placed in a heating device H and heated for 30 minutes at the heating temperature (°C) shown in Table 2 below. Specifically, the first semiconductor substrate 100 (semiconductor chip) was heated to 200°C so that the curing rate was 100%. On the other hand, the second semiconductor substrate (semiconductor wafer) was heated to 120°C, but the curing rate was 0%.

[0072] Next, the heat-hardened first semiconductor substrate 100 was singulated using a dicer to obtain multiple semiconductor chips 10. The obtained semiconductor chips 10 were then picked up using a chip bonder CB and mounted on a semiconductor wafer, which was the second semiconductor substrate 200. The temperature during bonding using the chip bonder CB was 230°C, the bonding pressure was 1.5 MPa, and the bonding time was 10 seconds. Thereafter, the bonded body S, in which the semiconductor chips 10 were mounted on the second semiconductor substrate 200, was placed in a heating device H and reheated. The reheating conditions were 230°C and 2 hours.

[0073] The shear strength of the reheated bonded body S (semiconductor device 1) according to Example 1 was measured based on the shear strength test method shown in FIG. The shear strength evaluation was as follows: 20 MPa or more was "Evaluation S," 10 MPa or more but less than 20 MPa was "Evaluation A," 5 MPa or more but less than 10 MPa was "Evaluation B," and less than 5 MPa was "Evaluation C." Since a shear strength of 5 MPa or more is preferable, "Evaluations S, A, and B" for shear strength were considered acceptable. The shear strength of the semiconductor device according to Example 1 was "Evaluation S." Resin peeling during singulation into semiconductor chips was also evaluated, with no resin peeling being rated "Evaluation A," partial resin peeling being rated "Evaluation B," and severe resin peeling being rated "Evaluation C." The resin peeling of the semiconductor device according to Example 1 was "Evaluation A."

[0074] Example 2 In Example 2, a semiconductor device according to Example 2 was fabricated under the same conditions as Example 1, except that the bonding time was changed to 20 seconds, and the shear strength and resin peeling were evaluated. The shear strength of the semiconductor device according to Example 2 was evaluated as "S." Furthermore, the resin peeling during singulation into semiconductor chips was evaluated as "A."

[0075] Example 3 In Example 3, a semiconductor device was fabricated under the same conditions as Example 1, except that the heating temperature of the second semiconductor substrate 200 in step (c) was increased to 140°C, thereby increasing the cure rate of the second semiconductor substrate 200 to 50%, and the shear strength and resin peeling were evaluated. The shear strength of the semiconductor device according to Example 3 was evaluated as "Rating A." Furthermore, the resin peeling during singulation into semiconductor chips was also evaluated as "Rating A." It was confirmed that even when the second semiconductor substrate 200 was cured to a certain extent (50% cure rate), the shear strength was maintained at a high level of 10 MPa or more. However, a comparison between Example 1 and Example 3 confirmed that increasing the cure rate of the second semiconductor substrate 200 reduced the shear strength between the organic insulating layers.

[0076] Example 4 In Example 4, a semiconductor device was fabricated under the same conditions as in Example 1, except that the heating temperature in step (c) of the first semiconductor substrate 100 was lowered to 160°C, thereby reducing the cure rate of the first semiconductor substrate 100 (semiconductor chip 10) to 80%, and the shear strength and resin peeling were evaluated. The shear strength of the semiconductor device according to Example 4 was evaluated as "Rating A." Furthermore, the resin peeling during singulation into semiconductor chips was also evaluated as "Rating A." Comparing Example 1 and Example 4, it was confirmed that the shear strength was significantly improved when the cure rate of the organic insulating layer 102b of the first semiconductor substrate 100 (semiconductor chip 10) was increased (for example, the cure rate was 90% or higher).

[0077] Example 5 In Example 5, a semiconductor device was fabricated under the same conditions as in Example 4, except that the heating temperature in step (c) of the second semiconductor substrate 200 was increased to 160°C, thereby increasing the cure rate of the second semiconductor substrate 200 to 80%, and the shear strength and resin peeling were evaluated. The shear strength of the semiconductor device according to Example 5 was evaluated as "Evaluation A." Furthermore, the resin peeling during singulation into semiconductor chips was also evaluated as "Evaluation A."

[0078] Example 6 In Example 6, a semiconductor device was fabricated under the same conditions as in Example 5, except that the heating temperature in step (c) of the second semiconductor substrate 200 was lowered to 140°C, thereby lowering the cure rate of the second semiconductor substrate 200 to 50%, and the shear strength and resin peeling were evaluated. The shear strength of the semiconductor device according to Example 6 was evaluated as "Rating B." Furthermore, the resin peeling during singulation into semiconductor chips was evaluated as "Rating A."

[0079] Example 7 In Example 7, a semiconductor device was fabricated under the same conditions as in Example 1, except that the heating temperature in step (c) of the first semiconductor substrate 100 was lowered to 140°C to reduce the cure rate of the first semiconductor substrate 100 (semiconductor chip 10) to 50%, and the heating temperature in step (c) of the second semiconductor substrate 200 was raised to 140°C to increase the cure rate of the second semiconductor substrate 200 to 50%, and the shear strength and resin peeling were evaluated. The shear strength of the semiconductor device according to Example 7 was evaluated as "Rating A." Furthermore, the resin peeling during singulation into semiconductor chips was evaluated as "Rating B." However, it was possible to fabricate a semiconductor device 1 using the unpeeled portions.

[0080] Example 8 In Example 8, a semiconductor device was fabricated under the same conditions as Example 7, except that the heating temperature in step (c) of the second semiconductor substrate 200 was lowered to 120°C, thereby reducing the cure rate of the second semiconductor substrate 200 to 0%, and the shear strength and resin peeling were evaluated. The shear strength of the semiconductor device according to Example 8 was evaluated as "Rating A." Furthermore, the resin peeling during singulation into semiconductor chips was evaluated as "Rating B." However, it was possible to fabricate a semiconductor device 1 using the unpeeled portions.

[0081] Example 9 In Example 9, a semiconductor device was fabricated under the same conditions as in Example 1, except that the following photosensitive resin composition was used as the organic insulating material instead of the photosensitive resin composition used in Example 1, and the shear strength and resin peeling were evaluated. The shear strength of the semiconductor device according to Example 9 was evaluated as "Rating B." Furthermore, the resin peeling during singulation into semiconductor chips was evaluated as "Rating A."

[0082] [Photosensitive Resin Composition] 100 g of the following component (A), 10 g of component (B), 25 g of component (C), and ethyl lactate as a solvent were blended, and the mixture was filtered under pressure using a polytetrafluoroethylene filter with 0.2 μm pores to prepare a photosensitive resin composition.

[0083] <Component (A)> To synthesize component (A), a bisimide phenol compound having the structure (a1), a cresol compound having the structure (b1), 1,4-bis(methoxymethyl)benzene, 4,4-bis(methoxymethyl)biphenyl, and 37% by mass of formaldehyde were prepared. Alkali-soluble resins having the structural units (molar ratios) and weight-average molecular weights (Mw) shown in Table 1 were synthesized. (c1) is the structure introduced by 1,4-bis(methoxymethyl)benzene, and (c2) is the structure introduced by formaldehyde.

[0084]

[0085] N,N'-bis(3-hydroxyphenyl)-pyromellitimide, o-cresol, 1,4-bis(methoxymethyl)benzene, 37% by mass of formaldehyde, γ-butyrolactone, and p-toluenesulfonic acid were added to a 1 L three-neck flask equipped with a Dean-Stark apparatus, and the reaction was carried out for 6 hours at 180°C while stirring and removing the reaction by-product, methanol, by dehydration, and then cooled to 40°C. After cooling, the reaction liquid was added dropwise to 1 L of ion-exchanged water, and the precipitated resin was separated by filtration. The separated resin was vacuum-dried at 80°C for 12 hours to obtain an alkali-soluble resin of component (A).

[0086] The Mw of component (A) was measured by gel permeation chromatography (GPC) and calculated using a standard polystyrene calibration curve. The calibration curve was approximated by a cubic equation of a universal calibration curve according to JIS K 7252-2 (2016) using a set of five standard polystyrene samples (PStQuick MP-H, PStQuick B [product name, manufactured by Tosoh Corporation]). The GPC conditions are shown below.

[0087] (GPC conditions) Detector: L-2490 RI (Hitachi High-Tech Corporation) Column: Gelpack GL-R440+R450+R400M (Hitachi High-Tech Corporation) Eluent: tetrahydrofuran (THF) Measurement temperature: 40°C Flow rate: 2.05 mL / min Concentration: 5 mg / mL

[0088] <Component (B)> 1-naphthoquinone-2-diazide-5-sulfonic acid ester of 1,1-bis(4-hydroxyphenyl)-1-[4-{1-(4-hydroxyphenyl)-1-methylethyl}phenyl]ethane (esterification rate: approximately 90%, manufactured by Daito Chemix Co., Ltd., product name "PA28")

[0089] <Component (C)> 4,4'-[1-[4-[1-[4-hydroxy-3,5-bis(methoxymethyl)phenyl]-1-methylethyl]phenyl]ethylidene]bis[2,6-bis(methoxymethyl)phenol] (manufactured by Honshu Chemical Industry Co., Ltd., trade name "HMOM-TPPA")

[0090] Comparative Example 1 In Comparative Example 1, a semiconductor device was fabricated under the same conditions as in Example 1, except that the heating temperature in step (c) of the first semiconductor substrate 100 was lowered to 170°C to reduce the cure rate of the first semiconductor substrate 100 (semiconductor chip 10) to 90%, and the heating temperature in step (c) of the second semiconductor substrate 200 was raised to 170°C to increase the cure rate of the second semiconductor substrate 200 to 90%, and the shear strength and resin peeling were evaluated. That is, in Comparative Example 1, both cure rates were increased to 90%. The shear strength of the semiconductor device according to Comparative Example 1 was evaluated as "Evaluation C." Furthermore, peeling during singulation into semiconductor chips was evaluated as "Evaluation A." The shear strength in Comparative Example 1 was lower than the standard value of 5 MPa.

[0091] Comparative Example 2 In Comparative Example 2, a semiconductor device was fabricated under the same conditions as in Example 9, except that the heating temperature in step (c) of the first semiconductor substrate 100 was lowered to 170°C to increase the cure rate of the first semiconductor substrate 100 (semiconductor chip 10) to 90% or more, and the heating temperature in step (c) of the second semiconductor substrate 200 was raised to 170°C to increase the cure rate of the second semiconductor substrate 200 to 90% or more, and the shear strength and resin peeling were evaluated. That is, in Comparative Example 2, both cure rates were increased to 90% or more. The shear strength of the semiconductor device according to Comparative Example 2 was evaluated as "Evaluation C." Furthermore, peeling during singulation into semiconductor chips was evaluated as "Evaluation A." The shear strength in Comparative Example 2 was lower than the standard value of 5 MPa.

[0092]

[0093] The evaluation of shear strength and the evaluation of whether or not resin peeling occurred during dicing in Examples 1 to 9 and Comparative Examples 1 and 2 are summarized in Table 3 below.

[0094]

[0095] Tables 2 and 3 confirm that when bonding organic insulating layers 102b and 202 together, the bond strength (shear strength) between organic insulating layer 102b and organic insulating layer 202 can be increased by setting the cure rate of organic insulating layer 102b to 30% or more while suppressing the cure rate of organic insulating layer 202 to 85% or less. Specifically, by setting each organic insulating layer to the above-mentioned cure rate, it was confirmed that the bond strength (shear strength) between first semiconductor substrate 100 (semiconductor chip 10) and second semiconductor substrate 200 can be increased to the standard value of 5 MPa or more. Note that Comparative Examples 1 and 2 show that bonding when both organic insulating layers are bonded with cure rates of 90% or more tends to weaken the bond strength.

[0096] Furthermore, when bonding organic insulating layers 102b and 202 to each other, it was confirmed that by setting the curing rate of organic insulating layer 102b to 90% or more or 95% or more, while suppressing the curing rate of organic insulating layer 202 to 10% or less (including 0% for uncured), the bonding strength (shear strength) between organic insulating layer 102b and organic insulating layer 202 can be increased to 20 MPa or more (or 30 MPa or more).

[0097] 1...semiconductor device, 10...semiconductor chip (first semiconductor substrate), 20...semiconductor wafer (second semiconductor substrate), 100...first semiconductor substrate, 101, 101b...substrate body (first substrate body), 102, 102b...organic insulating layer (first organic insulating layer), 103...rewiring portion (first electrode), 200...second semiconductor substrate, 201...substrate body (second substrate body), 202...organic insulating layer (second organic insulating layer), 203...rewiring portion (second electrode).

Claims

1. A step of preparing a first semiconductor substrate having a first substrate body, a first organic insulating layer provided on one surface of the first substrate body, and at least one first electrode provided on the one surface of the first substrate body; a step of preparing a second semiconductor substrate having a second substrate body, a second organic insulating layer provided on one surface of the second substrate body, and at least one second electrode provided on the one surface of the second substrate body; a step of heating at least one of the first semiconductor substrate and the second semiconductor substrate, wherein at least one of the first organic insulating layer and the second organic insulating layer is cured by the heating; a step of bonding the first organic insulating layer and the second organic insulating layer to each other, and bonding the first electrode and the second electrode to each other after the heating step. The first organic insulating layer and the second organic insulating layer are configured to include a curable resin and a thermosetting crosslinking agent. After the heating step, the curing rate of the first organic insulating layer used in the bonding step is 30% or more. After the heating step, the curing rate of the second organic insulating layer used in the bonding step is 85% or less. A method for manufacturing a semiconductor device.

2. The first semiconductor substrate is a semiconductor chip, the second semiconductor substrate is a semiconductor wafer. In the heating step, the first semiconductor substrate is heated as a part of a large-sized semiconductor wafer. After the heating step and before the bonding step, the large-sized semiconductor wafer is diced to form the semiconductor chip. In the bonding step, the first semiconductor substrate, which is the semiconductor chip, is bonded to the second semiconductor substrate, which is the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 1.

3. In the heating step, the first semiconductor substrate is heated so that the curing rate of the first organic insulating layer is 70% or more. The method for manufacturing a semiconductor device according to claim 1 or 2.

4. In the heating step, the first semiconductor substrate is heated so that the curing rate of the first organic insulating layer is 90% or more. The method for manufacturing a semiconductor device according to claim 1 or 2.

5. In the heating step, the second semiconductor substrate is heated so that the curing rate of the second organic insulating layer is 60% or less. The method for manufacturing a semiconductor device according to any one of claims 1 to 4.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein when joining the first organic insulating layer and the second organic insulating layer, the curing rate of the second organic insulating layer is 10% or less.

7. The method for manufacturing a semiconductor device according to claim 6, wherein when joining the first organic insulating layer and the second organic insulating layer, the second organic insulating layer is in an uncured state.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, further comprising a step of reheating the joined body of the first semiconductor substrate and the second semiconductor substrate after the joining step, wherein the reheating temperature in the step of reheating the joined body is higher than the heating temperature in the step of heating at least one of the first semiconductor substrate and the second semiconductor substrate.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the first organic insulating layer and the second organic insulating layer contain a photosensitive resin composition, and the photosensitive resin composition contains the curable resin.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the photosensitive resin composition contains an alkali-soluble resin having a phenolic hydroxyl group, a compound that generates an acid upon irradiation with light, the thermal crosslinking agent, and an acrylic resin.

11. The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the first organic insulating layer and the second organic insulating layer contain a polyimide resin.

12. The method for manufacturing a semiconductor device according to any one of claims 1 to 11, wherein the first organic insulating layer and the second organic insulating layer are formed from the same type of resin material, and the step of heating at least one of the first semiconductor substrate and the second semiconductor substrate includes a step of heating the first semiconductor substrate at a first temperature and a step of heating the second semiconductor substrate at a second temperature, and the first temperature is higher than the second temperature.

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