Circuit board and semiconductor package comprising same

Abstract

An embodiment of the present invention provides a circuit board comprising: a core layer including a top surface, a bottom surface, and a via hole passing through the top surface and the bottom surface; and a via electrode disposed in the via hole, wherein: the via electrode includes a first metal part and a second metal part surrounding at least a portion of the first metal portion and comprising a different material from the first metal part; and the first metal part is disposed between the second metal part and the inner wall of the via hole.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of circuit boards, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In particular, as circuit boards become increasingly thinner, deformations such as warping and twisting that occur during circuit board manufacturing are increasing. To prevent this, a glass core structure, in which a glass plate is formed in the core portion of the circuit board, has been proposed.

[0007] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, in which warpage is suppressed and electrical characteristics are improved through a glass layer having high rigidity and a small coefficient of thermal expansion.

[0008] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability by forming a first metal part with high adhesion to a core layer and a second metal part within a via hole, thereby suppressing via formation.

[0009] In addition, the embodiment can implement a circuit board and a semiconductor package including the same with improved reliability of a via electrode through a first metal portion composed of a plurality of layers.

[0010] In addition, the embodiment can realize a circuit board and a semiconductor package including the same with improved structural reliability through stress balancing by ensuring chemical balance and causing the center axis of the via hole and the center axis of the via electrode in the core layer to be deviated so that stress is not concentrated during the formation of the electrode portion.

[0011] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0012] A circuit board according to an embodiment of the present invention comprises: a core layer including an upper surface and a lower surface, and a via hole penetrating the upper surface and the lower surface; and a via electrode disposed in the via hole; wherein the via electrode includes a first metal portion, a second metal portion surrounding at least a portion of the first metal portion and made of a different material from the first metal portion, and the first metal portion is disposed between the second metal portion and an inner wall of the via hole.

[0013] The second metal portion may include an upper metal layer adjacent to the upper surface of the core layer and a lower metal layer adjacent to the lower surface of the core layer.

[0014] The upper metal layer and the lower metal layer may be spaced apart from each other.

[0015] The first metal portion includes a seed layer arranged on the inner wall of the via hole, and the seed layer, the upper metal layer, and the lower metal layer can each overlap the inner wall of the via hole in a horizontal direction.

[0016] The first metal portion includes an inner electrode portion arranged inside the seed layer, and the size of crystal grains of the inner electrode portion may be larger than the size of crystal grains of the seed layer.

[0017] The above via hole may have a width that increases from the central portion toward the lower surface of the core layer, and a width that increases from the central portion toward the upper surface of the core layer.

[0018] The seed layer may have a ring-shaped exposed surface exposed from the upper or lower surface of the core layer.

[0019] The seed layer may increase in width from the central portion of the core layer toward the upper or lower surface of the core layer.

[0020] The above seed layer may have different extension directions from the center of the via hole toward the upper surface and from the center of the via hole toward the lower surface.

[0021] The above seed layer may include a material having a higher oxygen affinity than the inner electrode portion.

[0022] It may include a metal insulating layer disposed on the first metal portion.

[0023] The above metal insulating layer may be located on the inner side of the first metal portion on the upper or lower surface of the via electrode.

[0024] The second metal portion may be located on the inner side of the metal insulating layer on the upper or lower surface of the via electrode.

[0025] The thickness of the seed layer may be smaller than the thickness of the inner electrode portion.

[0026] A circuit board according to a third embodiment of the present invention comprises: a core layer including an upper surface, an upper surface, and a lower surface, and a first via hole penetrating the upper surface and the lower surface; an insulating layer disposed in the first via hole; and a via electrode disposed in the first via hole and penetrating the insulating layer; wherein a first horizontal central axis of the first via hole is misaligned with a second horizontal central axis of the via electrode.

[0027] The above via electrode includes a side surface facing the inner wall of the first via hole, and a horizontal length between the side surface of the via electrode and the inner wall of the first via hole may be different from each other along the perimeter of the side surface of the via electrode.

[0028] The above via electrode can penetrate the core layer and the insulating layer.

[0029] The first via hole may include a first region whose width decreases from the upper surface of the core layer toward the lower surface, and a second region whose width increases from the first region toward the lower surface of the core layer.

[0030] The width of the above via electrode may decrease from the upper surface of the core layer toward the lower surface of the core layer.

[0031] The core layer may include a second via hole spaced apart from the first via hole.

[0032] The above via electrode may include a first via electrode disposed within the first via hole and a second via electrode disposed within the second via hole.

[0033] A first length in the horizontal direction between the first via electrode and the inner wall of the first via hole and a third length in the horizontal direction between the second via electrode and the inner wall of the second via hole may be different from each other.

[0034] The first via hole may be closer to the center of a plane perpendicular to the stacking direction in the core layer than the second via hole.

[0035] The first length may be greater than the third length.

[0036] With respect to the third central axis of the second via hole, the second via electrode may be spaced apart from the first central axis.

[0037] The third central axis of the second via hole and the fourth central axis of the second via electrode may be misaligned.

[0038] An embodiment of the present invention provides a circuit board and a semiconductor package including the same, in which warpage is suppressed and electrical characteristics are improved through a glass layer having high rigidity and a small coefficient of thermal expansion.

[0039] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability by forming a first metal portion having high adhesion to a core layer and a second metal portion within a via hole, thereby suppressing via formation.

[0040] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved reliability of a via electrode through a first metal portion composed of a plurality of layers.

[0041] In addition, the embodiment can provide a circuit board and a semiconductor package including the same with improved structural reliability through stress balancing by ensuring chemical balance and causing the center axis of the via hole and the center axis of the via electrode in the core layer to be deflected so that stress is not concentrated during formation of the electrode portion.

[0042] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0043] Figure 1 is a plan view of a circuit board according to a first embodiment of the present invention.

[0044] Figure 2 is a drawing taken along line AA' in Figure 1,

[0045] Figure 3 is an enlarged view of K1 in Figure 2,

[0046] Fig. 4 is a plan view of a core layer and a via electrode in a circuit board according to the first embodiment.

[0047] Figure 5 is an enlarged view of K2 in Figure 2,

[0048] Figure 6 is an enlarged view of K3 in Figure 2,

[0049] Fig. 7 is a modified example of Fig. 5,

[0050] Fig. 8 is a modified example of Fig. 3,

[0051] Fig. 9 is another modified example of Fig. 3,

[0052] Figures 10 to 16 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0053] Fig. 17 is a cross-sectional view of a circuit board according to the second embodiment,

[0054] Figure 18 is an enlarged view of K4 in Figure 17,

[0055] Fig. 19 is a plan view of a core layer and a via electrode in a circuit board according to the second embodiment.

[0056] Figure 20 is an enlarged view of K5 in Figure 17,

[0057] Figure 21 is an enlarged view of K6 in Figure 17,

[0058] Fig. 22 is a modified example of Fig. 18,

[0059] Figure 23 is a plan view of a circuit board according to a third embodiment of the present invention.

[0060] Figure 24 is a drawing taken along line BB' in Figure 23.

[0061] Fig. 25 is a plan view of the insulating layer, via electrode, and via hole of the core layer in the circuit board according to the third embodiment.

[0062] Figure 26 is an enlarged view of K7 in Figure 24,

[0063] Figure 27 is an enlarged view of K8 in Figure 24,

[0064] Figure 28 is a drawing taken along the CC' line in Figure 23.

[0065] Fig. 29 is another plan view of the via hole of the insulating layer, via electrode, and core layer in the circuit board according to the third embodiment.

[0066] Figure 30a is a plan view of a circuit board according to the third embodiment,

[0067] Figure 30b is a plan view of a circuit board according to a modified example,

[0068] Figures 31 to 38 are drawings explaining a method for manufacturing a circuit board according to a third embodiment of the present invention.

[0069] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0070] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0071] Terms including ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0072] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0073] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0074] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0075] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0076] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various connecting members (e.g., semiconductor elements) may be mounted on the semiconductor package.

[0077] A connecting member can connect different dies (e.g., a central processor (CPU), a graphics processor (GPU), a digital signal processor, an application processor (AP), etc.). The connecting member can also be located within an interposer or a package substrate.

[0078] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0079] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0080] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0081] In the circuit board according to the embodiment of the present invention, the insulating layer may be formed of a plurality of insulating layers. The insulating layer may include a core layer (a glass layer described below) and an insulating layer.

[0082] In particular, as the integration density of semiconductor devices increases and multi-pin and miniaturization are promoted, a circuit board according to an embodiment, on which a semiconductor device having an increased number of pins and miniaturization is mounted, may be a multilayer printed circuit board using a built-up method. For example, the circuit board may be a multilayer circuit board having a build-up layer formed on the surface and back surface of a core layer.

[0083] In such multilayer circuit boards, the core layer uses, for example, a resin substrate (e.g., a glass epoxy substrate) in which reinforcing fibers are impregnated with resin, as described above. Furthermore, by utilizing the rigidity of the core substrate, a plurality of build-up layers can be formed by alternately laminating resin insulating layers and conductive layers on the front and back surfaces of the core substrate. Accordingly, the insulating layer (120) can correspond to a "build-up layer."

[0084] The build-up layer serves as an internal insulating layer of a circuit board on which circuit patterns, etc. are formed, and an insulating material is used as the forming material. As the insulating material, as described below, a thermosetting resin and / or a photocurable resin may be used, and an Ajinomoto build-up film may also be used, but is not particularly limited thereto.

[0085] Additionally, when forming dummy grooves and / or via holes in the build-up layer, laser processing and / or photolithography may be used depending on the insulating material.

[0086] Alternatively, a material with a high modulus can be used as the insulating material, and in addition, a material with a small curing shrinkage itself can be used, or an anisotropic material with a dominant vertical shrinkage can be used.

[0087] These build-up layers may be multiple layers and may be formed using the same materials or may be formed using different materials.

[0088] FIG. 1 is a plan view of a circuit board according to a first embodiment of the present invention, FIG. 2 is a view taken along line AA' in FIG. 1, FIG. 3 is an enlarged view of K1 in FIG. 2, FIG. 4 is a plan view of a core layer and a via electrode in a circuit board according to the first embodiment, FIG. 5 is an enlarged view of K2 in FIG. 2, FIG. 6 is an enlarged view of K3 in FIG. 2, FIG. 7 is a modified example of FIG. 5, FIG. 8 is a modified example of FIG. 3, and FIG. 9 is another modified example of FIG. 3.

[0089] Referring to FIGS. 1 and 2, a circuit board (100) according to the first embodiment may include a core layer (110), an insulating layer (120), a protective layer (130), and an electrode portion (140). In addition, the circuit board (100) according to the embodiment may include a semiconductor element (SD) and a conductive member (CB1, CB2) positioned on one side (e.g., an upper side).

[0090] A circuit board (100) according to the first embodiment may include a core layer (110), an insulating layer (120), a protective layer (130), and an electrode portion (140). In addition, the circuit board (100) according to the embodiment may include a semiconductor element (SD) and a conductive member (CB1, CB2) positioned on one side (e.g., the upper side).

[0091] The core layer (110) may be a 'core layer' or a 'substrate layer'. The core layer (110) can suppress warpage that occurs due to thinning of the circuit board. In other words, warpage can be reduced by placing a glass layer (or glass core) with high rigidity and a low coefficient of thermal expansion (CTE) at the center or core of the circuit board. For example, the core layer (110) may have high rigidity and a low coefficient of thermal expansion compared to an insulating layer or a protective layer.

[0092] And the core layer (110) can be made of a glass material. For example, the core layer (110) can include pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc., and is not limited to silicon-based glass compositions, and alternative glass materials such as fluorine glass, phosphate glass, chalcogen glass, etc. can also be used. In addition, the core layer (110) can further include other additives to form a glass having specific physical properties. These additives can include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these elements and other elements.

[0093] Additionally, the core layer (110) may be made of an insulating material. Accordingly, the core layer (110) may be referred to as an ‘insulating layer’.

[0094] Additionally, the core layer (110) may be positioned at the center of the insulating layer (120). Additionally, the core layer (110) may include a via hole (110h) as described below. The via holes (110h) may have various shapes and be formed at various locations, different from the number and structure illustrated in the drawing.

[0095] The insulating layer (120) can surround at least a portion of the core layer (110). For example, the insulating layer (120) can be positioned on the outer side of the core layer (110). Accordingly, damage to the core layer (110) can be prevented. In addition, the insulating layer (120) can be positioned on the upper or lower side of the core layer (110). In an embodiment, the insulating layer (120) can be in contact with the outer surface of the core layer (110) or the upper or lower surface. In an embodiment, the insulating layer (120) can be formed of a plurality of insulating layers. The plurality of insulating layers can be formed of the same insulating material or different insulating materials.

[0096] As an example, the insulating layer (120) may include a first insulating layer (121) and a second insulating layer (122) disposed above or below the core layer (110).

[0097] The first insulating layer (121) and the second insulating layer (122) may be positioned above and below the core layer (110), respectively. For example, the first insulating layer (121) may be positioned above the core layer (110). And the second insulating layer (122) may be positioned below the core layer (110). For example, the first insulating layer (121) may be in contact with the upper surface of the core layer (110). And the second insulating layer (122) may be in contact with the lower surface or bottom surface of the core layer (110).

[0098] The insulating layer (120) may be formed of multiple layers depending on the structure or design of the circuit board (100) as described above. For example, the first insulating layer (121) may be formed of multiple insulating layers. And the second insulating layer (122) may be formed of multiple insulating layers.

[0099] Additionally, a plurality of circuit patterns, via holes, etc. may be positioned in the insulating layer (120). For example, a via hole in the insulating layer (120) may be connected to a via hole in the core layer (110). In other words, a via electrode positioned in a via hole in the insulating layer (120) may be electrically connected to a via electrode positioned in a via hole in the core layer (110).

[0100] The insulating layer (120) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layer (120) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0101] For example, the insulating layer (120) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (120) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (120) may include a plurality of layers composed of ABF.

[0102] The protective layer (130) may be positioned above or below the insulating layer (120). For example, the protective layer (130) may include a first protective layer (131) positioned above the first insulating layer (121) and a second protective layer (132) positioned below the second insulating layer (122).

[0103] The protective layer (130) can have the function of protecting the pad from external moisture or contaminants, and to prevent short circuit problems caused by the occurrence of solder bridges, etc. during solder bonding between the semiconductor element and / or the main board and the circuit board, the protective layer (130) may be provided with a solder resist that does not have good solder wettability, for example. Specifically, the semiconductor element and / or the main board, etc. have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are joined, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good solder wettability may be arranged to solve this short circuit problem. In addition, the protective layer (130) may be formed of a material that has insulating properties for electrical connection. Accordingly, the protective layer (130) may be referred to as an 'insulating layer' and may be a component of the above-described insulating layer (120). The protective layer (130) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. In addition, the third insulating layer (not shown) may include any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0104] And the insulating layer or protective layer (130) located in the outer laminated area of ​​the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor elements, circuit boards, etc.

[0105] For the electrical connection described above, conductive members (CB1, CB2) may be positioned on the upper or lower portion of the circuit board (100). The conductive member (CB1) positioned on the upper portion may perform electrical connection with the semiconductor element (SD) and the electrode portion (140). In addition, the conductive member (CB2) positioned on the lower portion may perform electrical connection with another substrate, etc.

[0106] In an embodiment, a wiring or electrode portion (140) may be arranged for electrical connection between a main board, etc. and a chip (or semiconductor device (SD), die). In addition, the electrode portion (140) may include a circuit pattern (or circuit pattern layer), pad, or via electrode. The wiring may correspond to an 'electrode pattern', a 'pattern', a 'line', etc.

[0107] In the electrode portion (140), the circuit pattern can be designed in various forms for transmitting signals and / or power to the semiconductor element, and is placed within each laminated insulating layer (120).

[0108] In the electrode portion (140), via electrodes are arranged to penetrate a portion of each insulating layer for vertical connection between circuit patterns arranged on each vertically stacked core layer and insulating layer. That is, the insulating layer may include a via hole (e.g., 110h) for arrangement of the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for optimization of impedance or heat dissipation, but is not limited thereto and may be freely designed.

[0109] In the electrode portion (140), pads (e.g., 142) may be arranged on each insulating layer. And the pads (e.g., 142) may be electrically connected to a circuit pattern. In addition, the pads (e.g., 142) may be electrically connected to a semiconductor element and / or a main board or substrate, etc. In addition, the pads (e.g., 142) may be electrically connected to a via electrode.

[0110] In particular, pads positioned on the outer side of the pads can be bonded to semiconductor elements, substrates, boards, etc. using solder, wires, conductive adhesives, etc., and may be positioned with a width greater than the width of the circuit pattern to solve problems such as securing yield. However, this is not limited to this, and may have a width equal to the width of the circuit pattern depending on the technical limitations of the bonding process.

[0111] And the pads arranged on the inside have the function of connecting the via electrodes and the circuit patterns. When the via electrodes are arranged with a wider width than the circuit patterns, pads having a wider width than the circuit patterns are provided for positional alignment during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is positioned on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is positioned on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0112] The semiconductor device (SD) may be mounted on the upper portion of the circuit board (100). The semiconductor device (SD) may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above-mentioned elements. In addition, the memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory. The semiconductor device (SD) may be electrically connected to the electrode unit (140) through the conductive member (CB2) described above.

[0113] Circuit boards can be divided into package boards and interposers based on their function. The package board serves the function of mounting semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, to improve the yield of circuit boards with a high number of layers, the yield of the circuit board can be improved by separating them into an interposer and a package board. In addition, as the terminal density of semiconductor devices increases, it can be difficult to implement pads on the package board with an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package board can act as a buffer between the size of the pad and the fine pattern size of the terminals of the semiconductor devices.

[0114] In addition, an additional member (not shown) may be disposed within the core layer (110). The additional member (not shown) may be used interchangeably with a 'semiconductor element', a 'chip', a 'die', etc. In addition, the additional member (not shown) may be disposed within a cavity including a groove or hole within the core layer (110) as a connecting member and may be electrically connected to other multiple semiconductor elements disposed on the upper portion of the circuit board. The connecting member (not shown) is made of Si and may be referred to as a bridge. In this way, the connecting member (not shown) may be referred to as a bridge substrate. For example, the connecting member (not shown) may include a redistribution layer. The connecting member (not shown) may have a function of horizontally electrically connecting multiple semiconductor elements to each other. For example, the connecting member (not shown) may include a redistribution layer because the area that a semiconductor element should generally have is too large. Because semiconductor packages and semiconductor devices have significantly different circuit pattern widths and depths, a buffering function for the circuit pattern is necessary for electrical connection. This buffering function can mean ensuring that the circuit pattern width and depth of the semiconductor package are intermediate in size to the circuit pattern width and depth of the semiconductor device. The redistribution layer can also include a buffering function.

[0115] Additionally, the connecting member (not shown) may be an organic bridge. For example, the connecting member (not shown) may include an organic material. For example, the connecting member (not shown) may include an organic substrate containing an organic material instead of a silicon substrate.

[0116] Additionally, the connecting member (not shown) may include a connecting portion for electrical connection on one surface. Furthermore, a filling member may be disposed within the cavity. The filling member may surround the connecting member (not shown). The filling member may secure the connecting member (not shown) disposed within the cavity to the cavity. The filling member may be formed of an insulating material.

[0117] When a connecting member (not shown) is embedded in the core layer (110), it may be placed within a through hole (not shown) that penetrates the upper and lower surfaces of the core layer (110), or may be placed within a recess (not shown) that penetrates only a portion of the upper surface of the core layer (110) toward the lower surface of the core layer (110). In this case, the connecting member (not shown) may overlap the first metal portion (SL) described later in a horizontal direction to improve thermal expansion coefficient matching between the core layer (110), the first metal portion (SL), and the connecting member (not shown), thereby improving the reliability of the circuit board.

[0118] In addition, the connecting member (not shown) may be embedded in the inner insulating layer disposed on the core layer (110). Therefore, the connecting member (not shown) can improve the communication characteristics between the semiconductor elements (SD) by shortening the length of the electrical line with the semiconductor elements (SD) disposed on the circuit board. In addition, by overlapping with the first metal portion (SL) in the vertical direction, the overall thermal expansion coefficient matching of the circuit board can be improved, thereby improving the reliability of the circuit board. In the present specification, "disposed on" is used to mean either directly in contact or not in direct contact.

[0119] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In an embodiment according to the present invention, a circuit substrate having a core layer including glass is described.

[0120] Referring further to FIGS. 3 and 4, the core layer (110) according to the embodiment may include a bottom surface (BS) and an upper surface (US). The bottom surface (BS) and the upper surface (US) may be outer surfaces facing each other in the stacking direction or the vertical direction in the core layer (110).

[0121] For example, the first insulating layer (121) may be positioned on the upper portion of the core layer (110) in the vertical direction or the stacking direction (Z-axis direction). And the first insulating layer (121) may be in contact with the core layer (110). That is, the bottom surface of the first insulating layer (121) may be in contact with the top surface (US) of the core layer (110). For example, the bottom surface of the first insulating layer (121) and the top surface (US) of the core layer (110) may be in the same plane. And the second insulating layer (122) may be in contact with the bottom surface (BS) of the core layer (110). The top surface of the second insulating layer (122) may be in the same plane as the bottom surface (BS) of the core layer (110).

[0122] The core layer (110) may be a ‘glass layer’ as described above and may be made of glass material.

[0123] As an example, the core layer (110) may include a via hole (110h). The core layer (110) may include a via hole (110h). The via hole (110h) may penetrate the core layer (110). For example, the via hole (110h) may penetrate the upper surface (US) and the lower surface (BS) of the core layer (110).

[0124] The via hole (110h) may have a structure in which the diameter or width increases from the center toward the upper surface and the lower surface (bottom surface) of the core layer (110). For example, the diameter of the via hole (110h) may increase from the center of the core layer (110) toward the upper surface (US) and the lower surface (BS) within the core layer (110). Accordingly, the inner wall (or inner wall or inner side wall) of the via hole (110h) may be inclined with respect to the upper surface (US) and the lower surface (BS).

[0125] Furthermore, there may be multiple core layers (110). In addition, there may also be multiple via holes (110h) in the core layer (110). For example, when there are multiple core layers (110), each core layer (110) may overlap or not overlap in the stacking direction.

[0126] For example, the central axis of a via hole (110h) of one core layer and the central axis of a via hole of another core layer may be misaligned or overlap.

[0127] In an embodiment, the via hole (110h) may have a diameter that increases from the center toward the bottom surface (BS). The via hole (110h) may have a diameter that increases from the center toward the top surface (US). That is, in an embodiment, the diameter of adjacent via holes may increase toward the surface where they contact each other.

[0128] The central axis (AX) of the via hole (110h) may be parallel to the stacking direction. Furthermore, the central axis (AX) may be an axis that horizontally bisects the via hole (110h). For example, the via hole (110h) may have the same diameter with respect to the central axis (AX). In this case, the diameter may increase or decrease along the stacking direction. In addition, the via hole (110h) may have a symmetrical structure with respect to the central axis (AX).

[0129] Additionally, the electrode portion (140) may include a via electrode (141), an upper pad (142, 146), a lower pad (143, 147), a first through-hole electrode (144), and a second through-hole electrode (145).

[0130] The via electrode (141) may be placed in the via hole (110h). And the upper pads (142, 146) may be located on the core layer (110) or on the first insulating layer (121). The lower pads (143, 147) may be located on the lower side of the core layer (110) or the lower side of the second insulating layer (122). For example, the upper pad (142) may be located on the upper surface (US) of the core layer (110). And the upper pad (142) may be connected to the via electrode (141). In addition, the upper pad (142) may be connected to the first through-hole electrode (144). And the upper pad (146) may be connected to the first through-hole electrode (144). In addition, the lower pad (143) may be located on the lower side (BS) of the core layer (110). Additionally, the lower pad (143) can be connected to the second through-hole electrode (145). And the lower pad (147) can be connected to the second through-hole electrode (145). And the lower pad (147) can be connected to the bottom surface of the second insulating layer (122).

[0131] The first through-electrode (144) may be placed in the through-hole of the first insulating layer (121). The through-electrode may be positioned parallel to the via hole (110h). The via hole (110h) may overlap at least partially with the through-electrode in the stacking direction. Furthermore, the central axis of the through-electrode may correspond to the central axis (AX) of the via hole (110h). For example, the central axis of the through-electrode may overlap with the central axis (AX) of the via hole (110h). However, the present invention is not limited thereto, and the central axis of the through-electrode and the central axis of the via hole (110h) may be positioned to be misaligned.

[0132] The second through-hole electrode (145) may be positioned in a through-hole of the second insulating layer (122). The through-hole may be positioned parallel to the via-hole (110h). For example, the through-hole may at least partially overlap with the via-hole (110h) in the stacking direction. Similarly, the through-hole of the second insulating layer (122) may be positioned so that its central axis overlaps or is misaligned with the via-hole (110h).

[0133] Furthermore, the via electrode (141) may include a first metal portion (SL) and a second metal portion (EL). In the circuit board according to the embodiment, the first metal portion (SL) may be positioned on the inner wall (IS) of the via hole (110h). In addition, the first metal portion (SL) may be positioned adjacent to the bottom surface (BS) and the top surface (US) of the core layer (110). For example, the first metal portion (SL) may be positioned adjacent to the top and bottom along the stacking direction within the via hole (110h) of the core layer (110).

[0134] In addition, the second metal portion (EL) may be arranged on the inner wall (IS) of the via hole (110h) of the core layer (110), and the side and upper surface of the first metal portion (SL) within the via hole (110h). That is, the second metal portion (EL) may cover the first metal portion (SL) that is arranged on a portion of the inner wall (IS) of the via hole (110h) within the via hole (110h) of the core layer (110), and may also be arranged on the inner wall (IS) of the via hole (110h) where the first metal portion (SL) is not arranged. With respect to the arrangement relationship, the second metal portion (EL), the first metal portion (SL), and the core layer (110) may be sequentially arranged outside the central axis (AX) with respect to the central axis (AX). Additionally, the second metal part (EL) and the core layer (110) can be sequentially arranged outside the central axis (AX) based on the central axis (AX).

[0135] The inner wall (IS) of the via hole (110h) may include a second region (S2) disposed between a first region (S1) adjacent to the bottom surface (BS) and the top surface (US) of the core layer (110). For example, the first region (S1) may be a region spaced apart from the top surface (US) and the bottom surface (BS) in the stacking direction by a predetermined distance on the inner wall (IS). In addition, the first region (S1) may have a plurality of regions, including a region adjacent to the top surface (US) on the inner wall (IS) and a region adjacent to the bottom surface (BS). In addition, the second region (S2) may be a region disposed between the first region (S1) adjacent to the top surface (US) and the first region (S1) adjacent to the bottom surface (BS) on the inner wall (IS).

[0136] In addition, the first metal portion (SL) according to the embodiment may be in contact with the first region (S1). Alternatively, the first metal portion (SL) may be disposed in the first region (S1). The first metal portion (SL) may include an upper metal portion adjacent to the upper surface (US) of the core layer (110) and a lower metal portion adjacent to the lower surface (BS) of the core layer. The upper metal portion may be disposed on the first region adjacent to the upper surface. For example, the upper metal portion may overlap with the first region in a horizontal direction. The lower metal portion may be disposed on the first region adjacent to the lower surface (BS). For example, the lower metal portion may overlap with the first region in a horizontal direction. The first metal portions on the first region may be disposed spaced apart from each other in the stacking direction. For example, the upper metal portion and the lower metal portion may be disposed spaced apart from each other.

[0137] And the second metal portion (EL) can be in contact with the second region (S2). The second metal portion (EL) can be arranged in the second region (S2). In an embodiment, the second metal portion (EL) can include an upper metal layer (EL1) adjacent to the upper surface (US) of the core layer (110) and a lower metal layer (EL2) adjacent to the lower surface (BS) of the core layer. The upper metal layer can be arranged on the first region adjacent to the upper surface. The second metal portions on the first region can be arranged to be spaced apart from each other in the stacking direction. For example, the upper metal layer (EL1) and the lower metal layer (EL2) can be arranged to be spaced apart from each other.

[0138] For example, the upper metal layer may overlap horizontally with the first region. The lower metal layer may be disposed on the first region adjacent to the bottom surface (BS). For example, the lower metal layer may overlap horizontally with the first region.

[0139] The second metal portion (EL) can cover the inner side of the first metal portion (SL) or the first metal portion (SL). The second metal portion (EL) can surround at least a portion of the first metal portion (SL). And the first metal portion (SL) can be disposed between the second metal portion (EL) and the inner wall (IS) of the via hole. The second metal portion (EL) can be made of a different material from the first metal portion (SL). And the second metal portion (EL) can be disposed between the first metal portion (SL) and the inner wall of the via hole (110h).

[0140] According to an embodiment, the first metal portion (SL) may include a material such as a metal. The second metal portion (EL) may also be made of a material such as a metal. The first metal portion (SL) may be made of a material such as Ti, Cr, Ta, etc. The second metal portion (EL) may be made of a material such as Pd, Ni, Au, Cu, Ag, etc. Furthermore, both the first metal portion (SL) and the second metal portion (EL) may be made of a conductive material.

[0141] And the first metal part (SL) may include a seed layer disposed on the inner wall (IS) of the via hole (110h) and an inner electrode part disposed inside the seed layer. However, when the inner electrode part and the second metal part (EL) are made of the same material, the inner electrode part may be formed integrally with the second metal part. Accordingly, the second metal part (EL) and the inner electrode part may form a plating layer. Alternatively, the inner electrode part and the seed layer may be made of different materials. A structure in which the inner electrode part and the seed layer are made of different materials is illustrated in FIG. 9. That is, the second metal part (EL), which is a plating layer, may be positioned inside the seed layer and the inner electrode part. For example, the second metal part (EL), which is a plating layer, the inner electrode part, and the seed layer may be sequentially disposed toward the outside from the central axis of the via hole (110h). Furthermore, the size of the crystal grains of the inner electrode part may be larger than the size of the crystal grains of the seed layer. A detailed explanation of this will be provided later.

[0142] Furthermore, in this embodiment, it is described that the inner electrode portion and the seed layer are made of the same material. Accordingly, the first metal portion (SL) may be a seed layer disposed on or in contact with the inner wall (IS) of the via hole (110h).

[0143] Accordingly, in the embodiment, the seed layer, the upper metal layer (EL1), and the lower metal layer (EL2) which are the first metal portion (SL) may overlap the inner wall (IS) of the via hole (110h) along the horizontal direction. For example, the inner wall (IS), the seed layer, which is the first metal portion (SL), and the upper metal layer (EL1) of the second metal portion (EL) may overlap in the horizontal direction (X-axis direction). In addition, the inner wall (IS), the seed layer, which is the first metal portion (SL), and the lower metal layer (EL2) of the second metal portion (EL) may overlap in the horizontal direction.

[0144] In an embodiment, the first metal portion (SL) may be formed of a material having a higher oxygen affinity than the second metal portion (EL). Accordingly, the first metal portion (SL) may have improved bonding strength with the core layer (110) than the second metal portion (EL). That is, the first metal portion (SL) may have excellent adhesion to the core layer (110) made of an insulating material. In addition, the first metal portion (SL) may also have excellent adhesion with the second metal portion (EL). Accordingly, the occurrence of voids between the second metal portion (EL) and the core layer (110) may be easily suppressed. In other words, the structural reliability of the via electrode (141) within the core layer (110) may be improved.

[0145] Additionally, as illustrated in FIGS. 3 and 4, the via electrode (141) may include an upper surface (EUS) and a lower surface (EBS). And the first metal portion (SL) may be positioned at the edge of the upper surface (EUS) and the lower surface (EBS) of the via electrode (141).

[0146] As described above, the first metal portion (SL) may be positioned adjacent to at least one of the upper surface (US) and the lower surface (BS) of the core layer (110) within the via hole (110h). For example, the first metal portion (SL) may be positioned adjacent to the upper surface (US) of the core layer (110). In this case, the first metal portion (SL) may be positioned only at the edge of the upper surface (EUS) of the via electrode (141). That is, the first metal portion (SL) may not be present at the edge of the lower surface (EBS) of the via electrode (141).

[0147] In addition, the first metal portion (SL) may be exposed on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141). Accordingly, it may also be in contact with or connected to the upper pad or the lower pad. The first metal portion (SL) may have a ring-shaped exposed surface on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141). In other words, the seed layer may have a ring-shaped exposed surface on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141). For example, the exposed surface exposed on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141) may have a closed-loop circular shape.

[0148] In addition, the seed layer, which is the first metal portion (SL), may have a width (W1) that increases from the central portion of the core layer (110) toward the upper surface (US) or the lower surface (BS) of the core layer (110). For example, the seed layer, which is the first metal portion (SL), may have a width that increases from the central portion of the core layer (110) toward the upper surface (US) of the core layer (110). The seed layer, which is the first metal portion (SL), may have a width that increases from the central portion of the core layer (110) toward the lower surface (BS) of the core layer (110). That is, the seed layer, which is the first metal portion (SL), may have a ring shape with a plane perpendicular to the vertical direction and may have the smallest area at the center of the core layer.

[0149] Furthermore, as an example, the seed layer, which is the first metal portion (SL), may be arranged along the inner wall (IS) of the via hole (110h). Accordingly, the seed layer, which is the first metal portion (SL), may be arranged to be inclined with respect to the upper surface (US) or the lower surface (BS) of the core layer (110). In addition, the direction in which the seed layer, which is the first metal portion (SL), extends from the central portion of the via hole (110h) toward the upper surface (US) of the core layer (110) and the direction in which the seed layer extends from the central portion of the via hole (110h) toward the lower surface (BS) of the core layer (110) may be different.

[0150] And the second metal portion (EL) may be positioned on the inner side of the first metal portion (SL) on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141). With respect to the central axis (AX), the second metal portion (EL) and the first metal portion (SL) may be positioned sequentially toward the outside on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141).

[0151] Additionally, in the embodiment, the thickness (T2) of the second metal portion (EL) may be greater than the thickness (T1) of the first metal portion (SL). This can effectively provide improved bonding strength, easy via-fill, and reduced manufacturing costs.

[0152] In addition, in the embodiment, integration may occur when the material between the layer closest to the central axis among the first metal portion (SL) and the second metal portion (EL) is the same. However, integration may not occur when the material between the layer closest to the central axis among the first metal portion (SL) and the second metal portion (EL) is different. For example, when the layer closest to the central axis among the first metal portion (SL) and the second metal portion (EL) are made of the same material, Cu, the first metal portion (SL) may exist as a 'first metal portion' only in layers other than the layer closest to the central axis. In addition, the second metal portion (EL) may be formed by the layer closest to the central axis among the first metal portion and the second metal portion formed within the first metal portion.

[0153] For example, the first metal portion (SL) may be formed of multiple layers. For example, if the first metal portion (SL) is formed of Ti / Cu, the Cu on the Ti may be formed into a single second metal portion by via-fill (e.g., plating) if the material of the second metal portion is the same as that of the second metal portion. Alternatively, if the via-fill is formed of a different material, the second metal portion may be formed on the first metal portion (SL) formed of multiple layers.

[0154] Referring further to FIGS. 5 and 6, the first metal portion (SL) and the second metal portion (EL) can be in contact with adjacent pads. On the upper surface (EUS) of the via electrode (141), the first metal portion (SL) and the second metal portion (EL) can be in contact with the upper pad (142). And on the lower surface (EBS) of the via electrode (141), the first metal portion (SL) and the second metal portion (EL) can be in contact with the lower pad (143).

[0155] The upper pad (142) may have a width or diameter greater than the first metal portion (SL) and the second metal portion (EL). The lower pad (143) may have a width or diameter greater than the first metal portion (SL) and the second metal portion (EL).

[0156] Referring further to FIG. 7, the second metal portion may be arranged to extend to the upper surface (US) of the core layer (110). Hereinafter, the first metal portion arranged on the upper surface (US) of the core layer (110) is described as an extended first metal portion (SL').

[0157] The first extension metal portion (SL') can be connected to the first metal portion (SL) of the via electrode (141). And, an extension second metal portion (EL') can be positioned within the first extension metal portion (SL').

[0158] And the upper pad (142) can be positioned on the upper portion of the first extended metal portion (SL'). In addition, the upper pad (142) can be positioned on the second extended metal portion (EL'). Accordingly, the upper pad (142) can be in contact with and electrically connected to the first extended metal portion (SL') and the second extended metal portion (EL').

[0159] Furthermore, the extended first metal portion (SL') may be positioned between the upper pad (142) and the core layer (110). The extended first metal portion (SL') may overlap the upper pad (142) in the stacking direction. The extended first metal portion (SL') may be made of a material having a higher oxygen affinity than the upper pad (142). Accordingly, the extended first metal portion (SL') may have a greater bonding strength with the core layer (110) than with the upper pad (142). Accordingly, the bonding strength with respect to not only the via electrode but also the pad located on the upper side of the core layer may be improved. Accordingly, a circuit board with improved electrical or structural reliability may be provided.

[0160] These contents can be equally applied to the lower portion of the via electrode (141). For example, the first metal portion (SL) on the lower surface (EBS) of the via electrode (141) can extend to the lower surface (BS) of the core layer (110). That is, the extended first metal portion (SL') can also be positioned on the lower surface (BS) of the core layer (110). In addition, the extended second metal portion (EL') can be positioned between the extended first metal portions (SL') on the lower portion of the via electrode (141). Furthermore, the extended first metal portion (SL') on the lower surface (BS) of the core layer (110) can also overlap with the lower pad in the stacking direction.

[0161] Referring further to Fig. 8, the first metal portion (SL) may further include an additional metal portion (SLi) present in the second region (S2). The additional metal portion (SLi) may be spaced apart from the first metal portion (SL) in contact with the first region (S1). The additional metal portion (SLi) may be in contact with the second region (S2) and may be covered by the second metal portion (EL). Accordingly, the bonding strength between the second metal portion (EL) and the core layer (110) in the second region (S2) may be improved. There may be a plurality of additional metal portions (SLi) and they may be spaced apart from each other.

[0162] Referring further to FIG. 9, the first metal portion (SL) may include a seed layer (SLa) and an inner electrode portion (SLb). As described above, the seed layer (Sla) and the inner electrode portion (SLb) may be formed of different materials. In addition, the seed layer (SLa) and the inner electrode portion (SLb) may be sequentially positioned toward the inner or central axis in the via hole (110h). For example, the seed layer (SLa) may be positioned between the inner electrode portion (SLb) and the core layer (110) (or the inner wall (IS) of the via hole (110h)).

[0163] And the seed layer may have a material having a higher oxygen affinity than the inner electrode portion. The size of the crystal grains of the inner electrode portion may be larger than the size of the crystal grains of the seed layer. And as described above, the size of the crystal grains of the inner electrode portion (SLb) may be larger than the size of the crystal grains of the seed layer (Sla). For example, the inner electrode portion (SLb) can suppress the occurrence of migration from the seed layer (SLa) to the internal second metal portion (EL). Accordingly, the inner electrode portion (SLb) can improve the reliability of the via electrode.

[0164] As described above, when the material between the layer closest to the central axis (inner electrode part) among the first metal part (SL) and the second metal part (EL) is the same, integration can occur, and when the materials are different as in Fig. 9, a distinction between the layers, for example, a boundary surface, can exist.

[0165] Figures 10 to 16 are drawings explaining a method for manufacturing a circuit board according to an embodiment.

[0166] The same components described above are given the same drawing reference numerals, and duplicate descriptions of the same components are omitted, with only the differences described.

[0167] Additionally, the circuit board according to the embodiment may correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board may be composed of unit circuit boards. The mother circuit board may be separated into a plurality of unit circuit boards along a sawing line.

[0168] To form such a circuit board, a glass layer can be first placed. The following describes the manufacturing of a unit circuit board.

[0169] Referring to FIG. 10, a method for manufacturing a core layer (or core substrate) in a circuit board according to an embodiment may first prepare a core layer (110) made of glass (S510). The core layer (110) may correspond to the core layer or core layers described above.

[0170] Referring to FIG. 11, a via hole (110h) can be formed in the core layer (110) (S515). The via hole (110h) can correspond to the via hole and the via hole described above. The via hole (110h) can be formed by performing etching on both sides of the core layer (110). For example, a via electrode can be formed in a via hole or a through hole of a glass layer. For example, the via hole (110h) can be formed by a photolithography process using a photomask, a laser method, or the like.

[0171] Referring to FIG. 12, a first metal portion (SL) can be formed on one surface (upper surface or lower surface) of the core layer (110) (S520). For example, the first metal portion (SL) can be formed on the upper surface (US), the lower surface (BS) of the core layer (110), and a portion of the inner wall of the via hole (110h). The formation of the first metal portion (SL) can be performed by a method such as sputtering.

[0172] For example, before performing sputtering, the surface of the core layer (110) can be treated with an ion beam. An ion beam refers to a group of charged molecules or atoms in the form of a mass of ion flow. When an electric field or a magnetic field is applied to this ion beam, the flow of ions can be accelerated. The accelerated ions become high-energy, and by shooting these ions at the surface of the core layer (110), the electrical properties of the surface of the core layer (110) are changed. Examples of gases used in the ion beam treatment process include argon (Ar) and nitrogen gas.

[0173] When ion beam treatment is performed, the surface roughness is higher than when ion beam treatment is not performed, but since it is possible to form a uniform first metal portion (SL) using only the sputtering process, it can be omitted if necessary.

[0174] If the first metal portion by sputtering is composed of multiple metal layers, the process can be performed multiple times as many times as the number of metal layers.

[0175] Sputtering is a technology that bombards a target (metal plate) with an inert element, such as argon, to expel metal molecules and then attach a film to the surface. By applying direct current to the target while flowing an inert gas as a sputtering gas in a vacuum chamber, plasma can be generated between the substrate to be deposited and the target. Within this plasma, the inert gas can be ionized into positive ions by a high-power DC current source. These positive ions can then be accelerated toward the cathode by the DC current source and collide with the surface of the target. Target materials that collide with the surface of the target can be ejected from the surface through perfectly elastic collisions between atoms, exchanging momentum. When ions collide with kinetic energy greater than the interatomic bonding energy of the material, the ion impact pushes the atoms between the lattices of the material to different locations, resulting in the escape of atoms from the surface. This phenomenon is called sputtering.

[0176] Accordingly, when sputtering is performed targeting a metal plate made of a metal material to be plated, a thin and uniform metal film can be formed by attaching to the metal atom core layer (110) protruding from the metal plate. Examples of the metal material include Ni, Cr, Cu, and Ti.

[0177] In an embodiment according to the present invention, at least one layer can be formed through sputtering. For example, a layer of Ti / Cu, Ni / Cu, etc. can be formed. At this time, the upper Cu layer can be formed as a second metal portion (EL) through plating.

[0178] Referring further to Fig. 13, a second metal portion (ELa) can be formed on the core layer (110) or on the first metal portion (SL) (S525). The second metal portion (ELa) can be formed by chemical copper plating.

[0179] Referring further to FIGS. 14 and 15, a second metal portion (EL) can be formed within a via hole by electroplating (S530). That is, an electrode portion can be formed through plating on the core layer (110) (S535). For example, a via electrode, a pattern electrode, etc. can be formed on the core layer (110) by performing plating on another groove formed on the via hole (110h) of the core layer (110).

[0180] And the electrode portion can be removed so that both sides of the core layer are exposed (S535). For example, a portion of the electrode portion can be removed by performing an e-window or polishing.

[0181] By this polishing, an electrode portion (140) is formed in the core layer (110), and for example, a via electrode (141) can be formed.

[0182] Referring to Fig. 16, a core layer of a circuit board according to an embodiment can be manufactured using the method described above. Thereafter, an insulating layer can be applied to the upper or lower portion of the core layer, and an electrode portion can be formed through a pattern groove or via hole. The circuit pattern in the electrode portion can be formed using a manufacturing process for a printed circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP).

[0183] Additionally, a protective layer may be formed on top or bottom of the insulating layer. Additionally, an opening area for a conductive member may be formed in the protective layer.

[0184] Fig. 17 is a cross-sectional view of a circuit board according to the second embodiment, Fig. 18 is an enlarged view of K4 in Fig. 17, Fig. 19 is a plan view of a core layer and a via electrode in a circuit board according to the second embodiment, Fig. 20 is an enlarged view of K5 in Fig. 17, Fig. 21 is an enlarged view of K6 in Fig. 17, and Fig. 22 is a modified example of Fig. 18.

[0185] Referring to FIGS. 17 to 21, a circuit board (100A) according to the second embodiment may include a core layer (110), an insulating layer (120), a protective layer (130), and an electrode portion (140). In addition, the circuit board (100) according to the embodiment may include a semiconductor element (SD) and conductive members (CB1, CB2) positioned on one side (e.g., the upper side). Furthermore, the above-described contents may be equally applied, except for the contents described below.

[0186] Furthermore, in the electrode portion (140), the via electrode (141) may include a metal insulating layer (MO). The metal insulating layer (MO) is an insulating material and may include an oxidized metal, etc. For example, the metal insulating layer (MO) may be made of TiO2, Al2O3, BaTiO3, TaO2, TaN, etc.

[0187] This metal insulating layer (MO) may be positioned on the first metal portion (SL). Furthermore, the metal insulating layer (MO) may be in contact with the inner wall of the via hole (110h). Specifically, the metal insulating layer (MO) may be in contact with the second region (S2) on the inner wall (IS) of the via hole (110h). Accordingly, the via hole (110h), the first metal portion (SL), the metal insulating layer (MO), and the second metal portion (EL) may be sequentially positioned toward the central axis.

[0188] The first metal portion (SL) may not be in contact with the second metal portion (EL) due to the metal insulating layer (MO). Therefore, even if the material of the layer closest to the central axis among the first metal portion (SL) and the material of the second metal portion (EL) are the same, they may be partitioned by the metal insulating layer (MO). In other words, integration between the layer closest to the central axis among the first metal portion (SL) and the second metal portion (EL) may not occur due to plating.

[0189] Accordingly, the first metal portion (SL) may include a seed layer and an inner electrode portion. The seed layer may be in contact with the inner wall (IS) of the via hole (110h). The inner electrode portion may be made of a different material from the seed layer and may be positioned on the seed layer. That is, the inner electrode portion may be positioned closer to the central axis (AX) than the seed layer. For example, the seed layer may be made of Ti and the inner electrode portion may be made of Cu. Alternatively, the inner electrode portion may be made of a different material from the second metal portion (EL).

[0190] Furthermore, the thickness of the seed layer can be smaller than that of the inner electrode. This configuration can significantly improve adhesion while maintaining electrical reliability.

[0191] As an example, on the inner wall (IS) of the via hole (110h), a seed layer, an inner electrode portion, a metal insulating layer (MO), and a second metal portion (EL) may be sequentially positioned toward the central axis (AX) on the first region (S1). And, on the second region (S2), a metal insulating layer (MO) and a second metal portion (EL) may be sequentially positioned toward the central axis (AX).

[0192] Accordingly, the first metal portion (SL) may be positioned at the edge of the upper surface (EUS) or the lower surface (EBS) of the via electrode (141), and the metal insulating layer (MO) may be positioned on the inner side of the first metal portion (SL) on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141). And the second metal portion (EL) may be positioned on the inner side of the metal insulating layer (MO) on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141).

[0193] In addition, as described above, the first metal portion (SL) may be exposed on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141). Accordingly, it may also be in contact with or connected to the upper pad or the lower pad. Furthermore, the metal insulating layer (MO) may also be exposed on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141). Accordingly, the metal insulating layer (MO) may also be in contact with or connected to the upper pad or the lower pad.

[0194] And the second metal portion (EL) may be located on the inner side of the first metal portion (SL) on the upper surface (EUS) or the lower surface (EBS) of the via electrode (141). In addition, the first metal portion (SL) may be located on the inner side of the metal insulating layer (MO) within the via hole (110h) based on the central axis (AX).

[0195] Additionally, the metal insulating layer (MO) can be in contact with the upper pad (142) on the upper surface (EUS) of the via electrode (141). And, the metal insulating layer (MO) can be in contact with the lower pad (143) on the lower surface (EBS) of the via electrode (141).

[0196] Furthermore, as described above, the second metal portion may be arranged to extend to the upper surface (US) of the core layer (110). The metal insulating layer (MO) may be positioned on the inner side of the extended first metal portion. During manufacturing, the metal insulating layer positioned on the upper side of the extended first metal portion may be removed.

[0197] Referring further to FIG. 22, the first metal portion (SL) may further include an additional metal portion (SLi) present in the second region (S2). The additional metal portion (SLi) may be spaced apart from the first metal portion (SL) that contacts the first region (S1). The additional metal portion (SLi) contacts the second region (S2) and may be covered by the second metal portion (EL).

[0198] In this configuration, a metal insulating layer (MO) may be positioned between the first metal portion (SL) and the second metal portion (EL). That is, the metal insulating layer (MO) may be positioned on the first metal portion (SL) in the first region (S1). And the metal insulating layer (MO) may be in contact with the second region (S2) of the inner wall (IS). And the metal insulating layer (MO) may be positioned on the additional metal portion (SLi) of the second region (S2) to cover the additional metal portion (SLi). Accordingly, the bonding strength between the second metal portion (EL) and the core layer (110) in the second region (S2) may be improved. There may be a plurality of additional metal portions (SLi) and they may be spaced apart from each other.

[0199] Furthermore, the structures of the various embodiments and modifications described above can be equally applied to the circuit board according to the present embodiment.

[0200] FIG. 23 is a plan view of a circuit board according to a third embodiment of the present invention, FIG. 24 is a view taken along line BB' in FIG. 23, FIG. 25 is a plan view of an insulating layer, a via electrode, and a via hole of a core layer in a circuit board according to the third embodiment, FIG. 26 is an enlarged view of K7 in FIG. 24, and FIG. 27 is an enlarged view of K8 in FIG. 24.

[0201] Referring to FIGS. 23 and 24, the circuit board (100) according to the third embodiment may include a core layer (110), an insulating layer (120), a protective layer (130), and an electrode portion (140). In addition, the circuit board (100) according to the third embodiment may include a semiconductor element (SD) and a conductive member (CB1, CB2) positioned on one side (e.g., the upper side).

[0202] A circuit board (100) according to a third embodiment may include a core layer (110), an insulating layer (120), a protective layer (130), and an electrode portion (140). In addition, the circuit board (100) according to the third embodiment may include a semiconductor element (SD) and a conductive member (CB1, CB2) positioned on one side (e.g., the upper side).

[0203] The core layer (110) may be a 'core layer' or a 'substrate layer'. The core layer (110) can suppress warpage that occurs due to thinning of the circuit board. In other words, warpage can be reduced by placing a glass layer (or glass core) with high rigidity and a low coefficient of thermal expansion (CTE) at the center or core of the circuit board. For example, the core layer (110) may have high rigidity and a low coefficient of thermal expansion compared to an insulating layer or a protective layer.

[0204] And the core layer (110) can be made of a glass material. For example, the core layer (110) can include pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc., and is not limited to silicon-based glass compositions, and alternative glass materials such as fluorine glass, phosphate glass, chalcogen glass, etc. can also be used. In addition, the core layer (110) can further include other additives to form a glass having specific physical properties. These additives can include not only calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these elements and other elements.

[0205] Additionally, the core layer (110) may be made of an insulating material. Accordingly, the core layer (110) may be referred to as an ‘insulating layer’.

[0206] Additionally, the core layer (110) may be positioned at the center of the insulating layer (120). Additionally, the core layer (110) may include a via hole (110h) as described below. The via holes (110h) may have various shapes and be formed at various locations, different from the number and structure illustrated in the drawing.

[0207] There may be at least one core layer (110). In the circuit board (100) according to the third embodiment, there may be one core layer (110).

[0208] In an embodiment, the core layer (110) may include a bottom surface (BS) and an upper surface (US). The bottom surface (BS) and the upper surface (US) may be outer surfaces that face each other in the stacking direction or in the vertical direction in the core layer (110). In addition, the bottom surface (BS) and the upper surface (US) may face each other in the vertical direction in the core layer (110).

[0209] In an embodiment, the core layer (110) may include a via hole (110h). The core layer (110) may include a plurality of via holes (110h). The plurality of via holes (110h) may penetrate the core layer (110). That is, the plurality of via holes (110h) may penetrate the upper surface (US) and the lower surface (BS) of the core layer (110). The plurality of via holes (110h) may be spaced apart from each other within the core layer (110). For example, the core layer (110) may include a first via hole (110h1). The core layer (110) may include a second via hole (110h2). In addition, the core layer (110) may include a third via hole (110h3). The first via hole (110h1), the second via hole (110h2), and the third via hole (110h3) can be spaced apart from each other.

[0210] As an example, the first via hole (110h1) may be located at the center of the core layer (110) in the circuit board (100). Alternatively, among the plurality of via holes (110h), the first via hole (110h1) may be located closest to the center of the circuit board (100). For example, the center of the circuit board (100) may correspond to the intersection of horizontal / vertical bisectors or the center of gravity with respect to a plane perpendicular to the stacking direction. For example, the center of the circuit board (100) may correspond to the intersection of bisectors in the horizontal direction (X-axis direction) and the longitudinal direction (Y-axis direction). The second via hole (110h2) may be spaced apart from the first via hole (110h1) in the horizontal direction (X-axis direction). And the third via hole (110h3) can be spaced apart in the longitudinal direction (Y-axis direction) with respect to the first via hole (110h1).

[0211] In the circuit board (100), the via hole (110h) may have a structure in which the diameter or width increases from the center toward the upper surface and the lower surface in each of the core layers (110). For example, the diameter of the via hole (110h) may increase from the center of the core layer (110) toward the upper surface (US) and the lower surface (BS) within the core layer (110). Accordingly, the inner surface (IS) of the via hole (110h) may be inclined with respect to the upper surface (US) and the lower surface (BS). This may be equally applied to the core layer (110).

[0212] The insulating layer (120) may be disposed on the core layer (110). The insulating layer (120) may surround at least a portion of the core layer (110). In addition, the insulating layer (120) may be disposed on a via hole (110h) of the core layer (110). For example, the insulating layer (120) may be positioned within the via hole (110h) of the core layer (110). Accordingly, damage to the via hole (110h) of the core layer (110) may be prevented. In addition, the insulating layer (120) may be positioned on the upper or lower portion of the core layer (110). In an embodiment, the insulating layer (120) may be in contact with an outer surface of the core layer (110) or may be in contact with an upper or lower surface.

[0213] As an example, the insulating layer (120) may be formed of multiple insulating layers. The multiple insulating layers may be formed of the same insulating material or different insulating materials.

[0214] As an example, the insulating layer (120) may include a first insulating layer (121) and a second insulating layer (122) disposed above or below the core layer (110). In addition, the insulating layer (120) may include an intermediate insulating layer (123). The first insulating layer (121) and the second insulating layer (122) may be formed of a plurality of insulating layers.

[0215] The first insulating layer (121) and the second insulating layer (122) may be positioned on the lower and upper portions of the core layer (110), respectively. The second insulating layer (122) may be positioned on the lower portion of the core layer (110). And the first insulating layer (121) may be positioned on the upper portion of the core layer (110). For example, the first insulating layer (121) may be in contact with the upper surface (US) of the core layer (110). And the second insulating layer (122) may be in contact with the lower surface (BS) of the core layer (110).

[0216] And the intermediate insulating layer (123) may be positioned within a plurality of via holes (110h) of the core layer (110). For example, the intermediate insulating layer (123) may be positioned within a first via hole (110h1) or within a second via hole (110h2) of the core layer (110). In addition, the intermediate insulating layer (123) may be positioned within a third via hole (110h3).

[0217] The insulating layer (120) may be formed of multiple layers depending on the structure or design of the circuit board (100) as described above. For example, the first insulating layer (121) and the second insulating layer (122) may be formed of multiple insulating layers.

[0218] In addition, a plurality of circuit patterns (142, 143), through holes, via electrodes (141), etc. may be positioned in the insulating layer (120). For example, the through hole of the insulating layer (120) may be connected to the via hole of the core layer (110). The via electrode positioned in the through hole of the insulating layer (120) may be electrically connected to the via electrode positioned in the via hole of the core layer (110). In addition, the through hole of the insulating layer (120) may also pass through the via hole (110h) of the core layer (110).

[0219] The insulating layer (120) may include a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the insulating layer (120) may further include a reinforcing material in the resin. The reinforcing material may be, for example, a fabric reinforcing material, an inorganic filler, etc. The fabric reinforcing material may be glass fiber, and the glass fiber may be impregnated into the resin to form a prepreg (PPG).

[0220] For example, the insulating layer (120) may be formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto, can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The above-described arbitrary insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, it may include a reinforcing material formed of glass fiber or aramid fiber. For example, the insulating layer (120) may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., as an example, and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (120) may include a plurality of layers composed of ABF.

[0221] The protective layer (130) may be positioned above or below the insulating layer (120). For example, the protective layer (130) may include a first protective layer (131) positioned above the first insulating layer (121) and a second protective layer (132) positioned below the second insulating layer (122).

[0222] The protective layer (130) may have the function of protecting the pad from external moisture or contaminants, and may be formed of a solder resist, for example, to prevent a short circuit problem when bonding between a semiconductor element and / or a main board and a circuit board. Specifically, the semiconductor element and / or the main board, etc., have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, solder may be used, for example. When solder is used, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist that does not have good wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (130) may be formed of a material that has insulating properties for electrical connection. Accordingly, the protective layer (130) may be referred to as an 'insulating layer' and may be a component of the insulating layer (120) described above. The protective layer (130) may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. In addition, the third insulating layer (not shown) may include any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0223] And the insulating layer or protective layer (130) located in the outer laminated area of ​​the circuit board may have an opening. Through the opening, it may be electrically connected to other semiconductor elements, circuit boards, etc.

[0224] For the electrical connection described above, conductive members (CB1, CB2) may be positioned on the upper or lower portion of the circuit board (100). The conductive member (CB1) positioned on the upper portion may perform electrical connection with the semiconductor element (SD) and the electrode portion (140). In addition, the conductive member (CB2) positioned on the lower portion may perform electrical connection with another substrate, etc.

[0225] In an embodiment, a wiring or electrode portion (140) may be arranged for electrical connection between a main board, etc. and a chip (or semiconductor device (SD), die). And the electrode portion (140) may include a circuit pattern (or circuit pattern layer), a pad, and a via electrode (141). The wiring (142, 143) may correspond to an 'electrode pattern', a 'pattern', a 'line', etc.

[0226] In the electrode portion (140), the circuit pattern can be designed in various forms for transmitting signals and / or power to the semiconductor element, and is arranged within each laminated insulating layer (120). For example, the electrode portion (140) can include a via electrode or a through electrode. In an embodiment, the via electrode (141) can be positioned within a through hole penetrating the core layer (110) and the insulating layer (120).

[0227] And in the electrode section (140), the via electrode (141) is arranged to penetrate a portion of each insulating layer for vertical connection between the circuit patterns arranged on each vertically stacked core layer and insulating layer. That is, the insulating layer may include a through hole for arrangement of the via electrode. And the via electrode may have a wider width than the circuit pattern for optimization of impedance or heat dissipation, but is not limited thereto and may be freely designed.

[0228] And there may be a plurality of via electrodes (141). For example, the via electrodes (141) may penetrate a plurality of via holes (110h) of the core layer (110). As described above, the via electrodes (141) may penetrate the core layer (110) and the insulating layer (120) and be positioned within the via holes (110h). For example, the via electrodes (141) may include a first via electrode (141a) penetrating a first via hole (110h1), a second via electrode (141b) penetrating a second via hole (110h2), and a third via electrode (141c, see FIG. 28) penetrating a third via hole (110h3).

[0229] In the electrode portion (140), pads may be placed on each insulating layer. The pads may be electrically connected to circuit patterns. In addition, the pads may be electrically connected to semiconductor elements and / or main boards or substrates. In addition, the pads may be electrically connected to via electrodes.

[0230] In particular, pads positioned on the outer side of the pads can be bonded to semiconductor elements, substrates, boards, etc. using solder, wires, conductive adhesives, etc., and may be positioned with a width greater than the width of the circuit pattern to solve problems such as securing yield. However, this is not limited to this, and may have a width equal to the width of the circuit pattern depending on the technical limitations of the bonding process.

[0231] And the pads arranged on the inside have the function of connecting the via electrodes and the circuit patterns. When the via electrodes are arranged with a wider width than the circuit patterns, pads having a wider width than the circuit patterns are provided for positional alignment during the manufacturing process of the via electrodes to be arranged on each circuit pattern. Therefore, each via electrode may have an upper surface that is positioned on the same plane as the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is positioned on the same plane as the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0232] The semiconductor device (SD) may be mounted on the upper portion of the circuit board (100). The semiconductor device (SD) may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an AP including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above-mentioned elements. In addition, the memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory. The semiconductor device (SD) may be electrically connected to the electrode unit (140) through the conductive member (CB2) described above.

[0233] Circuit boards can be divided into package boards and interposers based on their function. The package board serves the function of mounting semiconductor devices and / or interposers. As data increases, the circuit board area increases or the number of insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, to improve the yield of circuit boards with a high number of layers, the yield of the circuit board can be improved by separating them into an interposer and a package board. In addition, as the terminal density of semiconductor devices increases, it can be difficult to implement pads on the package board with an area corresponding to the terminals of the semiconductor devices. Therefore, the pad size of the package board can act as a buffer between the size of the pad and the fine pattern size of the terminals of the semiconductor devices.

[0234] In addition, a connecting member (not shown) may be disposed within the core layer (110). The connecting member (not shown) may be used interchangeably with a 'semiconductor element', a 'chip', a 'die', etc. The connecting member (not shown) may be disposed within a cavity including a groove or hole within the core layer (110) and may be electrically connected to other plurality of semiconductor elements disposed on the upper portion of the circuit board. The connecting member (not shown) is made of Si and may be referred to as a bridge. In this way, the connecting member (not shown) may be referred to as a bridge substrate. For example, the connecting member (not shown) may include a redistribution layer. The connecting member (not shown) may have a function of horizontally electrically connecting a plurality of semiconductor elements to each other. For example, the connecting member (not shown) may include a redistribution layer because the area that a semiconductor element should generally have is too large. Because semiconductor packages and semiconductor devices have significantly different circuit pattern widths and depths, a buffering function for the circuit pattern is necessary for electrical connection. This buffering function can mean ensuring that the circuit pattern width and depth of the semiconductor package are intermediate in size to the circuit pattern width and depth of the semiconductor device. The redistribution layer can also include a buffering function.

[0235] Additionally, the connecting member (not shown) may be an organic bridge. For example, the connecting member (not shown) may include an organic material. For example, the connecting member (not shown) may include an organic substrate containing an organic material instead of a silicon substrate.

[0236] Additionally, the connecting member (not shown) may include a connecting portion for electrical connection on one surface. Furthermore, a filling member may be disposed within the cavity. The filling member may surround the connecting member (not shown). The filling member may secure the connecting member (not shown) disposed within the cavity to the cavity. The filling member may be formed of an insulating material.

[0237] The package substrate and interposer described above can be classified into core substrates and coreless substrates, respectively, depending on the composition of the insulating layer. In an embodiment according to the present invention, a circuit substrate having a core layer including glass is described.

[0238] Referring further to FIGS. 25 to 27, in an embodiment, the central axis of the via hole (110h) may be misaligned with the central axis of the via electrode (141) penetrating the via hole (110h). Alternatively, the central axis of the via hole (110h) may be offset from the central axis of the via electrode (141) within the via hole (110h). The central axis of the via hole (110h) and the central axis of the via electrode (141) may be spaced apart in the horizontal direction (X-axis direction) or the longitudinal direction (Y-axis direction).

[0239] For example, the first central axis (AX1) of the first via hole (110h) may be misaligned with the second central axis (AX2) of the first via electrode (141a). That is, the first central axis (AX1) and the second central axis (AX2) may be spaced apart from each other in the horizontal direction (X-axis direction). Alternatively, the first central axis (AX1) and the second central axis (AX2) may not overlap in the stacking direction.

[0240] Furthermore, in the embodiment, a first length in the horizontal direction (or longitudinal direction) between the inner wall (IS) of the via electrode (141) and the via hole (110h) and a second length in the opposite direction (or longitudinal direction) to the horizontal direction may be different from each other. That is, the via electrode (141) may be offset to the side of the circuit board or the core layer within the via hole (110h). For example, in the first via hole (110h1), a first length (W1) in the horizontal direction (X-axis direction) between the inner wall (IS) of the via hole (110h1) and the via electrode (141a) and a second length (W2) in the opposite direction to the horizontal direction may be different from each other. In other words, the via hole (110h) and the via electrode (141) penetrating the via hole (110h) or arranged inside the via hole (110h) may have different distances from the inner surface of the via hole (110h) along the outer surface. Alternatively, the via electrode (141) may have a side surface (141s) facing the inner wall of the via hole (110h). In addition, the length (W2) along the horizontal direction between the side surface (141s) of the via electrode (141) and the inner wall (IS) of the via hole (110h) may be different from each other along one perimeter of the side surface (141s). Accordingly, the distance between the side surface (141s) of the via electrode (141) and the inner wall (IS) of the via hole (110h) in one plane (XY plane) perpendicular to the stacking direction may vary along the perimeter of the side surface (141s). The maximum distance / shortest distance between the inner surface, inner side, or inner wall (IS) of the via electrode (141) and the via hole (110h) may be greater than 1.

[0241] And as described above, the first via hole (110h) may have a structure in which the diameter or width (W3) increases from the center toward the upper surface and the lower surface in each of the core layers (110). The diameter of the via hole (110h) may increase from the center of the core layer (110) toward the upper surface (US) and the lower surface (BS) within the core layer (110). For example, the via hole (110h) may include a first region (S1) in which the width decreases from the upper surface (US) of the core layer (110) toward the lower surface (BS), and a second region (S2) in which the width increases from the first region (S1) toward the lower surface (BS) of the core layer (110). In other words, the diameter or width of the via hole (110h) may increase in the first region (S1) toward the upper surface (US). In the second region (S2), the diameter or width of the via hole (110h) may decrease toward the upper surface (US). This may be applied to all of the multiple via holes. Corresponding to this configuration, the width or diameter of the intermediate insulating layer (123) may increase from the center of the via hole toward the upper surface and the lower surface, respectively.

[0242] In contrast, the width of the via electrode (141) may increase or decrease in the stacking direction (Z-axis direction). For example, the diameter or width (W4) of the via electrode (141) may increase in the stacking direction. And the width (W4) of the via electrode (141) may decrease as it goes from the upper surface (US) to the lower surface (BS) of the core layer (110). The via electrode (141), like the via hole (110h), may be inclined with respect to a plane perpendicular to the stacking direction. However, like the via hole (110h), it may not have a structure that is symmetrical with respect to the center.

[0243] And the via electrode (141) is arranged within the via hole (110h), so that its width may be smaller than the width of the via hole (110h). For example, the width (W4) of the first via electrode (41a) may be smaller than the width (W3) of the first via hole (110h1).

[0244] Furthermore, as described above, the first via hole (110h1) and the second via hole (110h2) may be spaced apart from each other. In addition, the via electrode (141) may include a first via electrode (141a) disposed within the first via hole (110h1) and a second via electrode (141b) disposed within the second via hole (110h2).

[0245] And the second via electrode (141b) may be arranged within the second via hole (110h2). At this time, the third central axis (AX3) of the second via hole (110h2) may be arranged spaced apart from the fourth central axis (AX4) of the second via electrode (141b). That is, the third central axis (AX3) and the fourth central axis (AX4) may not overlap in the stacking direction.

[0246] Furthermore, the third length (W5) in the horizontal direction (X-axis direction) between the inner wall (IS) and the second via electrode (141b) and the fourth length (W6) in the opposite direction to the horizontal direction may be different from each other. In other words, the second via electrode (141b) penetrating the second via hole (110h2) or positioned inside the second via hole (110h2) may have a different distance from the inner surface of the second via hole (110h2) along the outer surface.

[0247] Additionally, the separation distance between the third central axis (AX3) and the fourth central axis (AX4) may be different from the separation distance between the first central axis (AX1) and the second central axis (AX2). For example, the separation distance in the horizontal direction (X-axis direction) between the third central axis (AX3) and the fourth central axis (AX4) may be different from the separation distance in the horizontal direction (X-axis direction) between the first central axis (AX1) and the second central axis (AX2). In an embodiment, the separation distance in the horizontal direction (X-axis direction) between the third central axis (AX3) and the fourth central axis (AX4) may be greater than the separation distance in the horizontal direction (X-axis direction) between the first central axis (AX1) and the second central axis (AX2). That is, as the via hole (110h) is spaced farther apart from the center on the plane (e.g., XY plane) of the substrate or core layer, the distance between the center axis of the via electrode within the via hole and the center axis of the via hole may increase.

[0248] For example, a first length (W1) in the horizontal direction between the first via electrode (141a) and the inner wall of the first via hole (110h1) and a third length (W3) in the horizontal direction between the second via electrode (141b) and the inner wall of the second via hole (110h2) may be different from each other. The first length (W1) in the horizontal direction between the first via electrode (141a) and the inner wall of the first via hole (110h1) may be greater than the third length (W3) in the horizontal direction between the second via electrode (141b) and the inner wall of the second via hole (110h2).

[0249] Additionally, the second length (W2) in the horizontally opposite direction between the first via electrode (141a) and the inner wall of the first via hole (110h1) and the fourth length (W4) in the horizontally opposite direction between the second via electrode (141b) and the inner wall of the second via hole (110h2) may be different from each other. For example, the second length (W2) in the horizontally opposite direction between the first via electrode (141a) and the inner wall of the first via hole (110h1) may be smaller than the fourth length (W4) in the horizontally opposite direction between the second via electrode (141b) and the inner wall of the second via hole (110h2).

[0250] By this configuration, when vias such as via holes in the core layer are concentrated or crowded, the chemical drift phenomenon can be improved when forming a through hole in the insulating layer. In other words, even if stress is concentrated in one area due to an electrode such as a wiring, stress balancing can be achieved by forming the central axis between the via electrode and the via hole in the core layer to be biased. As a result, the circuit board according to the third embodiment can improve structural reliability.

[0251] Additionally, as another example, the degree of offset and the size of the separation distance between the via electrode and the via hole can be varied in response to the distribution of thermal or mechanical stress to alleviate the outwardly concentrated mechanical and thermal stress distribution.

[0252] FIG. 28 is a view taken along the CC' line in FIG. 23, FIG. 29 is another plan view of the via hole of the insulating layer, the via electrode, and the core layer in the circuit board according to the third embodiment, FIG. 30a is a plan view of the circuit board according to the third embodiment, and FIG. 30b is a plan view of the circuit board according to a modified example.

[0253] Referring to FIGS. 28 and 29, corresponding to the above, the via electrode (141) may include a first via electrode (141a) and a third via electrode (141c). The third via electrode (141a) may be spaced apart from the third via electrode (141c). For example, the third via electrode (141a) may be spaced apart from the first via electrode (141) in the longitudinal direction (Y-axis direction). Correspondingly, the third via electrode (141c) may be positioned within the third via hole (110h3). And the third via hole (110h3) may be spaced apart from the first via hole (110h1) in the longitudinal direction (Y-axis direction).

[0254] At this time, the fifth central axis (AX5) of the third via hole (110h3) may be spaced apart from the sixth central axis (AX6) of the third via electrode (141c). That is, the fifth central axis (AX5) and the sixth central axis (AX6) may not overlap in the stacking direction.

[0255] Furthermore, the third length in the longitudinal direction (Y-axis direction) between the inner wall (IS) and the third via electrode (141c) of the third via hole (110h3) and the fourth length in the opposite direction to the longitudinal direction may be different from each other. In this way, a maximum length and a minimum length may exist between the inner wall of the via hole and the via electrode within the via hole. In other words, the third via electrode (141c) penetrating the third via hole (110h3) or arranged inside the third via hole (110h3) may have a different distance from the inner surface of the third via hole (110h3) along the outer surface.

[0256] Additionally, the separation distance between the fifth central axis (AX5) and the sixth central axis (AX6) may be different from the separation distance between the first central axis (AX1) and the second central axis (AX2). For example, the separation distance in the longitudinal direction (X-axis direction) between the fifth central axis (AX5) and the sixth central axis (AX6) may be different from the separation distance in the longitudinal direction (X-axis direction) between the first central axis (AX1) and the second central axis (AX2). In an embodiment, the separation distance in the longitudinal direction (X-axis direction) between the fifth central axis (AX5) and the sixth central axis (AX6) may be greater than the separation distance in the longitudinal direction (X-axis direction) between the first central axis (AX1) and the second central axis (AX2). That is, as the via hole (110h) is spaced farther apart from the center on the plane (e.g., XY plane) of the substrate or core layer, the distance between the center axis of the via electrode within the via hole and the center axis of the via hole may increase.

[0257] For example, the first length (W1) in the longitudinal direction between the first via electrode (141a) and the inner wall of the first via hole (110h1) and the fifth length in the longitudinal direction between the third via electrode (141c) and the inner wall of the third via hole (110h3) may be different from each other. The first length (W1) in the longitudinal direction between the first via electrode (141a) and the inner wall of the first via hole (110h1) and the fifth length in the longitudinal direction between the third via electrode (141c) and the inner wall of the third via hole (110h3) may be greater than each other.

[0258] In addition, the second length (W2) in the longitudinal direction opposite to that between the first via electrode (141a) and the inner wall of the first via hole (110h1) and the sixth length in the longitudinal direction opposite to that between the third via electrode (141c) and the inner wall of the third via hole (110h3) may be different from each other. For example, the second length (W2) in the longitudinal direction opposite to that between the first via electrode (141a) and the inner wall of the first via hole (110h1) and the sixth length in the longitudinal direction opposite to that between the third via electrode (141c) and the inner wall of the third via hole (110h3) may be smaller than the sixth length.

[0259] Referring further to FIG. 30a, in the embodiment, the first via hole (110h1) may be located at the center or center (CE) of the core layer (110) in the circuit board (100). Alternatively, among the plurality of via holes (110h), the first via hole (110h1) may be located closest to the center (CE) of the circuit board (100). For example, the center (CE) of the circuit board (100) may correspond to the intersection of the horizontal (La) and vertical (Lb) bisectors with respect to a plane perpendicular to the stacking direction, or the center of gravity. For example, the center (CE) of the circuit board (100) may correspond to the intersection of the bisectors in the horizontal direction (X-axis direction) and the longitudinal direction (Y-axis direction).

[0260] In this way, the central axes of the plurality of via holes (110h1 to 110h3) may be spaced apart from the center (CE) of the circuit board or core layer (110). And the plurality of via electrodes (141a to 141c) may be positioned within the plurality of via holes. And the plurality of via electrodes (141a to 141c) may have central axes spaced apart from the center (CE) of the circuit board or core layer (110).

[0261] The first via hole (110h1) may be closest to the center (CE) of the circuit board or core layer (110). That is, the first via hole (110h1) may be positioned closer to the center (CE) on a plane perpendicular to the stacking direction in the core layer (110) than the second via hole (110h2) and the third via hole (110h3).

[0262] And the remaining via holes can be spaced apart in a direction perpendicular to the stacking direction with respect to the first via hole (110h1). For example, the second via hole (110h2) can be spaced apart in a horizontal direction (X-axis direction) with respect to the first via hole (110h1). And the third via hole (110h3) can be spaced apart in a longitudinal direction (Y-axis direction) with respect to the first via hole (110h1).

[0263] The second via electrode (141b) may be arranged far apart from the first central axis of the first via hole (110h1) with respect to the third central axis of the second via hole (110h2). That is, the second via electrode (141b) may be arranged far apart from the first central axis of the first via hole (110h1) with respect to the third central axis of the second via hole (110h2). Accordingly, the third central axis may be positioned between the fourth central axis and the first central axis. In addition, the third central axis of the second via hole (110h2) and the fourth central axis of the second via electrode (141b) may be misaligned.

[0264] In addition, the third via electrode (141c) may be positioned to be away from the first central axis of the first via hole (110h1) with respect to the fifth central axis of the third via hole (110h3). That is, the third via electrode (141c) may be positioned to be away from the first central axis of the first via hole (110h1) with respect to the fifth central axis of the third via hole (110h3). Accordingly, the fifth central axis may be positioned between the sixth central axis and the first central axis. In addition, the fifth central axis of the third via hole (110h3) and the sixth central axis of the third via electrode (141c) may be misaligned.

[0265] In this way, in the embodiment, the via electrode in the via hole may be positioned away from the center (CE) of the circuit board or the first center axis. Accordingly, a deviation may be formed between the center axis of the via electrode and the center axis of the via hole in the core layer. The degree of this deviation may increase or decrease in response to an increase or decrease in the separation distance between the via hole and the via electrode. For example, the thermal or mechanical stress may be smallest at the center (CE) of the circuit board or the core layer. And the magnitude of the thermal or mechanical stress may increase from the center (CE) toward the side. In addition, the degree of the deviation described above may be modified according to the concentration of stress due to the wiring arrangement of the electrode portion. For example, when the vias, such as the via holes in the core layer, are concentrated, the degree of the deviation can be adjusted. Accordingly, the chemical concentration phenomenon may be improved when forming the through hole in the insulating layer. In other words, even if the stress is concentrated in one area due to the electrode, such as the wiring, the stress can be balanced by forming the center axis between the via electrode and the via hole in the core layer to be deflected. Accordingly, the embodiment can provide a circuit board with increased structural reliability.

[0266] Referring to FIG. 30b, in the circuit board (100') according to the modified example, as described above, the first via hole (110h1) may be located at the center or center (CE) of the core layer in the circuit board (100). Alternatively, among the plurality of via holes (110h), the first via hole (110h1) may be located closest to the center (CE) of the circuit board (100). For example, the center (CE) of the circuit board (100) may correspond to the intersection of the horizontal (La) and vertical (Lb) bisectors with respect to a plane perpendicular to the stacking direction, or the center of gravity. For example, the center (CE) of the circuit board (100) may correspond to the intersection of the bisectors in the horizontal direction (X-axis direction) and the longitudinal direction (Y-axis direction).

[0267] In this way, the central axes of the plurality of via holes (110h1 to 110h3) may be spaced apart from the center (CE) of the circuit board or the core layer. And the plurality of via electrodes (141a to 141c) may be positioned within the plurality of via holes. And the plurality of via electrodes (141a to 141c) may have central axes spaced apart from the center (CE) of the circuit board or the core layer.

[0268] In such a circuit board (100'), a plurality of via electrodes may be biased relative to each via hole. That is, the central axes of the plurality of via electrodes may be offset or misaligned with the central axes of each via hole.

[0269] First, the first via hole (110h1) may be closest to the center (CE) of the circuit board or the core layer. Then, the second via hole (110h2), the third via hole (110h3), etc. may be spaced apart from the first via hole (110h1). At this time, the via electrode within each via hole may be offset toward the center (CE) of the circuit board or the core layer within the via hole or toward the center (CE) of the core layer.

[0270] For example, the second via electrode (141b) may be arranged adjacent to the first central axis of the first via hole (110h1) with respect to the third central axis of the second via hole (110h2). That is, the fourth central axis of the second via electrode (141b) may be arranged adjacent to the first central axis of the first via hole (110h1) and between the third central axis and the first central axis of the second via hole (110h2). The fourth central axis may be arranged so as to be closer to the first central axis and further away from the first central axis. Accordingly, the fourth central axis may be arranged between the third central axis and the first central axis. In addition, the third central axis of the second via hole (110h2) and the fourth central axis of the second via electrode (141b) may be misaligned.

[0271] Furthermore, the third via electrode (141c) may be positioned adjacent to the first central axis of the first via hole (110h1) with respect to the fifth central axis of the third via hole (110h3). For example, the sixth central axis of the third via electrode (141c) may be positioned closer to the first central axis of the first via hole (110h1) than to the fifth central axis of the third via hole (110h3). Accordingly, the sixth central axis may be positioned between the fifth central axis and the first central axis.

[0272] Figures 31 to 38 are drawings explaining a method for manufacturing a circuit board according to a third embodiment of the present invention.

[0273] The same components described above are given the same drawing reference numerals, and duplicate descriptions of the same components are omitted, with only the differences described.

[0274] Additionally, the circuit board according to the third embodiment may correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board may be composed of unit circuit boards. The mother circuit board may be separated into a plurality of unit circuit boards along a sawing line.

[0275] Referring to FIGS. 31 and 32, in a method for manufacturing a circuit board according to a third embodiment, a core layer (110) made of glass can be prepared (S510). Then, in order to form a via hole in the core layer (110), light from a laser (e.g., 1064, 1030 nm) can be irradiated at a location where the via hole is to be formed for several picoseconds (S515).

[0276] Referring to FIGS. 33 and 34, crystallization (DF) may be formed in a portion of a region where a via hole is desired to be formed in the core layer (110) by laser irradiation (S520). Then, an etching solution may be sprayed or applied to the core layer (110) (S525). Accordingly, isotropic etching due to the etching process and crystal defects due to partial crystallization may occur. The etching solution may penetrate into the crystal defects, facilitating the formation of a via hole.

[0277] Referring to Figure 35, a via hole (110h) having a tapered shape and a width that decreases toward the center can be formed in the core layer (110) by an etching solution or the like (S530).

[0278] Referring to FIG. 36, an insulating layer (120) may be applied to the upper and lower portions of the core layer (110) and within the via hole (S535). For example, a first insulating layer (121) may be formed on the upper portion of the core layer (110). And a second insulating layer (122) may be formed on the lower portion of the core layer (110). An intermediate insulating layer (123) may be formed within the via hole (110h).

[0279] Referring to Fig. 37, a through hole penetrating the insulating layer (120) and the core layer (110) can be formed, and a via electrode (141) can be formed within the through hole (S540). At this time, in order to secure a chemical balance when forming an electrode portion such as a chemical copper, the through hole of the insulating layer (120) can be formed so that the central axis of the via hole and the through hole or the via electrode is deflected, as described above. In addition, via filling can be performed using chemical copper, electrolytic copper, etc. within the through hole, so that the via electrode (141) can be formed.

[0280] Referring to Fig. 38, a protective layer can be formed on the upper or lower portion of the insulating layer. Additionally, an opening area for a conductive member can be formed in the protective layer. Accordingly, a core layer of the circuit board according to the third embodiment described above can be manufactured. Thereafter, an insulating layer can be applied on the upper or lower portion of the core layer, and an electrode portion (140) can be formed through a pattern groove or a via hole. The circuit pattern in the electrode portion (140) can be formed by a manufacturing process of a printed circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP).

[0281] In various semiconductor packages, circuit boards according to the various embodiments described above may be located in some areas or correspond to one substrate.

[0282] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0283] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0284] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0285] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A core layer including an upper surface and a lower surface, and including a via hole penetrating the upper surface and the lower surface; and A via electrode disposed in the above via hole; The above via electrode comprises a first metal portion, a second metal portion surrounding at least a portion of the first metal portion and made of a material different from the first metal portion, A circuit board in which the first metal portion is positioned between the second metal portion and the inner wall of the via hole.

2. In paragraph 1, A circuit board including an upper metal layer adjacent to an upper surface of the core layer and a lower metal layer adjacent to a lower surface of the core layer, wherein the second metal portion is 3. In paragraph 2, A circuit board wherein the upper metal layer and the lower metal layer are spaced apart from each other.

4. In paragraph 3, The above first metal portion includes a seed layer arranged on the inner wall of the via hole, A circuit board in which the seed layer, the upper metal layer, and the lower metal layer are each overlapped along the inner wall of the via hole in a horizontal direction.

5. In paragraph 4, The above first metal portion includes an inner electrode portion arranged inside the seed layer, A circuit board wherein the size of the crystal grains of the inner electrode portion is larger than the size of the crystal grains of the seed layer.

6. In paragraph 1, A circuit board wherein the width of the above via hole increases from the central portion toward the lower surface of the core layer, and the width increases from the central portion toward the upper surface of the core layer.

7. In paragraph 4, A circuit board in which the seed layer has a ring-shaped exposed surface exposed from the upper or lower surface of the core layer.

8. In paragraph 4, A circuit board in which the seed layer increases in width from the center of the core layer toward the upper or lower surface of the core layer.

9. In paragraph 4, A circuit board wherein the seed layer has different extension directions from the center of the via hole toward the upper surface and from the center of the via hole toward the lower surface.

10. In paragraph 5, A circuit board wherein the seed layer includes a material having a higher oxygen affinity than the inner electrode portion.

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