STT-MRAM reading and writing method using dual reference, and apparatus therefor

Abstract

The present specification relates to a writing and reading apparatus and method for spin-transfer torque magnetic RAM (STT-MRAM). An STT-MRAM writing apparatus using a dual reference and step-wise current increases, according to one embodiment, comprises: an array including a plurality of STT-MRAM cells; a reference voltage generation unit for generating reference data to be compared with data to be determined for STT-MRAM cells of a selected address from among the plurality of STT-MRAM cells; and a control unit that transmits a designation signal for obtaining the data to be determined for the STT-MRAM cells of the selected address, wherein the control unit can obtain, from the reference voltage generation unit, a first reference voltage, which is the largest value from among voltage values generated on the basis of a current flowing through an Rp resistor in a low state, and a second reference voltage, which is the smallest value from among voltage values generated on the basis of a current flowing through an Rap resistor in a high state, and generate, on the basis of the first reference voltage and the second reference voltage, a first write current from Rp to Rap, which is to be applied to designated STT-MRAM, or the first write current from Rap to Rp, which is to be applied to the designated STT-MRAM.

Description

STT-MRAM read and write method using dual reference and corresponding device

[0001] The embodiments are a technology for reading STT-MRAM using dual references and a technology for writing STT-MRAM using dual references and stepwise current increase.

[0002] STT-MRAM (Spin-Transfer Torque Magnetic RAM) is a non-volatile memory that utilizes magnetic rotational momentum. Compared to conventional memory types such as flash memory and DRAM, STT-MRAM offers advantages such as faster speed and lower power consumption.

[0003] STT-MRAM has a P resistance (P Resistance, Rp) state and an AP resistance (AP Resistance, Rap) state.

[0004] The P resistance state represents parallel resistance in STT-MRAM. The P resistance state exhibits a resistance change due to magnetically aligned electrons, resulting in a low resistance state. The polarization changes depending on the state of the bit (0 or 1) storing the data, and this change is reflected in the overall resistance of the device.

[0005] The AP resistance state represents the antiparallel resistance in STT-MRAM. The AP resistance state represents the resistance when a bit is polarized in the opposite direction, resulting in a high resistance state. The AP resistance represents the different states of the data bits.

[0006] Each cell within the STT-MRAM array has a different write critical current (WCC) due to the influence of Process / Voltage / Temperature (PVT), which causes the time and energy consumed for the write operation of each cell to be different.

[0007] Conventionally, in order to minimize errors in the write operation of STT-MRAM, which is vulnerable to Process / Voltage / Temperature (PVT) Variation, a sufficiently large voltage or current is applied for a certain period of time. At this time, the existing write bias method requires a process of applying a high current to the cell for a sufficiently long time to write in the P state (Logic 0) and AP state (Logic 1) to ensure that data is written reliably in order to prevent data errors from occurring during the write process. During the data writing process, cells that have already been written with the desired data also continue to have current and voltage applied, which can cause durability problems for STT-MRAM. In addition, because current and voltage are continuously applied, there is a problem of high energy consumption and a long write time at the same time.

[0008] Figure 1 (a) illustrates the most common STT-MRAM write method. Figure 1 (b) illustrates the concept of a WT proposed in the prior art, the range of voltage references for the WT, and the process of turning off the current of the current driver when writing is completed through the WT during the write process.

[0009] Referring to Figure 1 (a), data has been written to STT-MRAM by applying a constant current for a set period of time. However, because it is uncertain when a P-cell in STT-MRAM will be written to an AP-cell, the write current must be applied for a long period of time to ensure that all cells are reliably written, leading to issues with energy efficiency and cell durability.

[0010] To solve the above-mentioned problem, a method (Write Termination, WT) was proposed to check whether the currently written cell has had data written or not, and to reduce unnecessary energy waste by turning off the current and voltage drivers of the cells to which data has already been written.

[0011] Referring to (b) of Fig. 1, the process of WT (Write Termination) compares the voltage of the reference for WT with the voltage of the cell currently being written when writing a P-cell as an AP cell with a constant current. When writing data by flowing current to a cell of STT-MRAM, if an AP cell is written as a P-cell or a P-cell is written as an AP cell, the resistance value of the cell changes, causing the voltage of the Bit-line (BL) or Source-line (SL) to change. At this time, when the changed voltage is compared with the reference voltage and the data is written, the result of the comparison changes through the WT logic to control the current driver and turn off the write driver of the cell for which writing is complete. When writing to all cells is complete, the current driver is turned off to minimize wasted current and enable energy-efficient writing operation.

[0012] Although the average write energy can be reduced through WT, the WCC variation still occurs due to the influence of the PVT variation, so that certain cells within the array require a long time to write data before the write is completed. Therefore, when writing is performed at a constant current, the increase in the overall write time and the durability issue of certain cells cannot be avoided.

[0013] In addition to the durability issues above, there is also a problem with the reference voltage. The write reference voltage has a problem in that it cannot be reflected in real time when the temperature and voltage change. Since the existing write reference voltage inputs a single voltage generated externally, if the reference is not located in the middle of the AP cell and the P cell due to changes in temperature / voltage that change in real time in the chip, the write Bit Error Rate (BER) increases due to the reference voltage that does not reflect the PVT when writing from the AP cell to the P cell and from the P cell to the AP cell.

[0014] In addition, in order to prevent the phenomenon of read accuracy decreasing due to process / temperature changes in the read operation of STT-MRAM, the conventional technology generated and used a reference voltage based on the average resistance value of the P state (Logic 0) and the AP state (Logic 1).

[0015] Figures 2 (a) and 2 (b) are conceptual diagrams explaining a method of finding an average resistance value according to a conventional method and using the same to find a reference voltage.

[0016] In the prior art, to create a reference voltage for a read operation, multiple memory cells are connected in parallel, as shown in Fig. 2 (a) and Fig. 2 (b), so that the average resistance value can be utilized while minimizing process variation. However, the prior art has the disadvantage of high energy consumption due to the built-in self-test (BIST) that operates to find the optimal ratio of cells connected in parallel, and has the limitation of low energy efficiency due to the use of multiple reference memory cells for a single read operation due to the use of a large amount of current. In addition, there is a problem of loss of semiconductor area due to the essential placement of bit-lines (BL) for references in order to create multiple read references for each Array WL (Word Line).

[0017] In addition, the prior art uses a universal SA (Sense Amplifier) ​​with two inputs that compares the read reference voltage, which has a value of (P state + AP state) / 2, with the voltage of the memory cell. However, even if the exact half read reference is found using the previously generated AP cell and P cell, the maximum achievable read margin in the read operation is half of the difference between the P state and the AP state. However, in STT-MRAM, the resistance difference between the P state and the AP state is small, and the difference in resistance between the P state and the AP state becomes lower due to the change in resistance caused by the process / temperature variation. This has the problem of lowering the accuracy of the read operation and increasing the memory read BER (Bit-Error-Rate).

[0018] [Prior Art Literature]

[0019] [Patent Document]

[0020] Korean Patent Publication No. 10-2017-0086390 (July 26, 2017), “Memory system including STT-MRAM and method for constructing the same.”

[0021] In order to ensure stable operation and improve durability of STT-MRAM, a next-generation non-volatile memory, a device or method is required that can solve the problem caused by the small difference in resistance values ​​between the P state and the AP state, that is, the problem caused by the small read margin, and various problems caused by the existing writing method that is vulnerable to process, voltage, and temperature variations.

[0022] That is, a device or method is required that can generate a constant reference voltage for an STT-MRAM array regardless of process, voltage, and temperature variations, and can generate a write current based on the constant reference voltage.

[0023] Additionally, a device or method capable of applying a dynamically changing write current for efficient writing is required, which further reduces the time and energy required to write data.

[0024] In conventional memory reading devices that require a reference cell for each WL within the memory, a device or method capable of reducing the area of ​​the device is required.

[0025] In order to solve the problem that arises due to the small difference in resistance values ​​between the P state and the AP state of STT-MRAM, that is, the problem of a small read margin and a high BER, a device or method that can increase the read margin is required.

[0026] Additionally, a device or method is required that enables STT-MRA to perform accurate and fast read operations despite process / temperature changes based on power efficiency, performance, and area.

[0027] According to one embodiment, a STT-MRAM writing device using a dual reference and a stepwise current increase includes an array including a plurality of STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) cells, a reference voltage generation unit for generating reference data for comparison with judgment target data for STT-MRAM cells of a selected address among the plurality of STT-MRAM cells, and a control unit for transmitting a designation signal for obtaining the judgment target data for STT-MRAM cells of the selected address, wherein the control unit obtains a first reference voltage, which is a largest value among voltage values ​​generated based on a current flowing in a low-state Rp resistor, from the reference voltage generation unit, and a second reference voltage, which is a lowest value among voltage values ​​generated based on a current flowing in a high-state Rap resistor, and generates a first write current from Rp to Rap applied to a designated STT-MRAM or a first write current from Rap to Rp applied to the designated STT-MRAM based on the first reference voltage and the second reference voltage. Can be set.

[0028] In addition, the control unit can obtain a changed first reference voltage and a changed second reference voltage by controlling a current flowing to the reference voltage generation unit, and can generate a first write current from the changed Rp to Rap and a first write current from the changed Rap to Rp based on the changed first reference voltage and the changed second reference voltage.

[0029] Additionally, the first reference voltage, the second reference voltage, the first write current from Rp to Rap, and the first write current from Rap to Rp may vary depending on the resistance distribution of the STT-MRAM cells included in the array.

[0030] In addition, the control unit can apply a first write current from Rp to Rap to the designated STT-MRAM for a first time, and detect a voltage change of the judgment target data to determine whether writing of the designated STT-MRAM is complete.

[0031] In addition, if the control unit determines that the designated STT-MRAM has not completed writing, it can apply a second write current from Rp to Rap, which increases the first write current from Rp to Rap, to the designated STT-MRAM for a second time, and detect a voltage change of the judgment target data to determine again whether the writing of the designated STT-MRAM has been completed.

[0032] In addition, if the control unit determines that the designated STT-MRAM has not completed writing, it can apply a third write current from Rp to Rap, which increases the second write current from Rp to Rap, to the designated STT-MRAM for a third time, and detect a voltage change of the judgment target data to determine again whether the writing of the designated STT-MRAM has been completed.

[0033] In addition, if the control unit determines that the voltage of the judgment target data is higher than the second reference voltage during the first time, the second time, or the third time, it can determine that the designated STT-MRAM has completed writing and control the first write current, the second write current, or the third write current to turn off.

[0034] According to another embodiment, a method for writing STT-MRAM using dual references and stepwise current increase may include a method for writing data to designated STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) cells, wherein a control unit including an array including a plurality of STT-MRAM cells obtains a first reference voltage, which is the largest value among voltage values ​​generated based on a current flowing in a low-state Rp resistor, and a second reference voltage, which is the lowest value among voltage values ​​generated based on a current flowing in a high-state Rap resistor, a step of transmitting a designation signal to STT-MRAM cells of a selected address among a plurality of STT-MRAM cells in the array, and obtaining judgment target data from designated STT-MRAM cells, and a step of generating a first write current from Rp to Rap applied to the designated STT-MRAM or a first write current from Rap to Rp applied to the designated STT-MRAM based on the first reference voltage and the second reference voltage.

[0035] In addition, the step of generating the write current may calculate the Rp read current or the Rap read current based on the first reference voltage and the second reference voltage, and convert the Rp read current or the Rap read current to generate the first write current from Rp to Rap or the first write current from Rap to Rp.

[0036] In addition, after the step of generating the write current, the method may further include a step of applying a first write current from Rp to Rap to the designated STT-MRAM for a first time, and a step of detecting a voltage change of the judgment target data to determine whether writing of the designated STT-MRAM is complete.

[0037] In addition, after the above-described judging step, if it is determined that the designated STT-MRAM is not write-completed, the method may further include a step of increasing the first write current from Rp to Rap and applying a second write current from Rp to Rap to the designated STT-MRAM for a second time, and a step of detecting a voltage change of the judgment target data to re-determine whether the writing of the designated STT-MRAM is complete.

[0038] In addition, after the re-judging step, if it is determined that the designated STT-MRAM is not write-completed, the method may further include a step of applying a third write current from Rp to Rap, which increases the second write current from Rp to Rap, to the designated STT-MRAM for a third time, and a step of detecting a voltage change of the judgment target data to determine again whether the writing of the designated STT-MRAM is complete.

[0039] In addition, if it is determined that the voltage of the judgment target data is higher than the second reference voltage during the first time, the second time, or the third time, the method may further include a step of determining that the designated STT-MRAM has completed writing, and a step of controlling the first write current, the second write current, or the third write current to off.

[0040] According to another embodiment, a STT-MRAM writing device using a dual reference and a stepwise current increase is a memory writing device controlled by a processor, comprising: a control unit including a processor; an array including a plurality of STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) cells electrically connected to the control unit; a reference voltage generation unit for generating reference data for comparing with judgment target data for STT-MRAM cells of a selected address among the plurality of STT-MRAM cells; and when the processor executes a plurality of instructions, the processor obtains, from the reference voltage generation unit, a first reference voltage, which is a largest value among voltage values ​​generated based on a current flowing in a low-state Rp resistor, and a second reference voltage, which is a lowest value among voltage values ​​generated based on a current flowing in a high-state Rap resistor, and, based on the first reference voltage and the second reference voltage, a first write current from Rp to Rap applied to the designated STT-MRAM or a first write current from Rap to Rp applied to the designated STT-MRAM. Can be set to generate.

[0041] Additionally, the processor may be configured to apply a first write current from Rap to Rp to the designated STT-MRAM for a first time, and detect a voltage change of the judgment target data to determine whether writing of the designated STT-MRAM is complete.

[0042] In addition, the processor may be configured to apply a second write current from Rap to Rp, which increases the first write current from Rap to Rp, to the specified STT-MRAM for a second time when it determines that the specified STT-MRAM is not write-completed, and to detect a voltage change of the judgment target data to determine again whether the specified STT-MRAM is write-completed.

[0043] In addition, the processor may be configured to apply a third write current from Rap to Rp, which increases the second write current from Rap to Rp, to the designated STT-MRAM for a third time when it determines that the designated STT-MRAM is not write-completed, and to detect a voltage change of the judgment target data to determine again whether the designated STT-MRAM is write-completed.

[0044] Additionally, the processor may be configured to determine that the voltage of the judgment target data is lower than the first reference voltage during the first time, the second time, or the third time, and to determine that the designated STT-MRAM has completed writing, and to control the first write current, the second write current, or the third write current to turn off.

[0045] According to another embodiment, a STT-MRAM read device using a dual reference includes an array including a plurality of STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) cells, a reference voltage generation unit for generating reference data to be compared with judgment target data for STT-MRAM cells of a selected address among the plurality of STT-MRAM cells, a detection circuit for judging a state of data, and a control unit for transmitting a designation signal for obtaining the judgment target data for STT-MRAM cells of the selected address, wherein the detection circuit obtains a first reference voltage, which is a largest value among voltage values ​​generated based on a current flowing in a low-state Rp resistor, from the reference voltage generation unit, and a second reference voltage, which is a lowest value among voltage values ​​generated based on a current flowing in a high-state Rap resistor, and compares the judgment target data with the first reference voltage and the second reference voltage and transmits a comparison result to the control unit.

[0046] In addition, the control unit can obtain the changed first reference voltage and the changed second reference voltage by controlling the current flowing to the reference voltage generation unit.

[0047] Additionally, the first reference voltage and the second reference voltage may vary depending on the resistance distribution of the STT-MRAM cells included in the array.

[0048] In addition, the control unit can determine the state of the data depending on whether the judgment target data obtained through the detection circuit is close to the value of the first reference voltage or close to the value of the second reference voltage.

[0049] In addition, the detection circuit may be connected in series with a first capacitor that is connected in series with designated STT-MRAM cells in response to the Rp resistor and the designation signal to store the first reference voltage and the judgment target data, and may be connected in series with a second capacitor that is connected in series with designated STT-MRAM cells in response to the Rap resistor and the designation signal to store the second reference voltage and the judgment target data.

[0050] Additionally, the detection circuit may further include a third capacitor connected in series with the first capacitor and the second capacitor to perform offset voltage compensation of the comparator.

[0051] A method for reading STT-MRAM using a dual reference according to another embodiment is provided, wherein a control unit including an array including a plurality of STT-MRAM cells and a detection circuit for determining a state of data determines a state of data of a designated STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) cell, the method comprising: obtaining a first reference voltage, which is the largest value among voltage values ​​generated based on a current flowing in a low-state Rp resistor, and a second reference voltage, which is the lowest value among voltage values ​​generated based on a current flowing in a high-state Rap resistor; transmitting a designation signal for designating an STT-MRAM of a selected address among a plurality of STT-MRAM cells in the array to obtain data to be determined; and comparing the data to be determined of designated STT-MRAM cells with the first reference voltage and the second reference voltage in response to the designation signal to determine a state of the data to be determined.

[0052] In addition, prior to the step of obtaining the reference voltage, a step of initializing the voltage values ​​of a first capacitor connected in series with the sensing circuit, a second capacitor connected in series with the sensing circuit, and an amplifier included in the sensing circuit may be further included.

[0053] In addition, before the step of judging the state of the data, the method may further include a step of storing the first reference voltage and the judgment target data in the first capacitor, and storing the second reference voltage and the judgment target data in the second capacitor.

[0054] In addition, after the step of storing in the first capacitor and the second capacitor, the method may further include a step of generating the first reference voltage and the judgment target data using the first capacitor coupling, and generating the second reference voltage and the judgment target data using the second capacitor coupling.

[0055] In addition, the sensing circuit may further include a third capacitor connected in series with the first capacitor and the second capacitor, and may further include a step of storing an offset voltage in the third capacitor before the step of storing a voltage using the coupling of the first capacitor and the second capacitor.

[0056] In addition, a method for reading STT-MRAM using a dual reference, further comprising a step of performing voltage compensation using the offset voltage after the step of generating a voltage using the first capacitor and the second capacitor coupling.

[0057] In addition, the step of judging the state of the data may be such that the control unit can judge the state of the data based on whether the judgment target data is close to the value of the first reference voltage or close to the value of the second reference voltage through the detection circuit.

[0058] According to another embodiment, a STT-MRAM read device using a dual reference is a memory read device controlled by a processor, comprising: a control unit including a processor; an array including a plurality of STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) cells electrically connected to the control unit; a detection circuit for determining a state of data; and a reference voltage generation unit for generating reference data to be compared with judgment target data for STT-MRAM cells of a selected address among the plurality of STT-MRAM cells; wherein, when the processor executes a plurality of instructions, a first reference voltage, which is the largest value among voltage values ​​generated based on a current flowing in a low-state Rp resistor, and a second reference voltage, which is the lowest value among voltage values ​​generated based on a current flowing in a high-state Rap resistor, acquires the judgment target data for STT-MRAM cells of the selected address in the array, transmits a designation signal for acquiring the judgment target data, and compares the judgment target data of designated STT-MRAM cells with the first reference voltage and the second reference voltage in response to the designation signal through the detection circuit, thereby performing the It can be set to judge the status of the judgment target data.

[0059] Additionally, the processor can obtain the changed first reference voltage and the changed second reference voltage by controlling the current flowing to the reference voltage generation unit.

[0060] Additionally, the processor may be configured to initialize voltage values ​​of a first capacitor connected in series with the sensing circuit, a second capacitor connected in series with the sensing circuit, and an amplifier included in the sensing circuit before acquiring the reference voltage.

[0061] Additionally, the processor may be configured to store the first reference voltage and the judgment target data in the first capacitor, and to store the second reference voltage and the judgment target data in the second capacitor, before judging the state of the data.

[0062] Additionally, the processor may be configured to generate the first reference voltage and the judgment target data using the first capacitor coupling, and to generate the second reference voltage and the judgment target data using the second capacitor coupling, before storing the judgment target data in the first capacitor and the second capacitor.

[0063] According to an embodiment, a constant reference voltage can be generated for an STT-MRAM array regardless of process, voltage, and temperature variations, or a reference voltage can be generated using minimal energy to respond to process / temperature variations of the memory.

[0064] In addition, according to the embodiment, the area of ​​the device can be reduced because the writing completion can be determined only based on two reference voltages and the judgment target data of the judgment target cell.

[0065] In addition, according to the embodiment, the problem that occurs due to the small difference in resistance values ​​between the P state and the AP state of the STT-MRAM device, that is, the problem that occurs due to the small read margin, and the existing problem that the STT-MRAM device is vulnerable to process, voltage, and temperature variations can be solved by introducing two new reference voltages instead of the method of generating one reference.

[0066] Additionally, according to the embodiment, the time and energy required for writing data can be further reduced by applying a dynamically changing write current.

[0067] In addition, the area of ​​the device can be reduced as a reference cell or reference BL is not required for each WL inside the memory, and by presenting two new reference voltages and a read circuit, less energy can be consumed compared to existing methods while achieving the same read speed and accuracy as existing methods.

[0068] Figure 1(a) illustrates the most common STT-MRAM write method. Figure 1(b) illustrates the concept of a WT proposed in the prior art, the range of voltage references for the WT, and the process of turning off the current when writing is completed in the WT.

[0069] Figures 2 (a) and 2 (b) are conceptual diagrams explaining a method of finding an average resistance value according to a conventional method and using the same to find a reference voltage.

[0070] Figure 3 shows the range of voltage references for WT and the voltage distribution of P cells and AP cells generated in an STT-MRAM array when a constant write current is applied.

[0071] FIG. 4 is a diagram of an STT-MRAM READ / WRITE system circuit having PVT mutation tolerance of an embodiment.

[0072] Figure 5 is a graph explaining dual reference generation.

[0073] Figure 6 is a graph showing the resistance distribution of the STT-MRAM array and the resistance distribution of the Rp and Rap reference cells and the value of the write reference voltage for the WT generated through current control of the reference cell.

[0074] Figure 7 is a graph explaining the change in write requirement time and resistance of Rp and Rap of STT-MRAM according to temperature and process.

[0075] Figure 8 is a graph showing the change in write requirement time according to the write current of STT-MARM.

[0076] Figure 9 is a flowchart of an STT-MRAM writing method using a dual reference step-wise current increase of an embodiment.

[0077] Figure 10 is a conceptual diagram and graph illustrating a process of writing data from Rp to Rap according to an embodiment.

[0078] Figure 11 is a conceptual diagram and graph explaining the process of writing data from Rap to Rp according to an embodiment.

[0079] FIG. 12 is a conceptual diagram of a device capable of performing STT-MRAM read using a dual reference according to an embodiment.

[0080] Fig. 13 is a flowchart of a STT-MRAM read method using a dual reference according to an embodiment.

[0081] Figures 14 (a), 14 (b) and 14 (c) are graphs explaining dual reference generation.

[0082] Fig. 15 shows the entire circuit diagram including the detection circuit of the embodiment.

[0083] Figure 16 shows the operation of each phase of the entire circuit including the detection circuit of the embodiment.

[0084] Figure 17 is a graph of the waveforms for each phase of the entire circuit including the detection circuit of the embodiment.

[0085] Figure 18 shows the entire circuit including a detection circuit capable of performing an offset function.

[0086] Figure 19 is a graph of the waveforms for each phase of the entire circuit including the detection circuit capable of performing the offset function.

[0087] Figure 20 is a graph explaining the disadvantages of generating a reference voltage using the existing method.

[0088] In describing the embodiments of this specification, if a detailed description of a known technology related to this specification is judged to unnecessarily obscure the gist of this specification, the detailed description will be omitted. In addition, the terms described below are terms defined in consideration of their functions in this specification, and this may vary depending on the intention or custom of the user or operator. Therefore, the definitions should be made based on the contents throughout this specification. The terms used in the detailed description are only for the purpose of describing the embodiments of this specification and should never be construed as limiting. Unless clearly used otherwise, the singular form includes the plural form. In this description, expressions such as "comprises" or "having" are intended to indicate certain features, numbers, steps, operations, elements, parts or combinations thereof, and should not be construed to exclude the presence or possibility of one or more other features, numbers, steps, operations, elements, parts or combinations thereof other than those described.

[0089] Terms containing ordinal numbers, such as "first" and "second," may be used to describe various components, but these components are not limited by these terms. These terms may only be used in a nominal sense to distinguish one component from another, and their ordinal meaning is determined not from the names but from the context of the description.

[0090] The term "and / or" is used to include any combination of the multiple items it refers to. For example, "A and / or B" means all three cases, "A," "B," and "A and B."

[0091] When it is said that a component is "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but there may also be other components in between.

[0092] Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. The following detailed description is provided to facilitate a comprehensive understanding of the methods, devices, and / or objects described herein. However, this is merely an example, and the present invention is not limited thereto.

[0093] Example 1: STT-MRAM writing device and method using dual reference and stepwise current increase

[0094] Figure 3 shows the range of voltage references for WT and the voltage distribution of P cells and AP cells generated in an STT-MRAM array when a constant write current is applied.

[0095] Referring to FIG. 3, since the distribution of resistance of the P cells and AP cells of the STT-MRAM array changes depending on the temperature during the WT process, only one reference voltage located in the middle of the P cells and AP cells cannot properly respond to the temperature change around the chip while writing data to the STT-MRAM.

[0096] In the case of P cells, the change in resistance is relatively small compared to AP cells, but in the case of AP cells, the temperature coefficient of resistance is large depending on the temperature, so it can be seen that the resistance of Rap changes significantly compared to Rp.

[0097] That is, there is a possibility that an error may occur in the WT operation because the reference voltage, which is the standard for controlling the current during a write operation, is not located in the middle of the P cell and the AP cell due to temperature changes.

[0098] In addition, because a single reference voltage was previously generated externally and transmitted internally using a circuit that can control resistance within the chip, the existing reference voltage has a problem in that the write reference does not reflect the PVT (Process, Voltage, Temperature) change of the chip when the temperature and voltage within the chip change.

[0099] By introducing WT in the memory write process, the energy efficiency consumed in the write operation of STT-MRAM can be improved, but since the WCC variation still occurs due to the influence of PVT variation, there are cases where data must be written to specific cells within the array for a long time before the write is completed, and when writing is performed at a constant current, there are still problems with the increase in the overall power and write time, as well as the durability of specific cells.

[0100] In order to solve the problem that the internal reference voltage generated through the resistance circuit or the external bias voltage cannot reflect the PVT variation in real time, the embodiment proposes a method to generate the reference voltage within the STT-MRAM array so that the reference voltage that changes with the PVT variation can be reflected in real time. At this time, in order to minimize the energy and area for generating the reference voltage, a new reference circuit for a write WT operation with PVT tolerance is proposed by using only one AP cell and one P cell each as the number of cells required for generation.

[0101] Fig. 4 is a diagram of an STT-MRAM READ / WRITE system circuit having PVT mutation tolerance of an embodiment. Fig. 5 is a graph explaining dual reference generation. Fig. 6 is a graph showing the resistance distribution of an STT-MRAM array and the resistance distribution of Rp and Rap reference cells and the value of a write reference voltage for WT generated through current control of the reference cells.

[0102] Referring to FIG. 4, an STT-MRAM writing device using a dual reference and stepwise current increase may include an STT-MRAM array (110), a control unit (120), and a reference voltage generation unit (130).

[0103] The STT-MRAM array (110) may include a plurality of STT-MRAM cells. For example, the STT-MRAM array (110) may be formed as an N x M matrix.

[0104] Each STT-MRAM cell can be connected to a bit line (BL) and a word line (WL).

[0105] The control unit (120) can perform the role of a memory controller. For example, the control unit (120) can receive information on STT-MRAM cells at a selected address to be read, and find designated STT-MRAM cells to be written through a command.

[0106] The control unit (120) can use the state of the found STT-MRAM cells, i.e., the specified STT-MRAM, as the judgment target data, detect the changed voltage by applying current, and determine whether the judgment target data has been written.

[0107] That is, the control unit (120) can apply a first write current from Rp to Rap and detect a voltage change in the judgment target data (e.g., voltage value) of the designated STT-MRAM to determine whether the designated STT-MRAM has completed writing.

[0108] The control unit (120) can obtain a first reference voltage, which is the largest value among the voltage values ​​generated based on the current flowing in the low-state Rp resistor, from the reference voltage generation unit (130), and a second reference voltage, which is the lowest value among the voltage values ​​generated based on the current flowing in the high-state Rap resistor.

[0109] The reference voltage generator (130) may include one P cell and one AP cell. The P cell may include a low-state Rp resistance, and the AP cell may include a high-state Rap May include resistance.

[0110] The Rp resistance is the resistance state when the magnetization of the free layer and the reference layer are in the same direction, and the Rap resistance is the resistance state when the magnetization of the free layer and the reference layer are in opposite directions.

[0111] The reference voltage generation unit (130) can receive a signal from the control unit (120) and control the current flowing through the Rp resistor and / or the Rap resistor. In addition, the reference voltage generation unit (130) can calculate a voltage value based on the current flowing through the Rp resistor and / or the Rap resistor and transmit the calculated value to the control unit (120).

[0112] The reference voltage generation unit (130) can receive a signal from the control unit (120) to increase the current of the P cell, and generates a first reference voltage by increasing the IΔ1 current so that it has the largest value among the read voltages generated in the array, as shown in FIG. 5.

[0113] The reference voltage generation unit (130) receives a signal from the control unit (120) and can reduce the current in the case of the AP cell, and generates a second reference voltage by reducing the IΔ2 current to have a smaller value among the read voltages generated in the array as shown in FIG. 5.

[0114] Write operations require a higher current than read operations. Since the currents for generating the first reference voltage and the second reference voltage, as described above, are generated based on the read current, the current for write operations must be generated based on the write current.

[0115] That is, as described above, the IΔ1 current applied to generate the largest value among the reference voltages is used to generate the largest value among the write voltages generated in the array as the first reference voltage, as shown in FIG. 6. The first write current from Rp to Rap can be referenced as IΔ1_for_write, and the control unit (120) can generate the first write current from Rp to Rap using a relationship such as the following mathematical expression 1.

[0116]

[0117] To generate the smallest value among the read voltages generated from the array, the generated IΔ2 is used to generate the second reference voltage, which is the smallest value among the write voltages generated from the array, as shown in Fig. 6. The first write current from Rap to Rp can be referenced as IΔ2_for_write, and the control unit (120) can generate the first write current from Rap to Rp using a relationship such as the following mathematical expression 2.

[0118]

[0119] From the viewpoint of responding to process variations, the two reference voltages of AP and P generated through current adjustment based on the results of the reading process can operate a current adjustment algorithm based on the detection results of the Sense Amplifier included in the control unit (120), so that the reference cell can always stably generate the largest reference voltage of P and the smallest reference voltage of AP regardless of process variations.

[0120] From the viewpoint of responding to temperature changes, the two reference voltages of AP and P generated through current control are voltages created using STT-MRAM cells, so the temperature coefficient of the array and the temperature coefficient of the reference cells are the same, automatically reflecting temperature changes and stably generating the largest reference voltage of P and the smallest reference voltage of AP at all times.

[0121] The algorithm that can control the current of the STT-MRAM reference cell was implemented as a digital circuit through RTL design, and two reference voltages of AP and P can be generated using two STT-MRAM cells.

[0122] According to the control unit (120) and the reference voltage generation unit (130) that can be included in the STT-MRAM writing device using the dual reference and stepwise current increase according to the embodiment described in FIGS. 4, 5 and 6, since the reference voltage is generated within the memory array without using an external voltage, compared to the existing write reference generation method, the reference voltage can be generated by reflecting the environmental variables for PVT in real time.

[0123] Figure 7 is a graph explaining the change in write requirement time and resistance of Rp and Rap of STT-MRAM according to temperature and process.

[0124] Figure 7 illustrates the phenomenon that the write time and resistance distribution of STT-MRAM vary depending on temperature / process variations. In the case of the AP cell of STT-MRAM, when the temperature is higher than room temperature, the resistance Rap decreases and the write time decreases. Conversely, when the temperature decreases, the resistance of Rap increases and the write time increases. In addition, due to process variations, the time and current required for data writing for numerous STT-MRAMs in an array may all vary, and the write time required for P cells also varies depending on the temperature / process.

[0125] While the average write energy can be reduced through the WT reference circuit generated within the existing STT-MRAM technology, the PVT variation still causes write critical current (WCC) variation, requiring long write times for certain cells within the array. Thus, memory write times are determined by cells with significant WCC variation and long write times.

[0126] Figure 8 is a graph showing the change in write requirement time according to the write current of STT-MARM.

[0127] Referring to Fig. 8, there is a method of reducing the write time by using a higher current for cells with a high WCC variation for fast writing in a memory circuit, but there is a problem of low energy efficiency due to high power consumption and a problem of reducing the durability of the memory cell due to the use of a high current.

[0128] To address these issues, another embodiment proposes a novel writing method that is energy efficient and capable of writing at a high speed even under WCC variations, using a programmable step write generator rather than the conventional memory writing method of applying a constant current or voltage.

[0129] In an embodiment, a write generator is proposed that gradually increases the write current at a programmed time interval and current interval over time in response to write temperature / process / voltage variations by implementing a programmable current driver. According to the embodiment, the deviation of the write time that varies from cell to cell is reduced to perform an energy-efficient write operation, and even when a write operation is performed on multiple cells within an array simultaneously, the write driver is powered off in the order in which the write operation of each cell is completed, so that the cell endurance can be increased while the write BER can be lowered while performing energy-efficient writing.

[0130] Figure 9 is a flowchart of an STT-MRAM writing method using a dual reference and stepwise current increase of an embodiment.

[0131] Referring to FIG. 9, the STT-MRAM writing method using the stepwise current increase of the embodiment comprises the steps of: obtaining a first reference voltage, which is the largest value among the voltage values ​​generated based on the current flowing in the Rp resistor in a low state, and a second reference voltage, which is the lowest value among the voltage values ​​generated based on the current flowing in the Rap resistor in a high state (S910); transmitting a designated signal to STT-MRAM cells of a selected address among a plurality of STT-MRAM cells in an array, and obtaining judgment target data from the designated STT-MRAM (S920); generating a first write current from Rp to Rap applied to the designated STT-MRAM or a first write current from Rap to Rp applied to the designated STT-MRAM based on the first reference voltage and the second reference voltage (S930); applying the first write current from Rp to Rap to the designated STT-MRAM for a first time and detecting a voltage change in the judgment target data to write the designated STT-MRAM The method may include a step (S940) of determining whether or not writing is completed, a step (S950) of applying a second write current from Rp to Rap, which is an increase in the first write current from Rp to Rap, to the designated STT-MRAM for a second time period, and detecting a change in the voltage of the judgment target data to determine again whether or not writing of the designated STT-MRAM is completed, and a step (S960) of controlling the first write current or the second write current to off, if it is determined that the voltage of the judgment target data is higher than the second reference voltage for the first time period or the second time period, determining that the writing of the designated STT-MRAM is completed.

[0132] In Fig. 9, a step of applying a first write current for a first time period, applying a second write current for a second time period, and determining whether the STT-MRAM has completed writing is shown, but this is due to space limitations and also for convenience of explanation.

[0133] The STT-MRAM writing method using the stepwise current increase of the embodiment may further include a step of applying a third write current that increases the second write current from Rp to Rap to the designated STT-MRAM for a third time when it is determined that the writing of the designated STT-MRAM is not completed, and detecting a voltage change of the judgment target data to determine again whether the writing of the designated STT-MRAM is completed.

[0134] The embodiment can generate a fourth write current and a fifth write current by gradually increasing the size of the current, detect a voltage change of the judgment target data by applying the increased current for a certain period of time (e.g., 10 ns, a fourth time, or a fifth time), and continuously and repeatedly determine whether the writing of the specified STT-MRAM is complete.

[0135] Additionally, the control unit of the embodiment can detect whether the voltage of the judgment target data has increased or decreased, and can further include a comparator to compare the voltage of the judgment target data with the magnitude of the first reference voltage or to compare the voltage of the judgment target data with the magnitude of the second reference voltage.

[0136] Additionally, the control unit of the embodiment can determine that the designated STT-MRAM has completed writing if it determines that the voltage of the judgment target data is higher than the second reference voltage or lower than the first reference voltage.

[0137] Fig. 10 is a conceptual diagram and graph illustrating a process of writing data from Rp to Rap according to an embodiment. Fig. 11 is a conceptual diagram and graph illustrating a process of writing data from Rap to Rp according to an embodiment.

[0138] According to an embodiment, when writing data from an Rp cell to a Rap cell, an operation process such as that shown in FIG. 10 may be performed.

[0139] Step 1: When writing AP in P, a programmable initial current (Initial Iwrite) (e.g., first write current) of Fig. 10 is applied to the data cell, and the reference voltage for WT uses the AP write reference voltage (e.g., first reference voltage) generated by the reference voltage generation unit (130). The tN value and Istep_APN of [Fig. 10] can be programmably adjusted through a digital controller.

[0140] Step 2: While pouring the initial current during the time t0 (e.g., the first time) of Fig. 10, the comparator (SA) checks whether the cell to which data is currently being written has had data written or not yet.

[0141] Step 3: If the cell currently being written with data has not had data written, the write current is increased from the initial current by Istep_AP0 of Fig. 10 and the increased current is applied for time t1 (e.g., the second time).

[0142] Step 4: If the cell being written has not had data written even after t1 time has passed, the write current is increased by Istep_APN of Fig. 10 from the previous current, and the process of pouring the increased current for tN time is repeated.

[0143] Step 5: If the cell currently being written with data has been written, the result (SAOUT) of the comparator changes as shown in Figure 10, and the current driver is turned off through the WT logic.

[0144] According to an embodiment, when writing data from a Rap cell to an Rp cell, an operation process such as that in FIG. 11 may be performed.

[0145] Step 1: When writing P in AP, a programmable initial current (Initial Iwrite) of FIG. 11 is applied to the data cell, and the reference voltage for WT uses the P write reference voltage (e.g., the second reference voltage) generated by the reference voltage generation unit (130). The tN value and Istep_PN of FIG. 11 can be programmably adjusted through a digital controller.

[0146] Step 2: While pouring the initial current during the time t0 (e.g., the first time) of Fig. 11, the comparator (SA) checks whether the cell to which data is currently being written has had data written or not yet been written.

[0147] Step 3: If the cell currently being written with data has not had data written, the write current is increased from the initial current by Istep_P0 of Fig. 11 and the increased current is applied for time t1 (e.g., the second time).

[0148] Step 4: If the cell being written has not had data written even after t1 time has passed, the write current is increased by Istep_PN of Figure 11 from the previous current, and the process of pouring the increased current is repeated for tN time.

[0149] Step 4: If the cell currently being written with data has been written, the result (SAOUT) of the comparator changes as shown in Figure 11, and the current driver is turned off through the WT logic.

[0150] According to the STT-MRAM writing device and method using dual reference and stepwise current increase according to the various embodiments described above, even if a write operation is performed by applying process / voltage / temperature changes used in the prior art to a 512X512 STT-MRAM Array, the required current is reduced by more than 30% compared to the method of applying a constant current used in the prior art.

[0151] Additionally, according to the embodiment, the write reference required for WT in the semiconductor area is less than 0.001% of the memory array area.

[0152] Example 2: STT-MRAM reading device and method using dual reference

[0153] FIG. 12 is a conceptual diagram of a device capable of performing STT-MRAM read using a dual reference according to an embodiment.

[0154] Referring to FIG. 12, an STT-MRAM read device using a dual reference according to an embodiment may include an STT-MRAM array (210), a control unit (220), a detection circuit (230), and a reference voltage generation unit (240).

[0155] The STT-MRAM array (210) may include a plurality of STT-MRAM cells. For example, the STT-MRAM array (210) may be formed as an N x M matrix.

[0156] Each STT-MRAM cell can be connected to a bit line (BL) and a word line (WL).

[0157] The control unit (220) can perform the role of a memory controller. For example, the control unit (220) can receive information on STT-MRAM cells to be read and find the STT-MRAM cells to be read through a command.

[0158] The control unit (220) uses the status of the designated STT-MRAM cells of the found address as the judgment target data, and can read the status of the designated STT-MRAM cells through the detection circuit (230).

[0159] The control unit (220) can obtain a first reference voltage, which is the largest value among the voltage values ​​generated based on the current flowing in the low-state Rp resistor, from the reference voltage generation unit (240), and a second reference voltage, which is the lowest value among the voltage values ​​generated based on the current flowing in the high-state Rap resistor. A detailed process for calculating the first reference voltage and the second reference voltage is described in Fig. 14.

[0160] The control unit (220) can obtain a changed first reference voltage and a changed second reference voltage by controlling the current flowing to the reference voltage generation unit (240).

[0161] According to an embodiment, the control unit (220) may include a detection circuit (230).

[0162] The control unit (220) can transmit the acquired judgment target data, the first reference voltage, and the second reference voltage to the detection circuit (230). The detection circuit (230) can compare the judgment target data with the first reference voltage and the second reference voltage, and transmit the comparison result of which value of the first reference voltage and the second reference voltage the judgment target data is closer to to the control unit (220). The detailed operation of the detection circuit (230) is described in FIGS. 15, 16, and 17.

[0163] The reference voltage generator (240) may include one P cell and one AP cell. The P cell may include a low-state Rp resistance, and the AP cell may include a high-state Rap May include resistance.

[0164] The Rp resistance is the resistance state when the magnetization of the free layer and the reference layer are in the same direction, and the Rap resistance is the resistance state when the magnetization of the free layer and the reference layer are in opposite directions.

[0165] The reference voltage generation unit (240) can receive a signal from the control unit (220) and control the current flowing through the Rp resistor and / or the Rap resistor. In addition, the reference voltage generation unit (240) can calculate a voltage value based on the current flowing through the Rp resistor and / or the Rap resistor, and transmit the calculated value to the control unit (220).

[0166] Fig. 13 is a flowchart of a STT-MRAM read method using a dual reference according to an embodiment.

[0167] Referring to FIG. 13, the STT-MRAM reading method using a dual reference of the embodiment may include a step (S1310) of initializing a voltage value of a first capacitor connected in series with a sensing circuit (230), a second capacitor connected in series with the sensing circuit (230), and an amplifier included in the sensing circuit (230), a step (S1320) of obtaining a first reference voltage, which is the largest value among voltage values ​​generated based on a current flowing in a low-state Rp resistor, and a second reference voltage, which is the lowest value among voltage values ​​generated based on a current flowing in a high-state Rap resistor, a step (S1330) of transmitting a designation signal for obtaining judgment target data by designating an STT-MRAM of a selected address among a plurality of STT-MRAM cells in the array, and a step (S1340) of comparing the judgment target data of the designated STT-MRAM cells with the first reference voltage and the second reference voltage in response to the designation signal to determine the state of the judgment target data.

[0168] Figures 14 (a), 14 (b) and 14 (c) are graphs explaining dual reference generation.

[0169] As in the Array R Distribution of Fig. 14, the distribution of the resistances of the reference P cell and the reference AP cell can be distributed arbitrarily within the array. The read operation is repeated while fixing the read current of the AP and P cell within the N x M array.

[0170] Referring to FIG. 14, the dual reference means a first reference voltage, which is the largest value among the voltage values ​​generated based on the current flowing in the low-state Rp resistor, and a second reference voltage, which is the lowest value among the voltage values ​​generated based on the current flowing in the high-state Rap resistor.

[0171] The first reference voltage can be calculated based on the current flowing through the largest resistance among the Rp resistances, when the distribution of the low-state Rp resistance is as shown in (b) of Fig. 14, and the reference voltage generation unit (240) receives a signal from the control unit (220) to control the current flowing through the RP resistance.

[0172] The second reference voltage can be calculated based on the current flowing through the smallest resistance among the Rap resistors, when the distribution of high-state Rap resistors is as shown in (b) of Fig. 14, and the reference voltage generation unit (240) receives a signal from the control unit (220) to adjust the current flowing through the Rap resistors.

[0173] According to one embodiment, the reference voltage generation unit (240) can generate a P reference voltage, i.e., a first reference voltage, by increasing the current by IΔ1 so as to have the largest value among the read voltages generated from the array, as shown in (b) of FIG. 14.

[0174] According to one embodiment, the reference voltage generation unit (240) can generate an AP reference voltage, i.e., a second reference voltage, by reducing the current by IΔ2 so as to have the smallest value among the read voltages generated from the array, as shown in (c) of FIG. 14.

[0175] According to the STT-MRAM reading device and method using a dual reference according to the embodiments of FIGS. 12, 13, and 14, the two reference voltages of the P cell and the AP cell generated through current control can be operated by a current control algorithm based on the detection result of the detection circuit (230), so that the reference cell can always stably generate the largest P reference voltage and the smallest AP reference voltage regardless of the STT-MRAM process variation.

[0176] In addition, from the viewpoint of responding to temperature changes, the two reference voltages of the P cell and AP cell generated through current control are voltages generated using STT-MRAM cells, so the temperature coefficient of the array and the temperature coefficient of the reference cell are the same, so the largest reference voltage of P and the smallest reference voltage of AP can always be stably generated regardless of temperature changes.

[0177] An algorithm capable of controlling the current of an STT-MRAM reference cell can be implemented through a digital circuit, and according to an embodiment, two reference voltages of a P-cell and an AP-cell can be generated using only two STT-MRAMs.

[0178] According to the proposed embodiment, compared to the existing reference generation circuit, the number of reference cells can be drastically reduced, thereby increasing the energy efficiency used in a read operation and reducing the area of ​​the device by not using an additional reference column.

[0179] Fig. 15 shows a full circuit diagram including the detection circuit of the embodiment. Fig. 16 shows the operation of each phase of the full circuit including the detection circuit of the embodiment. Fig. 17 is a graph of the waveforms of each phase of the full circuit including the detection circuit of the embodiment.

[0180] Referring to FIG. 15, the sensing circuit (230) may be configured with a Dual Reference Sense Amplifier (DSRA) to increase the read margin and thus improve accuracy in read operations. The read margin may be defined as the difference in resistance values ​​between the P state and the AP state.

[0181] The core principle of the detection circuit (230) is a structure that can read the data of the cell of the STT-MRAM by comparing it with two references (e.g., a first reference voltage and a second reference voltage). The capacitors C1 (e.g., a first capacitor) and C2 (e.g., a second capacitor) on both sides are used to generate a voltage difference between the data and the two references, which doubles the read margin compared to the conventional half reference (e.g., (b) of FIG. 2), and thus, a low read error can be obtained thanks to the increased read margin compared to the basic method.

[0182] Looking at the operation of each phase of the entire circuit including the detection circuit (230), in Phase 1, the voltage values ​​of the capacitor and amplifier are initialized by turning ON the switches S1, S5, and S6 of the DRSA, and the WL of the reference cell and data cell is turned ON to apply the BL voltage to the reference cell and data cell.

[0183] In Phase 2, one side of capacitors C1 and C2 of DRSA is grounded and S2 is turned ON to store the voltage generated in the reference cell and the voltage of the data cell in capacitors C1 and C2.

[0184] In Phase 3, S1 and S2 of DRSA are turned OFF and S4 is turned ON to generate the voltage generated from the reference cell and the voltage of the data cell across the capacitors by coupling them to capacitors C1 and C2.

[0185] In Phase 4, the voltage generated in Phase 3 is input to the Latch input through S5, and in Phase 4, S3 turns ON, the Latch operates, and the result of data reading can be obtained depending on which of the reference voltages Rp and Rap the data comparison result is closer to.

[0186] Figure 18 shows the entire circuit including a detection circuit capable of performing an offset function.

[0187] Figure 19 is a graph of the waveforms for each phase of the entire circuit including the detection circuit capable of performing the offset function.

[0188] The sensing circuit (230) of the embodiment may include Coffset (e.g., a third capacitor), and a Single-Cap Offset-Cancelled Sense Amplifier may also be applied to compensate for the offset voltage generated by the process variation of the Sense Amplifier.

[0189] In Phase 1, the voltage values ​​of the capacitor and amplifier are initialized by turning ON the S2, S3, and S6 switches of the DRSA, and the BL voltage of the reference cell and data cell is applied by turning ON the WL of the reference cell and data cell.

[0190] In Phase 2, S6 of DRSA is turned OFF to isolate the latch from the external structure, and S1 and S4 are turned ON to store the offset voltage of the latch in Coffset. One side of capacitors C1 and C2 is grounded through S2, and the voltage generated from the reference cell and the voltage of the data cell are stored in capacitors C1 and C2 through S3.

[0191] In Phase 3, the offset of the sense amplifier is canceled by compensating for the offset voltage stored in Coffset in Phase 2 by turning off S1 and S4 of the DRSA and turning on S6. In Phase 2, the voltage generated from the reference cell and the voltage of the data cell are continuously stored in capacitors C1 and C2.

[0192] In Phase 4, S2 and S3 of DRSA are turned OFF and S5 is turned ON to generate the voltage generated from the reference cell and the voltage of the data cell across the capacitors by coupling them to capacitors C1 and C2.

[0193] In Phase 5, the voltage generated in Phase 4 is input to the Latch input through S6, and in Phase 5, S4 turns ON and the Latch operates. The result of comparing the data is that the data voltage is closer to the reference voltage Rp or Rap, and the result of reading the data with the Latch offset compensated can be obtained.

[0194] Figure 20 is a graph explaining the disadvantages of generating a reference voltage using the existing method.

[0195] As shown in Fig. 2, when half the read reference voltage is generated by the conventional technology, the read Bit-Error-Rate (BER) is 13.32% at 25°C and 35.8% at 120°C due to process changes as shown in Fig. 20. This is a value that occurs due to process / temperature changes of the STT-MRAM without any application of the Offset of the Sense Amplifier circuit, and the read Bit-Error-Rate (BER) may increase further when the circuit is actually operated.

[0196] When the same process / temperature change is applied to a 512 X 512 STT-MRAM Array, two references are set through the algorithm of FIG. 14, and STT-MRAM Readout is driven, the read Bit-Error-Rate (BER) can achieve 0% at all temperatures, and considering the Offset of the Dual Reference Sense Amplifier (DRSA) circuit, the read Bit-Error-Rate (BER) is less than 0.01%. In terms of semiconductor area, the read reference of the prior art occupies about 5% of the memory array, but in the embodiment it is less than 0.001%. In addition, in terms of energy efficiency, according to the embodiment, the current required for one read process can be reduced by more than 10%.

[0197] The description of this specification above is provided for illustrative purposes only, and those skilled in the art will readily appreciate that the embodiments described herein can be readily modified into other specific forms without altering the technical spirit or essential characteristics of the embodiments. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

[0198] The scope of the embodiments is indicated by the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the embodiments.

Claims

1. An array comprising a plurality of STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) cells; A reference voltage generation unit that generates reference data for comparison with judgment target data for STT-MRAM cells of a selected address among the plurality of STT-MRAM cells; and A control unit for transmitting a designated signal to obtain the judgment target data for the STT-MRAM cells of the selected address, The above control unit obtains a first reference voltage, which is the largest value among the voltage values ​​generated based on the current flowing in the low-state Rp resistor from the reference voltage generation unit, and a second reference voltage, which is the lowest value among the voltage values ​​generated based on the current flowing in the high-state Rap resistor. An STT-MRAM writing device using dual references and stepwise current increase, which generates a first write current from Rp to Rap applied to a designated STT-MRAM or a first write current from Rap to Rp applied to the designated STT-MRAM based on the first reference voltage and the second reference voltage.

2. In paragraph 1, The above control unit, By controlling the current flowing to the above reference voltage generation unit, a changed first reference voltage and a changed second reference voltage are obtained, and a first write current from the changed Rp to Rap and a first write current from the changed Rap to Rp are generated based on the changed first reference voltage and the changed second reference voltage. An STT-MRAM writing device using dual references and stepwise current increase, wherein the first reference voltage, the second reference voltage, the first write current from Rp to Rap, and the first write current from Rap to Rp vary according to the resistance distribution of STT-MRAM cells included in the array.

3. In paragraph 1, The above control unit, An STT-MRAM writing device using a dual reference and stepwise current increase, which applies a first write current from Rp to Rap to the designated STT-MRAM for a first time, and detects a voltage change of the judgment target data to determine whether the writing of the designated STT-MRAM is complete.

4. In paragraph 3, The above control unit, If it is determined that the above-mentioned STT-MRAM is not write-completed, a second write current from Rp to Rap, which is an increased first write current from Rp to Rap, is applied to the above-mentioned STT-MRAM for a second time, and a voltage change in the judgment target data is detected to re-determine whether the write of the above-mentioned STT-MRAM is complete. An STT-MRAM writing device using a dual reference and stepwise current increase, which applies a third write current from Rp to Rap, which is a second write current increased from Rp to Rap, to the designated STT-MRAM for a third time, and detects a voltage change of the judgment target data to again judge whether the write of the designated STT-MRAM is completed, if it is determined that the designated STT-MRAM is still not written in completion.

5. In paragraph 4, The above control unit, An STT-MRAM writing device using a dual reference and stepwise current increase, wherein if it is determined that the voltage of the judgment target data is higher than the second reference voltage during the first time, the second time, or the third time, it is determined that the designated STT-MRAM has completed writing, and the first write current, the second write current, or the third write current is controlled to off.

6. A method for writing data to STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) cells, wherein a control unit includes an array including a plurality of STT-MRAM cells, A step of obtaining a first reference voltage, which is the largest value among the voltage values ​​generated based on the current flowing in the low-state Rp resistance, and a second reference voltage, which is the lowest value among the voltage values ​​generated based on the current flowing in the high-state Rap resistance; A step of transmitting a designated signal to STT-MRAM cells of a selected address among a plurality of STT-MRAM cells in the above array and obtaining judgment target data from the designated STT-MRAM cells; and A STT-MRAM write method using dual references and stepwise current increase, comprising: a step of generating a first write current from Rp to Rap applied to the designated STT-MRAM or a first write current from Rap to Rp applied to the designated STT-MRAM based on the first reference voltage and the second reference voltage.

7. In paragraph 6, The step of generating the above writing current is A STT-MRAM write method using dual references and stepwise current increase, which calculates an Rp read current or a Rap read current based on the first reference voltage and the second reference voltage, and converts the Rp read current or the Rap read current to generate a first write current from Rp to Rap or a first write current from Rap to Rp.

8. In paragraph 6, After the step of generating the above writing current, A step of applying a first write current from Rp to Rap to the above-mentioned STT-MRAM for a first time; and A STT-MRAM writing method using a dual reference and a stepwise current increase, further comprising a step of detecting a voltage change of the above judgment target data to determine whether the writing of the specified STT-MRAM is complete.

9. In paragraph 8, After the step of determining whether the above writing is complete, if it is determined that the above-mentioned STT-MRAM is not complete to write, a step of increasing the first writing current from Rp to Rap and applying a second writing current from Rp to Rap to the above-mentioned STT-MRAM for a second time; and Further comprising a step of detecting a voltage change of the above judgment target data and re-judging whether the writing of the above-mentioned STT-MRAM is complete, After the step of re-determining whether the above writing is complete, if it is determined that the above-mentioned STT-MRAM is not complete to write, a step of applying a third write current from Rp to Rap, which increases the second write current from Rp to Rap, to the above-mentioned STT-MRAM for a third time; and A STT-MRAM writing method using a dual reference and a stepwise current increase, further comprising a step of detecting a voltage change of the above judgment target data to determine again whether the writing of the specified STT-MRAM is complete.

10. In paragraph 9, A step of determining that the designated STT-MRAM has completed writing if it is determined that the voltage of the judgment target data is higher than the second reference voltage during the first time, the second time, or the third time; and A STT-MRAM write method using dual references and stepwise current increase, further comprising a step of controlling the first write current, the second write current, or the third write current to turn off.

11. An array comprising a plurality of STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) cells; A reference voltage generation unit that generates reference data for comparison with judgment target data for STT-MRAM cells of a selected address among the plurality of STT-MRAM cells; A detection circuit for judging the status of data; and A control unit for transmitting a designated signal to obtain the judgment target data for the STT-MRAM cells of the selected address, The above detection circuit obtains a first reference voltage, which is the largest value among the voltage values ​​generated based on the current flowing in the low-state Rp resistor from the reference voltage generation unit, and a second reference voltage, which is the lowest value among the voltage values ​​generated based on the current flowing in the high-state Rap resistor. A STT-MRAM read device using a dual reference that compares the above judgment target data with the first reference voltage and the second reference voltage and transmits the comparison result to the control unit.

12. In paragraph 11, The above control unit, By controlling the current flowing to the above reference voltage generation unit, the changed first reference voltage and the changed second reference voltage are obtained. An STT-MRAM read device using a dual reference, wherein the first reference voltage and the second reference voltage change according to the resistance distribution of the STT-MRAM cells included in the array.

13. In paragraph 11, The above control unit is an STT-MRAM read device using a dual reference that determines the state of the data based on whether the judgment target data obtained through the detection circuit is close to the value of the first reference voltage or close to the value of the second reference voltage.

14. In paragraph 11, The above detection circuit, A first capacitor is connected in series with the designated STT-MRAM cells in response to the above Rp resistor and the above designated signal, and stores the first reference voltage and the judgment target data, A STT-MRAM read device using a dual reference, the second capacitor being connected in series with the designated STT-MRAM cells in response to the Rap resistor and the designated signal and storing the second reference voltage and the judgment target data.

15. In paragraph 14, The above detection circuit, A STT-MRAM read device using a dual reference, further comprising a third capacitor connected in series with the first capacitor and the second capacitor to perform offset voltage compensation of a comparator.

16. A method for determining the data status of STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) cells, wherein the control unit includes a detection circuit for determining the data status and an array including a plurality of STT-MRAM cells, A step of obtaining a first reference voltage, which is the largest value among the voltage values ​​generated based on the current flowing in the low-state Rp resistance, and a second reference voltage, which is the lowest value among the voltage values ​​generated based on the current flowing in the high-state Rap resistance; A step of transmitting a designation signal to obtain judgment target data by designating an STT-MRAM of a selected address among a plurality of STT-MRAM cells in the above array; and A STT-MRAM read method using a dual reference, comprising the step of comparing the judgment target data of designated STT-MRAM cells with the first reference voltage and the second reference voltage in response to the above-mentioned designated signal to determine the state of the judgment target data.

17. In paragraph 16, Before the step of obtaining the above reference voltage, A STT-MRAM read method using a dual reference, further comprising the step of initializing a voltage value of a first capacitor connected in series with the sensing circuit, a second capacitor connected in series with the sensing circuit, and an amplifier included in the sensing circuit.

18. In paragraph 17, Before the step of judging the status of the above data, Store the first reference voltage and the judgment target data in the first capacitor, A STT-MRAM read method using a dual reference, further comprising the step of storing the second reference voltage and the judgment target data in the second capacitor.

19. In paragraph 18, After the step of storing in the first capacitor and the second capacitor, The above first reference voltage and the above judgment target data are generated using the first capacitor coupling, A STT-MRAM read method using a dual reference, further comprising a step of generating the second reference voltage and the judgment target data using a second capacitor coupling.

20. In paragraph 19, The above detection circuit further includes a third capacitor connected in series with the first capacitor and the second capacitor, Before the step of storing voltage using the first capacitor and the second capacitor coupling, Further comprising a step of storing an offset voltage in the third capacitor, After the step of generating a voltage using the first capacitor and the second capacitor coupling, A STT-MRAM read method using a dual reference, further comprising a step of performing voltage compensation using the above offset voltage.

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