Configurable power management techniques for in-memory compute arrays

Abstract

Devices and techniques can include an integrated circuit (IC), including: a plurality of compute-in-memory (CIM) arrays of computing cells, a plurality of programmable DC-DC converters each providing an output voltage as a function of a reference voltage, and a plurality of driver circuits configured to generate a plurality of analog voltages selectively provided to the CIM arrays. Devices and techniques can include a package housing the IC and including: a plurality of passive electrical components coupled with the programmable DC-DC converters and configured to generate a plurality of filtered output voltages, and a plurality of interconnects, each having one terminal coupled with at least one of the passive electrical components and another terminal coupled with another portion of the IC.

Description

CONFIGURABLE POWER MANAGEMENT TECHNIQUES FOR IN-MEMORY COMPUTE ARRAYSCROSS-REFERENCE TO RELATED APPLICATIONThis Application claims priority to and the benefit of United States Provisional Application 63 / 606,015, filed December 4, 2023.TECHNICAL FIELD

[0001] This disclosure relates to in-memory computing arrays, and in particular to providing power to one or more arrays on a chip.DESCRIPTION OF THE RELATED TECHNOLOGY

[0002] Using in-memory computing for neural network acceleration is an emerging and innovative approach that leverages the unique properties of memory devices to enhance the speed and efficiency of neural network computations. Traditional neural network training and inference processes involve moving data back and forth between memory (RAM) and processing units (CPUs or GPUs), which can be a significant bottleneck in terms of speed and energy consumption. In-memory computing seeks to overcome these limitations by processing data directly within the memory itself.SUMMARY

[0003] In some aspects, the techniques described herein relate to a device, including: an integrated circuit, including: a plurality of compute-in-memory (CIM) arrays of computing cells, each computing cell including a memory cell and an input port for receiving an input for computation with data stored in the memory cell, a plurality of programmable DC-DC converters, each programmable DC-DC converter of the plurality of DC-DC converters having a reference input that receives a reference voltage and an output port providing an output voltage that is a function of the reference voltage, and a plurality of driver circuits configured to generate a plurality of analog voltages, the plurality of analog voltages selectively provided to the plurality of CIM arrays; and a package housing the integrated circuit, the package including: a plurality of passive electrical components coupled with the plurality of programmable DC-DC converters on the integrated circuit, the plurality of passive components configured to filter the plurality of output voltages provided by the plurality of programmable DC-DC converters to generate a plurality of filtered output voltages, and a plurality of interconnects, eachinterconnect of the plurality of interconnects having one terminal coupled with at least one of the plurality of passive electrical components and another terminal coupled with another portion of the integrated circuit, wherein the plurality of interconnects provide the plurality of filtered output voltages to the plurality of driver circuits.

[0004] In some aspects, the techniques described herein relate to a device, wherein each DC-DC converter of the plurality of DC-DC converters provides one of at least two voltages as the output voltage.

[0005] In some aspects, the techniques described herein relate to a device, wherein the plurality of DC-DC converters positioned along a periphery of the integrated circuit, and wherein the plurality of interconnects are positioned to run across the integrated circuit within the package between DC-DC converters positioned on opposite sides of the integrated circuit.

[0006] In some aspects, the techniques described herein relate to a device, wherein a set of interconnects from the plurality of interconnects are electrically coupled with each other and with the plurality of CIM arrays, and wherein a set of DC-DC converters of the plurality of DC-DC converters provide a same output voltage at their respective output ports, their respective output ports having their respective filtered output voltages provided to the set of interconnects.

[0007] In some aspects, the techniques described herein relate to a device, wherein the package includes a plurality of vias that couple the plurality of interconnects with the plurality of DC-DC converters and with the another portion of the integrated circuit.

[0008] In some aspects, the techniques described herein relate to a device, wherein the plurality of DC-DC converters include buck converters.

[0009] In some aspects, the techniques described herein relate to a device, wherein the buck converters have an output programmable range configured to enable the buck converters to be set to the minimum voltage required for one or more of the plurality of the driver circuits in the CIM array.

[0010] In some aspects, the techniques described herein relate to a device, wherein the plurality of passive electrical components includes at least one of capacitors or inductors.

[0011] In some aspects, the techniques described herein relate to a method, the method including a method of an integrated circuit (IC), the IC including: a plurality of computein-memory (CIM) arrays of computing cells, each computing cell including a memory cell and an input port for receiving an input for computation with data stored in the memory cell; a plurality of programmable DC-DC converters, and a plurality of drivercircuits, wherein the IC is housed in a package, wherein the package includes a plurality of passive electrical components coupled with the plurality of programmable DC-DC converters, the package further including a plurality of interconnects, each interconnect of the plurality of interconnects having one terminal coupled with at least one of the plurality of passive electrical components and another terminal coupled with another portion of the IC, the method including: receiving, at each programmable DC-DC converter of the plurality of DC-DC converters, a reference voltage; providing a corresponding output voltage at each programmable DC-DC converter of the plurality of DC-DC converters, the corresponding output voltage being a function of the reference voltage; generating, by the plurality of driver circuits, a respective plurality of analog voltages, the plurality of analog voltages being selectively provided to the plurality of CIM arrays; filtering, by the plurality of passive components, the plurality of corresponding output voltages provided by the plurality of programmable DC-DC converters to generate a plurality of filtered output voltages, and providing, by the plurality of interconnects, the plurality of filtered output voltages to the plurality of driver circuits.

[0012] In some aspects, the techniques described herein relate to a method, the method including providing, at each DC-DC converter of the plurality of DC-DC converters, one of at least two voltages as the output voltage.

[0013] In some aspects, the techniques described herein relate to a method, wherein the plurality of DC-DC converters are positioned along a periphery of the IC, and wherein the plurality of interconnects are positioned to run across the IC within the package between DC-DC converters positioned on opposite sides of the IC.

[0014] In some aspects, the techniques described herein relate to a method, the method including electrically coupling a set of interconnects from the plurality of interconnects with each other and with the plurality of CIM arrays, providing, at respective outputs ports of a set of DC-DC converters of the plurality of DC-DC converters, a same output voltage, and providing filtered output voltages corresponding to the same output voltage at the respective output ports to the set of interconnects.

[0015] In some aspects, the techniques described herein relate to a method, wherein the package includes a plurality of vias that couple the plurality of interconnects with the plurality of DC-DC converters and with the another portion of the integrated circuit.

[0016] In some aspects, the techniques described herein relate to a method, wherein the plurality of DC-DC converters include buck converters.

[0017] In some aspects, the techniques described herein relate to a method, wherein the buck converters include an output programmable range, the method further including setting the buck converters to a minimum voltage required for one or more of the plurality of the driver circuits in the CIM array.

[0018] In some aspects, the techniques described herein relate to a method, wherein the plurality of passive electrical components includes at least one of capacitors or inductors.

[0019] In some aspects, the techniques described herein relate to a device, the device including an integrated circuit (IC), the IC including: a plurality of compute-in-memory (CIM) arrays of computing cells, each computing cell including a memory cell and an input for enabling computation with data stored in the memory cell, a plurality of programmable DC-DC converters, each programmable DC-DC converter having a reference input configured to receive a reference voltage and an output port configured to provide an output voltage based on the reference voltage, and a plurality of driver circuits configured to generate a plurality of analog voltages, the plurality of analog voltages selectively provided to the plurality of CIM arrays; and a package housing the IC and including: a plurality of passive electrical components coupled with the plurality of programmable DC-DC converters on the IC and configured to filter the plurality of output voltages provided by the plurality of programmable DC-DC converters to generate a plurality of filtered output voltages, and a plurality of interconnects, each interconnect having a first terminal coupled with at least one of the plurality of passive electrical components and a second terminal coupled with another portion of the IC, the plurality of interconnects configured to provide the plurality of filtered output voltages to the plurality of driver circuits.BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG. 1 depicts a block diagram of an example in-memory computing architecture.

[0021] FIG. 2 shows a block diagram of a compute in-memory array.

[0022] FIG. 3 shows an example circuit diagram of the computing cells discussed above in relation to FIG. 2.

[0023] FIG. 4 shows a schematic of an example device including analog voltage level generation and distribution.

[0024] FIG. 5 shows an example layout of DC-DC converters on an in-memory computing architecture.

[0025] FIG. 6 shows a topology for an example electrical network that includes DC-DC converters, passive components, and a CIM array.

[0026] FIG. 7 shows a block diagram of an example DC-DC converter.

[0027] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0028] The various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0029] As will be apparent to those of skill in the art upon reading this disclosure, each of the individual aspects described and illustrated herein has discrete components and features which can be readily separated from or combined with the features of any of the other several aspects without departing from the scope or spirit of the present disclosure.

[0030] Any recited method can be carried out in the order of events recited or in any other order that is logically possible. That is, unless otherwise expressly stated, it is in no way intended that any method or aspect set forth herein be construed as requiring that its steps be performed in a specific order. Accordingly, where a method claim does not specifically state in the claims or descriptions that the steps are to be limited to a specific order, it is no way intended that an order be inferred, in any respect. This holds for any possible nonexpress basis for interpretation, including matters of logic with respect to arrangement of steps or operational flow, plain meaning derived from grammatical organization or punctuation, or the number or type of aspects described in the specification.

[0031] All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and / or materials in connection with which the publications are cited. All such publications and patents are herein incorporated by references as if each individual publication or patent were specifically and individually indicated to be incorporated by reference. Such incorporation by reference is expressly limited to the methods and / or materials described in the cited publications and patents and does not extend to any lexicographical definitions from the cited publications and patents. Any lexicographical definition in the publications and patents cited that is not also expressly repeated in the instant specification should not be treated as such and should not be read as defining any terms appearing in the accompanying claims. The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the present invention is not entitled to antedate such publication by virtue of prior invention. Further, the datesof publication provided herein can be different from the actual publication dates, which can require independent confirmation.

[0032] While aspects of the present disclosure can be described and claimed in a particular statutory class, such as the system statutory class, this is for convenience only and one of skill in the art will understand that each aspect of the present disclosure can be described and claimed in any statutory class.

[0033] It is also to be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosed compositions and methods belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0034] It should be noted that ratios, concentrations, amounts, and other numerical data can be expressed herein in a range format. It will be further understood that the endpoints of each of the ranges are significant both in relation to the other endpoint, and independently of the other endpoint. It is also understood that there are a number of values disclosed herein, and that each value is also herein disclosed as “about” that particular value in addition to the value itself. For example, if the value “10” is disclosed, then “about 10” is also disclosed. Ranges can be expressed herein as from “about” one particular value, and / or to “about” another particular value. Similarly, when values are expressed as approximations, by use of the antecedent “about,” it will be understood that the particular value forms a further aspect. For example, if the value “about 10” is disclosed, then “10” is also disclosed.

[0035] When a range is expressed, a further aspect includes from the one particular value and / or to the other particular value. For example, where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the disclosure, e.g. the phrase “x to y” includes the range from ‘x’ to ‘y’ as well as the range greater than ‘x’ and less than ‘y’. The range can also be expressed as an upper limit, e.g. ‘about x, y, z, or less’ and should be interpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of Tess than x’, less than y’, and Tess than z’. Likewise, the phrase ‘about x, y, z, or greater’ should beinterpreted to include the specific ranges of ‘about x’, ‘about y’, and ‘about z’ as well as the ranges of ‘greater than x’, greater than y’, and ‘greater than z’. In addition, the phrase “about ‘x’ to ‘y’”, where ‘x’ and ‘y’ are numerical values, includes “about ‘x’ to about y”.

[0036] It is to be understood that such a range format is used for convenience and brevity, and thus, should be interpreted in a flexible manner to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited. To illustrate, a numerical range of “about 0.1% to 5%” should be interpreted to include not only the explicitly recited values of about 0.1% to about 5%, but also include individual values (e.g., about 1%, about 2%, about 3%, and about 4%) and the sub-ranges (e.g., about 0.5% to about 1.1%; about 5% to about 2.4%; about 0.5% to about 3.2%, and about 0.5% to about 4.4%, and other possible sub-ranges) within the indicated range.

[0037] As used herein, the terms “about,” “approximate,” “at or about,” and “substantially” mean that the amount or value in question can be the exact value or a value that provides equivalent results or effects as recited in the claims or taught herein. That is, it is understood that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but can be approximate and / or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art such that equivalent results or effects are obtained. In some circumstances, the value that provides equivalent results or effects cannot be reasonably determined. In such cases, it is generally understood, as used herein, that “about” and “at or about” mean the nominal value indicated ±10% variation unless otherwise indicated or inferred. In general, an amount, size, formulation, parameter or other quantity or characteristic is “about,” “approximate,” or “at or about” whether or not expressly stated to be such. It is understood that where “about,” “approximate,” or “at or about” is used before a quantitative value, the parameter also includes the specific quantitative value itself, unless specifically stated otherwise.

[0038] Prior to describing the various aspects of the present disclosure, the following definitions are provided and should be used unless otherwise indicated. Additional terms can be defined elsewhere in the present disclosure.

[0039] canAs used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when precedinga list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0040] As used in the specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a proton beam degrader,” “a degrader foil,” or “a conduit,” includes, but is not limited to, two or more such proton beam degraders, degrader foils, or conduits, and the like.

[0041] The terms “configured for” or “configured to,” as used herein with respect to a specified operation or function, refer to a device, component, circuit, structure, machine, signal, etc. that is physically constructed, programmed, formatted and / or arranged to perform the specified operation or function.

[0042] The various concepts introduced above and discussed in greater detail below can be implemented in any of numerous ways, as the described concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

[0043] As used herein, the terms “optional” or “optionally” means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where said event or circumstance occurs and instances where it does not.

[0044] Unless otherwise specified, temperatures referred to herein are based on atmospheric pressure (i.e., one atmosphere).

[0045] In-memory Computing Architecture

[0046] FIG. 1 depicts a block diagram of an example in-memory computing architecture 100. The in-memory computing architecture 100 can be adapted, for example, to a scalable neural network accelerator architecture based on in-memory computing (IMC). However, the in-memory computing architecture 100 is not limited to neural network applications, and can be employed in numerous applications where high data throughput with low power consumption is desired. The in-memory computing architecture 100 includes a plurality of Compute In-Memory unit (CIMU) tiles 102. The plurality of CIMU tiles 102 are arranged in an array within the architecture. The plurality of CIMU tiles 102 can be individually enabled / disabled based on the computations to be carried out by the in-memory computing architecture 100. In examples where the in-memory computing architecture 100 can be used to implement neural networks, the neural networks can be mapped to one or more CIMU tiles of the plurality of CIMU tiles 102. The remainder of the CIMU tiles of the plurality of CIMU tiles 102 can be disabled toreduce power consumption.

[0047] The in-memory computing architecture 100 can include, in part, activation buffers 104, segmented weight buffers 106, and one or more phase-locked loops (PLLs) 108. The activation buffers 104 can provide signals representative of activations from previous stages of computation, for instance previous layers in a neural network. The segmented weight buffers 106 can provide data required for computation together with the activations / data from previous stages, for instance these weight buffers could store the weights of neural network layers. The one or more PLLs 108 can provide reference clock signals to various portions of the in-memory computing architecture 100. The in-memory computing architecture 100 can also include off-chip control elements 110 or interfaces for communication with off-chip processors or software to send and receive control or data signals. The off-chip interface 110 can, by itself or in concert with other elements, provide circuits and protocols for high-speed interfaces for wired or wireless connections involving data, control signals, or both, to other processors or other arrays of CIMU tiles, for example, enabling the in-memory computing architecture 100 to scale upward as desired.

[0048] Each of the plurality of CIMU tiles 102 can include a plurality of CIMUs 112, an on-chip network 114, and a weight network 116. While FIG. 1 shows each of the plurality of CIMU tiles 102 including four CIMUs 112, this is only an example, and the CIMU tiles 102 can include fewer or more CIMUs 112. One or more of the CIMUs 112 can include a compute in-memory (CIM) array 118, compute dataflow buffers 120, programmable digital single instruction multiple data (SIMD) 122, and a programming and control module 124. The CIM array 118 can be an array of computing cells, discussed further below. The CIM array 118 can carry out computations based on data stored in the computing cells and data provided by the activation buffers 104. The computing cells can be used to perform computational operations between inputs and data stored in a memory cell within the computing cells. The operations can include logical operations (AND, NOR, etc.) or multiplication operations carried out between inputs. The CIM array 118 can carry out matrix operations between multi -bit operands, which is particularly useful in neural network computations where activations are multiplied with weights. In some such applications, the weights can be stored in the memory cells of the CIM array 118 and activations can be provided as input vectors. Each computing cell in the CIM array 118 can perform the multiplication operation between a 1 -bit weight and a portion of the input activation, which can be represented in digital or analog signal form.Some example computing cells can generate a result that is in the form of an electrical signal. For example, the computing cell can output an analog voltage that is representative of the computation result. In some other examples, the computing cell can output an electrical current that is representative of the computation result. The electrical signals of various computing cells can be accumulated and processed to generate the overall matrix multiplication result. For example, electrical signals representative of computation from all computing cells in a single column of the CIM array 118 can be accumulated to represent a portion of the computation. Accumulated electrical signals from multiple columns of computing cells of the CIM array 118 can be combined and processed to generate an overall matrix multiplication result. For instances where the electrical signal generated by the computing cells is an electrical current, the currents from various computing cells within a column can be summed to generate a representative accumulated electrical current. In instances where the electrical signal generated by the computing cell is an analog voltage, the analog voltage generated by each computing cell can be stored in capacitors within the computing cell and then accumulated as a voltage that is representative of a portion of the overall matrix multiplication result. The accumulated result, whether an electrical current or an analog voltage, can be converted into digital form using analog to digital converters (ADCs) and further processed, stored, or passed on to other CIM arrays 118 for further computations.

[0049] The programmable digital SIMD 122 can have an instruction set for flexible element-wise operation and the compute dataflow buffers 120 can support wide range of neural network dataflows. Each CIMUs 112 can provide a high-level of configurability and can be abstracted into a software library of instructions for interfacing with a compiler (for allocating / mapping an application, neural network and the like to the architecture), and where instructions can thus also be added prospectively. That is, the library can include single / fused instructions such as element mult / add, h(») activation, (N-step convolutional stride + matrix-vector-multiplication (MVM) + batch norm. +h(») activation + max. pool), (dense + MVM) and the like. In various nonlimiting examples, h(») can indicate an activation function, including without limitation the rectified linear unit ReLU(x) function, the sigmoid function (o(x)), and other such functions. Max pooling, a downsampling technique for reducing spatial dimensions to maintain computational efficiency while retaining other important features of the CIMU array or the network, can also be a subject of the computation. The N-step convolutional stride can refer to the number of pixels or other information bits that a kernel or convolutionalfilter moves or glides across the input image during convolution to effect operations like feature detection, pattern recognition, blurring, image sharpening, image recognition, and the like.

[0050] The on-chip network 114 (OCN) can include routing channels within Network In / Out Blocks, and a Switch Block, which provides flexibility via a disjoint architecture as shown, for example, by the disjoint buffer switch 133 in the enlarged view of OCN 114. This flexibility, among other benefits, enables modules that are independent of one another to work in parallel. The OCN 114 works with configurable CIMU input / output ports to optimize data structuring to / from an in-memory computing engine, to maximize data locality across MVM dimensionalities and tensor depth / pixel indices. The OCN 114 routing channels can include bidirectional wire pairs as shown by the exemplary duodirectional pipelined routing structure 131 in the expanded view if the OCN 114, so as to ease repeater / pipeline-FF insertion, while providing sufficient density.

[0051] The in-memory computing architecture 100 can be used to implement a neural network (NN) accelerator, wherein a plurality of compute in memory units (CIMUs 112) are arrayed and interconnected using a very flexible on-chip network (OCN 114) wherein the outputs of one CIMU can be connected to or flow to the inputs of another CIMU or to multiple other CIMUs, the outputs of many CIMUs can be connected to the inputs of one CIMU, the outputs of one CIMU can be connected to the inputs of another CIMU and so on. The OCN 114 can be implemented as a single on-chip network, as a plurality of on-chip network portions, or as a combination of on-chip and off-chip network portions.

[0052] The CIMUs 112 can be surrounded by an on-chip network 114 for moving activations between CIMUs 112 (activation network) as well as moving weights from embedded L2 memory to CIMUs 112 (weight-loading interface). This has similarities with architectures used for coarse-grained reconfigurable arrays (CGRAs), but with cores providing high-efficiency MVM and element-wise computations targeted for neural network acceleration. Various options exist for implementing the on-chip network. The approach in FIG. 1 enables routing segments along a CIMU 112 to take outputs from that CIMU 112 and / or to provide inputs to that CIMU 112. In this manner data originating from any CIMU 112 can be routed to any CIMU 112, and any number of CIMUs 112.

[0053] Each CIMU 112 is associated with an input buffer (not shown) for receiving computational data from the on-chip network and composing the received computational data into an input vector for matrix vector multiplication (MVM) processing by the CIMUto generate thereby computed data including an output vector.

[0054] Each CIMU 112 is associated with a shortcut buffer (not shown), for receiving computational data from the on-chip network 114, imparting a temporal delay to the received computational data, and forwarding delayed computation data toward a next CIMU 112 or an output in accordance with a dataflow map such that dataflow alignment across multiple CIMUs 112 is maintained. At least some of the input buffers can be configured to impart a temporal delay to computational data received from the on-chip network 114 or from a shortcut buffer. The dataflow map can support pixel-level pipelining to provide pipeline latency matching.

[0055] The temporal delay imparted by a shortcut or input buffers includes at least one of an absolute temporal delay, a predetermined temporal delay, a temporal delay determined with respect to a size of input computational data, a temporal delay determined with respect to an expected computational time of the CIMU 112, a control signal received from a dataflow controller, a control signal received from another CIMU 112, and a control signal generated by the CIMU 112 in response to the occurrence of an event within the CIMU. In some aspects, at least one of the input buffer and shortcut buffers of each of the plurality of CIMUs 112 in the array of CIMUs 112 can be configured in accordance with a dataflow map supporting pixel-level pipelining to provide pipeline latency matching. The array of CIMUs 112 can also include parallelized computation hardware configured for processing input data received from at least one of respective input and shortcut buffers.

[0056] A least a subset of the CIMUs 112 can be associated with on-chip network 114 portions including operand loading network portions configured in accordance with a dataflow of an application mapped onto the IMC. The application mapped onto the IMC includes a neural network (NN) mapped onto the IMC such that parallel output computed data of configured CIMUs executing at a given layer are provided to configured CIMUs 112 executing at a next layer, said parallel output computed data forming respective NN feature-map pixels.

[0057] The input buffer can be configured for transferring input NN feature-map data to parallelized computation hardware within the CIMU in accordance with a selected stride step, such as discussed above. The NN can include a convolution neural network (CNN), and the input buffer can be used to buffer a number of rows of an input feature map corresponding to a size or height of the CNN kernel.

[0058] The CIM array 118 in each CIMU 112 can perform matrix vector multiplication(MVM) in accordance with a bit-parallel, bit-serial (BP / BS) computing process in which single bit computations are performed using an iterative barrel shifting with column weighting process, followed by a results accumulation process.

[0059] FIG. 2 shows additional details of a portion of the in-memory computing architecture 100 shown in FIG. 1, and in particular, details of an example compute inmemory (CIM) array 200 and associated components. The CIM array 200 can be used, for example, to implement, in part, the CIM array 118 discussed above in relation to the in-memory computing architecture 100 shown in FIG. 1. In one example implementation, the CIM array 200 can include a fully row / column-parallel (1152 rowX 256 column) array of computing cells 202 of an in-memory-computing (IMC) macro enabling N-bit (5-bit) input processing. The number of rows (1152), the number or columns (256), and the number of bits (5-bit) of input shown in FIG. 2 are only examples, and any or all of these quantities or circuit configurations can be varied based on desired implementations. The computing cells can be used to perform computational operations between inputs and data stored in a memory cell within the computing cells. The operations can include logical operations (AND, NOR, etc.) or multiplication operations carried out between inputs. In some examples, the operands of the computation can be 1 -bit each. In some other examples, one of the operands can be an analog signal (voltage or current) while the other operand can be a 1 -bit operand stored in the memory cell.

[0060] The in-memory computing architecture 100, in some examples, can be utilized for matrix vector multiplication (MVM) operations, which dominate compute-intensive and data-intensive Al workloads, in a manner that reduces compute energy and data movement by orders of magnitude. This is achieved through efficient analog compute in the computing cells 202, and by thus accessing a compute result (e.g., inner product), rather than individual bits, from memory. But, doing so fundamentally instates an energy / throughput-vs.-SNR tradeoff, where going to analog introduces compute noise and accessing a compute result increases dynamic range (i.e., reducing SNR for given readout architecture). The computing cells 202, which store computational results in the form of a voltage in capacitors within the computing cells 202, can employ metal-fringing capacitors, which can achieve very low noise from analog nonidealities, and thus have the potential for extremely high dynamic range.

[0061] FIG. 2 shows a block diagram of the CIM array 200 including a 1152 (row) X 256 (col.) array of 10T (“ten transistor”) SRAM computing cells 202, which in this example are multiplying bit-cells (M-BCs) (such as, for example, a 10T M-BC 202, although thenumber of transistors of SRAM interface 204 and M-BCs 202 is implementationdependent and the circuit can use different numbers of transistors or other circuit elements without departing from the principles of the disclosure); peripheral circuits for standard writing / reading thereto (e.g., a bit line (BL) decoder 204 and 256 BL drivers 206-1 through 206-256 (collectively referred to as BL drivers 206), a word line (WL) or address decoder 208 and 1152 WL drivers 210-1 through 210-1152 (collectively referred to as WL drivers 210), and control block 212 for controlling the BL decoder such as SRAM interface 204 and the WL decoder 208); peripheral circuitry for providing 5-bit inputvector elements thereto (e.g., 1152 Dynamic-Range Doubling (DRD) DACs 214-1 through 214-1152 (collectively referred to as DRD DACs 214), and a corresponding inmemory computing (IMC) controller (“IMC control block”) 216); peripheral circuitry for digitizing the compute result from each column (e.g., 256 8-bit successive approximation register (SAR) ADCs 218-1 through 218-256 (collectively referred to as SAR ADCs 218), and column reset mechanisms 220-1 through 220-256 (collectively referred to as column reset mechanisms 220) (e.g., CMOS switches configured to pull the output voltage levels of column compute lines CLs to a reset voltage VRST during a reset phase of operation, and allow the voltage levels of column compute lines CLs to reflect their respective compute results during an evaluation phase of operation). For example, the RST switches corresponding to CL1-CL256, or a subset thereof, can close to produce the desired reset voltage VRST during the reset phase. The RST switches can then open during an ensuing evaluation phase, thereby enabling the voltage values at the CLs to reflect the computed product.

[0062] In addition, the lower right portion of FIG. 2 depicts an example enlarged view of a representative one of the 256 8-bit ADCs, which includes various switch mechanisms ADCRST (Analog-to-Digital Converter Reset), ADCSMP (Analog-to-Digital Converter Sample) and voltage designations VADCRST and VCMPR, the latter voltage designation connected in this example to a positive terminal of the comparator CMPR and the former voltage designation selectively applied via the ADCRST and ADCSMP switch to reset the comparator. The negative terminal of comparator CMPR receives a compute line (CL) value when the circuit is activated. An output of comparator CMPR is coupled to SAR logic for outputting an 8-bit digital result. It will be appreciated, however, that the implementation details of the above circuits are representative in nature and that variations to the circuits are possible without departing from the scope or spirit of the present disclosure.

[0063] While writing / reading is typically performed row-by-row, MVM operations are typically performed by applying input-vector elements corresponding to neural -network input activations to all rows at once. That is, each DRD DAC 214j, in response to a respective 5-bit input-vector element Xj [4:0], generates a respective differential output signal (lAj / IAbj) which is subjected to a 1-bit multiplication with the stored weights (Aij / Abij) at each computing cells 202j in the corresponding row of computing cells 202, and accumulation through charge-redistribution across computing cells 202 capacitors on the compute line (CL) to yield an inner product in each column, which is then digitized via the respective SAR ADCs 218 of each column as noted above.

[0064] FIG. 3 shows an example circuit diagram of the computing cells 202 discussed above in relation to FIG. 2. The computing cells 202 can include a highly dense structure for achieving weight storage and multiplication, thereby minimizing data-broad-cast distance and control signals within the context of i-row, j -column arrays implemented using such computing cells, such as the 1152 (row) X 256 (col.) CIM array 200 of 10T SRAM multiplying bit cells (M-BCs).

[0065] The exemplary computing cells 202 includes a six-transistor bit cell portion 222 (here, NMOS transistors 226a, 226b, 226e, 226f and PMOS transistors 226c and 226d), a first switch SW1, a second switch SW2, a capacitor C, a word line (WL) 224, a first bit line (BLj) 227, a second bit line (BLbj) 228, and a compute line (CL) 230.

[0066] The six-transistor bit cell portion 222 is depicted as being located in a middle portion of the computing cells 202, and includes six transistors 226a-226f in this example. The 6-transistor bit cell portion 222 can be used for storage, and to read and write data. In one example, the 6-transistor bit cell portion 222 stores the filter weight. In some examples, data is written to the computing cells 202 through the word line (WL) 224, the first bit line (BL) 227, and the second bit line (BLb) 228.

[0067] The computing cells 202 can include a first CMOS switch SW1 and a second CMOS switch SW2. The first switch SW 1 is depicted as being controlled by a first stored signal Aij such that, when closed, the first switch SW1 couples one of the received differential output signals provided by the DRD DACs 214, illustratively IA, to a first terminal of the capacitor C. The second switch SW2 is depicted as being controlled by a second stored signal Abij such that, when closed, the second switch SW2 couples the other one of the received differential output signals (lA / IAb) of the corresponding DRD DACs 214, illustratively lAb, to the first terminal of the capacitor C. The second terminal of the capacitor C is connected to a compute line (CL) 230 via an output port 232 that providesa result of the computation of the computing cell 202. It is noted that in various other examples, the input signals provided to the first and second switches SW 1 and SW2 can include a fixed voltage (e.g., Vaa), ground, or some other voltage level.

[0068] The computing cells 202, including the first SW1 and second SW2 switches, can implement computation on the data stored in the six-transistor bit cell portion 222. The result of a computation is sampled as charge on the capacitor C. According to various implementations, the capacitor C can be is positioned above the computing cell 202 and utilize no additional area on the circuit. In some implementations, a logic value of either Vdd or ground is stored on the capacitor C. In other implementations, the voltage stored on the capacitor C can include a positive or negative voltage in accordance with the operation of the first and the second switches SW 1 and SW2, and the output voltage level generated by the corresponding DRD DACs 214 as shown in FIG. 2.

[0069] Thus, with continued reference to FIG. 3, the value that is stored on the capacitor C is highly stable, since the capacitor C value is either driven up to a fixed analog voltage or down to ground. In some examples, the capacitor C is a metal-oxide-metal (MOM) finger capacitor, and in some examples, the capacitor C can be about 0.1 femto-Farhads (fF) to about 10 fF or can be about 1.2 fF. MOM capacitors have very good matching temperature and process characteristics, and thus have highly linear and stable compute operations. Note that other types of logic functions can be implemented using the computing cells 202 by changing the way the transistors 226a-226f and / or the first and the second switches SW 1 and SW2 are connected and / or operated during the reset and evaluation phases of operation. The six-transistor bit cell portion 222 can be implemented using different numbers of transistors and can have different architectures. In some examples, the six-transistor bit cell portion 222 can be a SRAM, DRAM, MRAM, or an RRAM.

[0070] Configurable Power Management

[0071] The generation of the analog voltage levels needed for the DRD-DACs 214 in the CIM array can be power inefficient and can be required to support large loads. For example, referring to FIG. 2, the DRD-DACs 214 use these analog levels to drive analog voltages to each row of computing cells of the CIM array 200. With each chip including multiple CIM arrays in a plurality of CIMU tiles 102, such as that discussed in relation to FIG. 1, power inefficiencies in design can be compounded. In one approach, a global DC voltage supply can be provided to the IMC architecture 100 and the desired analog voltage levels for the DRD-DACs 214 can be derived locally at each of the CIMUs 112 usinglocal voltage drivers such as, for example, low dropout regulators. In such implementations, while the voltage regulators can generate the local desired analog voltage levels, the global DC voltage supply must be set high enough to provide enough voltage headroom to accommodate the highest desired analog voltage as well as to enable functionality of all other circuits within the CIMU 112. The power efficiency of the voltage regulators can, in part, be a function of the difference between the global DC voltage supply and the voltage level generated. The power efficiency reduces with an increase in this difference. With various levels of analog voltages to be produced throughout the in-memory computing architecture 100, the power efficiency, with for example a single global DC voltage supply that is greater than the highest analog voltage level to be generated, can be negatively impacted. Moreover, the large number of voltage drivers that can be needed to generate the various analog voltage levels can further severely impact the overall power efficiency of the in-memory computing architecture 100.

[0072] As discussed herein, the in-memory computing architecture 100 can include multiple DC voltage supplies that can be used to generate multiple voltage levels. Providing multiple DC voltage supplies can allow the drivers or voltage regulators to select a DC voltage as a supply voltage that is the closest suitable higher voltage than the voltage the driver or regulator is configured to generate. As a result, the difference between the voltage supplied and the voltage generated by the voltage regulator can be minimized, thereby reducing power inefficiencies of the in-memory computing architecture 100. Additionally, the DC voltages can be generated by DC-DC converters integrated on the same die as the in-memory computing architecture 100. While a single integrated DC-DC converter can have limited load carrying ability, thereby limiting the number of voltage regulators it can support, in various aspects, multiple DC-DC converters that generate the same voltage level can be coupled together such that their voltage outputs are connected to the same electrical node. As such, the current provided by the multiple DC-DC converters at that electrical node can be sufficient to accommodate large electrical loads. Moreover, aspects discussed herein provide the use of the package for housing passive components of DC voltage supplies as well as housing interconnects that allow distribution of the supply voltages to various portions of the chip with efficiency. In the context of integrated circuits (ICs), the package is the physical enclosure or casing that houses the IC chip(s) and provides the necessary electrical and mechanical connections between the chip(s) and the external environment.

[0073] FIG. 4 shows a schematic of an example device 400 including voltage supply generation and distribution elements. In particular, the device 400 includes a die 401 (also referred to as an “integrated circuit” or “IC”) on which a plurality of programmable DC-DC converters 402 are fabricated, and a package 410 that houses the die 401. In aspects of the technology, a plurality of on-chip programmable DC-DC converters 402 are used with a plurality of passive electrical components that are coupled with the DC- DC converters 402, where the plurality of passive electrical components are housed in the package 410. The plurality of passive electrical components can be configured to filter the plurality of output voltages provided by the plurality of DC-DC converters 402 to generate a plurality of filtered output voltages. The passive electrical components housed in the package 410 can include, for example, inductors, capacitors, resistors, and interconnects. In some implementations, the passive electrical components can include package thin film magnetic inductors and deep trench capacitors. Some conventional systems may use DC-DC converters or linear regulators together with passive electrical components where the DC-DC converters or linear regulators and passive electrical components are installed off chip, external to the die and package implementing the inmemory computing architecture 100. However, the power efficiency of these systems can be significantly degraded by the off-chip positioning of the power delivery circuits and the power delivery network.

[0074] Examples of aspects discussed herein can include on-chip high frequency programmable DC-DC converters 402 that are located on the die 401 along with the CIM arrays 200. The DC-DC converters 402 can be coupled with thin film magnetic inductors and deep trench capacitors, for example, that are positioned in a package for the inmemory computing architecture 100. These aspects can improve the power efficiency of the in-memory CIM array 200. These aspects can also reduce the complexity and bill of materials that would otherwise be needed with designs using external power supplies.

[0075] In FIG. 4, a package 410 is illustrated housing the die 401 and other components, such as inductors, capacitors, and interconnects. The package can be plugged into, or surface mounted on, a printed circuit board. The package 410 can further serve to protect the die 401 and other components from damage and help to dissipate heat from the components.

[0076] As illustrated, a plurality of DC-DC converters 402 are integral to the die 401. While two DC-DC converters 402 are shown for simplicity in FIG. 4, any number of DC- DC converters can be used depending on implementation details. The DC-DC converters402 can have ports (e.g., output ports Voutl, Vout2, input ports, power / ground ports, etc.) to allow connection to components in the package. At least some interconnects between the DC-DC converters 402 and other components on the die 401 can be placed in the package 410 instead of on the die 401. Moving the interconnects to the package 410 allows space on the die 401 to be used for other active components, such as for additional CIM arrays 200. On the package 410, the interconnects can be wider / thicker than interconnects that are on the die 401. The wider / thicker interconnects have lower resistance over the length of the interconnect, resulting in overall higher currents with lower power losses due to heat. As illustrated, wiring or other connections between the components of the package 410 can be routed through the package 410 and outside of the die 401, such as, for example, a conductor carrying a power supply 407.

[0077] In an example, the DC-DC converters 402 are located along a periphery of the die401 to support multiple CIM arrays 200. The interconnections between one or more of the DC-DC converters 402 can be configured to run across the circuit via interconnects in the package 410 and not on the die 401.

[0078] Each programmable DC-DC converter 402 distributed on the die 401 can include a supply input that receives a supply voltage, such as, for example, 0.8 volts (V) - 0.9V and a reference voltage input that receives a reference voltage. The DC-DC converters402 include an output port that provides an output voltage that is a function of the reference voltage. In one example, the DC-DC converters 402 can provide voltages equally spaced between a global supply voltage level and ground. For example, for a global supply voltage of 0.8 V, DC-DC converters can be used to generate output voltages of, for example, 0.2V, 0.4V and 0.6V. In another example, some minimum voltage can be required for various circuits to operate and can negate the need for a lower voltage. In this case, the output voltage of the DC-DC converters 402 can be, for example, 0.4V or 0.6V. Each of these quantities are for illustrative purposes, and other or different values (and numbers of values) are possible. In an example, the DC-DC converters 402 are buck converters. A buck converter, also referred to as a step-down converter, provides a lower voltage at its output than the applied voltage at its supply voltage input, but with a current drive output that is higher than the current it draws from the supply voltage input. The DC-DC converters 402 can have an output programmable range allowing the DC-DC converters 402 outputs to be set to a minimum supply voltage required for one or more of the plurality of the driver circuits in the CIM array 200.

[0079] One or more of the CIM arrays (“Compute Arrays”) 200 are similarly located onthe die 401. The die 401 can include any number of CIM arrays 200, such as 10, 100, 500, or 1000, or another value. Each CIM array 200 requires high efficiency voltage supplies, such as provided by the DC-DC converters 402.

[0080] The remaining components are illustrated in the package 410, but outside of the die 401. The die 401 is illustrated with a DC-DC input power plane 405 integrated with the die 401. The power plane can be a dedicated conducting layer that provides a stable voltage source to power the various components of the IC. The DC-DC input power plane 405 can provide supply power to each of the DC-DC converters 402. Optional external power supplies 407 can provide power to each CIM array 200 instead of the DC-DC converters.

[0081] Thin film magnetic inductors 403 are illustrated in the package 410 but outside of the die 401. Deep trench capacitors 404 are illustrated in the package 410 but outside of the die 401. One or more package power planes 406 are illustrated to bring power to the components of the package 410. These and other components of the package combine to form circuits that filter the output voltages provided by the DC-DC converters 402 to create filtered output DC voltages that are suitable to be provided to the CIM arrays 200.

[0082] FIG. 5 shows an example layout of DC-DC converters 402 (FIG. 4) on an inmemory computing architecture 100. In particular, FIG. 5 shows an example spatial arrangement of the DC-DC converters 402 on the die 401. While not explicitly shown in FIG. 5 to avoid unduly obscuring the disclosure, it is implied that the outputs of the DC- DC converters are filtered by the plurality of passive components discussed above. The layout illustrates one or more DC-DC 0.6V converters 501 and one or more DC-DC 0.4V converters 502. However, additional DC-DC converters with different voltage outputs can also be included. The in-memory computing architecture 100 can include any number of CIM arrays 200 (not shown), such as 10, 100, 500, or 1000. In implementations involving a higher number of CIM arrays 200, the in-memory computing architecture 100 can require the power supplies to be distributed to multiple locations on the in-memory computing architecture 100 for proper or optimal operation.

[0083] Distributing the DC-DC converters 402 in multiple locations across a die 401 of the in-memory computing architecture 100 requires a low impedance voltage supply grid for the CIM arrays 200. DC-DC converters 402 with different voltage levels can be used in a single in-memory computing architecture 100. As illustrated, DC-DC 0.6V converters 501 and DC-DC 0.4V converters 502 are distributed around the perimeter of the die 401. The distribution of the DC-DC converters 402 reduces the complexity of thewiring and power distribution by eliminating certain external components for powering the in-memory computing architecture 100.

[0084] The DC-DC converters 402 with like voltages are illustrated as being coupled together via interconnects. In particular, a set of interconnects positioned in the package 410 can be utilized, where each interconnect of the set of interconnects is coupled with at least one of the plurality of passive electrical components and another terminal of each such interconnect is coupled with another portion of the die 401. This other portion can be, for example, a portion that has one or more circuit elements with terminals needing the same DC voltage or a lower voltage (in some cases, lower by some threshold as illustrated below in the example of the 0.2V voltage driver). For example, the DC-DC 0.6V converters 501 are interconnected with each other and to any of the CIM arrays 200 that require a 0.6V supply voltage or less with a first set of interconnects 504. Similarly, the DC-DC 0.4V converters 502 are interconnected with each other and to any of the CIM array 200 that require a 0.4V supply voltage or less with a second set of interconnects 503. In certain examples, some but not all of a set of DC-DC converters 402 of similar voltages can be coupled together. For example, if an in-memory computing architecture 100 includes 20 DC-DC 0.6V converters 501, the configuration can only include interconnects for two sets of ten DC-DC 0.6V converters 501. That is, ten DC-DC 0.6V converters 501 are interconnected in one set and another ten DC-DC 0.6V converters 501 are interconnected in another set. The number of DC-DC converters 402 interconnected in each set can be chosen configured based on any suitable factors, such as the size of the package, the size of the die, the amount of space available for interconnects, the number of CIM arrays 200 requiring inputs, power management considerations, optimization or efficiency factors, or any other suitable factors.

[0085] In some examples, the interconnections can be integrated with the package 410 and not directly on the die 401. By performing the interconnections in the package 401, space on the die 401 is conserved.

[0086] In some examples, if the DRD-DACs 214 requires 0.2 volts, the CIM array 200 can use a selection circuit on an analog voltage driver to select from an available DC-DC 0.6V converter 501 or a DC-DC 0.4V converter 502. If a DC-DC 0.6V converter 501 is used to power the voltage driver that provides the 0.2V voltage level, in the CIM array 200, then an additional 0.4V is provided than the amount that is needed, thereby reducing the power efficiency. If, however, a DC-DC 0.4V converter 502 is used, then only 0.2V extra voltage is provided and the power efficiency is increased, with less power beingused. The CIM array 200 can be programmed to select a DC-DC converter 402 output that has a voltage that is high enough to meet the requirements of the CIM array 200 but that also results in using the lowest power of the possible options of DC-DC converter 402 outputs. In the example, the DC-DC 0.4V converter 502 output is selected by the CIM array 200 to meet the 0.2V requirement. In an example in which 0.5V is required by the CIM array 200, the DC-DC 0.4V converter 502 output will not provide enough voltage and the DC-DC 0.6V converter 501 output is selected.

[0087] In some examples, a set of interconnects from the plurality of interconnects are electrically coupled with each other and with the plurality of CIM arrays 200. A set of DC-DC converters from the plurality of DC-DC converters outputting the same output voltage at their respective output ports can have their respective filtered output voltages, from passive components on the package, provided to the set of interconnects. For example, the first set of interconnects 503 can include at least a first interconnect 503-1 and a second interconnect 503-2 that are coupled with each other at the node 506. The first interconnect 503-1 and the second interconnect 503-2 can also be coupled with one or more CIM arrays 200 (not shown in FIG. 5). Further, the DC-DC converters outputting 0.4 V can be considered as a first set of DC-DC converters that output the same output voltage at their output ports. The filtered outputs of the first set of DC-DC converters, generated by the passive components on the package 410, can be provided to the first set of interconnects 503 — here, the first interconnect 503-1 and the second interconnect 503- 2. The package 410 can include a plurality of vias that couple the plurality of interconnects with the plurality of DC-DC converters and with another portion of the die 401. For example, the package can include vias that can extend between the interconnects in the package and the die surface where the vias can be electrically connected to the DC- DC converters formed on or in the die 401. The package 410 can also include vias that extend between the interconnects in the package and other portions (including, e.g., regions, areas, layers, etc.) of the die 401 such as, for example, the CIM arrays 200.

[0088] FIG. 6 shows a topology for an example electrical network 600 that includes DC- DC converters 402, passive component networks 601, and a CIM array 200. The diagram includes a depiction of a reference voltage input VREF (one of Vrefi - Vref\) and a digital control input (DCTRL[J:0]) (a corresponding one of DCTRLI[J:0] - DCTRLN[J:0]) being provided to each of the DC-DC converters 402. The digital control input DCTRL [J:0] can be combined with the reference voltage input VREF to generate a reference voltage internal to the DC-DC converter that is, in turn, used to generate the output of the DC-DCconverter. The output from the DC-DC converters 402 is routed through a passive component network 601 that can include the interconnects, capacitors, inductors, resistors, or any other passive components.

[0089] The output voltage, such as VDCi and VDCN of the DC-DC converters (and any intermediate output voltages, e.g., VDC2, VDC3, etc. of additional DC-DC converters not explicitly shown) and the respective passive component networks 601 are provided to the CIMU 112 and used to power one or more analog voltage drivers 602 of the CIM array 200. The output of the analog voltage drivers 602 is illustrated as VAi through VAM. The output of the analog voltage drivers 602 is provided to the DRD-DACs associated with the CIM array 200. Further, the output from the DC-DC converters 402 can be provided to other CIMUs 112 that are nodes on the interconnected network of DC-DC converters 402. In relation to the example arrangement shown in FIG. 5, the output voltages VDCi to VDCN can include the output voltages 0.4 V and 0.6 V. These output voltages are provided to the set of interconnects, which are positioned in the package, and these interconnects of the set of interconnects are then connected to the analog voltage drivers of CIMU 112 at other locations on the die 401. Within each CIMU 112, the output voltages VDCi to VDCN can be provided to respective analog voltage drivers 602, which output voltages VAi through VAM. DRD DACS can select the appropriate output voltages VAi through VAM to provide as activation analog voltages lA / IAb. The activation analog voltages lA / IAb are shown to be IAi / IAbi - lAn / IAbR. For example, the DRD-DACs shown in FIG. 6 can include multiplexers controlled by selection inputs Xi[4:0] - XR[4:0], which control the multiplexers 6131 - 613R to provide the appropriate output voltages VAi through VAM as the lA / IAb for row-1 to row-R of computing cells in the CIM array 200.

[0090] FIG. 7 shows a block diagram of an example DC-DC converter 700. The example DC-DC converter 700 can be utilized to implement the DC-DC converters 402 discussed herein. However, any other type of programmable DC-DC converter known in the art can additionally or alternatively be used. The DC-DC converter 700 is a high-bandwidth on-chip DC-DC power converter. In an example, the DC-DC converter 700 takes a 0.8V- 0.9V supply voltage (Vin) and generates multiple low voltage supplies in the range of 0.3 V to 0.7V depending on the value of Vref-intemai generated by an internal reference voltage generator 702 based on a reference voltage Vref and the digital code DcTRLn[J:0]. In some examples, the internal reference voltage generator can include switched resistors, the switches of which can be controlled by the digital code DcTRLn[J:0]. The switchedresistors can form reconfigurable voltage divider circuits, which can generate the desired Vref-intemai for the desired output voltage Vout of the DC-DC converter 700. Other input supply voltages and output voltages for the DC-DC converter 700 can be utilized depending on the requirements of the CIM array 200 and the power supplies available.

[0091] In the illustration, on die 401 components and on-package 410 components are shown. The DC-DC feedback controller 701 is located on the die 401. Other passive components are illustrated as being located on the package 410. In an example, the passive components can be combined to form a filter with electronic characteristics suitable to filter the inverted voltage 707 output from the die 401 and thereby provide a more stable Vout.ASPECTS OF THE DISCLOSURE

[0092] The present disclosure will be better understood upon reading the following numbered aspects, which should not be confused with the claims. Each of the numbered aspects described below can, in some instances, be combined with aspects described elsewhere in the disclosure. The following listing of example aspects is supported by the disclosure provided herein.

[0093] Aspect 1. A device, including: an integrated circuit, including: a plurality of compute-in-memory (CIM) arrays of computing cells, each computing cell including a memory cell and an input port for receiving an input for computation with data stored in the memory cell, a plurality of programmable DC-DC converters, each programmable DC-DC converter of the plurality of DC-DC converters having a reference input that receives a reference voltage and an output port providing an output voltage that is a function of the reference voltage, and a plurality of driver circuits configured to generate a plurality of analog voltages, the plurality of analog voltages selectively provided to the plurality of CIM arrays; and a package housing the integrated circuit, the package including: a plurality of passive electrical components coupled with the plurality of programmable DC-DC converters on the integrated circuit, the plurality of passive components configured to filter the plurality of output voltages provided by the plurality of programmable DC-DC converters to generate a plurality of filtered output voltages, and a plurality of interconnects, each interconnect of the plurality of interconnects having one terminal coupled with at least one of the plurality of passive electrical components and another terminal coupled with another portion of the integrated circuit, wherein the plurality of interconnects provide the plurality of filtered output voltages to the plurality of driver circuits.

[0094] Aspect 2. The device of any one of Aspects 1-8, wherein each DC-DC converter of the plurality of DC-DC converters provides one of at least two voltages as the output voltage.

[0095] Aspect 3. The device of any one of Aspects 1-8, wherein the plurality of DC- DC converters are positioned along a periphery of the integrated circuit, and wherein the plurality of interconnects are positioned to run across the integrated circuit within the package between DC-DC converters positioned on opposite sides of the integrated circuit.

[0096] Aspect 4. The device of any one of Aspects 1-8, wherein a set of interconnects from the plurality of interconnects are electrically coupled with each other and with the plurality of CIM arrays, and wherein a set of DC-DC converters of the plurality of DC-DC converters provide a same output voltage at their respective output ports, their respective output ports having their respective filtered output voltages provided to the set of interconnects.

[0097] Aspect s. The device of any one of Aspects 1-8, wherein the package includes a plurality of vias that couple the plurality of interconnects with the plurality of DC-DC converters and with the another portion of the integrated circuit.

[0098] Aspect 6. The device of any one of Aspects 1-8, wherein the plurality of DC- DC converters include buck converters.

[0099] Aspect 7. The device of any one of Aspects 1-8, wherein the buck converters have an output programmable range configured to enable the buck converters to be set to a minimum voltage required for one or more of the plurality of the driver circuits in the CIM array.

[0100] Aspect s. The device of any one of Aspects 1-7, wherein the plurality of passive electrical components includes at least one of capacitors or inductors.

[0101] Aspect 9. A method of an integrated circuit (IC), the IC including: a plurality of compute-in-memory (CIM) arrays of computing cells, each computing cell including a memory cell and an input port for receiving an input for computation with data stored in the memory cell; a plurality of programmable DC-DC converters, and a plurality of driver circuits, wherein the IC is housed in a package, wherein the package includes a plurality of passive electrical components coupled with the plurality of programmable DC-DC converters, the package further including a plurality of interconnects, each interconnect of the plurality of interconnects having one terminal coupled with at least one of the plurality of passive electrical components and another terminal coupled with another portion of the IC, the method including: receiving, at each programmable DC-DC converter of the plurality of DC-DC converters, a reference voltage; providing a corresponding output voltage at each programmable DC-DC converter of the plurality of DC-DC converters, the corresponding output voltage being a function of the reference voltage; generating, by the plurality of driver circuits, a respective plurality of analog voltages, the plurality of analog voltages being selectively provided to the plurality of CIM arrays; filtering, by the plurality of passive components, the plurality of corresponding output voltages provided by the plurality of programmable DC-DC converters to generate a plurality of filtered output voltages, and providing, by the plurality of interconnects, the plurality of filtered output voltages to the plurality of driver circuits.

[0102] Aspect 10. The method of any one of Aspects 9-16, further including: providing, at each DC-DC converter of the plurality of DC-DC converters, one of at least two voltages as the output voltage.

[0103] Aspect 11. The method of any one of Aspects 9-16, wherein the plurality of DC-DC converters are positioned along a periphery of the IC, and wherein the plurality of interconnects are positioned to run across the IC within the package between DC-DC converters positioned on opposite sides of the IC.

[0104] Aspect 12. The method of any one of Aspects 9-16, further including: electrically coupling a set of interconnects from the plurality of interconnects with each other and with the plurality of CIM arrays; providing, at respective outputs ports of a set of DC-DC converters of the plurality of DC-DC converters, a same output voltage; and providing filtered output voltages corresponding to the same output voltage at the respective output ports to the set of interconnects.

[0105] Aspect 13. The method of any one of Aspects 9-16, wherein the package includes a plurality of vias that couple the plurality of interconnects with the plurality of DC-DC converters and with the another portion of the integrated circuit.

[0106] Aspect 14. The method of any one of Aspects 9-16, wherein the plurality of DC-DC converters include buck converters.

[0107] Aspect 15. The method of any one of Aspects 9-16, wherein the buck converters include an output programmable range, the method further including: setting the buck converters to a minimum voltage required for one or more of the plurality of the driver circuits in the CIM array.

[0108] Aspect 16. The method of any one of Aspects 9-15, wherein the plurality of passive electrical components includes at least one of capacitors or inductors.

[0109] Aspect 17. A device, including: an integrated circuit (IC), the IC including: a plurality of compute-in-memory (CIM) arrays of computing cells, each computing cell including a memory cell and an input for enabling computation with data stored in the memory cell, a plurality of programmable DC-DC converters, each programmable DC- DC converter having a reference input configured to receive a reference voltage and an output port configured to provide an output voltage based on the reference voltage, and a plurality of driver circuits configured to generate a plurality of analog voltages, the plurality of analog voltages selectively provided to the plurality of CIM arrays; and a package housing the IC and including: a plurality of passive electrical components coupled with the plurality of programmable DC-DC converters on the IC and configured to filter the plurality of output voltages provided by the plurality of programmable DC- DC converters to generate a plurality of filtered output voltages, and a plurality of interconnects, each interconnect having a first terminal coupled with at least one of the plurality of passive electrical components and a second terminal coupled with another portion of the IC, the plurality of interconnects configured to provide the plurality of filtered output voltages to the plurality of driver circuits.

[0110] Aspect 18. The device of any one of Aspects 17-24, wherein each DC-DC converter of the plurality of DC-DC converters provides one of at least two voltages as the output voltage.

[0111] Aspect 19. The device of any one of Aspects 17-24, wherein the plurality of DC-DC converters are positioned along a periphery of the integrated circuit, and wherein the plurality of interconnects are positioned to run across the integrated circuit within the package between DC-DC converters positioned on opposite sides of the IC.

[0112] Aspect 20. The device of any one of Aspects 17-24, wherein a set of interconnects from the plurality of interconnects are electrically coupled with each other and with the plurality of CIM arrays, and wherein a set of DC-DC converters of the plurality of DC-DC converters provide a same output voltage at their respective output ports, their respective output ports having their respective filtered output voltages provided to the set of interconnects.

[0113] Aspect 21. The device of any one of Aspects 17-24, wherein the package includes a plurality of vias that couple the plurality of interconnects with the plurality of DC-DC converters and with the another portion of the integrated circuit.

[0114] Aspect 22. The device of any one of Aspects 17-24, wherein the plurality of DC-DC converters include buck converters.

[0115] Aspect 23. The device of any one of Aspects 17-24, wherein the buck converters have an output programmable range configured to enable the buck converters to be set to a minimum voltage required for one or more of the plurality of the driver circuits in the CIM array.

[0116] Aspect 24. The device of any one of Aspects 17-23, wherein the plurality of passive electrical components includes at least one of capacitors or inductors.

[0117] The examples disclosed herein are illustrative and not limiting in nature. Details disclosed with respect to the methods described herein included in one example or aspect can be applied to other examples and aspects. Any aspect of the present disclosure that has been described herein can be disclaimed, i.e., exclude from the claimed subject matter whether by proviso or otherwise.

[0118] Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.

Claims

CLAIMSWhat is claimed is:

1. A device, comprising: an integrated circuit, comprising: a plurality of compute-in-memory (CIM) arrays of computing cells, each computing cell including a memory cell and an input port for receiving an input for computation with data stored in the memory cell, a plurality of programmable DC-DC converters, each programmable DC- DC converter of the plurality of DC-DC converters having a reference input that receives a reference voltage and an output port providing an output voltage that is a function of the reference voltage, and a plurality of driver circuits configured to generate a plurality of analog voltages, the plurality of analog voltages selectively provided to the plurality of CIM arrays; and a package housing the integrated circuit, the package comprising: a plurality of passive electrical components coupled with the plurality of programmable DC-DC converters on the integrated circuit, the plurality of passive components configured to filter the plurality of output voltages provided by the plurality of programmable DC-DC converters to generate a plurality of filtered output voltages, and a plurality of interconnects, each interconnect of the plurality of interconnects having one terminal coupled with at least one of the plurality of passive electrical components and another terminal coupled with another portion of the integrated circuit, wherein the plurality of interconnects provide the plurality of filtered output voltages to the plurality of driver circuits.

2. The device of claim 1, wherein each DC-DC converter of the plurality of DC-DC converters provides one of at least two voltages as the output voltage.

3. The device of claim 1, wherein the plurality of DC-DC converters are positioned along a periphery of the integrated circuit, and wherein the plurality of interconnects arepositioned to run across the integrated circuit within the package between DC-DC converters positioned on opposite sides of the integrated circuit.

4. The device of claim 1, wherein a set of interconnects from the plurality of interconnects are electrically coupled with each other and with the plurality of CIM arrays, and wherein a set of DC-DC converters of the plurality of DC-DC converters provide a same output voltage at their respective output ports, their respective output ports having their respective filtered output voltages provided to the set of interconnects.

5. The device of claim 1, wherein the package includes a plurality of vias that couple the plurality of interconnects with the plurality of DC-DC converters and with the another portion of the integrated circuit.

6. The device of claim 1, wherein the plurality of DC-DC converters include buck converters.

7. The device of claim 6, wherein the buck converters have an output programmable range configured to enable the buck converters to be set to a minimum voltage required for one or more of the plurality of the driver circuits in the CIM array.

8. The device of claim 1, wherein the plurality of passive electrical components includes at least one of capacitors or inductors.

9. A method of an integrated circuit (IC), the IC comprising: a plurality of computein-memory (CIM) arrays of computing cells, each computing cell including a memory cell and an input port for receiving an input for computation with data stored in the memory cell; a plurality of programmable DC-DC converters, and a plurality of driver circuits, wherein the IC is housed in a package, wherein the package includes a plurality of passive electrical components coupled with the plurality of programmable DC-DC converters, the package further including a plurality of interconnects, each interconnect of the plurality of interconnects having one terminal coupled with at least one of the plurality of passive electrical components and another terminal coupled with another portion of the IC, the method comprising:receiving, at each programmable DC-DC converter of the plurality of DC-DC converters, a reference voltage; providing a corresponding output voltage at each programmable DC-DC converter of the plurality of DC-DC converters, the corresponding output voltage being a function of the reference voltage; generating, by the plurality of driver circuits, a respective plurality of analog voltages, the plurality of analog voltages being selectively provided to the plurality of CIM arrays; filtering, by the plurality of passive components, the plurality of corresponding output voltages provided by the plurality of programmable DC-DC converters to generate a plurality of filtered output voltages, and providing, by the plurality of interconnects, the plurality of filtered output voltages to the plurality of driver circuits.

10. The method of claim 9, further comprising: providing, at each DC-DC converter of the plurality of DC-DC converters, one of at least two voltages as the output voltage.

11. The method of claim 9, wherein the plurality of DC-DC converters are positioned along a periphery of the IC, and wherein the plurality of interconnects are positioned to run across the IC within the package between DC-DC converters positioned on opposite sides of the IC.

12. The method of claim 9, further comprising: electrically coupling a set of interconnects from the plurality of interconnects with each other and with the plurality of CIM arrays; providing, at respective outputs ports of a set of DC-DC converters of the plurality of DC-DC converters, a same output voltage; and providing filtered output voltages corresponding to the same output voltage at the respective output ports to the set of interconnects.

13. The method of claim 9, wherein the package includes a plurality of vias that couple the plurality of interconnects with the plurality of DC-DC converters and with the another portion of the integrated circuit.

14. The method of claim 9, wherein the plurality of DC-DC converters include buck converters.

15. The method of claim 14, wherein the buck converters include an output programmable range, the method further comprising: setting the buck converters to a minimum voltage required for one or more of the plurality of the driver circuits in the CIM array.

16. The method of claim 9, wherein the plurality of passive electrical components includes at least one of capacitors or inductors.

17. A device, comprising: an integrated circuit (IC), the IC comprising: a plurality of compute-in-memory (CIM) arrays of computing cells, each computing cell including a memory cell and an input for enabling computation with data stored in the memory cell, a plurality of programmable DC-DC converters, each programmable DC- DC converter having a reference input configured to receive a reference voltage and an output port configured to provide an output voltage based on the reference voltage, and a plurality of driver circuits configured to generate a plurality of analog voltages, the plurality of analog voltages selectively provided to the plurality of CIM arrays; and a package housing the IC and comprising: a plurality of passive electrical components coupled with the plurality of programmable DC-DC converters on the IC and configured to filter the plurality of output voltages provided by the plurality of programmable DC-DC converters to generate a plurality of filtered output voltages, and a plurality of interconnects, each interconnect having a first terminal coupled with at least one of the plurality of passive electrical components and a second terminal coupled with another portion of the IC, the plurality of interconnects configured to provide the plurality of filtered output voltages to the plurality of driver circuits.

18. The device of claim 17, wherein each DC-DC converter of the plurality of DC- DC converters provides one of at least two voltages as the output voltage.

19. The device of claim 17, wherein the plurality of DC-DC converters are positioned along a periphery of the integrated circuit, and wherein the plurality of interconnects are positioned to run across the integrated circuit within the package between DC-DC converters positioned on opposite sides of the IC.

20. The device of claim 17, wherein a set of interconnects from the plurality of interconnects are electrically coupled with each other and with the plurality of CIM arrays, and wherein a set of DC-DC converters of the plurality of DC-DC converters provide a same output voltage at their respective output ports, their respective output ports having their respective filtered output voltages provided to the set of interconnects.

21. The device of claim 17, wherein the package includes a plurality of vias that couple the plurality of interconnects with the plurality of DC-DC converters and with the another portion of the integrated circuit.

22. The device of claim 17, wherein the plurality of DC-DC converters include buck converters.

23. The device of claim 22, wherein the buck converters have an output programmable range configured to enable the buck converters to be set to a minimum voltage required for one or more of the plurality of the driver circuits in the CIM array.

24. The device of claim 17, wherein the plurality of passive electrical components includes at least one of capacitors or inductors.

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