Method and apparatus for comparing finite field elements

Abstract

Disclosed in the present application are a method and apparatus for comparing finite field elements. A register (i.e. a second register) is ingeniously used for recording an intermediate comparison result of a comparison between sub-segments constituting compared elements, so as to directly determine, on the basis of a comparison result of high sub-segments, whether adjacent low sub-segments need to be compared.

Description

A method and device for comparing finite field elements Technical Field

[0001] The present application relates to, but is not limited to, large number computing technology, and in particular to a method and a comparison device for implementing finite field element comparison. Background Art

[0002] Zero-knowledge proofs (ZKPs) were proposed by S. Goldwasser, S. Micali, and C. Rackoff in the early 1980s. As a highly secure encryption technology, ZKPs hold broad application prospects in future information transmission. ZKPs involve a large number of finite field calculations, namely, addition, subtraction, and multiplication operations bounded by a very large prime number. However, within a finite field, addition, subtraction, and multiplication require modular reduction after obtaining the direct result. This involves determining whether the result is within the range of 0 to the modulus p-1. If it is outside this range, an addition or subtraction operation of p is performed to adjust the result to within the range of 0 to the modulus p-1, where p represents the modulus of the finite field, i.e., the prime number p.

[0003] In practical applications, the modulus corresponding to the finite field, that is, the prime number p, is very large (more than several hundred bits). The corresponding calculation on a general 32-bit or 64-bit general-purpose processor will truncate the operand into several 32-bit or 64-bit parts before decomposing the calculation.

[0004] The related modular reduction calculation also requires decomposing the comparison calculation of two finite field elements, which makes the program structure more complicated. In addition, it is necessary to compare the two numbers in sequence from the high-bit segment to the low-bit segment, involving a large number of branch jump operations. Conditional branch operations may cause interruptions in the processor pipeline, thereby reducing computational efficiency.

[0005] SUMMARY OF THE INVENTION

[0006] The present application provides a method and a comparison device for implementing finite field element comparison, which can solve any of the above technical problems.

[0007] This embodiment of the present application provides a method for implementing finite field element comparison, including:

[0008] Comparing the highest subsegment of a first element with the highest subsegment of a second element, recording the comparison result in a first register, and recording flag information corresponding to an intermediate result of the comparison in a second register; wherein the first element is a finite field element including more than one subsegment, the second element is a finite field element including more than one subsegment, and the number of bits of each subsegment is the same as the number of bits of a processor used to perform the comparison;

[0009] For each subsegment of the first element and the second element except the highest subsegment, the comparisons are performed in sequence starting from the second highest subsegment until the lowest subsegment of the first element and the lowest subsegment of the second element are compared, and the comparison result in the first register is used as the comparison result of the first element and the second element; in each comparison, it is determined according to the flag information in the second register that the subsegment currently being compared needs to be compared, the flag information corresponding to the intermediate result of the comparison is updated in the second register, and the comparison result in the first register is updated according to the flag information in the second register.

[0010] In an exemplary embodiment, comparing the highest sub-segment of the first element with the highest sub-segment of the second element and recording the comparison result in the first register includes:

[0011] In the case where the comparison is to compare whether the first element is less than the second element, when the comparison result is less than, the comparison result recorded in the first register is the first comparison result; when the comparison result is not less than, the comparison result recorded in the first register is the second comparison result;

[0012] In the case where the comparison is to compare whether the first element is less than or equal to the second element, when the comparison result is less than or equal to, the comparison result recorded in the first register is the first comparison result; when the comparison result is neither less than nor equal to, the comparison result recorded in the first register is the second comparison result;

[0013] For the case where the comparison is to compare whether the first element is equal to the second element, when the comparison result is equal, the comparison result recorded in the first register is the first comparison result; when the comparison result is not equal, the comparison result recorded in the first register is the second comparison result.

[0014] In an exemplary embodiment, recording flag information corresponding to the intermediate result of the comparison in the second register includes:

[0015] When the comparison result is less than, the flag information corresponding to the intermediate result of the comparison is the first flag information; when the comparison result is equal to, the flag information corresponding to the intermediate result of the comparison is the second flag information; when the comparison result is neither less than nor equal to, the flag information corresponding to the intermediate result of the comparison is the third flag information.

[0016] In an exemplary embodiment, for each subsegment of the first element and the second element except the highest subsegment, recording flag information corresponding to the intermediate comparison result in the second register, and updating the comparison result in the first register according to the flag information in the second register includes:

[0017] Determine whether it is necessary to compare the sub-segment currently being compared based on the flag information in the second register. When the flag information in the second register indicates that comparison is not necessary, keep the flag information in the second register unchanged and keep the comparison result in the first register unchanged. When the flag information in the second register indicates that comparison is necessary, update the flag information in the second register based on the comparison result of the sub-segment currently being compared, and update the comparison result in the first register to the comparison result of the sub-segment currently being compared.

[0018] In an exemplary embodiment, determining whether the sub-segment currently being compared needs to be compared according to the flag information in the second register includes:

[0019] If the flag information stored in the second register is the first flag information or the third flag information, there is no need to compare the sub-segments currently being compared;

[0020] If the flag information stored in the second register is the second flag information, the sub-segments in the current comparison need to be compared.

[0021] In an exemplary embodiment, updating the flag information in the second register according to the comparison result of the sub-segment currently being compared includes:

[0022] The sub-segments in the current comparison are compared. If the comparison result is less than, the flag information in the second register is updated to the first flag information; if the comparison result is equal to, the flag information in the second register is updated to the second flag information; if the comparison result is greater than, the flag information in the second register is updated to the third flag information.

[0023] In an exemplary embodiment, updating the comparison result in the first register to the comparison result of the sub-segment currently being compared includes:

[0024] The comparison is to compare whether the first element is less than the second element. If the comparison result is less than, the comparison result in the first register is updated to the first comparison result; if the comparison result is not less than, the comparison result in the first register is updated to the second comparison result;

[0025] The comparison is to compare whether the first element is less than or equal to the second element. If the comparison result is less than or equal to, the comparison result in the first register is updated to the first comparison result; if the comparison result is not less than or equal to, the comparison result in the first register is updated to the second comparison result.

[0026] The comparison is to compare whether the first element is equal to the second element. If the comparison result is equal, the comparison result in the first register is updated to the first comparison result; if the comparison result is not equal, the comparison result in the first register is updated to the second comparison result.

[0027] In an exemplary embodiment, the first register is a register of at least 1 bit; and the second register is a register of at least 2 bits.

[0028] An embodiment of the present application further provides a computer device, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: for executing the steps of any of the above-mentioned methods for implementing finite field element comparison.

[0029] The present application embodiment further provides a comparison device, comprising: a comparator, a first register and a second register; wherein,

[0030] a comparator, configured to compare the highest subsegment of a first element with the highest subsegment of a second element, record the comparison result in a first register, and record flag information corresponding to an intermediate result of the comparison in a second register; compare each subsegment of the first element and the second element except the highest subsegment, starting from the second highest subsegment, in sequence; in each comparison, determine, based on the flag information in the second register, that the subsegment currently being compared needs to be compared, update the flag information corresponding to the intermediate result of the comparison in the second register, and update the comparison result in the first register based on the flag information in the second register; until the lowest subsegment of the first element and the lowest subsegment of the second element are compared, and use the comparison result in the first register as the comparison result of the first element and the second element; wherein the first element is a finite field element including more than one subsegment, the second element is a finite field element including more than one subsegment, and the number of bits of each subsegment is the same as the number of bits of the processor used to perform the comparison;

[0031] The first register is used to update and store comparison results;

[0032] The second register is used to update the flag information corresponding to the intermediate result of the storage comparison.

[0033] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0034] Summary of the Figures

[0035] The accompanying drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0036] FIG. 1 is a schematic flowchart of a method for implementing comparison of finite field elements in an embodiment of the present application;

[0037] FIG. 2 is a schematic structural diagram of a comparison device in an embodiment of the present application.

[0038] Detailed description

[0039] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0040] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant accompanying drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0042] In a finite field, since the operations in the finite field are modulo p operations, therefore, after performing addition, subtraction, and multiplication operations, modulo reduction calculation is usually required to ensure that the result is within the finite field, that is, between 0 and the modulus p - 1. The following is the processing method for each operation:

[0043] For an addition operation (such as a + b), by comparison, if the operation result (such as c1) does not exceed the modulus p, the operation result remains unchanged; if the operation result exceeds the modulus p, the operation result is subtracted by p until the operation result falls within the range of 0 to p - 1. Its logical expression is as shown in formula (1):

[0044] For a subtraction operation (such as a - b), by comparison, if the operation result (such as c2) is positive, that is, a ≥ b, the operation result remains unchanged; if the operation result (such as c2) is negative, that is, a < b, the operation result is added by p until the operation result falls within the range of 0 to p - 1. Its logical expression is as shown in formula (2):

[0045] For Montgomery multiplication, the value of the final reduced data d is between [0, 2p), so we have formula (3):

[0046] In ZKP applications, in order to ensure security, the modulus of the finite field, i.e., the value of p, is generally more than two or three hundred bits. For traditional 32-bit or 64-bit processors, it is necessary to compare the two operands in order from the high-bit segment to the low-bit segment. Taking two 256-bit unsigned finite field elements (or operands) a and b, using a 64-bit processor as an example, element a is decomposed into 4 sub-segments, such as sub-segment a[3], sub-segment a[2], sub-segment a[1], and sub-segment a[0], each field is 64 bits; element b is decomposed into 4 sub-segments, such as sub-segment b[3], sub-segment b[2], sub-segment b[1], and sub-segment b[0], each field is 64 bits. In order to determine whether element a is greater than or equal to element b, the pseudocode can be expressed as:

[0047] As can be seen from the above program segment, in order to compare two 256-bit finite field operands, complex conditional judgment operations are required, and there are a large number of branch jump operations. Conditional branch operations may cause interruptions in the processor pipeline, thereby reducing computational efficiency.

[0048] In order to simplify the comparison procedure, avoid a large number of branch jump operations, and improve computational efficiency, an embodiment of the present application provides a method for implementing finite field element comparison, as shown in FIG1 , including:

[0049] Step 100: Compare the highest subsegment of the first element and the highest subsegment of the second element, record the comparison result in a first register, and record flag information corresponding to the intermediate result of the comparison in a second register; wherein the first element is a finite field element including more than one subsegment, the second element is a finite field element including more than one subsegment, and the number of bits of each subsegment is the same as the number of bits of the processor used to perform the comparison.

[0050] In an exemplary embodiment, when comparing whether the first element is smaller than the second element, if the comparison result is smaller than, the comparison result recorded in the first register is the first comparison result such as 1; if the comparison result is not smaller than, the comparison result recorded in the first register is the second comparison result such as 0.

[0051] In an exemplary embodiment, when the comparison is whether the first element is less than or equal to the second element, if the comparison result is less than or equal to, the comparison result recorded in the first register is a first comparison result such as 1; if the comparison result is neither less than nor equal to, the comparison result recorded in the first register is a second comparison result such as 0.

[0052] In an exemplary embodiment, when comparing whether the first element is equal to the second element, if the comparison result is equal, the comparison result recorded in the first register is the first comparison result such as 1; if the comparison result is not equal, the comparison result recorded in the first register is the second comparison result such as 0.

[0053] In one embodiment, the first register may be a register of at least 1 bit.

[0054] In an exemplary embodiment, when the comparison result is less than, the flag information corresponding to the intermediate result of the comparison is first flag information, such as 0; when the comparison result is equal to, the flag information corresponding to the intermediate result of the comparison is second flag information, such as 1; when the comparison result is greater than, the flag information corresponding to the intermediate result of the comparison is third flag information, such as 2. In one embodiment, the second register may be a register of at least 2 bits.

[0055] In an exemplary embodiment, the number of subsegments included in the first element may be the same as or different from the number of subsegments included in the second element. If the number of subsegments included in the first element is different from the number of subsegments included in the second element, for example, if the number of subsegments in the first element is less than that in the second element, the subsegments above the high order bits of the first element may be padded with zeros so that the number of subsegments in the first element is the same as that in the second element.

[0056] In one illustrative example, the first element and the second element may be unsigned integers.

[0057] Step 101: For each sub-segment of the first element and the second element except the highest sub-segment, compare them in sequence starting from the second highest sub-segment until the lowest sub-segment of the first element and the lowest sub-segment of the second element are compared, and use the comparison result in the first register as the comparison result of the first element and the second element; in each comparison, determine whether the sub-segment in the current comparison needs to be compared based on the flag information in the second register, update the flag information corresponding to the intermediate result of the comparison in the second register, and update the comparison result in the first register based on the flag information in the second register.

[0058] In an exemplary embodiment, recording the flag information corresponding to the intermediate comparison result in the second register and updating the comparison result in the first register according to the flag information in the second register in step 101 may include:

[0059] Determine whether the sub-segment in the current comparison needs to be compared based on the flag information in the second register. When the flag information in the second register indicates that comparison is not required, keep the flag information in the second register unchanged and keep the comparison result in the first register unchanged. When the flag information in the second register indicates that comparison is required, first update the flag information in the second register based on the comparison result of the sub-segment in the current comparison, and update the comparison result in the first register to the comparison result of the sub-segment in the current comparison.

[0060] In an exemplary embodiment, determining whether the sub-segment currently being compared needs to be compared according to the flag information in the second register includes:

[0061] If the flag information stored in the second register is the first flag information or the third flag information, there is no need to compare the sub-segments currently being compared;

[0062] If the flag information stored in the second register is the second flag information, the sub-segments currently being compared need to be compared.

[0063] In an exemplary embodiment, updating the flag information in the second register according to the comparison result of the sub-segment currently being compared may include:

[0064] The sub-segment in the current comparison is compared. When the comparison result is less than, the flag information corresponding to the intermediate result of the comparison in the second register is updated to the first flag information such as 0. When the comparison result is equal to, the flag information corresponding to the intermediate result of the comparison in the second register is updated to the second flag information such as 1. When the comparison result is greater than (that is, not less than or equal to), the flag information corresponding to the intermediate result of the comparison in the second register is updated to the third flag information such as 2.

[0065] In an exemplary embodiment, updating the comparison result in the first register to the comparison result of the sub-segment currently being compared may include:

[0066] In the case of comparing whether the first element is less than the second element, if the comparison result is less than, the comparison result in the first register is updated to the first comparison result, such as 1; if the comparison result is not less than, the comparison result in the first register is updated to the second comparison result, such as 0.

[0067] For the case where the comparison is whether the first element is less than or equal to the second element, if the comparison result is less than or equal to, the comparison result in the first register is updated to the first comparison result, such as 1; if the comparison result is not less than or equal to, the comparison result in the first register is updated to the second comparison result, such as 0.

[0068] In the case of comparing whether the first element is equal to the second element, if the comparison result is equal, the comparison result in the first register is updated to the first comparison result, such as 1; if the comparison result is not equal, the comparison result in the first register is updated to the second comparison result, such as 0.

[0069] In an embodiment of the present application, by cleverly using a register (i.e., the second register) to record the intermediate comparison results of the sub-segments of the elements participating in the comparison, it is directly determined whether it is necessary to compare the adjacent low sub-segments again based on the comparison results of the high-order sub-segments, thereby eliminating a large number of jump instructions in the comparison, simplifying the comparison program, avoiding problems that may cause interruptions to the processor pipeline, and improving computing efficiency.

[0070] The present application also provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute any of the above methods for implementing finite field element comparison.

[0071] The present application further provides a computer device, comprising a memory and a processor, wherein the memory stores the following instructions executable by the processor: for executing the steps of any one of the above-mentioned methods for implementing finite field element comparison.

[0072] FIG2 is a schematic diagram of the structure of the comparison device in an embodiment of the present application. As shown in FIG2 , the comparison device at least comprises: a comparator, a first register and a second register; wherein,

[0073] A comparator is used to compare the highest subsegment of a first element with the highest subsegment of a second element, record the comparison result in a first register, and record the flag information corresponding to the intermediate result of the comparison in a second register; for each subsegment of the first element and the second element except the highest subsegment, compare them in sequence starting from the second highest subsegment, in each comparison, determine the need to compare the subsegment currently being compared based on the flag information in the second register, update the flag information corresponding to the intermediate result of the comparison in the second register, and update the comparison result in the first register based on the flag information in the second register; until the lowest subsegment of the first element and the lowest subsegment of the second element are compared, and use the comparison result in the first register as the comparison result of the first element and the second element; wherein the first element is a finite field element including more than one subsegment, the second element is a finite field element including more than one subsegment, and the number of bits of each subsegment is the same as the number of bits of the processor used to perform the comparison.

[0074] The first register is used to update and store comparison results;

[0075] The second register is used to update the flag information corresponding to the intermediate result of the storage comparison.

[0076] In one exemplary embodiment, the comparator comparing the highest sub-segment of the first element with the highest sub-segment of the second element may be used to:

[0077] When comparing whether the first element is less than the second element, if the comparison result is less than, the comparison result recorded in the first register is the first comparison result, such as 1; if the comparison result is not less than, the comparison result recorded in the first register is the second comparison result, such as 0;

[0078] When comparing whether the first element is less than or equal to the second element, if the comparison result is less than or equal to, the comparison result recorded in the first register is the first comparison result, such as 1; if the comparison result is not less than or equal to, the comparison result recorded in the first register is the second comparison result, such as 0;

[0079] When comparing whether the first element is equal to the second element, if the comparison result is equal, the comparison result recorded in the first register is the first comparison result, such as 1; if the comparison result is not equal, the comparison result recorded in the first register is the second comparison result, such as 0;

[0080] When the comparison result is less than, the flag information corresponding to the intermediate result of the comparison is the first flag information such as 0; when the comparison result is equal to, the flag information corresponding to the intermediate result of the comparison is the second flag information such as 1; when the comparison result is greater than, the flag information corresponding to the intermediate result of the comparison is the third flag information such as 2.

[0081] In one exemplary embodiment, each sub-segment except the highest sub-segment of the comparator for comparing the first element and the second element may be used to:

[0082] Determine whether the sub-segment in the current comparison needs to be compared based on the flag information in the second register. When the flag information in the second register indicates that comparison is not required, keep the flag information in the second register unchanged and keep the comparison result in the first register unchanged. When the flag information in the second register indicates that comparison is required, first update the flag information in the second register based on the comparison result of the sub-segment in the current comparison, and update the comparison result in the first register to the comparison result of the sub-segment in the current comparison.

[0083] In an exemplary embodiment, the comparator determines whether the sub-segment currently being compared needs to be compared according to the flag information in the second register, including:

[0084] If the flag information stored in the second register is the first flag information or the third flag information, there is no need to compare the sub-segments currently being compared;

[0085] If the flag information stored in the second register is the second flag information, the sub-segments currently being compared need to be compared.

[0086] In an exemplary embodiment, the comparator updates the flag information in the second register according to the comparison result of the sub-segment currently being compared, including:

[0087] Compare the sub-segments in the current comparison. When the comparison result is less than, the flag information corresponding to the intermediate result of the comparison is updated to the first flag information such as 0. When the comparison result is equal to, the flag information corresponding to the intermediate result of the comparison is updated to the second flag information such as 1. When the comparison result is greater than, the flag information corresponding to the intermediate result of the comparison is updated to the third flag information such as 2.

[0088] In an exemplary embodiment, updating the comparison result in the first register to the comparison result of the sub-segment currently being compared in the comparator includes:

[0089] In the case of comparing whether the first element is less than the second element, if the comparison result is less than, the comparison result in the first register is updated to the first comparison result, such as 1; if the comparison result is not less than, the comparison result in the first register is updated to the second comparison result, such as 0.

[0090] For the case where the comparison is whether the first element is less than or equal to the second element, if the comparison result is less than or equal to, the comparison result in the first register is updated to the first comparison result, such as 1; if the comparison result is not less than or equal to, the comparison result in the first register is updated to the second comparison result, such as 0.

[0091] In the case of comparing whether the first element is equal to the second element, if the comparison result is equal, the comparison result in the first register is updated to the first comparison result, such as 1; if the comparison result is not equal, the comparison result in the first register is updated to the second comparison result, such as 0.

[0092] In one embodiment, the first register may be a register of at least 1 bit.

[0093] In one embodiment, the second register may be a register of at least 2 bits.

[0094] In the comparison device provided by the embodiment of the present application, by cleverly borrowing a register (i.e., the second register) to record the intermediate comparison results of the comparison between sub-segments of the elements participating in the comparison, and directly determining whether it is necessary to further compare the adjacent lower sub-segments according to the comparison result of the higher-order sub-segment, a large number of jump instructions are omitted in the comparison, the comparison program is simplified, the problem of possible interruption of the processor pipeline is avoided, and the operation efficiency is improved. In one embodiment, the comparison device provided by the embodiment of the present application realizes the comparison of larger unsigned integers composed of multiple registers, thereby realizing the comparison calculation of elements in a large modulus finite field.

[0095] In one embodiment, with reference to FIG. 2, taking the judgment of two data composed of two bit segments, such as whether a[2] is less than b[2] as an example, the working processes of the first register r1 for storing the comparison result and the second register compareReg for temporarily storing the intermediate comparison result are as follows:

[0096] Judging whether a[1] is less than b[1] from the highest sub-segment: If a[1]<b[1], then, compareReg = 0, r1 = 1; if a[1] == b[1], then, compareReg = 1, r1 = 0; if a[1]>b[1], then, compareReg = 2, r1 = 0;

[0097] Judging whether a[0] is less than b[0] in order from high to low sub-segments: If compareReg == 0, then, there is no need to judge at this time, and the intermediate comparison result stored in the second register compareReg remains unchanged, that is, compareReg = 0, and the comparison result stored in the first register r1 remains unchanged, that is, r1 = 1; if compareReg == 1, then, continue to judge whether a[0] is less than b[0]: If a[0]<b[0], then, update compareReg = 0, update r1 = 1, if a[0] == b[0], then, update compareReg = 1, update r1 = 0, if a[0]>b[0], then, update compareReg = 2, update r1 = 0; if compareReg == 2, then, there is no need to judge at this time, and the intermediate comparison result stored in the second register compareReg remains unchanged, that is, compareReg = 2, and the comparison result stored in the first register r1 remains unchanged, that is, r1 = 0; Finally, the result stored in the first register r1 is the comparison result of a[2] and b[2]. If r1 = 1, then, it is judged that a[2] is less than b[2]; if r1 = 0, then, it is judged that a[2] is not less than b[2].

[0098] In one embodiment, taking the judgment of two data composed of two bit segments, such as whether a[2] is less than or equal to b[2] as an example, the working processes of the first register r1 for storing the comparison result and the second register compareReg for temporarily storing the intermediate comparison result are as follows:

[0099] Judge whether a[1] is less than or equal to b[1] starting from the highest sub-segment: If a[1] < b[1], then compareReg = 0, r1 = 1; if a[1] == b[1], then compareReg = 1, r1 = 1; if a[1] > b[1], then compareReg = 2, r1 = 0;

[0100] Judge whether a[0] is less than or equal to b[0] in descending order of sub-segments: If compareReg == 0, then there is no need to judge at this time, and the intermediate comparison result stored in the second register compareReg remains unchanged, that is, compareReg = 0, and the comparison result stored in the first register r1 remains unchanged, that is, r1 = 1; if compareReg == 1, then continue to judge whether a[0] is less than b[0]: If a[0] < b[0], then update compareReg = 0, update r1 = 1, if a[0] == b[0], then update compareReg = 1, update r1 = 1, if a[0] > b[0], then update compareReg = 2, update r1 = 0; if compareReg == 2, then there is no need to judge at this time, and the intermediate comparison result stored in the second register compareReg remains unchanged, that is, compareReg = 2, and the comparison result stored in the first register r1 remains unchanged, that is, r1 = 0; Finally, the result stored in the first register r1 is the comparison result of a[2] and b[2]. If r1 = 1, then it is judged that a[2] is less than or equal to b[2]; if r1 = 0, then it is judged that a[2] is greater than b[2].

[0101] In one embodiment, taking the judgment of two data composed of two bit segments, such as whether a[2] is equal to b[2] as an example, the working processes of the first register r1 for storing the comparison result and the second register compareReg for temporarily storing the intermediate comparison result are as follows:

[0102] Judge whether a[1] is equal to b[1] starting from the highest sub-segment: If a[1] < b[1], then compareReg = 0, r1 = 0; if a[1] == b[1], then compareReg = 1, r1 = 1; if a[1] > b[1], then compareReg = 2, r1 = 0;

[0103] Judge whether a[0] is equal to b[0] according to the sub-segments from high to low: If compareReg == 0, then there is no need to judge at this time, and the intermediate comparison result stored in the second register compareReg remains unchanged, that is, compareReg = 0, and the comparison result stored in the first register r1 remains unchanged, that is, r1 = 0; If compareReg == 1, then continue to judge whether a[0] is equal to b[0]: If a[0] < b[0], then update compareReg = 0 and update r1 = 0; if a[0] == b[0], then update compareReg = 1 and update r1 = 1; if a[0] > b[0], then update compareReg = 2 and update r1 = 0; If compareReg == 2, then there is no need to judge at this time, and the intermediate comparison result stored in the second register compareReg remains unchanged, that is, compareReg = 2, and the comparison result stored in the first register r1 remains unchanged, that is, r1 = 0; Finally, the result stored in the first register r1 is the comparison result of a[2] and b[2]. If r1 = 1, then it is judged that a[2] is equal to b[2]; if r1 = 0, then it is judged that a[2] is not equal to b[2].

[0104] To implement the finite field element comparison method provided by the embodiments of the present application, the embodiments of the present application provide the following comparison instructions, which can be used to continuously judge the corresponding sub-segments of two finite field elements. For example: The first comparison instruction slt for judging whether two finite field data are in a less-than relationship; Another example: The second comparison instruction sle for judging whether two finite field data are in a less-than-or-equal relationship; Another example: The third comparison instruction seq for judging whether two finite field data are in an equal relationship.

[0105] In an exemplary example, to implement comparing the highest sub-segment of the first element and the highest sub-segment of the second element in step 100, the comparison instructions in the embodiments of the present application may include: The first comparison instruction slt is the first start comparison instruction sltStart, which is used to judge whether the corresponding highest sub-segments of two finite field data are in a less-than relationship. The second comparison instruction is the second start comparison instruction sleStart, which is used to judge whether the corresponding highest sub-segments of two finite field data are in a less-than-or-equal relationship. The third comparison instruction seq is the third start comparison instruction seqStart, which is used to judge whether the corresponding highest sub-segments of two finite field data are in an equal relationship. According to the method for implementing finite field element comparison provided by the embodiments of the present application, it can be seen that when using the start comparison instruction for judging the magnitude relationship of the corresponding highest sub-segments of two finite field data, the flag information corresponding to the intermediate comparison result of the comparison is directly stored in the second register, and at the same time, the corresponding comparison result is directly recorded in the first register.

[0106] In an exemplary embodiment, to implement the comparison of subsegments other than the highest subsegment of the first element and the second element in step 101, the comparison instructions in the embodiment of the present application may include: a first comparison instruction slt is a first continue comparison instruction sltContinue, which is used to determine whether the corresponding subsegments of the two finite field data other than the highest subsegment are in a less than relationship based on the intermediate comparison result stored in the second register. A second comparison instruction is a second continue comparison instruction sleContinue, which is used to determine whether the corresponding subsegments of the two finite field data other than the highest subsegment are in a less than or equal relationship based on the intermediate comparison result stored in the second register. A third comparison instruction seq is a third continue comparison instruction seqContinue, which is used to determine whether the corresponding subsegments of the two finite field data other than the highest subsegment are in an equal relationship based on the intermediate comparison result stored in the second register. According to the method for implementing finite field element comparison provided by the embodiment of the present application, it can be seen that when using a continue comparison instruction for determining the size relationship between corresponding sub-segments other than the highest sub-segment of two finite field data, whether to continue the comparison will be determined based on the flag information corresponding to the intermediate comparison result stored in the second register, and when no further comparison is required, the information in the second register and the first register remains unchanged. When further comparison is required, the intermediate comparison result in the second register is updated based on the comparison of the current corresponding sub-segment, and the new comparison result is updated to the first register at the same time.

[0107] Taking the comparison of two 256-bit finite field data, such as determining whether operand a is less than operand b, as an example, the comparison instruction in the embodiment of the present application is used in assembly, and the schematic program is as follows:

[0108] uint64 a[4],b[4]; / / indicates that a 64-bit processor is used for processing

[0109] sltStart r1,a[3],b[3]; / / Check whether the highest sub-segment 64 bits of a is less than the highest sub-segment 64 bits of b. If it is less than r1=1, otherwise r1=0

[0110] sltContinue r1,a[2],b[2]; / / According to the flag information in the hidden second register, only when the highest subsegment 64 bits of a are equal to the highest subsegment 64 bits of b, determine whether the second highest subsegment 64 bits of a are less than the second highest subsegment 64 bits of b. If less than, update r1 = 1; otherwise, update r1 = 0

[0111] sltContinue r1,a[1],b[1]; / / According to the flag information in the hidden second register, only when the second highest subsegment 64 bits of a are equal to the second highest subsegment 64 bits of b, determine whether the second lowest subsegment 64 bits of a is less than the second lowest subsegment 64 bits of b. If it is less than, update r1 = 1; otherwise, update r1 = 0

[0112] sltContinue r1,a[0],b[0]; / / Based on the flag information in the hidden second register, only when the second lowest subsegment 64 bits of a are equal to the second lowest subsegment 64 bits of b, determine whether the lowest subsegment 64 bits of a are less than the lowest subsegment 64 bits of b. If so, update r1 = 1; otherwise, update r1 = 0

[0113] Here, r1 represents the first register, which is used to record the comparison result of whether operand a is less than operand b. It should be noted that the second register is a hidden register, which is only used to store the intermediate comparison result and therefore does not appear in the above program segment.

[0114] Taking the comparison of two 256-bit finite field data, such as whether operand a is less than or equal to operand b, as an example, the comparison instruction in the embodiment of the present application is used in assembly, and the schematic program is as follows:

[0115] uint64 a[4],b[4]; / / indicates that a 64-bit processor is used for processing

[0116] sleStart r1,a[3],b[3]; / / Check whether the highest sub-segment 64 bits of a is less than or equal to the highest sub-segment 64 bits of b. If it is less than r1=1, otherwise r1=0

[0117] sleContinue r1,a[2],b[2]; / / Based on the flag information in the hidden second register, only when the highest subsegment 64 bits of a are equal to the highest subsegment 64 bits of b, determine whether the second highest subsegment 64 bits of a are less than or equal to the second highest subsegment 64 bits of b. If less than, update r1 = 1; otherwise, update r1 = 0

[0118] sleContinue r1,a[1],b[1]; / / Based on the flag information in the hidden second register, only when the second highest subsegment 64 bits of a is equal to the second highest subsegment 64 bits of b, determine whether the second lowest subsegment 64 bits of a is less than or equal to the second lowest subsegment 64 bits of b. If less than, update r1 = 1; otherwise, update r1 = 0

[0119] sleContinue r1,a[0],b[0]; / / Based on the flag information in the hidden second register, only when the second lowest subsegment 64 bits of a are equal to the second lowest subsegment 64 bits of b, determine whether the lowest subsegment 64 bits of a are less than or equal to the lowest subsegment 64 bits of b. If less than, update r1 = 1; otherwise, update r1 = 0

[0120] Here, r1 represents the first register, which is used to record the comparison result of whether operand a is less than operand b. It should be noted that the second register is a hidden register, which is only used to store the intermediate comparison result and therefore does not appear in the above program segment.

[0121] Taking the comparison of two 256-bit finite field data, such as determining whether operand a is equal to operand b, as an example, the comparison instruction in the embodiment of the present application is used in assembly, and the schematic program is as follows:

[0122] uint64 a[4],b[4]; / / indicates that a 64-bit processor is used for processing

[0123] seqStart r1,a[3],b[3]; / / Check whether the highest sub-segment 64 bits of a is equal to the highest sub-segment 64 bits of b, and is less than r1=1, otherwise r1=0

[0124] seqContinue r1,a[2],b[2]; / / Based on the flag information in the hidden second register, only when the highest subsegment 64 bits of a are equal to the highest subsegment 64 bits of b, determine whether the second highest subsegment 64 bits of a are equal to the second highest subsegment 64 bits of b. If less than, update r1 = 1; otherwise, update r1 = 0

[0125] seqContinue r1,a[1],b[1]; / / According to the flag information in the hidden second register, only when the second highest subsegment 64 bits of a are equal to the second highest subsegment 64 bits of b, determine whether the second lowest subsegment 64 bits of a are equal to the second lowest subsegment 64 bits of b. If less than, update r1 = 1; otherwise, update r1 = 0

[0126] seqContinue r1,a[0],b[0]; / / Based on the flag information in the hidden second register, only when the second lowest subsegment 64 bits of a are equal to the second lowest subsegment 64 bits of b, determine whether the lowest subsegment 64 bits of a are equal to the lowest subsegment 64 bits of b. If less than, update r1 = 1; otherwise, update r1 = 0

[0127] Here, r1 represents the first register, which is used to record the comparison result of whether operand a is less than operand b. It should be noted that the second register is a hidden register, which is only used to store the intermediate comparison result and therefore does not appear in the above program segment.

[0128] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A method for implementing comparison of finite field elements, comprising: Compare the highest sub - segments of the first element and the second element, record the comparison result in the first register, and record the flag information corresponding to the intermediate result of the comparison in the second register; wherein, the first element is a finite - field element including more than one sub - segment, the second element is a finite - field element including more than one sub - segment, and the number of bits of each sub - segment is the same as the number of bits of the processor used to perform the comparison. For each sub - segment of the first element and the second element except the highest sub - segment, start comparing from the second - highest sub - segment in sequence until the lowest sub - segment of the first element and the lowest sub - segment of the second element are compared, and use the comparison result in the first register as the comparison result of the first element and the second element; in each comparison, determine whether the sub - segment in the current comparison needs to be compared according to the flag information in the second register, update the flag information corresponding to the intermediate result of the comparison in the second register, and update the comparison result in the first register according to the flag information in the second register.

2. The method according to claim 1, wherein, The step of comparing the highest sub - segments of the first element and the second element and recording the comparison result in the first register includes: For the case where the comparison is to compare whether the first element is less than the second element, when the comparison result is less than, the comparison result recorded in the first register is the first comparison result; when the comparison result is not less than, the comparison result recorded in the first register is the second comparison result. For the case where the comparison is to compare whether the first element is less than or equal to the second element, when the comparison result is less than or equal to, the comparison result recorded in the first register is the first comparison result; when the comparison result is not less than and not equal to, the comparison result recorded in the first register is the second comparison result. For the case where the comparison is to compare whether the first element is equal to the second element, when the comparison result is equal, the comparison result recorded in the first register is the first comparison result; when the comparison result is not equal, the comparison result recorded in the first register is the second comparison result.

3. The method according to claim 2, wherein, The step of recording the flag information corresponding to the intermediate result of the comparison in the second register includes: When the comparison result is less than, the flag information corresponding to the intermediate result of the comparison is the first flag information; when the comparison result is equal, the flag information corresponding to the intermediate result of the comparison is the second flag information; when the comparison result is not less than and not equal to, the flag information corresponding to the intermediate result of the comparison is the third flag information.

4. The method according to claim 1, wherein, For each sub - segment of the first element and the second element except the highest sub - segment, the step of recording the flag information corresponding to the intermediate result of the comparison in the second register and updating the comparison result in the first register according to the flag information in the second register includes: Determine whether it is necessary to compare the sub - segment in the current comparison according to the flag information in the second register. When the flag information in the second register indicates that comparison is not required, keep the flag information in the second register unchanged and keep the comparison result in the first register unchanged; when the flag information in the second register indicates that comparison is required, update the flag information in the second register according to the comparison result of comparing the sub - segment in the current comparison, and update the comparison result in the first register to the comparison result of comparing the sub - segment in the current comparison.

5. The method according to claim 4, wherein, The determination of whether it is necessary to compare the sub - segment in the current comparison according to the flag information in the second register includes: If the flag information stored in the second register is the first flag information or the third flag information, then it is not necessary to compare the sub - segment in the current comparison; If the flag information stored in the second register is the second flag information, then it is necessary to compare the sub - segment in the current comparison.

6. The method according to claim 4, wherein, The update of the flag information in the second register according to the comparison result of comparing the sub - segment in the current comparison includes: Compare the sub - segment in the current comparison. If the comparison result is less than, update the flag information in the second register to the first flag information; if the comparison result is equal to, update the flag information in the second register to the second flag information; if the comparison result is greater than, update the flag information in the second register to the third flag information.

7. The method according to claim 4, wherein, The update of the comparison result in the first register to the comparison result of comparing the sub - segment in the current comparison includes: When the comparison is to compare whether the first element is less than the second element, if the comparison result is less than, update the comparison result in the first register to the first comparison result; if the comparison result is not less than, update the comparison result in the first register to the second comparison result; When the comparison is to compare whether the first element is less than or equal to the second element, if the comparison result is less than or equal to, update the comparison result in the first register to the first comparison result; if the comparison result is not less than and not equal to, update the comparison result in the first register to the second comparison result; When the comparison is to compare whether the first element is equal to the second element, if the comparison result is equal to, update the comparison result in the first register to the first comparison result; if the comparison result is not equal to, update the comparison result in the first register to the second comparison result.

8. The method according to any one of claims 1-7, wherein, The first register is a register with at least 1 bit; the second register is a register with at least 2 bits.

9. A computer device, comprising a memory and a processor, wherein, The memory stores the following instructions executable by a processor: steps for implementing the method for comparing finite - field elements according to any one of claims 1 to 8.

10. A comparison device, comprising: A comparator, a first register, and a second register; wherein, A comparator is used to compare the highest sub - segment of a first element and the highest sub - segment of a second element, record the comparison result in a first register, and record the flag information corresponding to the intermediate result of the comparison in a second register; for each sub - segment of the first element and the second element except the highest sub - segment, starting from the second - highest sub - segment, compare them separately in sequence. In each comparison, determine whether it is necessary to compare the sub - segment in the current comparison according to the flag information in the second register, update the flag information corresponding to the intermediate result of the comparison in the second register, and update the comparison result in the first register according to the flag information in the second register; until the lowest sub - segment of the first element and the lowest sub - segment of the second element are compared, take the comparison result in the first register as the comparison result of the first element and the second element; wherein, the first element is a finite - field element including more than one sub - segment, the second element is a finite - field element including more than one sub - segment, and the number of bits of each sub - segment is the same as the number of bits of the processor used to perform the comparison; A first register is used to update and store the comparison result; A second register is used to update and store the flag information corresponding to the intermediate result of the comparison.

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