Memory array, manufacturing method therefor, memory and electronic device

Abstract

The embodiments of the present application relate to the technical field of semiconductor storage. Provided are a memory array, a manufacturing method therefor, a memory and an electronic device, which are used for reducing the size of a memory while not affecting the capacity of the memory. The memory array comprises a substrate, transistor chains, a capacitor array and an electrical connection structure. Each transistor chain comprises a plurality of transistors connected in series. In the capacitor array, a vertical projection of one columnar capacitor on one transistor chain overlaps with a first electrode or a second electrode of one transistor. Each transistor chain and columnar capacitors electrically connected to the transistor chain form a chain type storage architecture. Electrodes of two adjacent columnar capacitors electrically connected to the same transistor chain are electrically connected to the two ends of the electrical connection structure respectively, such that the two adjacent columnar capacitors are connected in series by means of the electrical connection structure. The electrical connection structure does not occupy the distance between the two adjacent columnar capacitors, such that the distance between the two adjacent columnar capacitors is the same or approximately the same as the distance between the first electrode and the second electrode of one transistor.

Description

Storage array and manufacturing method thereof, memory and electronic device Technical Field

[0001] The present application relates to the field of semiconductor storage technology, and in particular to a storage array and a manufacturing method thereof, a memory, and an electronic device. Background Art

[0002] As users' requirements for the diversification of electronic device functions continue to increase, the amount of information processed by electronic devices is increasing, so that the memory in the electronic device needs to have a larger storage capacity. The above-mentioned memory, such as the storage unit of dynamic random access memory (DRAM), may include a transistor and a capacitor, and the capacitor is used to store information. The capacity of the capacitor needs to meet certain requirements before it can match the information processing requirements of the electronic device. However, in general, the capacity of the capacitor is proportional to the size of the capacitor. When the capacity of the capacitor increases, the size of the capacitor also increases, which cannot meet the requirements of the integration of the electronic device.

[0003] Summary of the Invention

[0004] The present application provides a memory array and a manufacturing method thereof, a memory, and an electronic device, which are used to reduce the size of the memory without affecting the memory capacity.

[0005] To achieve the above objectives, this application adopts the following technical solutions:

[0006] In one aspect of the present application, a memory array is provided, which includes a substrate, a transistor chain, a capacitor array, and at least one electrical connection structure. At least a portion of at least two transistor chains is disposed in the substrate, and the transistor chain includes a plurality of transistors connected in series. In the same transistor chain, the first electrode or the second electrode of two adjacent transistors is shared, so that the two adjacent transistors are connected in series. The capacitor array is stacked on the side of the transistor chain away from the substrate, and the capacitor array includes a plurality of columnar capacitors. The vertical projection of a columnar capacitor on the transistor chain at least partially overlaps with the first electrode or the second electrode of a transistor. In addition, the two electrodes of a columnar capacitor are respectively electrically connected to the first electrode and the second electrode of a transistor to form a memory cell. On this basis, at least one electrical connection structure is stacked on the side of the capacitor array away from the transistor chain, and the electrodes of two adjacent columnar capacitors electrically connected to the same transistor chain are respectively electrically connected to the two ends of the electrical connection structure, so that the two adjacent columnar capacitors are connected in series through the electrical connection structure.

[0007] In summary, the first or second pole of two adjacent transistors is shared, and multiple transistors can be connected in series to form the above-mentioned transistor chain. In addition, the two electrodes of the columnar capacitor are respectively electrically connected to the first and second poles of the same transistor, so that a transistor and a columnar capacitor electrically connected to the first and second poles of the transistor can constitute a storage unit. In this case, the above-mentioned transistor chain and the columnar capacitor electrically connected to the transistor chain can constitute a chain storage architecture. Compared with the 1T1C (one transistor and one capacitor) structure used in traditional DRAM, the chain storage architecture has a more compact storage unit arrangement, which is conducive to reducing the size of the storage array and the memory having the storage array. In addition, compared with the planar capacitor, in the same horizontal plane (for example, the supporting surface of the substrate of the storage capacitor), when the capacitance is the same, the area occupied by the columnar capacitor is smaller than the area occupied by the planar capacitor, thereby reducing the size of the storage unit without affecting the memory capacity, and further reducing the size of the storage array and the memory having the storage array. On this basis, the vertical projection of a columnar capacitor on the transistor chain at least partially overlaps with the first or second pole of a transistor. Furthermore, the electrical connection structure for connecting two adjacent columnar capacitors in series in the chain storage architecture is placed on the side of the capacitor array away from the transistor chain, thereby preventing the electrical connection structure from occupying the spacing between the two adjacent columnar capacitors. This allows the spacing between the two adjacent columnar capacitors to be the same or approximately the same as the spacing between the first and second poles of the transistor (twice the minimum semiconductor processing dimension F). In this way, the single-side size of the storage unit can reach 2F, allowing the area of ​​the entire storage unit to reach 4F. 2 , achieving the purpose of reducing the size of the storage unit, and then reducing the size of the storage array and the memory having the storage array.

[0008] In an optional embodiment, the columnar capacitor includes a first columnar electrode, a second columnar electrode and a dielectric layer. The first columnar electrode is electrically connected to the first pole or the second pole of the transistor toward one end of the transistor chain. At least a portion of the second columnar electrode is disposed in the first columnar electrode. At least a portion of the dielectric layer is disposed in the first columnar electrode, and the dielectric layer is located between the first columnar electrode and the second columnar electrode. The two adjacent columnar capacitors electrically connected to the same transistor chain are the first columnar capacitor and the second columnar capacitor, respectively. In addition, the two ends of the electrical connection structure are electrically connected to the second columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor, respectively. In this way, the two adjacent columnar capacitors electrically connected to the same transistor chain, such as the first columnar capacitor and the second columnar capacitor mentioned above, can be electrically connected through the above-mentioned electrical connection structure.

[0009] In an optional embodiment, the storage array further includes a first insulating layer, which covers the capacitor array. In addition, the electrical connection structure includes a first conductive hole, a second conductive hole and a first conductive portion. The first conductive hole passes through the first insulating layer, and the first end of the first conductive hole is electrically connected to the second columnar electrode of the first columnar capacitor. The second conductive hole passes through the first insulating layer, and the first end of the second conductive hole is electrically connected to the first columnar electrode of the second columnar capacitor. The first conductive portion is arranged on the side of the first insulating layer away from the capacitor array, and the two ends of the first conductive portion are electrically connected to the second end of the first conductive hole and the second end of the second conductive hole, respectively. In this way, the first conductive hole, the second conductive hole and the first conductive portion that are electrically connected to each other can constitute an electrical connection structure, and the two ends of the electrical connection structure can be electrically connected to the second columnar electrode of the adjacent first columnar capacitor and the first columnar electrode of the second columnar capacitor, respectively, so that the two adjacent columnar capacitors electrically connected to the same transistor chain are electrically connected through the above-mentioned electrical connection structure 40.

[0010] In an optional embodiment, in any one of the first columnar capacitor and the second columnar capacitor, the second columnar electrode extends out of the first columnar electrode toward one end of the electrical connection structure. In addition, the storage array further includes a first insulating layer, which covers the capacitor array. The electrical connection structure includes a third conductive hole and a second conductive portion. The third conductive hole passes through the first insulating layer, and the first end of the third conductive hole is electrically connected to the first columnar electrode of the second columnar capacitor. The second conductive portion is arranged on the side of the first insulating layer away from the capacitor array, and the two ends of the second conductive portion are respectively electrically connected to the end of the second columnar electrode of the first columnar capacitor facing the electrical connection structure and the second end of the third conductive hole. In this way, the second columnar electrode of the first columnar capacitor can be indirectly electrically connected to the first columnar electrode of the second columnar capacitor through the above-mentioned second conductive portion and the third conductive hole in sequence. In addition, only one conductive hole is provided between two adjacent columnar capacitors electrically connected to the same transistor chain, such as the first columnar capacitor and the second columnar capacitor, namely the above-mentioned third conductive hole. Therefore, the distance between two adjacent third vias is larger, and the precision requirement of the photolithography process for manufacturing the third vias is lower, which can simplify the manufacturing process of the memory array and the memory. The above-mentioned photolithography process may include exposure, development, etching and other processes for forming the film layer pattern.

[0011] In an optional embodiment, the memory array further includes a second insulating layer and an electrical connection post. The second insulating layer is disposed on a side of the transistor chain facing away from the substrate, and the capacitor array is embedded within the second insulating layer. The electrical connection post is disposed within the second insulating layer and is located on a side of the third conductive via facing away from the second conductive portion; the electrical connection post is electrically connected to the sidewall of the first columnar electrode and the third conductive via. In this way, since the electrical connection post is electrically connected to the sidewall of the first columnar electrode, the electrical connection post can increase the probability of electrical connection between the third conductive via and the first columnar electrode, thereby ensuring the reliability of the electrical connection.

[0012] In an optional embodiment, the columnar capacitor includes a first columnar electrode, a second columnar electrode, and a dielectric layer. At least a portion of the second columnar electrode is disposed within the first columnar electrode. At least a portion of the dielectric layer is disposed within the first columnar electrode, and the dielectric layer is located between the first columnar electrode and the second columnar electrode. The two adjacent columnar capacitors electrically connected to the same transistor chain are the first columnar capacitor and the second columnar capacitor. The first columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor are connected to form an integral structural member. One end of the integral structural member facing the transistor chain is electrically connected to the first electrode of the transistor. The second columnar electrode of the first columnar capacitor passes through the integral structural member and is electrically connected to the second electrode of the transistor. A first blind hole is provided on a side of the integral structural member facing away from the transistor chain, and the second columnar electrode of the second columnar capacitor is located within the first blind hole. At least one electrical connection structure includes a first electrical connection structure. In adjacent integral structural members, the second columnar electrode of the second columnar capacitor and the second columnar electrode of the first columnar capacitor are electrically connected to both ends of the first electrical connection structure, respectively. In this way, one end of the integrated structural member facing the transistor chain is electrically connected to the first electrode of the transistor, thereby electrically connecting one electrode of the transistor constituting the above-mentioned memory cell, such as the source, to one electrode of the columnar capacitor, such as the first columnar electrode. Furthermore, another electrode of the transistor constituting the above-mentioned memory cell, such as the drain, is electrically connected to another electrode of the columnar capacitor, such as the second columnar electrode. Furthermore, two adjacent columnar capacitors electrically connected to the same transistor chain but having different integrated structural members can be connected in series via the above-mentioned first electrical connection structure.

[0013] In an optional embodiment, the storage array further includes a first insulating layer, which covers the capacitor array. The adjacent integral structural members are respectively a first integral structural member and a second integral structural member, and the first electrical connection structure includes a fourth conductive hole, a fifth conductive hole and a third conductive portion. Among them, the fourth conductive hole passes through the first insulating layer, and the first end of the fourth conductive hole is electrically connected to the second columnar electrode of the second columnar capacitor in the first integral structural member. The fifth conductive hole passes through the first insulating layer, and the first end of the fifth conductive hole is electrically connected to the second columnar electrode of the first columnar capacitor in the second integral structural member. The third conductive portion is arranged on the side of the first insulating layer away from the capacitor array, and the two ends of the third conductive portion are electrically connected to the second end of the fourth conductive hole and the second end of the fifth conductive hole, respectively. In this way, in the adjacent integral structural members, the second columnar electrode of the second columnar capacitor in the first integral structural member can be electrically connected to the second columnar electrode of the first columnar capacitor in the second integral structural member through the fourth conductive hole, the third conductive portion and the fifth conductive hole in sequence.

[0014] In one optional embodiment, in a columnar capacitor, the second columnar electrode extends from the first columnar electrode at one end facing away from the transistor chain. The capacitor array includes multiple integral structural members, and the two ends of the first electrical connection structure are respectively electrically connected to the ends of two adjacent second columnar electrodes located in different integral structural members, facing away from the transistor chain. In this way, two adjacent columnar capacitors with different integral structures, such as the first columnar capacitor and the second columnar capacitor, can be connected in series via the first electrical connection structure.

[0015] In an optional embodiment, in the transistor chain, the columnar capacitor electrically connected to the transistor at the end or the beginning is a third columnar capacitor. A second blind hole is provided on the side of the third columnar capacitor facing away from the transistor chain, and the second columnar electrode of the third columnar capacitor is located in the second blind hole. In addition, at least one electrical connection structure also includes a second electrical connection structure; the second columnar electrode of the third columnar capacitor and the second columnar electrode of the adjacent first columnar capacitor or the second columnar capacitor are respectively electrically connected to the two ends of the second electrical connection structure. In this way, the third columnar capacitor can be electrically connected to the first columnar capacitor or the second columnar capacitor adjacent to the third columnar capacitor through the above-mentioned second electrical connection structure. The second electrical connection structure can be obtained by the same logic as the structure of the first connection structure, and will not be repeated here.

[0016] In an optional embodiment, the dielectric layer includes a ferroelectric thin film layer. In this case, the columnar capacitor can be a ferroelectric capacitor, and the memory having the ferroelectric capacitor can be a ferroelectric random access memory. The ferroelectric random access memory has the characteristics of low leakage and high density. Alternatively, the dielectric layer includes a resistive switching layer. In this case, the columnar capacitor can be a resistive switching capacitor, and the memory having this set of edge capacitors can be a resistive switching memory.

[0017] In an optional embodiment, the first electrode or the second electrode of the transistor is located within the range of the vertical projection of the columnar capacitor on the transistor chain, thereby reducing the distance between the first electrode and the second electrode of the transistor occupied by the columnar capacitor.

[0018] In an optional embodiment, the columnar capacitor can be located directly above the first or second electrode of the transistor. In this case, the center of the columnar capacitor can overlap or approximately overlap with the center of the first or second electrode of the transistor, thereby reducing the distance between the first and second electrodes of the transistor occupied by the columnar capacitor.

[0019] In an optional embodiment, the first electrode and the second electrode of the transistor are arranged in the substrate. The memory array also includes a first electrode line, which is electrically connected to the gate of the transistor. The first electrode line is arranged on the surface of the substrate facing the capacitor array. Alternatively, the first electrode line is arranged in the substrate. When the first electrode line is arranged in the substrate and the first electrode line is electrically connected to or shared with the gate of the transistor, the length of the channel between the first electrode and the second electrode of the transistor can be increased. In addition, since the first electrode line is located in the substrate, the size of the entire memory array occupied by the first electrode line along the thickness direction of the memory can be reduced.

[0020] In one optional embodiment, the memory array further includes a second electrode line and a third electrode line. The first end of a transistor chain is electrically connected to a second electrode line. The third electrode line is electrically connected to the second ends of at least two transistor chains. In this manner, one or more of the electrical connections between the first, second, and third electrode lines is used to select a memory cell to be read or written in the memory array by receiving a control level output by the control circuit, thereby enabling data reading and writing.

[0021] In an optional embodiment, the memory array further includes a contact portion, which is disposed between the transistor chain and the capacitor array, wherein one contact portion is electrically connected to an electrode of a columnar capacitor and a first electrode or a second electrode of a transistor. Thus, the electrode of the columnar capacitor can be accurately electrically connected to the first electrode or the second electrode of the transistor T through the contact portion.

[0022] In one optional embodiment, the multiple columnar capacitors electrically connected to at least two transistor chains are arranged in a matrix. In this case, provided that the spacing between two adjacent first electrode lines, such as word lines, meets process requirements, such as minimum processing dimensions, the size of the columnar capacitors within the substrate support surface can be reduced to reduce the spacing between the columnar capacitors electrically connected to the two adjacent transistor chains. This allows for a more compact arrangement of memory cells in the memory array, resulting in a memory having a high density. Alternatively, the multiple columnar capacitors electrically connected to at least two transistor chains are arranged in a honeycomb pattern. In this case, the columnar capacitor electrically connected to one of the two adjacent transistor chains can be located between two adjacent columnar capacitors electrically connected to the other transistor chain, thereby making the arrangement of the multiple transistor chains more compact. Furthermore, provided that the spacing between the columnar capacitors electrically connected to the two adjacent transistor chains meets process requirements, such as minimum processing dimensions, the size of the columnar capacitors within the substrate support surface can be increased, which is beneficial for increasing the capacity of the memory array and the memory having the memory array.

[0023] Another aspect of the present application provides a memory device, comprising any of the aforementioned memory arrays and a memory device. A controller is electrically connected to the memory array and configured to control read and write operations in the memory array. The aforementioned memory device has the same technical effects as the memory arrays provided in the aforementioned embodiments and will not be further described herein.

[0024] Another aspect of the present application provides an electronic device comprising a circuit board and any of the above-described memories, wherein the circuit board is electrically connected to the memories. The electronic device has the same technical effects as the memory array provided in the aforementioned embodiment, and will not be further described here.

[0025] On the other hand, the present application provides a method for manufacturing a memory array, comprising: first, forming at least a portion of a plurality of transistors in a substrate, wherein the first pole or the second pole of two adjacent transistors is shared, so that the two adjacent transistors are connected in series to form a transistor chain. Next, a plurality of columnar capacitors are formed, wherein the vertical projection of a columnar capacitor on the transistor chain at least partially overlaps with the first pole or the second pole of a transistor. The two electrodes of a columnar capacitor are electrically connected to the first pole and the second pole of a transistor, respectively, to form a memory cell. Next, at least one electrical connection structure is formed on the side of the plurality of columnar capacitors away from the transistor chain; the two ends of the electrical connection structure are electrically connected to the electrodes of two adjacent columnar capacitors electrically connected to the same transistor chain, respectively, so that the two adjacent columnar capacitors are connected in series through the electrical connection structure. The method for manufacturing the memory array has the same technical effect as the memory array provided in the aforementioned embodiment, and will not be repeated here.

[0026] In an optional embodiment, forming any one of a plurality of columnar capacitors includes: first forming a first columnar electrode. Next, forming a dielectric layer in the first columnar electrode. Next, forming a second columnar electrode in the dielectric layer, the dielectric layer being located between the first columnar electrode and the second columnar electrode. Among them, the two adjacent columnar capacitors electrically connected to the same transistor chain are the first columnar capacitor and the second columnar capacitor, respectively. Forming an electrical connection structure includes electrically connecting the two ends of the electrical connection structure to the second columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor, respectively. The technical effects of the electrical connection method of the above-mentioned electrical connection structure and the first columnar capacitor and the second columnar capacitor are the same as described above and will not be repeated here.

[0027] In an optional embodiment, the two adjacent columnar capacitors electrically connected to the same transistor chain are a first columnar capacitor and a second columnar capacitor. Forming the first columnar capacitor and the second columnar capacitor includes: first, forming a first columnar electrode of the first columnar capacitor and a first columnar electrode of the second columnar capacitor, and connecting the first columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor to form an integral structure. Next, electrically connecting the end of the integral structure facing the transistor chain to the first electrode of the transistor. Next, forming a through hole through the integral structure on the integral structure, and forming a second columnar electrode of the first columnar capacitor in the through hole, and electrically connecting the second columnar electrode to the second electrode of the transistor. Next, forming a first blind hole on a side of the integral structure facing away from the transistor chain, and forming a second columnar electrode of the second columnar capacitor in the first blind hole. Next, forming at least one electrical connection structure includes: forming a first electrical connection structure on a side of the plurality of columnar capacitors facing away from the transistor chain, and electrically connecting the two ends of the first electrical connection structure to the second columnar electrode of the second columnar capacitor and the second columnar electrode of the first columnar capacitor in the adjacent integral structure. The technical effects of the electrical connection structure and the electrical connection method between the first columnar capacitor and the second columnar capacitor are the same as those described above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0029] FIG2 is a schematic diagram of a structure of a memory provided in an embodiment of the present application;

[0030] FIG3 is another structural diagram of the memory in FIG2 ;

[0031] FIG4A is a schematic structural diagram of the storage unit in FIG3 ;

[0032] FIG4B is a schematic diagram of a chain storage architecture provided by an embodiment of the present application;

[0033] FIG4C is a schematic diagram of another chain storage architecture provided in an embodiment of the present application;

[0034] FIG5A is a schematic structural diagram of a columnar capacitor provided in an embodiment of the present application;

[0035] FIG5B is a schematic structural diagram of another columnar capacitor provided in an embodiment of the present application;

[0036] FIG6 is a schematic diagram of the structure of a storage array provided in an embodiment of the present application;

[0037] FIG7 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0038] FIG8 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0039] FIG9 is a schematic diagram of a top view of the structure obtained along the direction A in FIG8 ;

[0040] FIG10 is a flow chart of a method for manufacturing a memory array according to an embodiment of the present application;

[0041] FIG11(a), FIG11(b), FIG11(c), and FIG11(d) are structural diagrams obtained by respectively executing at least a portion of the manufacturing method shown in FIG10 ;

[0042] FIG12 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0043] FIG13A is a schematic diagram of a top view of the structure obtained along the direction B in FIG7 or FIG12;

[0044] FIG13B is another schematic top view of the structure obtained along the direction B in FIG7 or FIG12;

[0045] FIG14A is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0046] FIG14B is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0047] FIG15 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0048] FIG16A is a schematic diagram of a top view of the structure obtained along the direction C in FIG15;

[0049] FIG16B is another schematic diagram of a top view of the structure obtained along the direction C in FIG15;

[0050] FIG16C is another schematic diagram of a top view of the structure obtained along the direction C in FIG15;

[0051] FIG17 is another schematic diagram of a top view of the structure obtained along the direction C in FIG15;

[0052] FIG18 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0053] FIG19 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0054] FIG20 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0055] FIG21 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0056] FIG. 22 (a) and FIG. 22 (b) are structural diagrams obtained by respectively performing at least a portion of the manufacturing method shown in FIG. 10 ;

[0057] FIG23 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application;

[0058] FIG24A is a schematic diagram of a top view of the structure obtained along the direction D in FIG19;

[0059] FIG24B is another schematic diagram of a top view of the structure obtained along the direction D in FIG19;

[0060] FIG25 is a schematic diagram of the structure of another storage array provided in an embodiment of the present application.

[0061] Reference numerals: 01-electronic device; 100-PCB; 101-bus; 102-SoC; 103-second RAM; 104-communication chip; 105-power management chip; 112-AP; 122-GPU; 132-first RAM; 20-memory; 21-storage array; 22-controller; 210-storage unit; 220-decoder; 230-driver; 240-timing controller; 250-cache; 260-input / output driver; 2100-transistor chain; 300-capacitor array; 200-substrate; 30-columnar capacitor; 301-first columnar electrode; 302-second columnar electrode; 303-dielectric layer; 40-electrical connection structure; 401 -first conductive hole; 402-second conductive hole; 403-first conductive portion; 30a-first columnar capacitor; 30b-second columnar capacitor; 211-contact portion; 51-first insulating layer; 52-second insulating layer; 501-via; 404-third conductive hole; 405-second conductive portion; 500-hard mask; 60-electrical connection column; 70-integral structural member; 70a-first integral structural member; 70b-second integral structural member; 30c-third columnar capacitor; 41-first electrical connection structure; 42-second electrical connection structure; 701-first blind hole; 702-second blind hole; 711-through hole; 411-fourth conductive hole; 412-fifth conductive hole; 413-third conductive portion. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0063] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0064] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed mechanical connection, a detachable mechanical connection, or an integrated connection; or, "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0065] In addition, unless otherwise clearly specified and limited, the term "electrical connection" should be understood in a broad sense. For example, "electrical connection" can be a direct electrical connection, for example, physical contact and electrical conduction between two components. It can also be understood as the electrical connection between different components in the circuit structure through physical lines such as printed circuit board (PCB) copper foil or wires that can transmit electrical signals to transmit electrical signals; or, "electrical connection" can be an indirect electrical connection between two components through an intermediate medium; or, "electrical connection" can be an electrical connection between two components in an air / non-contact manner, for example, two components are electrically connected by capacitive coupling to transmit electrical signals.

[0066] In the embodiments of the present application, the descriptions "vertical" and "parallel" respectively indicate approximately vertical and approximately parallel within a certain error range, and the error range may be a range in which the deviation angle relative to absolute vertical and absolute parallel is less than or equal to 5°, 8° or 10°, respectively, and no specific limitation is made here.

[0067] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0068] In the drawings of the embodiments of the present application, components are represented by guide lines with arrows; parts are represented by guide lines only; openings, holes and the like are represented by guide lines with wavy lines at the ends.

[0069] The embodiment of the present application provides an electronic device. The electronic device can be applied to various communication systems or communication protocols, such as: Bluetooth (BT) communication technology, global positioning system (GPS) communication technology, global system of mobile communication (GSM) communication technology, wireless fidelity (WiFi) communication technology, wideband code division multiple access wireless (WCDMA) communication technology, long term evolution (LTE), 5G communication technology and other future communication technologies. The electronic device in the embodiment of the present application can be a mobile phone, a tablet computer (pad), a laptop computer, a smart home, a smart wearable device (for example, a smart watch, a smart bracelet, smart glasses, a smart helmet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, etc. The electronic device can also be a handheld device with wireless communication function, a computing device or other processing device connected to a wireless modem, an in-vehicle device, an electronic device in a 5G network or an electronic device in a future public land mobile network (PLMN), etc., and the embodiment of the present application is not limited to this.

[0070] For example, as shown in FIG1 , the electronic device 01 may include a circuit board (e.g., the PCB) 100, a bus 101 disposed on the PCB 100 and electrically connected to the PCB 100, and a processor connected to the bus 101, such as a system on chip (SoC) 102. The SoC 102 may be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SoC 102 may include an application processor (AP) 112 for processing applications, a graphics processing unit (GPU) 122 for processing image data, and a first RAM 132 for caching high-speed data. The first RAM 132 may be a static random access memory (SRAM) or an embedded flash memory (EFlash), etc. The AP 112, GPU 122, and first RAM 132 may be integrated into a single die, or may be separately disposed in multiple dies.

[0071] In addition, as shown in Figure 1, the electronic device 01 may further include a second RAM 103 connected to the SoC 102 via the bus 101. The second RAM 103 may be a dynamic random access memory (DRAM). The second RAM 103 may be used to store volatile data, such as temporary data generated by the SoC 102. The storage capacity of the second RAM 103 may generally be larger than the first RAM 132, but the reading speed is generally slower than the first RAM 132. In addition, the electronic device 01 may further include a communication chip 104 and a power management chip 105 connected to the SoC 102 via the bus 101. The communication chip 104 may be used for processing the protocol stack, or for amplifying and filtering analog radio frequency signals, or for performing the above functions simultaneously. The power management chip 105 may be used to power other chips. In one embodiment, the SoC 102 and the second RAM 103 may be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, to obtain a faster data transmission rate between chips.

[0072] In this case, the memory in the electronic device 01 provided in the embodiment of the present application can be the first RAM 132 or the second RAM 103 in Figure 1. This application does not limit the application scenarios of the above-mentioned memory. Based on this, as shown in Figure 2, the above-mentioned memory 20 may include a storage array 21 and a controller 22 for accessing the storage array 21, wherein the controller 22 is electrically connected to the above-mentioned storage array 21, and the controller 22 can be used to control the read and write operations of the storage array 21.

[0073] For example, in the above-mentioned memory 20, the memory array 21 and the controller 22 can be two independent chips (die). The memory array 21 and the controller 22 can be respectively disposed on a carrier board (for example, a packaged transistor chain or an adapter board), and the memory array 21 and the controller 22 are respectively electrically connected to the above-mentioned carrier board. In this way, the memory array 21 and the controller 22 can realize signal transmission through the metal traces within the carrier board. Based on this, the memory 20 with the above-mentioned memory array 21 can be called a stand-alone memory.

[0074] Alternatively, as another example, in the memory 20, the memory array 21 and the controller 22 can be two independent chips (dies), and the memory array 21 and the controller 22 are stacked on the carrier board. The memory array 21 and the controller 22 can be electrically connected via through silicon vias (TSVs) or redistribution layers (RDLs), thereby enabling signal transmission between the memory array 21 and the controller 22 and the carrier board. Similarly, the memory array 21 is the independent memory described above.

[0075] Alternatively, for example, in the memory 20, the memory array 21 and the controller 22 may be integrated into the same chip, and the integrated chip may be electrically connected to the carrier board. Based on this, the memory 20 having the memory array 21 may be referred to as an embedded memory.

[0076] On this basis, as shown in Figure 3, the memory array 21 may include a plurality of memory cells 210, wherein each memory cell 210 may be used to store 1 bit (bit) or multiple bits of data. For example, as shown in Figure 4A, the memory cell 210 may include a transistor T and a capacitor C. The two ends of the capacitor C may be connected to the first pole of the transistor T, for example, the source (source, S) and the second pole, for example, the drain (drain, D), respectively. Alternatively, the first pole (for example, the drain D) and the second pole (for example, the source S) of the transistor T are connected respectively. For the sake of convenience of explanation, the following examples are all taken as examples in which the first pole of the transistor T is the source S and the second pole is the drain D.

[0077] FIG4A above is merely an example of a memory cell 210 of the memory array 21 being 1T1C (i.e., one transistor T and one storage capacitor C). The embodiment of the present application does not limit the number of transistors and storage capacitors in the memory cell 210. In addition, the controller 22 in FIG2 may include one or more circuit structures of the decoder 220, driver 230, timing controller 240, buffer 250, or input / output driver 260 shown in FIG3. The decoder 220 is used to decode the address of the memory cell 210. The decoder 220 is used to decode the received address to determine the memory cell 210 to be accessed. The driver 230 is used to control the level of the signal line according to the decoding result generated by the decoder 220, thereby accessing the specified memory cell 210. The buffer 250 is used to cache the read data, for example, a first-in first-out (FIFO) method can be used for caching. The timing controller 240 is used to control the timing of the buffer 250 and the timing of the driver 230 driving the signal lines in the storage unit 210. The input / output driver 260 is used to drive transmission signals, such as received data signals and transmitted data signals, so that the data signals can be transmitted over long distances. The storage array 21, decoder 220, driver 230, timing controller 240, buffer 250, and input / output driver 260 can be integrated into a single chip or integrated into multiple chips.

[0078] Based on this, in some embodiments of the present application, the memory 20 may be a chain cell memory architecture. In this case, as shown in FIG4B , the memory array 21 may include at least two transistor chains 2100 ( FIG4B uses one as an example). The transistor chain 2100 may include at least two transistors T connected in series. Among them, among two adjacent transistors T in the same transistor chain 2100, one electrode of one transistor T, such as the source S or the drain D, is electrically connected to one electrode of the other transistor T, such as the drain D or the source S, so that the two adjacent transistors T in the transistor chain 2100 are connected in series.

[0079] The above-mentioned transistor T can be a metal-oxide-semiconductor field-effect transistor (MOSFET). Based on this, in order to enable multiple transistors T in the transistor chain 2100 to be connected in series, as shown in Figure 4C, the storage array 21 can also include a substrate 200. For example, the substrate 200 can be a semiconductor substrate, such as a silicon (Si) substrate. In the process of manufacturing the above-mentioned transistor chain 2100 (as shown in Figure 4B), the first electrode (for example, source S) and the second electrode (for example, drain D) of the transistor can be formed in the substrate 200 through a doping process. Among them, the first electrode (for example, source S) or the second electrode (for example, drain D) of two adjacent transistors is shared.

[0080] For example, as shown in FIG4C , the two adjacent transistors may be transistor T1 and transistor T2. The second electrode (e.g., drain D) of transistor T1 and the second electrode (e.g., drain D) of transistor T2 are shared, which means that the second electrode (e.g., drain D) between transistor T1 and transistor T2 can serve as both the second electrode of transistor T1 and the second electrode of transistor T2. In this way, the second electrode (e.g., drain D) of transistor T1 and the second electrode (e.g., drain D) of transistor T2 can be electrically connected, thereby connecting transistors T1 and T2 in series.

[0081] The above description uses the example of transistors T1 and T2 being connected in series, with the second electrode (e.g., drain D) of transistor T1 being shared with the second electrode (e.g., drain D) of transistor T2 as an example. In other embodiments of the application, transistors T1 and T2 may be connected in series, with the first electrode (e.g., source S) of transistor T1 being shared with the first electrode (e.g., source S) of transistor T2. Furthermore, the series connection method of the other transistors in the transistor chain 2100 (as shown in FIG. 4B ) is the same as described above and will not be further described here.

[0082] In addition, it can be seen from the above that as shown in Figure 4B, each transistor T is electrically connected to a capacitor C, and multiple capacitors C can constitute a capacitor array 300. Since the first and second poles of each transistor T in the transistor chain 2100 are electrically connected to the two ends of a capacitor C, and two adjacent transistors T are connected in series, multiple capacitors C electrically connected to the same transistor chain 2100 can also be connected in series. Among them, the capacitor C can be a columnar capacitor 30 as shown in Figure 5A or Figure 5B, wherein the columnar capacitor 30 shown in Figure 5A can be a cylinder, and the columnar capacitor 30 shown in Figure 5B can be a cubic body. This application does not limit the external shape of the columnar capacitor 30. For the convenience of explanation below, the columnar capacitor 30 is taken as an example of a cylinder as shown in Figure 5A.

[0083] Continuing with FIG5A , the columnar capacitor 30 may include a first columnar electrode 301, a second columnar electrode 302, and a dielectric layer 303. At least a portion of the second columnar electrode 302 is disposed within the first columnar electrode 301. At least a portion of the dielectric layer 303 is disposed within the first columnar electrode 301, and the dielectric layer 303 is located between the first columnar electrode 301 and the second columnar electrode 302. The first columnar electrode 301 may be referred to as a bottom electrode (BE), and the second columnar electrode 302 located within the first columnar electrode 301 may be referred to as a top electrode (TE).

[0084] In some embodiments of the present application, the dielectric layer 303 may be a ferroelectric thin film layer, or a ferroelectric insulator. In this case, the columnar capacitor 30 may be a ferroelectric capacitor (FeCAP), and the memory 20 having the ferroelectric capacitor may be a ferroelectric random access memory (FeRAM or FRAM). FeRAM has the characteristics of low leakage and high density.

[0085] Alternatively, in some other embodiments of the present application, the dielectric layer 303 may be a resistive switching layer. In this case, the columnar capacitor 30 may be a resistive switching capacitor, and the memory 20 having the set of edge capacitors may be a resistive random access memory (RRAM).

[0086] On this basis, the memory array 21 of the above-mentioned memory may include two or more transistor chains 2100 as shown in Figure 6. Since in the memory array 21, a transistor T and a capacitor C electrically connected to the transistor T constitute a memory cell 210, the multiple memory cells 210 in the memory array 21 composed of the above-mentioned transistor chain 2100 and multiple transistors T can be arranged in an array. In addition, the above-mentioned memory array 21 may also include a first electrode line, such as a word line (WL), a second electrode line, such as a bit line (BL), and a third electrode line, such as a plate line PL. The gate (gate, G) of the transistor T can be electrically connected to the first electrode line, such as the word line WL. The first end (e.g., the right end) of a transistor chain 2100 can be electrically connected to a second electrode line, such as the bit line BL. The third electrode line, such as the plate line PL, can be electrically connected to the second end (e.g., the left end) of at least two transistor chains 2100.

[0087] In addition, the transistor chain 2100 may further include a gate transistor T BS , the gate transistor T BS The gate of the transistor T is electrically connected to the control signal line BS. The control signal line BS can control the gate transistor T BS is turned on, so that the gate transistor T BS The transistor chain 2100 is selected.

[0088] As can be seen from the above, different memory cells 210 can be electrically connected to word lines WL, bit lines BL, and plate lines PL. One or more of the above-mentioned word lines WL, bit lines BL, and plate lines PL are used to select the memory cell 210 to be read or written in the memory array 21 by receiving the control level output by the control circuit, so as to change the polarization direction (upward polarization or downward polarization) of the capacitor C in the memory cell 210 in the ferroelectric memory, or change the resistance state (high resistance state or low resistance state) of the capacitor C in the resistive random access memory, thereby realizing data read and write operations. Among them, the states corresponding to the two polarization directions (upward polarization and downward polarization) of the capacitor C in the ferroelectric memory, or the two resistance states (high resistance state or low resistance state) of the capacitor C in the resistive random access memory can be identified as the state of storing information "0" or "1", thereby realizing the reading operation of the data stored in the capacitor C.

[0089] The following describes an example of the structure of a memory array 21 having the aforementioned transistor chains 2100 and columnar capacitors 30. As described above, as shown in FIG6 , the memory array 21 includes at least two transistor chains 2100 and a capacitor array 300. In some embodiments of the present application, as shown in FIG7 , at least a portion of the aforementioned transistor chains 2100 is disposed within the substrate 200. For example, the first electrode (e.g., source S) and the second electrode (e.g., drain D) of the transistor T in the transistor chains 2100 are disposed within the substrate 200. The capacitor array 300 is stacked and disposed on a side of the transistor chains 2100 facing away from the substrate 200.

[0090] To illustrate the structure of the memory array 21, an XYZ coordinate system as shown in FIG6 may be established, wherein the XY plane is parallel to the upper surface of the substrate 200 in FIG4C (the surface used for doping to form the transistor source and drain, hereinafter referred to as the substrate support surface). The X direction may be the extension direction of a transistor chain 2100, the Y direction may be the arrangement direction of multiple transistor chains 2100, and the Z direction may be the stacking direction of the transistor chain 2100 and the capacitor array 300 (as shown in FIG7).

[0091] 7 , in the capacitor array 300 , a vertical projection of a columnar capacitor 30 on the transistor chain 2100 at least partially overlaps with a first electrode (e.g., source S) or a second electrode (e.g., drain D) of a transistor T, thereby reducing the distance between the first electrode and the second electrode of the transistor T occupied by the columnar capacitor 30 .

[0092] In some embodiments of the present application, the first pole (e.g., source S) or the second pole (e.g., drain D) of the transistor T may be located within the range of the vertical projection of the columnar capacitor 30 on the transistor chain 2100, that is, the columnar capacitor 30 may completely cover the first pole (e.g., source S) or the second pole (e.g., drain D) of the transistor T. For example, the columnar capacitor 30 may be located directly above the first pole (e.g., source S) or the second pole (e.g., drain D) of the transistor T. In this case, the center (e.g., the axis of the cylinder) of the columnar capacitor 30 may overlap or approximately overlap with the center (e.g., geometric center) of the first pole (e.g., source S) or the second pole (e.g., drain D) of the transistor T, thereby achieving the purpose of reducing the distance between the first pole and the second pole of the transistor occupied by the columnar capacitor.

[0093] Alternatively, in some other embodiments of the present application, a portion of the vertical projection of the columnar capacitor 30 on the transistor chain 2100 may overlap with a portion of the first electrode (eg, source S) or the second electrode (eg, drain D) of the transistor T.

[0094] Furthermore, in some embodiments, the gate of transistor T, i.e., the location of word line WL, may not overlap with the vertical projection of columnar capacitor 30 on transistor chain 2100, as shown in FIG7 . Alternatively, in other embodiments, as shown in FIG8 , a portion of the gate of transistor T, i.e., a portion of the location of word line WL, may overlap with a portion of the vertical projection of a columnar capacitor, such as first columnar capacitor 30a, on transistor chain 2100, although this application is not limited thereto. In FIG8 , first columnar capacitor 30a and second columnar capacitor 30b are two adjacent columnar capacitors electrically connected to the same transistor chain 2100 shown in FIG7 .

[0095] As can be seen from the above, as shown in Figure 8, the two electrodes of a columnar capacitor, such as the first columnar capacitor 30a or the second columnar capacitor 30b (the first columnar electrode 301 and the second columnar electrode 302, respectively) are electrically connected to the first electrode (e.g., source S) or the second electrode (e.g., drain D) of a transistor T, respectively, to form a storage unit 210.

[0096] For example, as shown in FIG8 , the first columnar electrode 301 of the first columnar capacitor 30a can be electrically connected to the first pole (e.g., source S) of the transistor T. In some embodiments of the present application, the above-mentioned storage array 21 may further include a contact portion 211. The contact portion 211 may be arranged between the transistor chain 2100 shown in FIG7 and the capacitor array 300. Continuing with FIG8 , a contact portion 211 is electrically connected to a columnar capacitor, such as the electrode (e.g., first columnar electrode 301) of the first columnar capacitor 30a and the first pole (e.g., source S) of a transistor T, so that the first columnar electrode 301 of the first columnar capacitor 30a can be electrically connected to the first pole (e.g., source S) of the transistor T through the above-mentioned contact portion 211. In this way, through the contact portion, the electrode of the columnar capacitor 30 can be accurately electrically connected to the first pole or the second pole of the transistor T.

[0097] On this basis, in order to electrically connect the second columnar electrode 302 of the first columnar capacitor 30a to the second electrode (e.g., drain D) of the transistor T, and to connect two adjacent columnar capacitors 30 electrically connected to the same transistor chain 2100 in series, as shown in FIG7 , the memory array 21 may further include at least one electrical connection structure 40. The electrical connection structure 40 may be stacked on a side of the capacitor array 300 facing away from the transistor chain 2100. The electrodes of two adjacent columnar capacitors 30 electrically connected to the same transistor chain 2100 are electrically connected to both ends of the electrical connection structure 40, respectively, so that the two adjacent columnar capacitors 30 electrically connected to the same transistor chain 2100 are connected in series.

[0098] For example, as shown in FIG8 , the two ends of the electrical connection structure 40 can be electrically connected to the second columnar electrode 302 of the first columnar capacitor 30a and the first columnar electrode 301 of the second columnar capacitor 30b, respectively. Since the first columnar electrode 301 of the second columnar capacitor 30b is electrically connected to the second electrode (e.g., drain D) of the transistor T, the second columnar electrode 302 of the first columnar capacitor 30a can be indirectly electrically connected to the second electrode (e.g., drain D) of the transistor T through the electrical connection structure 40 and the first columnar electrode 301 of the second columnar capacitor 30b. Furthermore, the second columnar electrode 302 of the first columnar capacitor 30a is electrically connected to the first columnar electrode 301 of the second columnar capacitor 30b through the electrical connection structure 40, thereby electrically connecting adjacent first columnar capacitors 30a or second columnar capacitors 30 electrically connected to the same transistor chain 2100.

[0099] The above description uses the electrical connection between the first columnar capacitor 30a and the transistor T, and the electrical connection between the first columnar capacitor 30a or the second columnar capacitor 30 in FIG8 as examples to illustrate the connection between the columnar capacitors and the transistors, and the series connection between two adjacent columnar capacitors electrically connected in the same transistor chain 2100. The connection between the remaining columnar capacitors and the transistor T, and the series connection between the remaining adjacent columnar capacitors in the same transistor chain 2100, are similar to those described above and will not be further described here.

[0100] In summary, in the memory array 21 shown in FIG7 provided by the embodiment of the present application, the first pole (e.g., source S) or the second pole (e.g., drain D) of two adjacent transistors T is shared, and multiple transistors T can be connected in series to form the above-mentioned transistor chain 2100. In addition, the two electrodes of the columnar capacitor 30 (e.g., the first columnar electrode 301 and the second columnar electrode 302) are respectively electrically connected to the first pole (e.g., source S) or the second pole (e.g., drain D) of the same transistor T, so that a transistor T and a columnar capacitor 30 electrically connected to the first pole (e.g., source S) and the second pole (e.g., drain D) of the transistor T can constitute a memory cell 210. In this case, the above-mentioned transistor chain 2100 and the columnar capacitor 30 electrically connected to the transistor chain 2100 can constitute the above-mentioned chain storage architecture. Compared with the 1T1C structure adopted by traditional DRAM, the chain storage architecture has a more compact storage unit arrangement, which is conducive to reducing the size of the memory array and the memory having the memory array, so that the memory has high density and high speed characteristics.

[0101] Moreover, in the process of reading and writing data, the transistors in the storage cells used to participate in data reading and writing are in the on state, and the transistors in the storage cells not involved in data reading and writing are in the off state. In this case, there is a voltage drop across the transistors of the storage cells not involved in data reading and writing, which will cause crosstalk to the data stored in the storage cells not involved in data reading and writing. In comparison, in the process of reading and writing data, the transistors in the storage cells used to participate in data reading and writing are in the off state, and the transistors in the storage cells not involved in data reading and writing are in the on state. Therefore, there is almost no voltage drop across the transistors of the storage cells not involved in data reading and writing, which will not cause crosstalk to the data stored in the storage cells not involved in data reading and writing.

[0102] On this basis, as shown in FIG7 , relative to the planar capacitor (the plane where the capacitor electrode is located is parallel to the supporting surface of the substrate), within the same horizontal plane (for example, the supporting surface of the substrate of the storage capacitor), when the capacitance is the same, the area occupied by the columnar capacitor 30 is smaller than the area occupied by the planar capacitor, thereby helping to reduce the size of the storage unit 210 without affecting the capacity of the memory 20.

[0103] 8 , the vertical projection of a columnar capacitor (the first columnar capacitor 30 a or the second columnar capacitor 30 b ) on the transistor chain 2100 overlaps with the first electrode (e.g., source S) or the second electrode (e.g., drain D) of a transistor T. Furthermore, the electrical connection structure 40 for connecting two adjacent columnar capacitors (e.g., the first columnar capacitor 30 a and the second columnar capacitor 30 b ) in series in the chain storage architecture is disposed on the side of the capacitor array 300 facing away from the transistor chain 2100 as shown in FIG7 . This prevents the electrical connection structure 40 from occupying the spacing H between the two adjacent columnar capacitors (e.g., the first columnar capacitor 30 a and the second columnar capacitor 30 b ). This allows the spacing H between the two adjacent columnar capacitors (e.g., the first columnar capacitor 30 a and the second columnar capacitor 30 b ) to be the same as or approximately the same as the spacing between the first electrode (e.g., source S) and the second electrode (e.g., drain D) of the transistor T (twice the minimum semiconductor processing dimension F). In this way, the single side size of the memory cell 210 can reach 2F, so that the area of ​​the entire memory cell 210 can reach 4F. 2 , achieving the purpose of reducing the size of the storage unit 210, and further reducing the size of the storage array 21 and the memory 20 having the storage array 21.

[0104] The following describes an example of an electrical connection structure 40 for electrically connecting two adjacent columnar capacitors 30 in the same transistor chain 2100. In some embodiments of the present application, as shown in FIG8 , the memory array 21 may further include a first insulating layer 51 that covers the capacitor array 300 (as shown in FIG7 ). Furthermore, the electrical connection structure 40 may include a first via 401, a second via 402, and a first conductive portion 403.

[0105] Continuing with FIG8 , the first conductive via 401 can penetrate the first insulating layer 51, and the first end a1 of the first conductive via 401 can be electrically connected to the second columnar electrode 302 of the first columnar capacitor 30a. The second conductive via 402 penetrates the first insulating layer 51, and the first end a2 of the second conductive via 402 can be electrically connected to the first columnar electrode 301 of the second columnar capacitor 30b. In addition, the first conductive portion 403 is disposed on a side of the first insulating layer 51 facing away from the capacitor array 300 (as shown in FIG7 ), and the two ends of the first conductive portion 403 are electrically connected to the second end b1 of the first conductive via 401 and the second end b2 of the second conductive via 402, respectively.

[0106] In this case, the first conductive via 401 and the second conductive via 402 can be formed on the first insulating layer 51. For example, as shown in FIG9 (a top view taken along the direction A in FIG8 ), the vertical projection of the first conductive via 401 on the capacitor array 300 (as shown in FIG7 ) can overlap with at least a portion of the second columnar electrode 302 of the first columnar capacitor 30a, so that the first end a1 of the first conductive via 401 is electrically connected to the second columnar electrode 302 of the first columnar capacitor 30a.

[0107] Similarly, the vertical projection of the second via 402 on the capacitor array 300 (as shown in FIG7 ) can overlap with at least a portion of the first columnar electrode 301 of the second columnar capacitor 30b, thereby electrically connecting the first end a2 of the second via 402 to the first columnar electrode 301 of the second columnar capacitor 30b. Next, the first via 401 and the second via 402 are electrically connected via a first conductive portion 403 that spans over the first and second vias 401, 402. In this way, the second columnar electrode 302 of the first columnar capacitor 30a can be indirectly electrically connected to the first columnar electrode 301 of the second columnar capacitor 30b via the first via 401, the first conductive portion 403, and the second via 402, in sequence.

[0108] The following describes an example of a method for manufacturing the memory array 21 shown in FIG. 7 . In some embodiments of the present application, the method for manufacturing the memory array 21 may include steps S101 to S103 as shown in FIG. 10 .

[0109] S101. Prepare a transistor chain.

[0110] For example, as shown in (a) of FIG11 , at least a portion of a plurality of transistors T is formed in a substrate 200, that is, at least a portion of the transistors T is fabricated in the substrate 200. For example, a doping process may be used in the substrate 200 to form a first electrode (e.g., source S) and a second electrode (e.g., drain D) of the transistor T. The first electrode (e.g., source S) and the second electrode (e.g., drain D) are alternately arranged, so that the first electrode (e.g., source S) or the second electrode (e.g., drain D) of two adjacent transistors T are shared, thereby allowing the two adjacent transistors T to be connected in series to form a transistor chain 2100. In addition, on the substrate 200, a bit line BL, a contact portion 211, and a word line WL are fabricated at the position of the gate of the transistor T (or the word line WL is used as the gate of the transistor T).

[0111] At this time, at least a portion of the transistor T located within the substrate 200 may be the first electrode (e.g., source S) and the second electrode (e.g., drain D) of the transistor T. Alternatively, in other embodiments, the first electrode (e.g., source S), the second electrode (e.g., drain D) of the transistor T, and a word line WL serving as the gate of the transistor T may all be disposed within the substrate 200. In this case, the entire transistor T is located within the substrate 200. This solution will be explained in subsequent embodiments.

[0112] The present application does not limit the arrangement of the transistor T in the substrate 200. Furthermore, the arrangement of the transistor T in the substrate 200 is independent of the arrangement of the electrical connection structure 40 used to connect two adjacent columnar capacitors (e.g., the first columnar capacitor 30a and the second columnar capacitor 30b) in series in the chain storage architecture shown in FIG. 7 . In other words, the arrangement of the electrical connection structure 40 in the memory array 21 is not affected by the arrangement of the transistor T in the substrate 200.

[0113] S102. Prepare a capacitor array.

[0114] For example, as shown in FIG11( b ), a second insulating layer 52 is formed on a substrate 200, and a via 501 is formed in the second insulating layer 52. The position of a via 501 may correspond to the position of a first electrode (e.g., source S) or a second electrode (e.g., drain D) of a transistor T. That is, the vertical projection of the via 501 on the substrate 200 overlaps with the vertical projection of the first electrode (e.g., source S) or the second electrode (e.g., drain D) corresponding to the via 501 on the substrate 200. Furthermore, the via 501 may expose the first electrode (e.g., source S) or the second electrode (e.g., drain D) of the transistor T.

[0115] Next, as shown in FIG11( c ), a plurality of columnar capacitors 30 are formed within the via hole 501. For example, a first columnar electrode 301 can be formed within the via hole 501 using a thin film deposition method such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The first columnar electrode 301 can be electrically connected to a first electrode (e.g., source electrode S) or a second electrode (e.g., drain electrode D) corresponding to the position of the first columnar electrode 301.

[0116] Then, as shown in FIG11( c ), a dielectric layer 303 and a second columnar electrode 302 are sequentially formed within the first columnar electrode 301 using the thin film deposition process described above, such that the dielectric layer 303 is located between the first columnar electrode 301 and the second columnar electrode 302. Since the position of a via 501 can correspond to the first electrode (e.g., source S) or the second electrode (e.g., drain D) of a transistor T, the vertical projection of a columnar capacitor 30 on the transistor chain 2100 overlaps with the first electrode (e.g., source S) or the second electrode (e.g., drain D) of a transistor T. The two electrodes of the columnar capacitor 30 (e.g., first columnar electrode 301 and second columnar electrode 302) are electrically connected to the first electrode (e.g., source S) and the second electrode (e.g., drain D) of a transistor T, respectively, to form a memory cell 210.

[0117] S103: Prepare an electrical connection structure.

[0118] For example, as shown in (d) of FIG11 , a first insulating layer 51 and a plurality of first vias 401 and a plurality of second vias 402 are formed in the first insulating layer 51 on a side of the plurality of columnar capacitors 30 facing away from the transistor chain 2100. Adjacent first vias 401 and second vias 402 are electrically connected to the second columnar electrodes 302 and first columnar electrodes 301 of the adjacent columnar capacitors 30, respectively. Next, as shown in FIG8 , a first conductive portion 403 is formed on a side of the first via 401 and the second via 402 facing away from the substrate 200, and both ends of the first conductive portion 403 are electrically connected to the adjacent first via 401 and the second via 402, respectively.

[0119] In this way, the first conductive hole 401, the second conductive hole 402 and the first conductive portion 403 electrically connected to each other can form an electrical connection structure 40, and the two ends of the electrical connection structure 40 can be electrically connected to the second columnar electrode 302 of the adjacent first columnar capacitor 30a and the first columnar electrode 301 of the second columnar capacitor 30b, respectively, so that the two adjacent columnar capacitors electrically connected to the same transistor chain 2100 are electrically connected through the above-mentioned electrical connection structure 40.

[0120] The above is an example of the memory array 21 shown in FIG7 , in which the first electrode line, such as the word line WL, is arranged on the surface of the side of the substrate 200 facing the capacitor array 300. In other embodiments of the present application, as shown in FIG12 , the first electrode line, such as the word line WL, can be arranged in the substrate 200. In this case, since the first electrode line, such as the word line WL, is arranged at the gate of the transistor T and serves as the gate of the transistor T, when the word line WL is manufactured, the thickness of the word line WL can be increased along the thickness direction of the substrate 200, that is, the Z direction. In this way, the length of the channel between the first electrode (e.g., the source S) and the second electrode (e.g., the drain D) of the transistor T can be increased. Moreover, since the word line WL is located in the substrate 200, the size of the word line WL in the Z direction of the entire memory array 21 can be reduced.

[0121] Based on this, by increasing the length of the first electrode line, such as the word line WL, along the Z direction, the length of the gate of the transistor T along the Z direction can be increased. This can reduce the distance between the first electrode (e.g., source S) and the second electrode (e.g., drain D) of the transistor T while ensuring that the performance of the transistor T (e.g., channel length) remains unchanged, thereby facilitating a reduction in the size of the entire memory array 21 in the XY plane. Alternatively, by increasing the length of the first electrode line, such as the word line WL, along the Z direction, the length of the gate of the transistor T along the Z direction can be increased. This can increase the length of the channel of the transistor T while keeping the distance between the source and drain of the transistor T unchanged, further facilitating control of the on and off state of the transistor T.

[0122] In addition, for any of the memory arrays 21 shown in FIG7 or FIG12, in the memory array 21, as shown in FIG13A (a top view obtained along the B direction in FIG7 or FIG12), a plurality of columnar capacitors 30 electrically connected to at least two transistor chains 2100 can be arranged in a matrix. In this case, under the premise that the spacing h1 between two adjacent first electrode lines, such as word lines WL, meets the process requirements, such as the minimum processing size, the size of the columnar capacitor 30 in the XY plane can be reduced to reduce the spacing h2 between the columnar capacitors 30 electrically connected to the two adjacent transistor chains 2100. In this way, the arrangement of the memory cells in the memory array can be made more compact, so that the memory having the memory array has high-density characteristics.

[0123] Alternatively, in other embodiments of the present application, as shown in FIG13B (a top view obtained along the direction B in FIG7 or FIG12 ), the plurality of columnar capacitors 30 electrically connected to at least two transistor chains 2100 may be arranged in a honeycomb pattern. In this case, among two adjacent transistor chains 2100, the columnar capacitor 30 electrically connected to one transistor chain 2100 may be located between two adjacent columnar capacitors 30 electrically connected to the other transistor chain 2100, thereby making the arrangement of the plurality of transistor chains 2100 more compact. In addition, under the premise that the spacing h2 between the columnar capacitors 30 electrically connected to two adjacent transistor chains 2100 meets the process requirements, such as the minimum processing size, the size of the columnar capacitor 30 in the XY plane may be increased, which is beneficial to increasing the capacity of the memory array and the memory having the memory array.

[0124] The above description uses the example of the electrical connection structure 40 shown in FIG8 in the memory array 21, which includes a first conductive via 401, a second conductive via 402, and a first conductive portion 403, to illustrate the electrical connection method for two adjacent columnar capacitors 30 electrically connected to the same transistor chain 2100 in the memory array 21. In other embodiments of the present application, as shown in FIG14A , in either the first columnar capacitor 30a or the second columnar capacitor 30b, the second columnar electrode 302 extends outward from the first columnar electrode 301 toward one end of the electrical connection structure 40.

[0125] In addition, the memory array 21 may further include a first insulating layer 51 and a second insulating layer 52. The second insulating layer 52 is located on the side of the transistor chain 2100 facing away from the substrate 200, and the capacitor array 300 is embedded in the second insulating layer 52, and at least a portion of the second insulating layer 52 is provided between two adjacent columnar capacitors, such as the first columnar capacitor 30a and the second columnar capacitor 30b. The first insulating layer 51 is stacked on the side of the second insulating layer 52 facing away from the capacitor array 300 and covers the capacitor array 300. The material of the first insulating layer 51 and the material of the second insulating layer 52 may be the same or different, and this application does not limit this.

[0126] On this basis, as further shown in FIG. 14A , the electrical connection structure 40 may include a third via 404 and a second conductive portion 405. The third via 404 is disposed within the first insulating layer 51, and a first end a3 of the third via 404 is electrically connected to the first columnar electrode 301 of the second columnar capacitor 30b. A vertical projection of the third via 404 on the capacitor array 300 may overlap with at least a portion of the first columnar electrode 301 of the second columnar electrode 30b, such that the first end a3 of the third via 404 is electrically connected to the first columnar electrode 301 of the second columnar electrode 30b.

[0127] Furthermore, as shown in FIG14A , a second conductive portion 405 is disposed on a side of the first insulating layer 51 facing away from the capacitor array 300. The two ends of the second conductive portion 405 can be electrically connected to the end of the second columnar electrode 302 of the first columnar capacitor 30a that faces the electrical connection structure 40 and the second end b3 of the third conductive via 404, respectively. In this way, the second columnar electrode 302 of the first columnar capacitor 30a can be indirectly electrically connected to the first columnar electrode 301 of the second columnar capacitor 30b via the second conductive portion 405 and the third conductive via 404, respectively.

[0128] Furthermore, as shown in FIG14A , only one via, namely the third via 404, is provided between two adjacent columnar capacitors electrically connected to the same transistor chain 2100, for example, the first columnar capacitor 30a and the second columnar capacitor 30b. Therefore, the spacing between the two adjacent third vias 404 is relatively large, which reduces the precision requirements for the photolithography process used to fabricate the third vias 404, thereby simplifying the manufacturing process of the memory array and the memory. The photolithography process may include processes such as exposure, development, and etching for forming the film pattern.

[0129] As can be seen from the above, as shown in Figure 14A, in any one of the first columnar capacitor 30a and the second columnar capacitor 30b, the end of the second columnar electrode 302 facing the electrical connection structure 40 needs to extend out of the first columnar electrode 301 so as to be electrically connected to the second conductive portion 405. Based on this, as shown in Figure 14B, during the process of manufacturing the above-mentioned columnar capacitor 30, a hard mask 500 can be covered on the surface of the second columnar electrode 302 on the side facing away from the substrate 200. In this way, during the process of etching the first columnar electrode 301 in the direction indicated by the arrow through the etching process, the hard mask 500 can protect the second columnar electrode 302 from being etched, so that the second columnar electrode 302 can extend out of the first columnar electrode 301. After the first columnar electrode 301 is etched, the hard mask 500 can be removed. Alternatively, when the hard mask 500 is made of a conductive material, the hard mask 500 may be retained to serve as a portion of the second pillar-shaped electrode 302 , which is not limited in the present application.

[0130] In addition, the manufacturing method of other components in the memory array 21 shown in FIG14A can be obtained similarly to the manufacturing method of the memory array 21 shown in FIG7 , and will not be described again here.

[0131] Alternatively, in some other embodiments of the present application, in order to facilitate the electrical connection structure 40 to connect the first columnar capacitor 30a and the second columnar capacitor 30b in series, as shown in FIG15 , the memory array 21 may further include an electrical connection column 60. The electrical connection column 60 may be disposed in the second insulating layer 52, and the electrical connection column 60 may be located on the side of the third conductive hole 404 away from the second conductive portion 405. For example, as shown in FIG16A (a top view taken along the direction C in FIG15 ), there is a large gap between adjacent transistor chains 2100, so the electrical connection column 60 may be located between adjacent transistor chains 2100, thereby reducing the area of ​​the XY surface occupied by the electrical connection column 60.

[0132] In addition, the electrical connection pillar 60 can be electrically connected to the sidewall of the first pillar-shaped electrode 301 and the third conductive via 404. For example, as shown in FIG16B (a top view taken along the direction C in FIG15 ), after the electrical connection pillar 60 is formed, the third conductive via 404 can be formed so that the vertical projection of the third conductive via 404 on the substrate 200 (as shown in FIG15 ) can cover the vertical projection of the electrical connection pillar 60 on the substrate 200 (as shown in FIG15 ), so that the third conductive via 404 is electrically connected to the electrical connection pillar 60.

[0133] Next, as shown in FIG16C (a top view taken along line C in FIG15 ), the second conductive portion 405 is formed so that the second columnar electrode 302 of one of the two adjacent columnar capacitors 30 is indirectly electrically connected to the first columnar electrode 301 of the other columnar capacitor 30 via the second conductive portion 405, the third conductive via 404, and the electrical connection column 60. In this way, since the electrical connection column 60 is electrically connected to the sidewall of the first columnar electrode 301, the electrical connection column 60 increases the probability of electrical connection between the third conductive via 404 and the first columnar electrode 301, thereby ensuring the reliability of the electrical connection.

[0134] In addition, the manufacturing method of other components in the memory array 21 shown in FIG15 can be obtained similarly to the manufacturing method of the memory array 21 shown in FIG7 , and will not be described again here.

[0135] On this basis, FIG16C illustrates an example in which a plurality of columnar capacitors 30 electrically connected to at least two transistor chains 2100 in a memory array are arranged in a matrix. In other embodiments, as shown in FIG17 (a top view taken along the direction C in FIG15 ), the plurality of columnar capacitors 30 electrically connected to at least two transistor chains 2100 in a memory array can be arranged in a honeycomb pattern. The technical effects of the above-mentioned matrix and honeycomb arrangements are the same as those described above and will not be further elaborated here.

[0136] Furthermore, the above description is based on the example of the memory array 21 shown in FIG15 , in which the first electrode lines, such as word lines WL, are disposed on the surface of the substrate 200 facing the capacitor array 300. In other embodiments of the present application, as shown in FIG18 , the first electrode lines, such as word lines WL, may be disposed within the substrate 200. Furthermore, the first electrode lines, such as word lines WL, shown in FIG14A may also be disposed within the substrate 200. The technical effect of disposing the word lines WL within the substrate 200 is the same as described above and will not be further elaborated here.

[0137] The above description uses an example in which two adjacent columnar capacitors electrically connected to the same transistor chain 2100 are connected in series via the electrical connection structure 40. For example, the second columnar electrode 302 of the first columnar capacitor 30a is electrically connected to the first columnar electrode 301 of the second columnar capacitor 30b via the electrical connection structure 40, thereby electrically connecting the first columnar capacitor 30a and the second columnar capacitor 30b.

[0138] In other embodiments of the present application, to electrically connect the same transistor chain 2100, two adjacent columnar capacitors are connected in series via an electrical connection structure 40. As shown in FIG19 , in the memory array 21 described above, two adjacent columnar capacitors electrically connected to the same transistor chain 2100, such as a first columnar capacitor 30a and a second columnar capacitor 30b, have a first columnar electrode 301 of the first columnar capacitor 30a and a first columnar electrode 301 of the second columnar capacitor 30b connected to form an integral structural member 70. The adjacent integral structural members are the first integral structural member 70a and the second integral structural member 70b.

[0139] On this basis, as shown in FIG19 , the integrated structural member 70 is electrically connected to the first electrode (e.g., source S) of the transistor T at one end facing the transistor chain 2100, thereby electrically connecting one electrode of the transistor T used to constitute the above-mentioned storage unit, such as the source S, and one electrode of the columnar capacitor, such as the first columnar electrode 301.

[0140] In addition, a first blind hole 701, as shown in FIG20 , is defined on a side of the integral structural member 70 facing away from the transistor chain 2100. The second columnar electrode 302 of the second columnar capacitor 30b, as shown in FIG19 , is located within the first blind hole 701. Furthermore, as shown in FIG19 , the at least one electrical connection structure may include a first electrical connection structure 41.

[0141] Among the adjacent integral structural members, the second columnar electrode 302 of the second columnar capacitor 30b in the first integral structural member 70a and the second columnar electrode 302 of the first columnar capacitor 30a in the second integral structural member 70b are respectively electrically connected to both ends of the first electrical connection structure 41. The second columnar electrode 302 of the first columnar capacitor 30a passes through the second integral structural member 70b and is electrically connected to the second electrode (e.g., drain D) of the transistor T.

[0142] In this way, the other electrode of the transistor T constituting the memory cell, such as the drain D, can be electrically connected to the other electrode of the columnar capacitor, such as the second columnar electrode 302. Furthermore, two adjacent columnar capacitors electrically connected to the same transistor chain 2100 and having different integral structural members 70 can be connected in series via the first electrical connection structure 41.

[0143] In some embodiments of the present application, the structure of the first electrical connection structure 41 can be as shown in Figure 21. The first electrical connection structure 41 can include a fourth conductive hole 411, a fifth conductive hole 412, and a third conductive portion 413. Among them, the fourth conductive hole 411 passes through the first insulating layer 51, and the first end a4 of the fourth conductive hole 411 is electrically connected to the second columnar electrode 302 of the second columnar capacitor 30b in the first integral structure 70a. The fifth conductive hole 412 passes through the first insulating layer 51, and the first end a5 of the fifth conductive hole 412 is electrically connected to the second columnar electrode 302 of the first columnar capacitor 30a in the second integral structure 70b. In addition, the third conductive portion 413 can be arranged on the side of the first insulating layer 51 away from the capacitor array 300 (as shown in Figure 19), and the two ends of the third conductive portion 413 are electrically connected to the second end b4 of the fourth conductive hole 411 and the second end b5 of the fifth conductive hole 412, respectively.

[0144] In this way, in adjacent integral structural members, the second columnar electrode 302 of the second columnar capacitor 30b in the first integral structural member 70a can be electrically connected to the second columnar electrode 302 of the first columnar capacitor 30a in the second integral structural member 70b through the fourth conductive hole 411, the third conductive portion 413 and the fifth conductive hole 412 in sequence.

[0145] The following is an example of a method for manufacturing the storage array 21 shown in FIG19. For example, the manufacturing method may also include S101 to S103 as shown in FIG10. Among them, S101 is the same as described above and will not be repeated here. In the process of executing S102, as shown in (a) in FIG22, the first columnar electrode 301 of the first columnar capacitor 30a and the first columnar electrode 301 of the second columnar capacitor 30b are formed, and the first columnar electrode 301 of the first columnar capacitor 30a and the first columnar electrode 301 of the second columnar capacitor 30b are connected to form an integrated structural member 70.

[0146] For example, as shown in FIG19 , a via hole can be formed in the second insulating layer 52, and the via hole can expose the first electrode (e.g., source electrode S) of the transistor T. Then, through the same thin film deposition process described above, an integral structural member 70 is formed in the blind hole in the via hole, and the end of the integral structural member 70 facing the transistor chain 2100 is electrically connected to the first electrode (e.g., source electrode S) of the transistor T. A portion of the integral structural member 70 can serve as the first columnar electrode 301 of the first columnar capacitor 30a, and another portion can serve as the first columnar electrode 301 of the second columnar capacitor 30b.

[0147] Next, a through hole 711 (as shown in FIG. 20 ) is formed on the integral structural member 70 , penetrating the integral structural member 70 . The second columnar electrode 302 of the first columnar capacitor 30a , as shown in FIG. 22( b ), is formed within the through hole 711 , electrically connecting the second columnar electrode 3302 to the second electrode (e.g., drain D) of the transistor T. Furthermore, a first blind via 701 , as shown in FIG. 20 , is formed on a side of the integral structural member 70 facing away from the transistor chain 2100 . The second columnar electrode 302 of the second columnar capacitor 30b , as shown in FIG. 22( b ), is formed within the first blind via 701 .

[0148] Next, during the execution of S103, as shown in (b) of FIG22, at least a fourth conductive hole 411 and a fifth conductive hole 412 may be formed on a side of the plurality of columnar capacitors facing away from the transistor chain 2100 (as shown in FIG19), and a third conductive portion 413 as shown in FIG21 may be formed above the fourth conductive hole 411 and the fifth conductive hole 412 for electrically connecting the fourth conductive hole 411 and the fifth conductive hole 412. Continuing with FIG21, the first electrical connection structure 41 mainly composed of the fourth conductive hole 411, the fifth conductive hole 412, and the third conductive portion 413 is electrically connected at both ends to the second columnar electrode 301 of the second columnar capacitor 30b and the second columnar electrode 302 of the first columnar capacitor 30a in the adjacent integral structural member 70, respectively.

[0149] Based on this, as shown in FIG19 , the columnar capacitor electrically connected to the transistor T at the end or the beginning of the transistor chain 2100 may be a third columnar capacitor 30c. A second blind hole 702, as shown in FIG20 , is defined on the side of the third columnar capacitor 30c facing away from the transistor chain 2100. The second columnar electrode 302 of the third columnar capacitor 30c shown in FIG19 is located within the second blind hole 702.

[0150] Based on this, as shown in Figure 19, at least one electrical connection structure further includes a second electrical connection structure 42. The second columnar electrode 302 of the third columnar capacitor 30c and the second columnar electrode 302 of the adjacent first columnar capacitor 30a or second columnar capacitor 30b are respectively electrically connected to the two ends of the second electrical connection structure 42. In this way, the third columnar capacitor 30c can be electrically connected to the first columnar capacitor 30a or second columnar capacitor 30b adjacent to the third columnar capacitor 30c through the above-mentioned second electrical connection structure 42. The structure of the second electrical connection structure 42 can be obtained by the same logic as the structure of the first connection structure 41, and will not be repeated here.

[0151] The above description is based on the example of a memory array 21 shown in FIG19 , in which the first electrode lines, such as word lines WL, are disposed on the surface of the substrate 200 facing the capacitor array 300. In other embodiments of the present application, as shown in FIG23 , the first electrode lines, such as word lines WL, may be disposed within the substrate 200. The technical effect of disposing the word lines WL within the substrate 200 is the same as described above and will not be further elaborated here.

[0152] On this basis, FIG24A (a top view taken along the direction D in FIG19 ) illustrates an example in which a plurality of columnar capacitors 30 electrically connected to at least two transistor chains 2100 in a memory array are arranged in a matrix. In other embodiments, as shown in FIG24B (a top view taken along the direction D in FIG19 ), the plurality of columnar capacitors 30 electrically connected to at least two transistor chains 2100 in a memory array may be arranged in a honeycomb pattern. The technical effects of the above-mentioned matrix and honeycomb arrangements are the same as those described above and will not be further elaborated here.

[0153] The above description uses the example of the first electrical connection structure 41 shown in FIG. 21 in the memory array 21, including the fourth conductive via 411, the fifth conductive via 412, and the third conductive portion 413, to illustrate the electrical connection between two adjacent columnar capacitors in the memory array 21, which are electrically connected to the same transistor chain 2100 and do not have the same integral structural member 70. In other embodiments of the present application, as shown in FIG. 25 , in any columnar capacitor, the second columnar electrode 302 extends from the first columnar electrode 301 at one end facing away from the transistor chain 2100.

[0154] Based on this, the two ends of the first electrical connection structure 41 can be electrically connected to the ends of two adjacent second columnar electrodes 302 located in different integral structures 70, facing away from the transistor chain 2100. In this way, two adjacent columnar capacitors with different integral structures 70, such as the first columnar capacitor 30a and the second columnar capacitor 30b, can be connected in series via the first electrical connection structure 41.

[0155] Similarly, as shown in FIG. 25 , the second columnar electrode 302 of the third columnar capacitor 30c can extend beyond the first columnar electrode 301 of the third columnar capacitor 30c and can be electrically connected to the second columnar electrode 302 of the adjacent first columnar capacitor 30a or second columnar capacitor 30b extending beyond the first columnar electrode 301. In this case, the second electrical connection structure 42 can be electrically connected to the portion of the second columnar electrode 302 of the third columnar capacitor 30c extending beyond the first columnar electrode 301, as well as to the portion of the second columnar electrode 302 of the adjacent first columnar capacitor 30a or second columnar capacitor 30b extending beyond the first columnar electrode 301.

[0156] In this way, the first electrical connection structure 41 and the second electrical connection structure 42 can both be metal film layers made above the capacitor array 300, so there is no need to make conductive holes to connect adjacent columnar capacitors in series, thereby simplifying the manufacturing process of the storage array and the memory.

[0157] The arrangement of the columnar capacitors in the memory array 21 shown in FIG25 and the method for fabricating the memory array 21 are the same as those described above and will not be further described here. Furthermore, the first electrode lines, such as the word lines WL, shown in FIG25 may also be fabricated within the substrate 200. The beneficial effects of the above structure are the same as those described above and will not be further described here.

[0158] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that, include: substrate; at least two transistor chains, at least a portion of the transistor chains being disposed within the substrate, the transistor chains comprising a plurality of transistors connected in series; In the same transistor chain, the first electrode or the second electrode of two adjacent transistors is shared, so that the two adjacent transistors are connected in series; A capacitor array is stacked and arranged on a side of the transistor chain away from the substrate; the capacitor array comprises a plurality of columnar capacitors; a vertical projection of one of the columnar capacitors on the transistor chain at least partially overlaps with a first electrode or a second electrode of one of the transistors; Two electrodes of one of the columnar capacitors are electrically connected to a first electrode and a second electrode of one of the transistors, respectively, to form a storage unit; At least one electrical connection structure is stacked on a side of the capacitor array away from the transistor chain, and electrodes of two adjacent columnar capacitors electrically connected to the same transistor chain are respectively electrically connected to two ends of the electrical connection structure, so that the two adjacent columnar capacitors are connected in series through the electrical connection structure.

2. The storage array according to claim 1, characterized in that, The columnar capacitor comprises: A first columnar electrode, facing one end of the transistor chain and electrically connected to the first electrode or the second electrode of the transistor; a second columnar electrode, at least a portion of which is disposed within the first columnar electrode; a dielectric layer, at least a portion of which is disposed in the first columnar electrode, and the dielectric layer is located between the first columnar electrode and the second columnar electrode; Among them, the two adjacent columnar capacitors electrically connected to the same transistor chain are respectively a first columnar capacitor and a second columnar capacitor; and the two ends of the electrical connection structure are respectively electrically connected to the second columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor.

3. The storage array according to claim 2, characterized in that, The storage array further comprises a first insulating layer, wherein the first insulating layer covers the capacitor array; The electrical connection structure comprises: A first conductive hole, passing through the first insulating layer, wherein a first end of the first conductive hole is electrically connected to a second columnar electrode of the first columnar capacitor; a second conductive via hole penetrating through the first insulating layer, wherein a first end of the second conductive via hole is electrically connected to a first columnar electrode of the second columnar capacitor; The first conductive portion is disposed on a side of the first insulating layer away from the capacitor array, and two ends of the first conductive portion are electrically connected to the second end of the first conductive hole and the second end of the second conductive hole respectively.

4. The storage array according to claim 2, characterized in that, In any one of the first columnar capacitor and the second columnar capacitor, the second columnar electrode extends out of the first columnar electrode toward one end of the electrical connection structure; The storage array further comprises a first insulating layer, wherein the first insulating layer covers the capacitor array; The electrical connection structure comprises: a third conductive hole, penetrating through the first insulating layer; a first end of the third conductive hole is electrically connected to the first columnar electrode of the second columnar capacitor; The second conductive portion is arranged on a side of the first insulating layer away from the capacitor array, and two ends of the second conductive portion are respectively electrically connected to one end of the second columnar electrode of the first columnar capacitor facing the electrical connection structure and the second end of the third conductive hole.

5. The storage array according to claim 4, characterized in that, The storage array further comprises: A second insulating layer is disposed on a side of the transistor chain away from the substrate, and the capacitor array is embedded in the second insulating layer; An electrical connection post is disposed in the second insulating layer, and the electrical connection post is located on a side of the third via away from the second conduction portion; the electrical connection post is electrically connected to a sidewall of the first columnar electrode and the third via.

6. The storage array according to claim 2, characterized in that, The columnar capacitor includes: A first columnar electrode; A second columnar electrode, at least a part of which is disposed in the first columnar electrode; A dielectric layer, at least a part of which is disposed in the first columnar electrode, and the dielectric layer is located between the first columnar electrode and the second columnar electrode; Wherein, two adjacent columnar capacitors electrically connected to the same transistor chain are respectively a first columnar capacitor and a second columnar capacitor; the first columnar electrodes of the first columnar capacitor and the second columnar capacitor are connected to form an integral structural member; One end of the integral structural member facing the transistor chain is electrically connected to a first pole of the transistor; the second columnar electrode of the first columnar capacitor penetrates through the integral structural member and is electrically connected to a second pole of the transistor; A first blind hole is formed on a side of the integral structural member away from the transistor chain, and the second columnar electrode of the second columnar capacitor is located in the first blind hole; The at least one electrical connection structure includes a first electrical connection structure; in adjacent integral structural members, the second columnar electrodes of the second columnar capacitor and the first columnar capacitor are respectively electrically connected to two ends of the first electrical connection structure.

7. The storage array according to claim 6, wherein The storage array further includes a first insulating layer, and the first insulating layer covers the capacitor array; Adjacent integral structural members are respectively a first integral structural member and a second integral structural member, and the first electrical connection structure includes: A fourth via, penetrating through the first insulating layer, and a first end of the fourth via is electrically connected to the second columnar electrode of the second columnar capacitor in the first integral structural member; A fifth via, penetrating through the first insulating layer, and a first end of the fifth via is electrically connected to the second columnar electrode of the first columnar capacitor in the second integral structural member; A third conduction portion is disposed on a side of the first insulating layer away from the capacitor array, and two ends of the third conduction portion are respectively electrically connected to a second end of the fourth via and a second end of the fifth via.

8. The storage array according to claim 6, wherein In the columnar capacitor, one end of the second columnar electrode away from the transistor chain extends out of the first columnar electrode; The capacitor array includes a plurality of the integral structural members, and two ends of the first electrical connection structure are respectively electrically connected to one ends of two adjacent second columnar electrodes away from the transistor chain located in different integral structural members.

9. The storage array according to any one of claims 6-8, wherein In the transistor chain, the columnar capacitor electrically connected to the transistor at the end or the beginning is a third columnar capacitor; A second blind hole is formed on a side of the third columnar capacitor away from the transistor chain, and the second columnar electrode of the third columnar capacitor is located in the second blind hole; The at least one electrical connection structure further includes a second electrical connection structure; the second columnar electrode of the third columnar capacitor and the second columnar electrodes of the adjacent first columnar capacitor or the second columnar capacitor are respectively electrically connected to both ends of the second electrical connection structure.

10. The storage array according to any one of claims 2-9, wherein The dielectric layer includes a ferroelectric thin film layer or a resistive switching layer.

11. The storage array according to any one of claims 1-10, wherein The first pole or the second pole of the transistor is located within the range of the vertical projection of the columnar capacitor on the transistor chain.

12. The storage array according to any one of claims 1-11, wherein The first pole and the second pole of the transistor are disposed within the substrate; the memory array further includes: A first electrode line electrically connected to the gate of the transistor; the first electrode line is disposed on the surface of the substrate facing the capacitor array; or, the first electrode line is disposed within the substrate.

13. The storage array according to claim 12, wherein The memory array further includes: A second electrode line, and the first end of one transistor chain is electrically connected to one second electrode line; A third electrode line electrically connected to the second ends of the at least two transistor chains.

14. The storage array according to any one of claims 1-13, wherein The memory array further includes: A contact portion disposed between the transistor chain and the capacitor array, and one contact portion is electrically connected to an electrode of one columnar capacitor and the first pole or the second pole of one transistor.

15. The storage array according to any one of claims 1-14, wherein The multiple columnar capacitors electrically connected by the at least two transistor chains are arranged in a matrix; Or, The multiple columnar capacitors electrically connected by the at least two transistor chains are arranged in a honeycomb pattern.

16. A memory, wherein Including: The memory array according to any one of claims 1-15; A controller, the controller is electrically connected to the memory array, and the controller is used to control the reading and writing of the memory array.

17. An electronic device, characterized in that Including: A circuit board; The memory according to claim 16, and the circuit board is electrically connected to the memory.

18. A method for manufacturing a storage array, characterized in that Including: Forming at least a part of multiple transistors within the substrate, and the first pole or the second pole of two adjacent transistors are shared so that the two adjacent transistors are connected in series to form a transistor chain; Forming multiple columnar capacitors, and the vertical projection of one columnar capacitor on the transistor chain at least partially overlaps with the first pole or the second pole of one transistor; Electrically connecting the two electrodes of one columnar capacitor to the first pole and the second pole of one transistor respectively to form a memory cell; Forming at least one electrical connection structure on the side of the multiple columnar capacitors facing away from the transistor chain; Electrically connecting both ends of the electrical connection structure to the electrodes of two adjacent columnar capacitors electrically connected to the same transistor chain respectively, so that the two adjacent columnar capacitors are connected in series through the electrical connection structure.

19. The method for manufacturing a storage array according to claim 18, characterized in that Forming any one of the multiple columnar capacitors includes: Forming a first columnar electrode; Forming a dielectric layer within the first columnar electrode; Forming a second columnar electrode within the dielectric layer, and the dielectric layer is located between the first columnar electrode and the second columnar electrode; Two adjacent columnar capacitors electrically connected to the same transistor chain are respectively a first columnar capacitor and a second columnar capacitor; the forming of the electrical connection structure includes: Electrically connect two ends of the electrical connection structure to the second columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor, respectively.

20. The method for manufacturing a storage array according to claim 18, characterized in that Two adjacent columnar capacitors electrically connected to the same transistor chain are a first columnar capacitor and a second columnar capacitor, respectively. Forming the first columnar capacitor and the second columnar capacitor includes: Forming the first columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor, and connecting the first columnar electrode of the first columnar capacitor and the first columnar electrode of the second columnar capacitor into an integral structural member. Electrically connect one end of the integral structural member facing the transistor chain to the first pole of the transistor. Fabricate a through hole penetrating the integral structural member on the integral structural member, and form the second columnar electrode of the first columnar capacitor in the through hole, and electrically connect the second columnar electrode to the second pole of the transistor. Form a first blind hole on a side of the integral structural member facing away from the transistor chain, and form the second columnar electrode of the second columnar capacitor in the first blind hole. Forming at least one electrical connection structure includes: forming a first electrical connection structure on a side of the plurality of columnar capacitors facing away from the transistor chain, and electrically connecting two ends of the first electrical connection structure to the second columnar electrode of the second columnar capacitor and the second columnar electrode of the first columnar capacitor in adjacent integral structural members, respectively.

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