Dual conversion gain pixel unit and image sensor

Abstract

The present invention provides a dual conversion gain (DCG) pixel unit and an image sensor. The pixel unit comprises: a DCG transistor, a first floating diffusion node capacitor, and a second floating diffusion node capacitor, wherein the node capacitors comprise a junction capacitor and a metal capacitor. The DCG transistor and the second floating diffusion node junction capacitor are arranged in different regions. According to the present invention, the DCG transistor and the second floating diffusion node junction capacitor are arranged in different regions, that is, the second floating diffusion node junction capacitor is separately arranged. A layout design method for solving the problem of limited LCG values caused by small-size pixels limiting the areas of DCG junction capacitors is provided. The LCG value is effectively reduced while it is ensured that the HCG value is unchanged, the ratio of the HCG to the LCG is increased and the ratio can be adjusted according to requirements, thereby implementing reading of a higher FWC on the basis of a lower LCG, expanding a DR, and making SNR improvement possible.

Description

Dual conversion gain pixel unit and image sensor Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a dual-conversion-gain pixel unit and an image sensor. Background Art

[0002] As the application scope of image sensors expands, the market has increasingly higher requirements for image sensor resolution and size. Small-size, high-resolution pixels have become the mainstream demand.

[0003] The basic circuit of a 4T pixel unit in an image sensor is shown in Figure 1. The photodiode PD converts light signals into electrical signals, and the transfer transistor TX controls signal transmission. When the transfer transistor TX turns on, the signal charge is transferred to the floating diffusion node FD and converted into a voltage signal. The voltage signal is then amplified and output by the source follower transistor SF and the row select transistor RS, completing the conversion from light signal to charge signal to voltage signal. However, as pixel size decreases, the space left for the PD and FD also decreases, further reducing the pixel's full well capacity (FWC) and dynamic range (DR), resulting in a deterioration in the signal-to-noise ratio (SNR).

[0004] To improve FWC, DR, and SNR, and broaden the image sensor's light intensity application range and image quality, a dual conversion gain (DCG) transistor is added to the pixel circuit at the pixel level to provide the pixel with both high conversion gain (HCG) and low conversion gain (LCG) modes, thereby improving DR and FWC. The pixel circuit diagram is shown in Figure 2. The addition of the DCG transistor allows the pixel to flexibly switch the CG used depending on the lighting environment. It operates at a high CG in low illumination conditions requiring low dark noise, and at a low CG in high illumination conditions requiring high FWC. This achieves high FWC and effectively increases DR and improves SNR.

[0005] In DCG technology, the ratio of LCG to HCG is particularly important. The larger the ratio, the smaller the LCG is when operating under high illumination, the larger the FWC is used, and the larger the DR range is. CG is closely related to the capacitance value of the FD node: CG = q / C FD, when the additional FD capacitance that DCG can provide is larger, the ratio of HCG to LCG will be larger, which will also make the FWC and DR values ​​larger, and can also effectively improve the SNR, so that the sensor can output better quality and clearer images, increasing the linear FWC.

[0006] Generally, methods for increasing the capacitance of the FD node in LCG mode are as follows: 1) Increasing the junction capacitance provided by the DCG, including increasing the junction area, increasing the ion implant concentration, increasing the ion implant area, and increasing the ion implant energy; 2) Increasing the DCG FD2 metal capacitance, including using MOM capacitors and increasing the metal line area. However, these methods are limited in increasing the junction area for small-sized pixels, and it is impossible to increase the junction capacitance ion implant area, energy, and doping dose without affecting the DCG transistor. Summary of the Invention

[0007] The object of the present invention is to provide a dual conversion gain pixel unit and image sensor, which can solve the problem that small-size pixels limit the junction capacitance area and thus limit the LCG value, effectively reduce the LCG value while ensuring that the HCG value remains unchanged, and increase the ratio of HCG to LCG.

[0008] To solve the above technical problems, according to a first aspect of the present invention, a dual conversion gain pixel unit is provided, comprising: a dual conversion gain transistor, a first floating diffusion node capacitor, and a second floating diffusion node capacitor, wherein the first floating diffusion node capacitor comprises a first floating diffusion node junction capacitor and a first floating diffusion node metal capacitor, and the second floating diffusion node capacitor comprises a second floating diffusion node junction capacitor and a second floating diffusion node metal capacitor, wherein the dual conversion gain transistor and the second floating diffusion node junction capacitor are arranged in different areas.

[0009] Optionally, the source or drain of the dual conversion gain transistor is connected to the second floating diffusion node junction capacitor through a metal wire.

[0010] Optionally, the dual conversion gain transistor and the second floating diffusion node junction capacitor are arranged around the pixel unit.

[0011] Optionally, the pixel unit further includes a source follower transistor and a row selection transistor, and the source follower transistor and the row selection transistor are located at sides of the pixel unit.

[0012] Optionally, the source follower transistor includes a first source follower transistor and a second source follower transistor, the row selection transistor includes a first row selection transistor and a second row selection transistor, the gates of the first source follower transistor and the second source follower transistor are connected to a first floating diffusion node through a metal line; the gates of the first row selection transistor and the second row selection transistor are connected through a metal line; wherein the first floating diffusion node is a node corresponding to the first floating diffusion node capacitance.

[0013] Optionally, the pixel unit further includes a reset transistor, the source of the reset transistor and the drain of the dual conversion gain transistor are connected to the first floating diffusion node; or, the source of the reset transistor is connected to the drain of the dual conversion gain transistor, and the source of the dual conversion gain transistor is connected to the first floating diffusion node.

[0014] Optionally, the drain of the reset transistor, the drain of the first source follower transistor, and the drain of the second source follower transistor are connected to a power supply voltage.

[0015] Optionally, the source of the first row selection transistor is connected to the source of the second row selection transistor and serves as an output end; the source of the first source follower transistor is connected to the drain of the first row selection transistor, and the source of the second source follower transistor is connected to the drain of the second row selection transistor.

[0016] Optionally, the second floating diffusion nodes in the pixel units of every two adjacent rows are connected via a metal line, wherein the second floating diffusion node is a node corresponding to the second floating diffusion node capacitance.

[0017] To solve the above technical problem, according to a second aspect of the present invention, an image sensor is further provided, comprising a pixel array composed of a plurality of pixel units arranged in rows and columns, wherein the pixel units include the dual conversion gain pixel units described above.

[0018] In summary, in the dual-conversion-gain pixel unit and image sensor provided by the present invention, the dual-conversion-gain transistor and the second floating diffusion node junction capacitor are disposed in different regions, i.e., the second floating diffusion node junction capacitor is disposed separately. This provides a layout design method for addressing the problem of small-size pixels limiting the DCG junction capacitor area, and thus the LCG value. While maintaining the HCG value unchanged, the LCG value is effectively reduced, the HCG to LCG ratio is increased, and this value is adjustable as needed. This allows for a higher FWC readout at a lower LCG, improving the DR range and potentially improving the SNR. Furthermore, because the dual-conversion-gain transistor and the second floating diffusion node junction capacitor are disposed separately, the junction capacitor size and ion implantation conditions can be adjusted as needed, thereby achieving adjustable DCG ratios. This maximizes the layout of the second floating diffusion node junction capacitor region. Furthermore, by modifying the metal line routing, the MOM capacitance of the second floating diffusion node can be increased, thereby further increasing the total FD node capacitance in the low CG mode, thereby maximizing the CG ratio without reducing the HCG value.

[0019] Furthermore, the second floating diffusion nodes in the pixel units of every two adjacent rows are connected by metal lines, which can minimize the LCG value in the low CG mode without increasing the area of ​​the junction capacitance of the second floating diffusion node. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1 is a schematic diagram of a 4T pixel unit circuit of an image sensor in the prior art.

[0021] FIG. 2 is a schematic diagram of a pixel unit circuit including a DCG transistor of an image sensor in the prior art.

[0022] FIG3 is a layout design diagram of a dual conversion gain pixel unit.

[0023] FIG4 is a circuit diagram of a dual-conversion-gain pixel unit.

[0024] FIG5 is a layout design diagram of a dual conversion gain pixel unit provided by an embodiment of the present invention.

[0025] FIG6 is a circuit diagram of a dual-conversion-gain pixel unit according to an embodiment of the present invention.

[0026] FIG. 7 a is a side view illustrating the connection relationship between the dual conversion gain transistor and the second floating diffusion node junction capacitance.

[0027] FIG. 7 b is a top view of the connection relationship between the dual conversion gain transistor and the second floating diffusion node junction capacitor.

[0028] FIG8 a is a schematic diagram of the motion trajectory of electrons in the HCG mode provided by an embodiment of the present invention.

[0029] FIG8 b is a schematic diagram of the motion trajectory of electrons in the LCG mode provided by an embodiment of the present invention.

[0030] FIG9 is a layout design diagram of a dual conversion gain pixel unit provided by another embodiment of the present invention.

[0031] FIG10 is a circuit diagram of a dual conversion gain pixel unit provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0032] Figure 3 is a layout design diagram of a dual-conversion-gain pixel unit, and Figure 4 is a circuit diagram of the dual-conversion-gain pixel unit. Referring to Figures 3 and 4, using a 2x4 shared DCG pixel as an example, the dual-conversion-gain pixel unit includes a dual-conversion-gain transistor DCG, a reset transistor RST, a source-follower transistor SF, a row-select transistor RS, a first floating diffusion node FD1 capacitor, and a second floating diffusion node FD2 capacitor. The second floating diffusion node FD2 capacitor comprises the second floating diffusion node junction capacitance and the second floating diffusion node metal capacitance. Of course, the first floating diffusion node FD1 capacitor also comprises the first floating diffusion node junction capacitance and the first floating diffusion node metal capacitance. In Figure 3, FD1 is located at the first floating diffusion node junction capacitance, and FD2 is located at the second floating diffusion node junction capacitance. The second floating diffusion node metal capacitance is not shown in the figure. In Figure 4, the first floating diffusion node FD1 corresponds to the first floating diffusion node capacitance, and the second floating diffusion node FD2 corresponds to the second floating diffusion node capacitance.

[0033] In this embodiment, please refer to Figure 3, the reset transistor RST, the dual conversion gain transistor DCG and the second floating diffusion node FD2 junction capacitor are located on one side of the pixel unit, and the source or drain of the dual conversion gain transistor DCG is connected to the second floating diffusion node FD2 junction capacitor.

[0034] The drain or source of the dual conversion gain transistor DCG, the source of the reset transistor RST, and the gate of the source follower transistor SF are connected to the first floating diffusion node FD1. The drain of the reset transistor RST and the drain of the source follower transistor SF are connected to the power supply voltage VDD. The source of the source follower transistor SF is connected to the drain of the row select transistor RS, and the source of the row select transistor RS serves as the output terminal Vout.

[0035] The dual conversion gain pixel unit also includes 8 photodiodes PD (PD1, PD2, ..., PD8) and 8 transfer transistors TX (TX1, TX2, ..., TX8). The photodiodes PD correspond to the transfer transistors TX one by one. For example, the cathode of the first photodiode PD1 is connected to the source of the first transfer transistor TX1, and the drain of the first transfer transistor TX1 is connected to the first floating diffusion node FD1.

[0036] With respect to the dual conversion gain pixel units shown in FIG3 and FIG4 , the present invention provides a dual conversion gain pixel unit. Based on FIG3 and FIG4 , the dual conversion gain transistor and the second floating diffusion node junction capacitor are separated and arranged in different regions.

[0037] Specifically, the present invention provides a dual conversion gain pixel unit, including: a dual conversion gain transistor, a first floating diffusion node capacitor and a second floating diffusion node capacitor, the node capacitor includes a junction capacitor and a metal capacitor, wherein the dual conversion gain transistor and the second floating diffusion node junction capacitor are arranged in different areas.

[0038] The present invention places the dual-conversion gain transistor and the second floating diffusion node junction capacitor in separate regions, i.e., independently placing the second floating diffusion node junction capacitor. This design method addresses the issue of small-size pixels limiting the DCG junction capacitor area, and thus the LCG value. While maintaining the HCG value unchanged, the LCG value is effectively reduced, the HCG to LCG ratio is increased, and this value is adjustable as needed. This allows for a higher FWC readout at a lower LCG, improving the DR range and potentially improving the SNR. Furthermore, because the dual-conversion gain transistor and the second floating diffusion node junction capacitor are separately placed, the junction capacitor size and ion implantation conditions can be adjusted as needed, thereby achieving an adjustable DCG ratio and maximizing the layout of the second floating diffusion node junction capacitor area. Furthermore, by modifying the metal line routing, the MOM capacitance of the second floating diffusion node can be increased, further increasing the total FD node capacitance in low CG mode, thereby maximizing the CG ratio without reducing the HCG value.

[0039] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0040] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense including "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense including "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense including "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0041] In the dual conversion gain pixel unit provided in an embodiment of the present application, the dual conversion gain pixel unit includes: a dual conversion gain transistor, a first floating diffusion node capacitor, and a second floating diffusion node capacitor, the node capacitor includes a junction capacitor and a metal capacitor, wherein the dual conversion gain transistor and the second floating diffusion node junction capacitor are arranged in different areas.

[0042] In one embodiment of the present invention, a source or a drain of the dual conversion gain transistor is connected to the second floating diffusion node junction capacitor via a metal wire.

[0043] In one embodiment of the present invention, the dual conversion gain transistor and the second floating diffusion node junction capacitor are disposed around the pixel unit, for example, on two opposite sides of the pixel unit.

[0044] In one embodiment of the present invention, the pixel unit further includes a source follower transistor and a row select transistor, and the source follower transistor and the row select transistor are located at sides of the pixel unit.

[0045] In this embodiment, the dual conversion gain transistor and the second floating diffusion node junction capacitor are separated and positioned in different areas. This separate arrangement of the second floating diffusion node junction capacitor provides a layout design method that addresses the issue of small-size pixels limiting the DCG junction capacitor area, and thus the LCG value. This effectively reduces the LCG value while maintaining the HCG value constant, increasing the HCG to LCG ratio and making this value adjustable as needed. This allows for a higher FWC readout at a lower LCG, improving the DR range and potentially improving the SNR. Furthermore, since the dual conversion gain transistor and the second floating diffusion node junction capacitor are separated, the junction capacitor size and ion implantation conditions can be adjusted as needed, achieving adjustable DCG ratios. This also maximizes the layout of the second floating diffusion node junction capacitor area. Furthermore, by modifying the metal line routing, the MOM capacitance of the second floating diffusion node FD2 can be increased, further increasing the total FD node capacitance in low CG mode, thereby maximizing the CG ratio without reducing the HCG value.

[0046] The following also uses 2x4 shared DCG pixels as an example for description, but is not limited to this.

[0047] Figure 5 is a layout design diagram of a dual-conversion-gain pixel unit according to an embodiment of the present invention, and Figure 6 is a circuit diagram of a dual-conversion-gain pixel unit according to an embodiment of the present invention. As shown in Figures 5 and 6, the dual-conversion-gain pixel unit includes a dual-conversion-gain transistor DCG, a first floating diffusion node FD1 capacitor, and a second floating diffusion node FD2 capacitor. Node capacitance includes junction capacitance and metal capacitance. The dual-conversion-gain transistor DCG and the second floating diffusion node FD2 junction capacitance are located in different regions.

[0048] The second floating diffusion node FD2 capacitance includes a second floating diffusion node junction capacitance and a second floating diffusion node metal capacitance. The first floating diffusion node FD1 capacitance also includes a first floating diffusion node junction capacitance and a first floating diffusion node metal capacitance. In Figure 5 , FD1 is located at the first floating diffusion node junction capacitance, and FD2 is located at the second floating diffusion node junction capacitance. The first floating diffusion node metal capacitance and the second floating diffusion node metal capacitance are only schematically illustrated in the figure. In Figure 6 , the first floating diffusion node capacitance corresponds to the first floating diffusion node FD1, and the second floating diffusion node capacitance corresponds to the second floating diffusion node FD2.

[0049] The source or drain of the dual conversion gain transistor DCG is connected to the second floating diffusion node FD2 junction capacitor via a metal line. Figure 7a is a side view of the connection relationship between the dual conversion gain transistor and the second floating diffusion node junction capacitor, and Figure 7b is a top view of the connection relationship between the dual conversion gain transistor and the second floating diffusion node junction capacitor. Referring to Figures 7a and 7b, the source or drain D / S of the dual conversion gain transistor DCG is connected to the second floating diffusion node FD2 junction capacitor via a metal line.

[0050] In this embodiment, the dual conversion gain transistor DCG and the second floating diffusion node FD2 junction capacitor can be disposed on opposite sides of the pixel unit. Continuing with Figures 5 and 6 , since this embodiment utilizes a 2x4 shared DCG pixel, the dual conversion gain transistor DCG and the second floating diffusion node FD2 junction capacitor are disposed on opposite sides of a group of photodiodes PD. Exemplarily, the second floating diffusion node FD2 junction capacitor is disposed on the top side of the group of photodiodes PD, while the dual conversion gain transistor DCG is disposed on the bottom side of the group of photodiodes PD.

[0051] The dual conversion gain pixel unit also includes a source follower transistor SF and a row selection transistor RS, and the source follower transistor SF and the row selection transistor RS are arranged on the side of the pixel unit. For example, the source follower transistor SF and the row selection transistor RS are arranged on the left side of a group of the photodiodes PD. In this embodiment, two source follower transistors SF and two row selection transistors RS are included, and one source follower transistor SF and one row selection transistor RS form a group arranged on the side of a group of the photodiodes PD. Compared with the dual conversion gain pixel unit shown in Figures 3 and 4, in this embodiment, the source follower transistor SF and the row selection transistor RS are arranged on the side of the pixel unit, so that the dual conversion gain transistor DCG and the second floating diffusion node FD2 junction capacitance can be arranged in different areas, for example, respectively on the opposite sides of the pixel unit (but not limited to this).

[0052] In this embodiment, the source follower transistor SF and the row select transistor RS are positioned on the side of the pixel unit, thereby making room for the junction capacitance between the dual conversion gain transistor DCG and the second floating diffusion node FD2. This allows for the separation of the dual conversion gain transistor DCG and the second floating diffusion node FD2 junction capacitance. A metal line then connects the source or drain of the dual conversion gain transistor DCG to the second floating diffusion node FD2 junction capacitance. In high CG mode, the dual conversion gain transistor DCG is turned off, and the pixel unit only uses the first floating diffusion node FD1 capacitance as the floating diffusion node FD capacitance. In low CG mode, the dual conversion gain transistor DCG is turned on to provide additional second floating diffusion node FD2 capacitance. In low CG mode, the FD node capacitance in low CG mode uses the FD1 node capacitance and the FD2 node capacitance to increase the FD capacitance value, thereby achieving a higher DCG ratio. At the same time, due to the space given up, the junction capacitance is newly designed to be separated from the dual conversion gain transistor DCG. The size of the junction capacitance and the ion implantation conditions can be adjusted as needed, thereby achieving adjustable DCG ratio. At the same time, the layout of the second floating diffusion node junction capacitance area can be maximized, and the MOM capacitance value of the second floating diffusion node FD2 (i.e., the metal capacitance value of the second floating diffusion node) can be increased by modifying the metal line layout, thereby further increasing the total capacitance value of the FD node in the low CG mode, thereby achieving maximization of the CG ratio without reducing the HCG value.

[0053] Continuing with reference to Figures 5 and 6, the dual-conversion-gain pixel unit further includes a reset transistor RST, which is disposed on the same side of the pixel unit as the dual-conversion-gain transistor DCG. The source follower transistor SF includes a first source follower transistor SF1 and a second source follower transistor SF2, and the row select transistor RS includes a first row select transistor RS1 and a second row select transistor RS2. The first source follower transistor SF1, the second source follower transistor SF2, the first row select transistor RS1, and the second row select transistor RS2 are disposed on the same side of the pixel unit. Exemplarily, the first source follower transistor SF1 and the first row select transistor RS1 are disposed on the side of the same group of photodiodes PD, and the second source follower transistor SF2 and the second row select transistor RS2 are disposed on the side of another group of photodiodes PD.

[0054] The gates of the first source follower transistor SF1 and the second source follower transistor SF2 are connected to the first floating diffusion node FD1 through a metal line; the gates of the first row selection transistor RS1 and the second row selection transistor RS2 are connected through a metal line.

[0055] In one embodiment of the present invention, the source of the reset transistor RST and the drain of the dual conversion gain transistor DCG are connected to the first floating diffusion node FD1 junction capacitance. In another embodiment of the present invention, the source of the reset transistor RST is connected to the drain of the dual conversion gain transistor DCG, and the source of the dual conversion gain transistor DCG is connected to the first floating diffusion node FD1 junction capacitance.

[0056] The drain of the reset transistor RST, the drain of the first source follower transistor SF1, and the drain of the second source follower transistor SF2 are connected to the power supply voltage VDD. The source of the first row select transistor RS1 and the source of the second row select transistor RS2 are connected to the output terminal Vout; the source of the first source follower transistor SF1 is connected to the drain of the first row select transistor RS1, and the source of the second source follower transistor SF2 is connected to the drain of the second row select transistor RS2.

[0057] In this embodiment, the dual-conversion-gain pixel unit includes eight photodiodes PD (respectively, PD1, PD2, ..., PD8) and eight transfer transistors TX (respectively, TX1, TX2, ..., TX8). The photodiodes PD correspond one to one with the transfer transistors TX. The cathode of each photodiode PD is connected to the source of the corresponding transfer transistor TX, and the drain of the transfer transistor TX is connected to the first floating diffusion node FD1. As shown in FIG6 , a group of four transfer transistors TX forms a ring, and the corresponding four photodiodes PD are grouped around the four transfer transistors TX (the group of photodiodes PD described above refers to the four photodiodes PD surrounding the four transfer transistors TX).

[0058] Figure 8a is a schematic diagram of the motion trajectory of electrons in the HCG mode provided by an embodiment of the present invention, and Figure 8b is a schematic diagram of the motion trajectory of electrons in the LCG mode provided by an embodiment of the present invention. Please refer to Figures 8a and 8b, the ordinate represents the voltage (the voltage increases in the direction of the arrow), the abscissa represents the position of each component in the pixel unit, and the upper figure in each figure represents the photodiode PD converting the light signal into an electrical signal, and the lower figure represents the start of electron transmission. The HCG and LCG modes are achieved by turning on / off the dual conversion gain transistor DCG. When the number of photogenerated electrons obtained at low illumination is small but low dark noise is required, the dual conversion gain transistor DCG is turned off to use the HCG mode. When TX is turned on, electrons flow from the PD area only to the FD1 capacitor area (as shown in Figure 8a). Under high illumination conditions where a large number of photogenerated electrons are generated and higher requirements are placed on FWC and DR, the dual conversion gain transistor DCG is turned on to use the LCG mode, and electrons flow from the PD region to the FD1 and FD2 regions (as shown in Figure 8b). The combined action of FD1 and FD2 increases the ability of the FD node to accommodate electrons, while also reducing the blooming (halo or highlight overflow) risk of the pixel unit and increasing the SNR. This allows the LCG value to be significantly reduced while increasing the CG ratio while keeping the HCG value unchanged.

[0059] In the dual-conversion-gain pixel cell provided in this embodiment, the dual-conversion-gain transistor DCG and the second floating diffusion node FD2 junction capacitor are located in separate areas, that is, the second floating diffusion node junction capacitor is separately arranged. This provides a layout design method that addresses the issue of small-size pixels limiting the DCG junction capacitor area, and thus the LCG value. While maintaining the HCG value unchanged, the LCG value is effectively reduced, the HCG to LCG ratio is increased, and this value is adjustable as needed. This allows for a higher FWC readout at a lower LCG, improving the DR range and potentially improving the SNR. Furthermore, because the dual-conversion-gain transistor DCG is separated from the second floating diffusion node FD2 junction capacitor, the junction capacitor size and ion implantation conditions can be adjusted as needed, thereby achieving an adjustable DCG ratio. This also maximizes the layout of the second floating diffusion node FD2 junction capacitor area. Furthermore, by modifying the metal line routing, the MOM capacitance of the second floating diffusion node FD2 can be increased, further increasing the total FD node capacitance in low CG mode, thereby maximizing the CG ratio without reducing the HCG value.

[0060] FIG9 is a layout design diagram of a dual-conversion-gain pixel cell according to another embodiment of the present invention, and FIG10 is a circuit diagram of a dual-conversion-gain pixel cell according to another embodiment of the present invention. Referring to FIG9 and FIG10 , this embodiment differs from the previous embodiment in that the second floating diffusion nodes FD2 in every two adjacent rows of pixel cells are connected by a metal line. Specifically, the second floating diffusion node FD2 in the pixel cells in row n (Row_n) is connected to the second floating diffusion node FD2 in the pixel cells in row n+1 (Row_n+1) by a metal line. Similarly, the second floating diffusion node FD2 in the pixel cells in row n+2 (Row_n+2) is connected to the second floating diffusion node FD2 in the pixel cells in row n+3 (Row_n+3) by a metal line, and so on. The second floating diffusion nodes in every two rows of pixel cells are connected by a metal line. This minimizes the LCG value in low CG mode without increasing the junction capacitance area of ​​the second floating diffusion node FD2.

[0061] Correspondingly, the present invention further provides an image sensor, comprising a pixel array composed of a plurality of pixel units arranged in rows and columns, wherein the pixel units include the dual conversion gain pixel units described above.

[0062] In summary, in the dual-conversion-gain pixel unit and image sensor provided by the present invention, the dual-conversion-gain transistor and the second floating diffusion node junction capacitor are disposed in different regions, i.e., the second floating diffusion node junction capacitor is disposed separately. This provides a layout design method for addressing the problem of small-size pixels limiting the DCG junction capacitor area, and thus the LCG value. While maintaining the HCG value unchanged, the LCG value is effectively reduced, the HCG to LCG ratio is increased, and this value is adjustable as needed. This allows for a higher FWC readout at a lower LCG, improving the DR range and potentially improving the SNR. Furthermore, because the dual-conversion-gain transistor and the second floating diffusion node junction capacitor are disposed separately, the junction capacitor size and ion implantation conditions can be adjusted as needed, thereby achieving adjustable DCG ratios. This maximizes the layout of the second floating diffusion node junction capacitor region. Furthermore, by modifying the metal line routing, the MOM capacitance of the second floating diffusion node can be increased, thereby further increasing the total FD node capacitance in the low CG mode, thereby maximizing the CG ratio without reducing the HCG value.

[0063] Furthermore, the second floating diffusion nodes in the pixel units of every two adjacent rows are connected by metal lines, which can minimize the LCG value in the low CG mode without increasing the area of ​​the second floating diffusion node junction capacitance.

[0064] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A dual conversion gain pixel unit, characterized in that: include: A dual conversion gain transistor, a first floating diffusion node capacitor and a second floating diffusion node capacitor, wherein the first floating diffusion node capacitor includes a first floating diffusion node junction capacitor and a first floating diffusion node metal capacitor, and the second floating diffusion node capacitor includes a second floating diffusion node junction capacitor and a second floating diffusion node metal capacitor, wherein the dual conversion gain transistor and the second floating diffusion node junction capacitor are arranged in different areas.

2. The dual conversion gain pixel unit according to claim 1, characterized in that: It also includes eight photodiodes and eight transfer transistors, wherein the photodiodes correspond to the transfer transistors one by one, the cathode of each photodiode is connected to the source of the corresponding transfer transistor, and the drain of the transfer transistor is connected to the first floating diffusion node junction capacitor; a group of four transfer transistors forms a ring, and a group of four corresponding photodiodes surrounds the four transfer transistors.

3. The dual conversion gain pixel unit according to claim 2, characterized in that: The dual conversion gain transistor and the second floating diffusion node junction capacitor are arranged on both sides of a group of the photodiodes.

4. The dual conversion gain pixel unit according to claim 1, characterized in that: A source or a drain of the dual conversion gain transistor is connected to the second floating diffusion node junction capacitor through a metal line.

5. The dual conversion gain pixel unit according to claim 1, characterized in that: The dual conversion gain transistor and the second floating diffusion node junction capacitor are arranged around the pixel unit.

6. The dual conversion gain pixel unit according to claim 2, characterized in that: The pixel unit further includes a source follower transistor and a row selection transistor, and the source follower transistor and the row selection transistor are located at the side of the pixel unit.

7. The dual conversion gain pixel unit according to claim 6, characterized in that: The source follower transistor includes a first source follower transistor and a second source follower transistor, the row selection transistor includes a first row selection transistor and a second row selection transistor, the gates of the first source follower transistor and the second source follower transistor are connected to a first floating diffusion node through a metal line; the gates of the first row selection transistor and the second row selection transistor are connected through a metal line; wherein the first floating diffusion node is a node corresponding to the first floating diffusion node capacitance.

8. The dual conversion gain pixel unit according to claim 7, characterized in that: The first source follower transistor and the first row selection transistor are disposed on a side of the same group of photodiodes, and the second source follower transistor and the second row selection transistor are disposed on a side of another group of photodiodes.

9. The dual conversion gain pixel unit according to claim 7, characterized in that: The pixel unit further includes a reset transistor, a source of the reset transistor and a drain of the dual conversion gain transistor being connected to the first floating diffusion node; or, a source of the reset transistor is connected to the drain of the dual conversion gain transistor, and a source of the dual conversion gain transistor is connected to the first floating diffusion node.

10. The dual conversion gain pixel unit according to claim 9, characterized in that: A drain of the reset transistor, a drain of the first source follower transistor, and a drain of the second source follower transistor are connected to a power supply voltage.

11. The dual conversion gain pixel unit according to claim 10, characterized in that: The source of the first row selection transistor is connected to the source of the second row selection transistor and serves as an output terminal; the source of the first source follower transistor is connected to the drain of the first row selection transistor, and the source of the second source follower transistor is connected to the drain of the second row selection transistor.

12. The dual conversion gain pixel unit according to any one of claims 1 to 11, characterized in that: The second floating diffusion nodes in the pixel units of every two adjacent rows are connected through a metal line, wherein the second floating diffusion node is a node corresponding to the second floating diffusion node capacitance.

13. An image sensor, characterized in that: The invention comprises a pixel array composed of a plurality of pixel units arranged in rows and columns, wherein the pixel units comprise the dual conversion gain pixel units as claimed in any one of claims 1 to 12.

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