Test tool and test method for interface of motherboard to be tested of server

Abstract

The present application relates to a test tool and test method for an interface of a motherboard to be tested of a server. The test tool for an interface of a motherboard to be tested of a server comprises a test tool, wherein the test tool comprises a tool core board, a Riser adapter card and an OCP adapter card. The Riser adapter card and the OCP adapter card each comprise a gold finger interface and a SlimSAS connector, and the Riser adapter card and the OCP adapter card are respectively used for transferring and transmitting signals of Riser interfaces and OCP interfaces on said motherboard to the tool core board. The tool core board, the Riser adapter card and the OCP adapter card are respectively connected to the corresponding interfaces on said motherboard by means of cables, so that the test of the interfaces on said motherboard can be realized.

Description

A server motherboard interface test tool and test method

[0001] Related applications

[0002] This application claims priority to the Chinese patent application filed on December 12, 2023, with application number 202311706672.X and entitled “A test tool and test method for the interface of a server motherboard to be tested,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present invention relates to the technical field of production testing of a server motherboard to be tested, and more particularly to an interface testing tool and a testing method for a server motherboard to be tested. Background Art

[0004] During server R&D and production, the server's motherboard (under test) is the core framework, carrying the interconnection functions of the central processing unit, memory, hard disk, and PCIe standard expansion cards. The reliability and stability of the server motherboard under test determines the reliability and stability of the entire server. To ensure stable and reliable server functions and performance, the functionality and correctness of the external interface signals of the server motherboard under test must be fully tested before production and installation.

[0005] How to solve the technical problem that technicians in this field need to solve during the production process of the server motherboard to be tested, ensure the correctness and integrity of the external interface signals of the motherboard to be tested through testing methods, improve production efficiency, and ensure that product quality meets the requirements. Summary of the Invention

[0006] In order to overcome the above-mentioned defects of the prior art, the present invention provides a server motherboard interface test tool, including a test tool, the test tool includes a tool core board, a riser adapter card and an OCP adapter card, the riser adapter card and the OCP adapter card both include a gold finger interface and a SlimSAS connector, the riser adapter card and the OCP adapter card are respectively used to transfer the riser interface and OCP interface signals on the motherboard to be tested to the tool core board, and the integrated circuit on the tool core board has:

[0007] PCIe Switch circuit used to test PCIe Lanes link signals in the SlimSAS interface, Riser interface, and OCP interface on the motherboard to be tested;

[0008] A power supply and ground test circuit for testing power supply signals and ground signals in an external interface on a motherboard to be tested;

[0009] CPLD circuit used to test the sideband signal and I2C interface signal of the external interface on the motherboard to be tested;

[0010] Clock test circuit for testing the 100MHz differential clock in the external interface of the motherboard to be tested;

[0011] UART serial port circuit used to connect to an external PC serial port, configure the firmware of the PCIe Switch chip, and read the test results of the PCIe link signal of the motherboard under test;

[0012] A power conversion circuit is used to convert the 12V power supply voltage obtained from the mainboard to be tested and supply power to the tooling core board.

[0013] The PCIe Switch circuit includes two PCIe Switch chips, namely PCIe Switch1 and PCIe Switch2.

[0014] The power and ground test circuit includes an I / O expander.

[0015] The clock test circuit includes an 8:1 differential multiplexer with a dual output buffer and a differential-to-single-ended output amplifier.

[0016] A server motherboard interface testing method is implemented based on the above-mentioned server motherboard interface testing tool. The specific testing steps include:

[0017] S1: Fix the tooling core board on the tooling fixture, and install the riser adapter card and OCP adapter card on the riser interface and OCP interface of the motherboard to be tested;

[0018] S2: Connect the mainboard to be tested, the Riser adapter card and the OCP adapter card to the cables on the tooling core board according to the topological relationship for implementing the interface test function of the mainboard to be tested, including: connecting the SlimSAS interface of the mainboard to be tested to the SlimSAS interface of the tooling core board, connecting the SlimSAS interface on the Riser adapter card to the SlimSAS interface on the tooling core board, connecting the SlimSAS interface on the OCP adapter card to the SlimSAS interface on the tooling core board, connecting the I2C interface cable of the mainboard to be tested to the wiring terminal on the tooling core board, connecting the Power interface cable of the mainboard to be tested to the wiring terminal on the tooling core board, and connecting the Power interface cable of the mainboard to be tested to the Power interface on the tooling core board;

[0019] S3: Turn on the power of the motherboard to be tested, and the motherboard to be tested starts to be powered on and waits for the POST self-test and PCIe bifurcation of the motherboard to be tested to be completed;

[0020] S4: Connect the GbE network port of the motherboard to be tested to the network port of the local PC, and use IPMI Command to open the NCSI sideband interface between the BMC management controller of the motherboard to be tested and the GbE network controller;

[0021] S5: Through the PXE function of the GbE network port of the motherboard under test, the functional test script in the local PC is loaded into the memory of the motherboard under test for execution. The functional test script uses the Chiplink Tool Command and OS Command to determine the connectivity and correctness of the PCIe Lanes link signal of each interface under test. At the same time, the IMPItool tool is used in conjunction with the IPMI Command to read and determine the connectivity and correctness of the signals of each interface on the motherboard under test through the I2C interface. After the test is completed, the test results are generated after the overall test is compared with the expected results.

[0022] S6: Check the test results of all signals of each interface on each motherboard to be tested, and determine the test results of each interface test item. If all test items of all interfaces are PASS, it means that the test has passed, and the signals of each interface on the motherboard to be tested are normal. If some test items of a certain interface on the motherboard to be tested are FAIL, it means that the test has failed, and there is an abnormality in the signal of the interface on the motherboard to be tested.

[0023] S7: Determine the abnormality of the external interfaces on the motherboard under test based on the test content corresponding to the FAIL item. The external interfaces include the SlimSAS interface, Riser interface, OCP interface, I2C interface, and power interface.

[0024] If the PCIe B / D / F Number displayed for a certain item is incorrect, the PCIe connection relationship corresponding to this B / D / F Number can be used to determine which PCIe Lanes link signal in the SlimSAS interface, Riser interface, or OCP interface of the motherboard under test is abnormal.

[0025] If a power and ground test shows an error, the corresponding relationship between the I / O expander pins and the test signals can be used to determine which power connector and external interface power signal on the motherboard under test is abnormal.

[0026] If the differential clock signal of a certain item is displayed incorrectly, the differential signal currently detected by the CPLD can be read based on I2C, and it can be determined which external interface differential clock signal of the motherboard under test is abnormal.

[0027] If the sideband signal of a certain item is displayed incorrectly, the I2C reads which sideband signal the CPLD is currently detecting, and can determine which external interface sideband signal of the motherboard under test is abnormal.

[0028] The specific test method of the power supply and ground test circuit includes:

[0029] Connect the power signal, ground signal, and I2C interface signal of the external interface on the motherboard to be tested to the tooling core board through cables;

[0030] Connect the 12V power supply signal and ground signal to the I / O expander after isolation and conversion;

[0031] The voltage of each port of the I / O expander is read through the I2C bus to determine whether the power signal and ground signal in the external interface of the motherboard under test are normal.

[0032] The specific testing method of the clock test circuit includes:

[0033] During the test, the CPLD is used to control the selection pins of the 8:1 differential multiplexer, and each differential clock signal to be tested is output in a time sequence according to the corresponding relationship of the multiple selection input truth table;

[0034] The output differential clock signal to be tested is converted into a single-ended signal by a differential-to-single-ended output amplifier and then input to the clock pin of the CPLD.

[0035] After frequency division, it is synchronized with the main clock of CPLD to generate synchronous clock, and then it is judged whether the rising edge of synchronous clock jumps;

[0036] If a jump occurs, the CPLD detects that the clock is normal and determines that the 100M differential clock is normal;

[0037] If no jump occurs, the CPLD detects the clock abnormality and determines that the 100M differential clock is abnormal.

[0038] The CPLD test tests the JATG signal, PERST signal, WAKE_N signal, PRSNT signal, and sideband signal in the SlimSAS interface, Riser interface, and OCP interface of the motherboard to be tested. The specific test method is as follows:

[0039] Read the level status of the sideband signal input to the CPLD pin, and compare the level status of the sideband signal input to the CPLD pin with the preset level threshold to determine whether it is normal;

[0040] If the level of the sideband signal input to the CPLD pin is within the preset level threshold, it is judged to be normal;

[0041] If the level of the sideband signal input to the CPLD pin exceeds or falls below the preset level threshold, it is judged as abnormal. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0043] FIG1 is a schematic diagram of the overall structure of the test tool of the present invention;

[0044] FIG2 is a schematic diagram of the connection between the tooling core board, the riser adapter card, the OCP adapter card and the external interface of the motherboard to be tested;

[0045] FIG3 is a functional schematic diagram of the tooling core board of the present invention;

[0046] FIG4 is a schematic diagram of the structure of a riser adapter card according to the present invention;

[0047] FIG5 is a schematic diagram of the structure of the OCP adapter card of the present invention;

[0048] FIG6 is a test flow chart of the present invention;

[0049] Description of the accompanying drawings: 1. Tooling fixture; 2. Tooling core board; 3. Riser adapter card; 4. OCP adapter card. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0051] The present invention provides a server motherboard interface test tool as shown in Figures 1-6, including a test tool for performing signal testing on the external interface of the server motherboard to be tested. The server motherboard to be tested is collectively referred to as the motherboard to be tested below. The test tool includes a tool core board 2, a riser adapter card 3 and an OCP adapter card 4. The integrated circuits on the tool core board 2 include a PCIe switch circuit, a power supply and ground test circuit, a CPLD circuit, a clock test circuit, a UART serial port circuit and a power conversion circuit. The integrated circuits on the tool core board 2 are electrically connected to a SlimSAS interface, an I2C interface and a power supply interface. In the test tool, the tool core board 2 is installed on a tool fixture 1. During testing, the motherboard to be tested can be placed on the tool fixture 1.

[0052] The external interfaces of the motherboard to be tested include SlimSAS interface, Riser card interface, OCP interface, I2C interface, and power interface. Each type of interface has multiple signals. It is inconvenient to directly test the external interface signals of the motherboard to be tested. Therefore, it is necessary to use different cables to introduce all the signals of the external interfaces of the motherboard to be tested into the tooling core board 2 to complete the test. Among them, the SlimSAS interface of the motherboard to be tested is a high-speed signal interface that can be directly introduced into the SlimSAS interface of the tooling core board through the SlimSAS cable;

[0053] As shown in Figure 3, the PCIe Switch circuit is used to test the PCIe Lanes link signals in the SlimSAS interface, Riser interface, and OCP interface on the motherboard under test; the power and ground test circuit is used to test the power signal and ground signal in the external interface of the motherboard under test; the CPLD circuit is used to test the sideband signal and I2C interface signal in the external interface of the motherboard under test; the clock test circuit is used to test the 100MHz differential clock in the external interface of the motherboard under test; the UART serial port circuit is used to connect to the computer serial port and read the test results of the PCIe link signal of the motherboard under test; the power conversion circuit is used to convert the 12V power supply from the motherboard under test into 5V, 3V3, 1V8 and 0, 9V voltages for use by other test circuits on the tooling board. The specific conversion voltage is set by those skilled in the art according to actual application requirements.

[0054] The PCIe Switch circuit has two PCIe Switch chips, PCIe Switch 1 and PCIe Switch 2. In this embodiment, the PCIe Switch chip uses PM8536B. Each chip has 96 PCIe Lanes and 48 Ports, corresponding to CPU 1 and CPU 2 in the test.

[0055] The x8 SlimSAS PCIe Lanes interface of CPU1 is connected to the x8 SlimSAS PCIe Lanes interface of PCIe Switch1. The x16 OCP PCIe Lanes interface of CPU1 is split into two x8 PCIe Lanes interfaces after passing through the OCP riser card and connected to the x8 SlimSAS PCIe Lanes interface of PCIe Switch1. The x32 Riser PCIe Lanes interface of CPU1 is split into four x8 PCIe Lanes interfaces after passing through the Riser riser card and connected to the x8 SlimSAS PCIe Lanes interface of PCIe Switch1. Similarly, the x8 SlimSAS PCIe Lanes interface of CPU2 is connected to the x8 SlimSAS PCIe Lanes interface of PCIe Switch2. The x32 Riser PCIe Lanes interface of CPU2 is split into four x8 PCIe Lanes interfaces after passing through the Riser riser card and connected to the x8 SlimSAS PCIe Lanes interface of PCIe Switch2.

[0056] It should be noted that the SlimSAS interfaces on the tooling core board 2 are all x8 PCIe, so the PCIe Port of the PCIe Switch chip needs to be allocated. Before testing, the firmware of the PCIe Switch chip is configured through the serial port circuit using a configuration tool. According to the physical connection relationship, the 64 PCIe Lanes of the PCIe Switch1 and PCIe Switch2 chips are configured as 8 upstream ports, each of which is x8 PCIe Lanes, connected to the x8 width SlimSAS interface. Since each upstream port of the PCIe Switch requires a corresponding downstream port, the remaining 32 PCIe Lanes of each chip of PCIe Switch1 and PCIe Switch2 need to be configured as 8 downstream ports, each of which is x4 PCIe Lanes. They are not physically connected and are used as downstream ports corresponding to the upstream ports.

[0057] In this embodiment, the functions of the power supply and ground test circuit are realized by multiple low-power I / O expanders with I2C buses. In this embodiment, PCA9535 is used on the tooling core board 2 to complete the judgment of voltage and ground signals. PCA9535 is a multifunctional chip with multiple functions and characteristics. Those skilled in the art can complete the design of voltage and ground signal judgment based on PCA9535.

[0058] The testing method of the power supply and ground test circuit is to first transmit the power supply signal, ground signal and I2C interface signal in the motherboard to be tested to the tooling core board 2 through a cable, and then connect the 12V power supply signal and ground signal to the I / O port of each PCA9535 after isolation and conversion. Among them, the normal 12V power supply signal is converted into a low voltage after MOSFET isolation and conversion, and the abnormal 12V power supply signal is converted into a 3.3V high voltage after MOSFET isolation and conversion. The normal ground signal is still a low voltage after voltage division conversion, and the abnormal ground signal is a 3.3V high voltage after voltage division conversion. Then, the voltage of each port of PCA9535 is read through the I2C bus to determine whether the power supply signal and ground signal in the external interface of the motherboard are normal.

[0059] The clock test circuit consists of an 8:1 differential multiplexer with dual output buffers and a differential-to-single-ended output amplifier. Since each SlimSAS interface on the motherboard under test has a 100MHz differential clock, and a differential-to-single-ended output amplifier can only detect one differential clock signal at a time, to reduce the number of differential-to-single-ended output amplifier chips, an 8:1 differential multiplexer is used on tooling core board 2 to select the differential clock signal of the SlimSAS interface of the motherboard under test.

[0060] During the test, the CPLD controls the three selection pins of the 8:1 differential multiplexer and outputs each differential clock signal to be tested in a time sequence according to the corresponding relationship in the multiplexer selection input truth table. The output differential clock signal to be tested is then converted to a single-ended signal by the differential-to-single-ended output amplifier and input to the clock pin of the CPLD. After frequency division, it is synchronized with the CPLD's master clock to generate a synchronous clock. The test then determines whether the rising edge of the synchronous clock jumps. If a jump occurs, the CPLD detects that the clock is normal, and thus determines that the 100M differential clock is normal. If no jump occurs, the CPLD detects that the clock is abnormal, and the 100M differential clock is abnormal.

[0061] Furthermore, in this embodiment, the CPLD is the control core of the entire tooling core board 2 and plays a key role. In addition to providing power-on reset and selecting control functions for the tooling core board 2, the CPLD test circuit is also used to test the sideband signals in the SlimSAS interface, Riser card interface, and OCP interface of the motherboard to be tested, such as JATG signal, PERST signal, WAKE_N signal, and PRSNT signal. These sideband signals are introduced from the external interface of the motherboard to be tested to the tooling core board 2 through a cable, and finally connected to the GPIO port of the CPLD. During the test, the level state of the sideband signal input to the CPLD pin is read through I2C to determine whether the signal currently being tested is normal.

[0062] The test method is as follows: read the level status of the sideband signal input to the CPLD pin, compare the level status of the sideband signal input to the CPLD pin with a preset level threshold to determine whether it is normal. The preset level threshold is obtained by a technician in this field based on test data. If the level status of the sideband signal input to the CPLD pin is within the preset level threshold, it is judged to be normal. If the level status of the sideband signal input to the CPLD pin exceeds or falls below the preset level threshold, it is judged to be abnormal. Under normal circumstances, the sideband signal should change within the expected level range, such as switching between a high level (usually VCC voltage) and a low level (usually GND voltage). Under abnormal circumstances, the sideband signal may be unstable, the level may exceed the expected range, or continue to remain at a certain level; check the signal source: ensure that the source of the sideband signal (such as a sensor, external device, etc.) is working properly and providing correct signals. If the signal source fails or provides incorrect signals, the sideband signal on the CPLD pin may be affected.

[0063] It is worth mentioning that since there are two PCIe Switch chips, there are also two UART serial port circuits, which are respectively led out from the serial port interfaces of PCIe Switch1 chip and PCIe Switch2 chip. After RS232 level conversion, they can be connected to the serial port of the computer through a three-core serial port cable. They are used to configure the firmware of the PCIe Switch chip and read the communication status of the PCIe Lanes signal. The configured firmware can be burned into the flash of the PCIe Switch through this serial port circuit, making the firmware update operation more convenient. The serial port circuit can also be used to obtain the current test PCIe Lanes connection status and communication information.

[0064] In addition, it should be noted that, in the present embodiment, tool core board 2 does not additionally configure power supply, all power supplies are taken from mainboard to be tested, based on power conversion circuit realization, power conversion circuit is connected to the power connector on mainboard to be tested by power line, obtain 12V voltage, convert voltage for all test circuits on tool core board 2 by power conversion circuit, power conversion circuit adopts a kind of step-down circuit, based on switch mode power supply (Switch Mode Power Supply, SMPS) technology, realize voltage conversion by controlling the switch state and duty cycle of switch element, relate to inductor, diode, capacitor, switch element, control circuit (such as PWM controller), 12V input voltage is connected to the input end of circuit, inductor and diode are connected into an inductor-diode (LC) filter, to smooth output voltage, switch element is connected in circuit, for controlling the flow of electric current.Switch element can control switch state and duty cycle by PWM controller, capacitor is connected to the output end of switch element, to further smooth output voltage, load is connected to the output end of circuit, specific circuit connection is known public technology, does not do too much elaboration at this.

[0065] As shown in Figures 2, 3 and 4, the Riser adapter card includes a gold finger and a SlimSAS connector. The gold finger is used to connect to the Riser interface on the motherboard to be tested. The Riser card interface signal is output from the SlimSAS connector through the gold finger, and then connected to the SlimSAS interface on the tooling core board 2 through a cable, which plays the role of signal transfer. Specifically, in this embodiment, the gold finger of the Riser adapter card adopts an x32 width gold finger interface and four x8 SlimSAS interfaces. The x32 width gold finger matches the Riser card interface of the motherboard to be tested, and the Riser card interface signal can be introduced into the x8 SlimSAS interface, and then transferred to the tooling core board 2 through the SlimSAS cable for testing.

[0066] As shown in Figures 2, 3 and 5, the OCP adapter card includes a gold finger and a SlimSAS connector. The gold finger is used to connect to the OCP interface on the motherboard to be tested. The OCP card interface signal is output from the SlimSAS connector through the gold finger, and then connected to the SlimSAS interface on the tooling core board 2 through a cable, thereby playing the role of signal transfer. Specifically, in this embodiment, the gold finger of the OCP adapter card adopts an x16 width gold finger and two x8 SlimSAS interfaces. The x16 width gold finger matches the OCP card interface of the motherboard to be tested, and is used to introduce the OCP card interface signal of the motherboard to be tested into the x8 SlimSAS interface, and then transfer it to the tooling core board 2 through the SlimSAS cable for testing.

[0067] It is worth mentioning that the SlimSAS connector is a high-density, small-size connector commonly used in high-speed data transmission and storage systems. It adopts the SlimSAS standard, has a 0.60mm pitch, and can provide high-speed signal transmission and reliable connection performance.

[0068] As shown in FIG6 , a method for testing the interface of a server motherboard to be tested is implemented based on the above-mentioned server motherboard interface testing tool. The specific testing steps include:

[0069] S1: Fix the tooling core board (2) on the tooling fixture (1), and simultaneously install the riser adapter card (3) and the OCP adapter card (4) on the riser interface and the OCP interface of the motherboard to be tested;

[0070] S2: According to the topological relationship for realizing the test function of the interface of the motherboard to be tested, the motherboard to be tested, the riser adapter card (3) and the OCP adapter card (4) are connected to the cables on the tooling core board (2), including: connecting the SlimSAS interface of the motherboard to be tested to the cable on the SlimSAS interface of the tooling core board (2), connecting the SlimSAS interface on the riser adapter card (3) to the cable on the SlimSAS interface of the tooling core board (2), connecting the SlimSAS interface on the OCP adapter card (4) to the cable on the SlimSAS interface of the tooling core board (2), connecting the I2C interface cable of the motherboard to be tested to the wiring terminal on the tooling core board (2), connecting the power interface cable of the motherboard to be tested to the wiring terminal on the tooling core board (2), and connecting the power interface cable of the motherboard to be tested to the power interface on the tooling core board (2);

[0071] S3: Turn on the power of the motherboard to be tested, and the motherboard to be tested starts to be powered on and waits for the POST self-test and PCIe bifurcation of the motherboard to be tested to be completed;

[0072] S4: Connect the GbE network port of the motherboard under test to the network port of the local PC. Use IPMI Command to open the NCSI sideband interface between the baseboard management controller (BMC) of the motherboard under test and the GbE network controller. IPMI Command is a set of commands used to remotely manage and control server platforms. It allows users to remotely monitor system health, obtain information, and perform various management tasks. IPMI Command commands can be executed using IPMI tools (such as IPMItool). Using IPMI commands makes it easy to manage and monitor servers.

[0073] S5: Through the PXE function of the GbE network port of the motherboard under test, the functional test script in the local PC is loaded into the memory of the motherboard under test for execution. The functional test script uses the Chiplink Tool Command and OS Command to determine the connectivity and correctness of the PCIe Lanes link signal of each interface under test. At the same time, the IMPItool tool is used in conjunction with the IPMI Command to read and determine the connectivity and correctness of the signals of each interface on the motherboard under test through the I2C interface. After the test is completed, the test results are generated after the overall test is compared with the expected results.

[0074] S6: Check the test results of all signals of each interface on each motherboard to be tested. Different interfaces have different signal types, such as PCIe, power, clock, sideband, I2C, etc. According to the output of the test script and test tool in step 5, judge the test results of each interface test item. If all test items of all interfaces are PASS, it means that the test has passed and the signals of each interface on the motherboard to be tested are normal. If some test items of a certain interface on the motherboard to be tested are FAIL, it means that the test has failed and the signal of the interface on the motherboard to be tested is abnormal.

[0075] S7: Determine the abnormality of the external interfaces on the motherboard under test based on the test content corresponding to the FAIL item. The external interfaces include the SlimSAS interface, Riser interface, OCP interface, I2C interface, and power interface.

[0076] It should be noted that, in this embodiment, if the PCIe B / D / F Number of a certain item is displayed incorrectly, based on the PCIe connection relationship corresponding to this B / D / FNumber, it can be determined which specific PCIe Lanes link signal in the SlimSAS interface, Riser interface, and OCP interface of the motherboard under test is abnormal; if the power and ground test display of a certain item is incorrect, based on the correspondence between the pins of the I / O expander and the test signal, it can be determined which power connector and external interface power signal of the motherboard under test are abnormal; if the differential clock signal of a certain item is displayed incorrectly, based on the I2C reading of which differential signal the current CPLD detects, it can be determined which external interface differential clock signal of the motherboard under test is abnormal; if the sideband signal of a certain item is displayed incorrectly, based on the I2C reading of which sideband signal the current CPLD detects, it can be determined which external interface sideband signal of the motherboard under test is abnormal.

[0077] The technical effects and advantages of the present invention are as follows:

[0078] 1. By concentrating the signal test of the external interface of the motherboard to be tested on the tooling core board, the signal test of the SlimSAS interface, power interface, I2C interface and OCP interface of the motherboard to be tested is performed using functional devices such as PCIe Switch, CPLD, PCA9535, and the interface test of the motherboard to be tested can be achieved by connecting the tooling core board, Riser adapter card and OCP adapter card to the corresponding interfaces on the motherboard to be tested through cables. This is low-cost and highly versatile.

[0079] 2. By using a simple, reliable and method to quickly and accurately determine the correctness and integrity of the external interface signals of the motherboard under test on the production line, the problem of complex operating procedures, low testing efficiency and high labor costs caused by the use of expensive components after connecting functional boards to form a complete link in the traditional method of testing the external interface of the motherboard under test is solved.

[0080] 3. The test method has low cost and high integration. It can be quickly deployed on the production line and used for repeated testing, which greatly improves production efficiency and ensures that product quality meets factory requirements.

[0081] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A server motherboard interface test tool, characterized in that: The invention comprises a test tool, wherein the test tool comprises a tool core board (2), a riser adapter card (3) and an OCP adapter card (4), wherein the riser adapter card (3) and the OCP adapter card (4) both comprise a gold finger interface and a SlimSAS connector, and the riser adapter card (3) and the OCP adapter card (4) are respectively used for transferring the riser interface and the OCP interface signals on the mainboard to be tested to the tool core board (2), and the integrated circuits on the tool core board (2) include: PCIe Switch circuit used to test PCIe Lanes link signals in SlimSAS interface, Riser interface, and OCP interface on the motherboard to be tested; A power supply and ground test circuit for testing power supply signals and ground signals in an external interface on a motherboard to be tested; CPLD circuit used for testing the sideband signal and I2C interface signal in the external interface of the motherboard to be tested; A clock test circuit for testing the 100MHz differential clock in the external interface of the motherboard to be tested; UART serial port circuit used to connect to an external PC serial port and configure the firmware of the PCIe Switch chip and read the test results of the PCIe link signal of the motherboard to be tested; A power conversion circuit is used for converting a 12V power supply voltage obtained from a mainboard to be tested and supplying power to a tooling core board (2).

2. A server motherboard interface test tool according to claim 1, characterized in that: The PCIe Switch circuit includes two PCIe Switch chips, namely PCIe Switch1 and PCIe Switch2. The power and ground test circuit includes an I / O expander. The clock test circuit includes an 8:1 differential multiplexer with dual output buffers and a differential to single-ended output amplifier.

3. A server motherboard interface testing method, which is implemented based on the server motherboard interface testing tooling according to any one of claims 1-2, characterized in that: The specific test steps include: S1: Fix the tooling core board (2) on the tooling fixture (1), and install the riser adapter card (3) and the OCP adapter card (4) on the riser interface and the OCP interface of the mainboard to be tested; S2: Connecting the mainboard to be tested, the riser adapter card (3) and the OCP adapter card (4) to the cables on the tooling core board (2) according to the topological relationship for realizing the interface test function of the mainboard to be tested, including: connecting the SlimSAS interface of the mainboard to be tested to the cable on the SlimSAS interface of the tooling core board (2), connecting the SlimSAS interface on the riser adapter card (3) to the cable on the SlimSAS interface of the tooling core board (2), connecting the SlimSAS interface on the OCP adapter card (4) to the cable on the SlimSAS interface of the tooling core board (2), connecting the I2C interface cable of the mainboard to be tested to the wiring terminal on the tooling core board (2), connecting the power supply Power interface cable of the mainboard to be tested to the wiring terminal on the tooling core board (2), and connecting the power supply Power interface cable of the mainboard to be tested to the power supply Power interface on the tooling core board (2); S3: Turn on the power of the motherboard to be tested, and the motherboard to be tested starts to be powered on and waits for the completion of the POST self-test and PCIe bifurcation of the motherboard to be tested; S4: Connect the GbE network port of the motherboard to be tested to the network port of the local PC, and use IPMI Command to open the NCSI sideband interface between the BMC management controller of the motherboard to be tested and the GbE network controller; S5: Through the PXE function of the GbE network port of the motherboard to be tested, the function test script in the local PC is loaded into the memory of the motherboard to be tested for execution. The function test script uses the Chiplink Tool Command and OS Command to determine the connectivity and correctness of the PCIe Lanes link signals of each interface to be tested. At the same time, the IMPItool tool is used in conjunction with the IPMI Command to read and determine the connectivity and correctness of the signals of each interface on the motherboard to be tested through the I2C interface. After the test is completed, the test results are generated after the overall test is compared with the expected results. S6: Check the test results of all signals of each interface on each motherboard to be tested, and determine the test results of each interface test item. If all test items of all interfaces are PASS, it means that the test is passed and the signals of each interface on the motherboard to be tested are normal. If some test items of a certain interface on the motherboard to be tested are FAIL, it means that the test is not passed and the signal of the interface on the motherboard to be tested is abnormal. S7: Determine the abnormal situation of the external interface on the tested motherboard according to the test content corresponding to the FAIL item. The external interfaces include SlimSAS interface, Riser interface, OCP interface, I2C interface and power interface.

4. A method for testing a server motherboard interface according to claim 3, characterized in that: If the PCIe B / D / F Number of a certain item is displayed incorrectly, based on the PCIe connection relationship corresponding to this B / D / F Number, it can be determined which PCIe Lanes link signal in the SlimSAS interface, Riser interface, and OCP interface of the motherboard to be tested is abnormal.

5. A method for testing the interface of a server motherboard to be tested according to claim 3, characterized in that: If a power and ground test shows an error, based on the correspondence between the I / O expander's pins and the test signals, it can be determined which power connector of the motherboard under test and the external interface power signal are abnormal.

6. A method for testing the interface of a server motherboard to be tested according to claim 3, characterized in that: If the differential clock signal of a certain item is displayed incorrectly, the differential signal currently detected by the CPLD can be read based on I2C, and it can be determined which external interface of the motherboard to be tested has the abnormal differential clock signal.

7. A server motherboard interface test tool and test method according to claim 3, characterized in that: If the sideband signal display of a certain item is incorrect, the I2C read can determine which sideband signal the current CPLD is detecting, and which external interface sideband signal of the motherboard to be tested is abnormal.

8. A method for testing the interface of a server motherboard to be tested according to claim 3, characterized in that: The specific test method of the power supply and ground test circuit includes: Connect the power signal and ground signal of the external interface and the I2C interface signal on the mainboard to be tested to the tooling core board (2) through cables; Connect the 12V power supply signal and ground signal to the I / O expander after isolation and conversion; The voltage of each port of the I / O expander is read through the I2C bus to determine whether the power signal and ground signal in the external interface of the motherboard to be tested are normal.

9. A method for testing the interface of a server motherboard to be tested according to claim 3, characterized in that: The specific testing method of the clock testing circuit includes: During the test, the CPLD is used to control the selection pins of the 8:1 differential multiplexer, and each differential clock signal to be tested is output in a time sequence according to the corresponding relationship of the multi-channel selection input truth table; The output differential clock signal to be tested is converted into a single-ended signal by a differential to single-ended output amplifier and then input to the clock pin of the CPLD; After frequency division, it is synchronized with the main clock of CPLD to generate a synchronous clock, and then it is determined whether the rising edge of the synchronous clock jumps; If a jump occurs, the CPLD detects that the clock is normal and determines that the 100M differential clock is normal; If no jump occurs, the CPLD detects that the clock is abnormal and determines that the 100M differential clock is abnormal.

10. A method for testing the interface of a server motherboard to be tested according to claim 3, characterized in that: CPLD tests the JATG signal, PERST signal, WAKE_N signal, PRSNT signal and sideband signal in the SlimSAS interface, Riser interface and OCP interface of the motherboard to be tested. The specific test method is as follows: Read the level state of the sideband signal input to the CPLD pin, and compare the level state of the sideband signal input to the CPLD pin with the preset level threshold to determine whether it is normal; If the level state of the sideband signal input to the CPLD pin is within the preset level threshold, it is judged to be normal; If the level state of the sideband signal input to the CPLD pin exceeds or is lower than the preset level threshold, it is judged as abnormal.

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