Instruction acquisition method, central processing unit, device, medium, and program product

Abstract

The present application relates to the field of processors, and discloses an instruction acquisition method, a central processing unit, a device, a medium, and a program product. The method comprises: acquiring a main path predicted for each branch instruction (310); on the basis of the magnitude relationship between the historical error prediction quantity of the main path for the same branch instruction and a confidence threshold, determining a confidence level of the main path corresponding to each branch instruction (320); determining a confidence level proportion (330), the confidence level proportion being the proportion of branch instructions corresponding to a first level in all instructions, and the first level being a confidence level in which the historical error prediction quantity is greater than the confidence threshold; and taking the confidence level proportion as an expected proportion to serve as a control objective, adjusting the confidence threshold (340). According to the method, the problem of the proportion of first branch instructions (branch instructions corresponding to a main path of which the confidence level is the first level) in all instructions being too large due to a fixed threshold being too small for different load programs can be avoided.

Description

Instruction acquisition method, central processing unit, device, medium and program product

[0001] This application claims priority to Chinese patent application number 202311733099.1, filed on December 15, 2023, entitled “Instruction Acquisition Method, Central Processing Unit, Device, Medium and Program Product,” the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of processors, and in particular to an instruction acquisition method, a central processing unit, a device, a medium, and a program product. Background Art

[0003] In the design of a central processing unit (CPU), the CPU's branch predictor predicts the subsequent execution path of a branch instruction. The subsequent execution path of a branch instruction corresponds to the instruction following the branch instruction. The CPU's instruction cache is used to cache the instruction following the branch instruction in advance, allowing the CPU to quickly retrieve the instruction from the instruction cache when executing the next instruction.

[0004] Related art introduces the concept of confidence classification, which is used to indicate the likelihood of a primary path prediction being accurate. A branch instruction corresponds to two candidate subsequent execution paths: the primary path is the path predicted to be executed among the two subsequent execution paths, and the secondary path is a subsequent execution path different from the primary path. Confidence classification includes a first classification and a second classification. Related art determines the confidence classification based on whether the value of a counter in a branch predictor is greater than a fixed threshold. In the first classification, a first caching method is used, which caches instructions based on the address of the primary path or the address of the secondary path. In the second classification, a second caching method is used, which caches instructions based on the address of the primary path.

[0005] However, a program's total instructions include branch instructions and other instructions. When the related art uses a fixed total instruction count for a program with varying numbers of branch instructions, the large number of branch instructions and a small fixed threshold can lead to a situation where the proportion of first branch instructions to the total number of instructions is too large. These first branch instructions correspond to the main path with a confidence classification of the first category. This situation can lead to an excessive number of instructions being cached, resulting in insufficient space in the instruction cache. Summary of the Invention

[0006] The present application provides an instruction acquisition method, a central processing unit, a device, a medium, and a program product. The technical solution at least includes:

[0007] According to one aspect of an embodiment of the present application, a method for obtaining an instruction is provided. The method is executed by a central processing unit and includes:

[0008] Obtain the main path predicted for each branch instruction. Each branch instruction corresponds to two candidate subsequent execution paths. The main path is the path predicted to be executed among the two subsequent execution paths.

[0009] Based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold, the confidence classification of the main path corresponding to each branch instruction is determined, and the confidence classification is used to indicate the likelihood classification of the main path prediction accuracy;

[0010] Determine a confidence classification ratio, where the confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, where the first classification is a confidence classification for which the number of historical mispredictions is greater than a confidence threshold;

[0011] The confidence classification ratio is taken as the expected ratio as the control target, and the confidence threshold is adjusted.

[0012] According to another aspect of an embodiment of the present application, a central processing unit is provided, the central processing unit comprising:

[0013] A branch predictor is used to obtain a predicted main path for each branch instruction. Each branch instruction corresponds to two candidate subsequent execution paths. The main path is the path predicted to be executed among the two subsequent execution paths.

[0014] A branch predictor is configured to determine a confidence classification for the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path for the same branch instruction and a confidence threshold. The confidence classification is used to indicate the likelihood that the prediction of the main path is accurate.

[0015] A branch predictor is used to determine a confidence classification ratio, where the confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, where the first classification is the confidence classification for which the number of historical mispredictions is greater than a confidence threshold;

[0016] The branch predictor is used to adjust the confidence threshold by taking the confidence classification ratio as the expected ratio as a control target.

[0017] According to another aspect of an embodiment of the present application, a computer device is provided, comprising: a processor and a memory, wherein at least one program is stored in the memory; the processor is configured to execute at least one program in the memory to implement the above-mentioned instruction acquisition method.

[0018] According to another aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one program is stored. The at least one program is loaded and executed by a processor to implement the above-mentioned instruction acquisition method.

[0019] According to another aspect of an embodiment of the present application, a computer program product or computer program is provided, which includes computer instructions, the computer instructions are stored in a computer-readable storage medium, a processor obtains the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to implement the instruction acquisition method as described above.

[0020] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0021] The method obtains a main path predicted for each branch instruction, each branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed in the two subsequent execution paths; based on the size between the number of historical erroneous predictions of the main path of the same branch instruction and the confidence threshold, the confidence classification of the main path corresponding to each branch instruction is determined, and the confidence classification is used to indicate the possibility classification of the accuracy of the prediction of the main path; the confidence classification ratio is determined, and the confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, and the first classification is the confidence classification with the number of historical erroneous predictions greater than the confidence threshold; the confidence threshold is adjusted with the confidence classification ratio as the expected ratio as the control target, which can avoid or reduce the problem that the fixed threshold is too small for different load programs, thereby resulting in the first branch instruction accounting for too large a proportion of the total instructions, and the first branch instruction is the branch instruction corresponding to the main path with the confidence classification of the first classification. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 shows a schematic diagram of a CPU provided by an exemplary embodiment of the present application;

[0023] FIG2 shows a schematic diagram of an instruction acquisition system provided by an exemplary embodiment of the present application;

[0024] FIG3 shows a flow chart of an instruction acquisition method provided by an exemplary embodiment of the present application;

[0025] FIG4 shows a flow chart of an instruction acquisition method provided by an exemplary embodiment of the present application;

[0026] FIG5 shows a flow chart of an instruction acquisition method provided by an exemplary embodiment of the present application;

[0027] FIG6 is a structural block diagram of a computer device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0028] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0029] It should be noted that the object information (including but not limited to object device information, object personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the object or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0030] It should be understood that although the terms first, second, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0031] The terminal devices involved in the embodiments of this application include but are not limited to mobile phones, computers, intelligent voice interaction devices, smart home appliances, vehicle terminals, aircraft, etc. The embodiments of this application can be applied to various scenarios, including but not limited to cloud technology, artificial intelligence, smart transportation, assisted driving, etc.

[0032] First, let me introduce the relevant contents of this application:

[0033] The Central Processing Unit (CPU) is one of the main components of a computer and its core component. The CPU's primary function is to interpret computer instructions and process data from computer software. The CPU is the core component in a computer responsible for reading, decoding, and executing instructions.

[0034] Instruction Fetch: Instruction fetch is when the CPU gets the next instruction to be executed from the instruction cache. During execution, the CPU needs to fetch the instruction from the instruction cache and then execute it.

[0035] Hit instruction: means that when the CPU needs to obtain a certain instruction, since the instruction or the address corresponding to the instruction has been stored in the instruction cache, the instruction can be found. Finding the instruction means the instruction is hit, and not finding the instruction means the instruction is missed.

[0036] Branch instruction: A type of instruction in a computer program that changes the flow of execution during the program. A branch instruction determines the next step in the program's execution based on whether a condition is met.

[0037] Branch Instruction Prediction: Branch instruction prediction refers to the CPU's prediction of the subsequent execution path when executing a branch instruction. Branch instruction prediction generally has two outcomes: taken and not taken. If the prediction is a taken, the CPU assumes the branch instruction will be executed and will jump to the target address to continue execution. If the prediction is not taken, the CPU assumes the branch instruction will not be executed and will continue executing the instruction following the branch instruction.

[0038] Main path / secondary path: A branch instruction corresponds to two candidate subsequent execution paths. The main path is the path predicted to be executed among the two subsequent execution paths, and the secondary path is a subsequent execution path different from the main path.

[0039] Confidence classification: Confidence classification is used to indicate the possibility classification of the accuracy of the prediction of the main path, including the first classification and the second classification. For example, the first classification indicates that the possibility of the accuracy of the prediction of the main path is low, and the second classification indicates that the possibility of the accuracy of the prediction of the main path is high.

[0040] In the design of the CPU, the branch predictor in the CPU is used to predict the subsequent execution path of the branch instruction. The subsequent execution path of the branch instruction corresponds to the next instruction of the branch instruction. The instruction cache in the CPU is used to obtain and store the next instruction of the branch instruction in advance, so that it can be quickly read from the instruction cache when executing the next instruction. If the CPU finds that there is an error in the subsequent execution path of the predicted branch instruction, it will clear the instruction and re-fetch it (re-fetch the next instruction to be executed). Re-fetching requires obtaining instructions from a cache lower than the instruction cache in the CPU, or even from memory outside the CPU, which will reduce the efficiency of obtaining instructions and affect the performance of the CPU.

[0041] In the related art, when the branch predictor in the CPU predicts the execution path of a branch instruction, since the branch instruction corresponds to two candidate subsequent execution paths, the address of the predicted execution path (primary path) is used as the prefetch address of the primary path, the prefetch address of the primary path is stored in the instruction cache, and the address of the subsequent execution path (secondary path) different from the primary path is used as the prefetch address of the secondary path, the prefetch address of the secondary path is stored in the instruction cache, and the instruction cache obtains the corresponding instructions according to the prefetch address of the primary path and the prefetch address of the secondary path. When the CPU re-fetches the instruction, it obtains the instruction corresponding to the prefetch address of the secondary path from the instruction cache to improve this problem. The confidence classification is used to indicate the possibility classification of the accuracy of the prediction of the primary path. The confidence classification includes a first classification and a second classification. The first classification indicates that the possibility of the accuracy of the prediction of the primary path is low, and the second classification indicates that the possibility of the accuracy of the prediction of the primary path is high. The related technology determines the confidence classification based on whether the value of the counter in the branch predictor is greater than a fixed threshold. Each counter is used to count the number of historical correct predictions of a single branch instruction. For example, when the value of the counter is greater than the fixed threshold, the confidence classification is the second classification. When the value of the counter is less than or equal to the fixed threshold, the confidence classification is the first classification.

[0042] In related technologies, there are two methods for expressing confidence classification:

[0043] Method 1: Confidence classification is represented according to the numerical value of the counter in the branch predictor.

[0044] The counter is used to count the number of historical correct predictions of branch instructions. The confidence classification of the branch instruction is confirmed by judging whether the value of the counter is greater than a fixed threshold. If the value of the counter is less than or equal to the fixed threshold, it means that the confidence classification is the first category.

[0045] Method 2: Confidence classification is expressed by calculating the misprediction rate of branch instructions.

[0046] The error counter counts the number of historical mispredictions of branch instructions, the correct counter counts the number of historical correct predictions of branch instructions, and the error counter is divided by the sum of the error and correct counters to obtain the error prediction rate. The error prediction rate is then compared with a fixed prediction rate threshold. If the error prediction rate is greater than the fixed prediction rate threshold, the confidence classification is the first classification.

[0047] However, the total number of instructions in a program includes branch instructions and other instructions. When the related technology has a fixed total number of instructions and faces a load program including a different number of branch instructions, since the confidence classification is determined based on a fixed threshold, it is possible that due to the large number of branch instructions and the small fixed threshold, the number of first branch instructions accounts for too large a proportion of the total number of instructions. The first branch instruction is the branch instruction corresponding to the main path with the confidence classification of the first classification. For example, the first load program includes 10 branch instructions and the second load program includes 50 branch instructions. Assuming the fixed threshold value is 3, there are 4 branch instructions corresponding to the main path with the confidence classification of the first classification in the first load program, then the prefetched addresses of the prefetched secondary paths correspond to 4 instructions. In the second load program, there are 20 branch instructions corresponding to the main path with the confidence classification of the first classification, then the prefetched addresses of the prefetched secondary paths correspond to 20 instructions. Compared with the first load program, the second load program has a larger proportion of the number of first branch instructions to the total number of instructions, and the number of instructions corresponding to the prefetched addresses of the prefetched secondary paths is also larger, which affects the performance of the CPU.

[0048] To address the above-mentioned issues, an embodiment of the present application provides an instruction acquisition method that can be applied to a processor, such as a CPU in a server or terminal device. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, but is not limited thereto. The terminal device can be an electronic device such as a personal computer (PC), a mobile phone, a tablet computer, an in-vehicle terminal (car computer), a wearable device, or the like.

[0049] Figure 1 shows a schematic diagram of a CPU 100 provided by an exemplary embodiment of the present application, wherein the CPU 100 includes at least one of the following: a branch predictor 110, an address selector 120, an instruction fetch queue 130, a prefetch queue 140, a first cache 150, a second cache 160, and a third cache 170.

[0050] In some embodiments, the branch predictor 110 includes a first storage unit 112, such as a branch target buffer (BTB). The first storage unit 112 is a storage unit for storing branch prediction information, and the branch prediction information includes a confidence classification of the main path. The first storage unit 112 includes multiple items (multiple branch prediction information), each item corresponding to a counter. For example, if the counter is a saturation counter, the number of bits occupied by the saturation counter is small, such as 3 bits. When the branch predictor makes an incorrect prediction, the value of the saturation counter of the corresponding item is increased by 1. When the saturation counter is saturated (equal to 7 in the case of 3 bits), it no longer increases.

[0051] In order to extend the service life of the saturation counter, when the total number of branch instruction mispredictions reaches a certain threshold, the values ​​of the saturation counters corresponding to all items are reduced by 1. For example, when the total number of branch instruction mispredictions reaches 32 times, the values ​​of the saturation counters corresponding to all items are reduced by 1. When the value of the saturation counter is 0, it will no longer decrease.

[0052] When the branch predictor 110 makes a prediction, if an item in the first storage unit 112 is hit, it is determined whether the value of the saturation counter corresponding to the hit item is greater than a preset confidence threshold. If it is greater than the confidence threshold, the confidence classification of the item is marked as the first classification (low confidence); if it is less than or equal to the confidence threshold, the confidence classification of the item is marked as the second classification (high confidence). For example, the confidence classification is represented by one bit, and when the bit value is 1, it indicates low confidence, and when the bit value is 0, it indicates high confidence; or when the bit value is 1, it indicates high confidence, and when the bit value is 0, it indicates low confidence. This embodiment of the present application is not limited to this.

[0053] In some embodiments, the branch predictor 110 predicts the subsequent execution path of the branch instruction to obtain a prediction result for the branch instruction. The branch instruction corresponds to two candidate subsequent execution paths, and the primary path is the path predicted to be executed among the two subsequent execution paths. The prediction result of the branch instruction carries the address of the primary path. The branch predictor 110 sends the address of the primary path to the instruction fetch queue 130, which is used to temporarily store the address of the primary path. When it is not the turn to execute the branch instruction, the instruction fetch queue 130 sends the address of the primary path as the prefetch address of the primary path to the first cache 150, which can be called an instruction cache.

[0054] In some embodiments, the prediction result of the branch instruction also carries the confidence classification of the main path. When the confidence classification of the main path is the first classification, it is necessary to select the address of the subsequent execution path different from the main path through the address selector 120 as the address of the secondary path and send it to the prefetch queue 140. The prefetch queue 140 can be called a secondary path prefetch queue, which is used to temporarily store the address of the secondary path. When it is not the turn to execute the branch instruction, the prefetch queue 140 sends the address of the secondary path as the prefetch address of the secondary path to the first cache 150. In the embodiment of the present application, the confidence classification is simply referred to as confidence, which is used to indicate the possibility classification of the accuracy of the prediction of the main path. The confidence classification includes a first classification and a second classification. The first classification indicates that the possibility of the accuracy of the prediction of the main path is low (low confidence), and the second classification indicates that the possibility of the accuracy of the prediction of the main path is high (high confidence).

[0055] In some embodiments, the instruction fetch queue 130 and the prefetch queue 140 send instruction requests to the corresponding caches respectively. The instruction requests include at least one of: instruction fetch requests, primary path prefetch requests, and secondary path prefetch requests. For example, the instruction fetch queue 130 sends the instruction fetch request to the first cache 150 and the second cache 160, the instruction fetch queue 130 sends the primary path prefetch request to the first cache 150, and the prefetch queue 140 sends the secondary path prefetch request to the first cache 150. The primary path prefetch request is used to request the prefetch of the instruction corresponding to the prefetch address of the primary path, and the secondary path prefetch request is used to request the prefetch of the instruction corresponding to the prefetch address of the secondary path. The three instruction requests carry corresponding request addresses respectively. The first cache 150 determines whether the instruction request is a hit by comparing the request address with the address stored in the first cache 150. If the request address matches the stored address, the instruction request is a hit; if the request address does not match the stored address, the instruction request is a miss.

[0056] In some embodiments, for missed instruction requests, a request to retrieve the instruction is made from the third cache 170. A missed instruction request includes at least one of an instruction fetch request, a primary path prefetch request, and a secondary path prefetch request. The third cache 170 is a lower-level cache of the first cache 150, for example, a cache lower than the instruction cache.

[0057] Based on the missed instruction request, third cache 170 returns the corresponding instruction to first cache 150 or second cache 160, respectively. The instruction includes at least one of the following: the instruction currently to be executed (the instruction fetch result), the instruction of the primary path (the instruction corresponding to the prefetch address of the primary path, i.e., the prefetch result of the primary path), and the instruction of the secondary path (the instruction corresponding to the prefetch address of the secondary path, i.e., the prefetch result of the secondary path). For example, third cache 170 returns the instruction currently to be executed or the instruction of the primary path to first cache 150, and returns the instruction of the secondary path to second cache 160.

[0058] FIG2 is a schematic diagram of an instruction fetch system 200 provided in an exemplary embodiment of the present application. In some embodiments, when the CPU does not include any caches other than the first cache 150 and the second cache 160, a missed instruction request requires a request to fetch the instruction from the memory 210. The missed instruction request includes at least one of an instruction fetch request, a primary path prefetch request, and a secondary path prefetch request.

[0059] Based on the missed instruction request, memory 210 returns the corresponding instruction to first cache 150 or second cache 160, respectively. The instruction includes at least one of the following: the instruction currently to be executed (the instruction fetch result), the instruction of the primary path (the instruction corresponding to the prefetch address of the primary path, i.e., the primary path prefetch result), and the instruction of the secondary path (the instruction corresponding to the prefetch address of the secondary path, i.e., the secondary path prefetch result). For example, memory 210 returns the instruction currently to be executed or the instruction of the primary path to first cache 150, and returns the instruction of the secondary path to second cache 160.

[0060] In some embodiments, when an instruction fetch request hits an instruction in the second cache 160 , ie, an instruction of the secondary path, the second cache 160 stores the instruction of the secondary path in the first cache 150 .

[0061] In some embodiments, the confidence threshold is dynamically adjusted for load programs including different numbers of branch instructions.

[0062] For different branch instructions, the confidence classification ratio is compared with the expected ratio. The confidence classification ratio is the ratio of branch instructions corresponding to the first category to the total instructions. For example, when the total number of instructions is 1000, a 10-bit threshold counter is used to accumulate and count the number of branch instructions whose confidence classification is the first category. The confidence classification ratio is the ratio of the value of the threshold counter to the total number of instructions. The expected ratio represents the expected confidence classification ratio.

[0063] When the confidence classification ratio is greater than the expected ratio, the confidence threshold is increased; when the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered.

[0064] In some embodiments, the confidence threshold can be changed based on a predetermined step size, or based on a dynamic step size determined by the difference between the confidence classification ratio and the expected ratio. For example, if the predetermined step size is 1, if the confidence classification ratio is greater than the expected ratio, the confidence threshold value is increased by 1, otherwise the confidence threshold value is decreased by 1. For example, if the expected ratio is 15%, the initial confidence threshold value is 4, and the total number of instructions is 1000, the threshold counter value is 100, the confidence classification ratio is 10%, which is less than 15%, so the confidence threshold value is adjusted to 3.

[0065] The counter used to represent the confidence threshold is also a saturated counter. When occupying 3 bits, the saturated counter will not decrease after the value is 0, and will not increase after saturation (the value is 7).

[0066] In summary, the method provided in this embodiment, by adjusting the confidence threshold using the confidence classification ratio as the desired ratio as the control target, can avoid or reduce the problem of the fixed confidence threshold being too large or too small for different load programs, thereby resulting in an unreasonable ratio of the number of first branch instructions to the total number of instructions. The first branch instruction is the branch instruction corresponding to the main path with the confidence classification of the first category;

[0067] The method provided in this embodiment also adds a second cache for storing instructions corresponding to the prefetch address of the secondary path. When the instruction fetch request hits the instruction corresponding to the prefetch address of the secondary path, the instruction corresponding to the prefetch address of the secondary path is stored in the first cache, thereby avoiding overwriting of the instructions in the first cache.

[0068] FIG3 shows a flow chart of an instruction acquisition method provided by an exemplary embodiment of the present application. The method is executed by a CPU and includes:

[0069] Step 310: Get the main path predicted for each branch instruction.

[0070] Each branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed among the two subsequent execution paths.

[0071] For example, the subsequent execution path is other instructions and the next instruction in sequence. When the predicted branch instruction execution path is to jump to other instructions, the main path is the other instructions; when the predicted branch instruction execution path is not to jump and continue to execute the next instruction in sequence, the main path is the next instruction in sequence.

[0072] For example, in FIG1 , the branch predictor 110 predicts the subsequent execution path of the branch instruction to obtain a predicted main path. The branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed among the two subsequent execution paths.

[0073] Step 320: Determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold.

[0074] The confidence classification is used to indicate the likelihood of accurate prediction of the main path.

[0075] The confidence classification can also be called prediction confidence, or simply confidence, and includes the first classification and the second classification. For example, when the confidence classification is the first classification, the possibility of indicating that the prediction of the main path is accurate is low, that is, the confidence classification is low; when the confidence classification of the main path is the second classification, the possibility of indicating that the prediction of the main path is accurate is high, that is, the confidence classification is high.

[0076] In some embodiments, when the number of historical mispredictions of the main path of the branch instruction is greater than the confidence threshold, the confidence classification of the main path corresponding to the branch instruction is determined to be the first classification (low confidence classification);

[0077] When the number of historical mispredictions of the main path of the branch instruction is less than the confidence threshold, the confidence classification of the main path corresponding to the branch instruction is determined to be the second classification (high confidence classification).

[0078] Through the above determination method, the confidence classification of the main path corresponding to each branch instruction is determined.

[0079] In some embodiments, the confidence threshold is a dynamically adjusted threshold value.

[0080] For load programs including different numbers of branch instructions, the confidence threshold is allowed to be dynamically adjusted. For example, for a load program including a large number of branch instructions (100), the confidence threshold is adjusted from 3 to 6; for a load program including a small number of branch instructions (30), the confidence threshold is adjusted from 6 to 3.

[0081] Step 330: Determine the confidence classification ratio.

[0082] The confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, and the first classification is a confidence classification in which the number of historical incorrect predictions is greater than the confidence threshold.

[0083] For example, the total number of instructions is 1000, and the number of branch instructions corresponding to the first category is 100, then the confidence classification ratio is 10%.

[0084] In some embodiments, the CPU includes a first storage unit, which is used to store branch prediction information corresponding to the main path, each branch prediction information corresponds to a prediction counter, and the prediction counter is used to indicate the number of historical incorrect predictions corresponding to the branch prediction information; when the value of the prediction counter is greater than the confidence threshold, the confidence classification is the first classification; when the value of the prediction counter is less than or equal to the confidence threshold, the confidence classification is the second classification.

[0085] Step 340: Taking the confidence classification ratio as the desired ratio as the control target, adjust the confidence threshold.

[0086] In some embodiments, the expected ratio is a preset confidence classification ratio, which is used to represent an expected relatively stable confidence classification ratio.

[0087] For different workloads, if the fixed confidence threshold is too low, the confidence classification ratio will be too high. This will lead to an excessive number of prefetched instructions, which will result in insufficient instruction cache space for storing instructions. If the fixed confidence threshold is too high, the confidence classification ratio will be too low. This will result in an insufficient number of prefetched instructions. When the CPU needs to fetch an instruction, it may not be able to quickly find the instruction in the instruction cache, wasting instruction cache space. By adjusting the confidence threshold, these problems can be avoided or reduced.

[0088] For example, when the confidence classification ratio is greater than the expected ratio, the confidence threshold is increased, thereby reducing the confidence classification ratio; when the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered, thereby increasing the confidence classification ratio.

[0089] To sum up, the method provided in this embodiment adjusts the confidence threshold by taking the confidence classification ratio as the expected ratio as the control target, which can avoid or reduce the problem that the fixed confidence threshold is too large or too small for different load programs, thereby resulting in an unreasonable ratio of the number of first branch instructions to the total number of instructions. The first branch instruction is the branch instruction corresponding to the main path of the first confidence classification.

[0090] In some embodiments, when the confidence classification ratio is greater than or less than the expected ratio, the confidence threshold is adjusted. FIG4 shows a flowchart of an instruction acquisition method provided by an exemplary embodiment of the present application. The method is executed by a CPU and includes:

[0091] Step 310: Get the main path predicted for each branch instruction.

[0092] Each branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed among the two subsequent execution paths.

[0093] For example, the subsequent execution path is other instructions and the next instruction in sequence. When the predicted branch instruction execution path is to jump to other instructions, the main path is the other instructions; when the predicted branch instruction execution path is not to jump and continue to execute the next instruction in sequence, the main path is the next instruction in sequence.

[0094] For example, in FIG1 , the branch predictor 110 predicts the subsequent execution path of the branch instruction to obtain a predicted main path. The branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed among the two subsequent execution paths.

[0095] Step 320: Determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold.

[0096] The confidence classification is used to indicate the likelihood of accurate prediction of the main path.

[0097] The confidence classification can also be called prediction confidence, or simply confidence, and includes the first classification and the second classification. For example, when the confidence classification is the first classification, the possibility of indicating that the prediction of the main path is accurate is low, that is, the confidence classification is low; when the confidence classification of the main path is the second classification, the possibility of indicating that the prediction of the main path is accurate is high, that is, the confidence classification is high.

[0098] In some embodiments, when the number of historical mispredictions of the main path of the branch instruction is greater than the confidence threshold, the confidence classification of the main path corresponding to the branch instruction is determined to be the first classification (low confidence classification);

[0099] When the number of historical mispredictions of the main path of the branch instruction is less than the confidence threshold, the confidence classification of the main path corresponding to the branch instruction is determined to be the second classification (high confidence classification).

[0100] Through the above determination method, the confidence classification of the main path corresponding to each branch instruction is determined.

[0101] In some embodiments, the confidence threshold is a dynamically adjusted threshold value.

[0102] For load programs including different numbers of branch instructions, the confidence threshold is allowed to be dynamically adjusted. For example, for a load program including a large number of branch instructions (100), the confidence threshold is adjusted from 3 to 6; for a load program including a small number of branch instructions (30), the confidence threshold is adjusted from 6 to 3.

[0103] Step 330: Determine the confidence classification ratio.

[0104] The confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, and the first classification is a confidence classification in which the number of historical incorrect predictions is greater than the confidence threshold.

[0105] For example, the total number of instructions is 1000, and the number of branch instructions corresponding to the first category is 100, then the confidence classification ratio is 10%.

[0106] In some embodiments, the CPU includes a first storage unit, the first storage unit is used to store branch prediction information corresponding to the main path, each branch prediction information corresponds to a prediction counter, and the prediction counter is used to indicate the number of historical mispredictions corresponding to the branch prediction information;

[0107] In the case where the value of the prediction counter is greater than the confidence threshold, the confidence classification is the first classification;

[0108] In case the value of the prediction counter is less than or equal to the confidence threshold, the confidence classification is the second classification.

[0109] Step 342: When the confidence classification ratio is less than the expected ratio, lower the confidence threshold.

[0110] In some embodiments, when the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered based on a predetermined step size, or the confidence threshold is lowered based on a dynamic step size determined based on the difference between the confidence classification ratio and the expected ratio.

[0111] As shown in FIG1 , a branch predictor 110 is used to adjust a confidence threshold. The branch predictor 110 includes a first storage unit 112. The first storage unit 112 is a storage unit for storing branch prediction information. The branch prediction information includes a confidence classification of a main path. The first storage unit 112 includes multiple items (multiple branch prediction information), each of which corresponds to a counter. For example, if the counter is a saturated counter, the number of bits occupied by the saturated counter is relatively small, for example, 3 bits. When the branch predictor makes an incorrect prediction, the value of the saturated counter of the corresponding item is increased by 1. When the saturated counter is saturated (equal to 7 in the case of 3 bits), it no longer increases.

[0112] When the branch predictor 110 makes a prediction, if an item in the first storage unit 112 is hit, it is determined whether the value of the saturation counter corresponding to the hit item is greater than a preset confidence threshold. If it is greater than the confidence threshold, the confidence classification of the item is marked as the first classification (low confidence); if it is less than or equal to the confidence threshold, the confidence classification of the item is marked as the second classification (high confidence). For example, the confidence classification is represented by one bit, and when the bit value is 1, it indicates low confidence, and when the bit value is 0, it indicates high confidence; or when the bit value is 1, it indicates high confidence, and when the bit value is 0, it indicates low confidence. This embodiment of the present application is not limited to this.

[0113] For different branch instructions, the confidence classification ratio is compared with the expected ratio. The confidence classification ratio is the ratio of branch instructions corresponding to the first category to the total instructions. For example, when the total number of instructions is 1000, a 10-bit threshold counter is used to accumulate and count the number of branch instructions whose confidence classification is the first category. The confidence classification ratio is the ratio of the value of the threshold counter to the total number of instructions. The expected ratio represents the expected confidence classification ratio.

[0114] When the confidence classification ratio is greater than the expected ratio, the confidence threshold is increased; when the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered.

[0115] In some embodiments, the confidence threshold can be changed based on a predetermined step size. For example, if the predetermined step size is 1, if the confidence classification ratio is greater than the expected ratio, the confidence threshold value is increased by 1; otherwise, the confidence threshold value is decreased by 1. For example, if the expected ratio is 15%, the initial confidence threshold value is 4, and the total number of instructions is 1000, the threshold counter value is 100, and the confidence classification ratio is 10%, which is less than 15%, so the confidence threshold value is adjusted to 3.

[0116] In some embodiments, the confidence threshold can be changed based on a dynamic step size determined by the difference between the confidence classification ratio and the expected ratio. For example, if the expected ratio is 15%, the initial confidence threshold value is 5, and the total number of instructions is 1000, the threshold counter value is 100, and the confidence classification ratio is 10%, which is less than 15%. Therefore, the confidence threshold value is adjusted to 3, so that when the total number of instructions is 1000, the threshold counter value is 150, and the confidence classification ratio is 15%.

[0117] Step 344: When the confidence classification ratio is greater than the expected ratio, increase the confidence threshold.

[0118] In some embodiments, when the confidence classification ratio is greater than the expected ratio, the confidence threshold is increased based on a predetermined step size, or the confidence threshold is increased based on a dynamic step size determined based on the difference between the confidence classification ratio and the expected ratio.

[0119] The principle of increasing the confidence threshold is the same as the principle of decreasing the confidence threshold. For specific implementation details, refer to step 342 and will not be repeated here.

[0120] To sum up, the method provided in this embodiment adjusts the confidence threshold by taking the confidence classification ratio as the expected ratio as the control target, for example, adjusting the confidence threshold according to a predetermined step size or a dynamic step size determined by the difference between the confidence classification ratio and the expected ratio. This can avoid or reduce the problem that the fixed confidence threshold is too large or too small for different load programs, thereby resulting in an unreasonable ratio of the number of first branch instructions to the total number of instructions. The first branch instruction is a branch instruction corresponding to the main path of the first confidence classification.

[0121] In some embodiments, different cache methods are used when the confidence classification is different. FIG5 shows a flowchart of an instruction acquisition method provided by an exemplary embodiment of the present application, which is executed by a CPU and includes:

[0122] Step 310: Get the main path predicted for each branch instruction.

[0123] Each branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed among the two subsequent execution paths.

[0124] For example, the subsequent execution path is other instructions and the next instruction in sequence. When the predicted branch instruction execution path is to jump to other instructions, the main path is the other instructions; when the predicted branch instruction execution path is not to jump and continue to execute the next instruction in sequence, the main path is the next instruction in sequence.

[0125] For example, in FIG1 , the branch predictor 110 predicts the subsequent execution path of the branch instruction to obtain a predicted main path. The branch instruction corresponds to two candidate subsequent execution paths, and the main path is the path predicted to be executed among the two subsequent execution paths.

[0126] Step 320: Determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold.

[0127] The confidence classification is used to indicate the likelihood of accurate prediction of the main path.

[0128] The confidence classification can also be called prediction confidence, or simply confidence, and includes the first classification and the second classification. For example, when the confidence classification is the first classification, the possibility of indicating that the prediction of the main path is accurate is low, that is, the confidence classification is low; when the confidence classification of the main path is the second classification, the possibility of indicating that the prediction of the main path is accurate is high, that is, the confidence classification is high.

[0129] In some embodiments, when the number of historical mispredictions of the main path of the branch instruction is greater than the confidence threshold, the confidence classification of the main path corresponding to the branch instruction is determined to be the first classification (low confidence classification);

[0130] When the number of historical mispredictions of the main path of the branch instruction is less than the confidence threshold, the confidence classification of the main path corresponding to the branch instruction is determined to be the second classification (high confidence classification).

[0131] Through the above determination method, the confidence classification of the main path corresponding to each branch instruction is determined.

[0132] In some embodiments, the confidence threshold is a dynamically adjusted threshold value.

[0133] For load programs including different numbers of branch instructions, the confidence threshold is allowed to be dynamically adjusted. For example, for a load program including a large number of branch instructions (100), the confidence threshold is adjusted from 3 to 6; for a load program including a small number of branch instructions (30), the confidence threshold is adjusted from 6 to 3.

[0134] Step 322: Get the instruction request.

[0135] In some embodiments, the instruction request includes at least one of the following: an instruction fetch request; a primary path prefetch request; and a secondary path prefetch request.

[0136] Among them, the instruction fetch request is used to request to obtain the instruction to be executed; the main path prefetch request is used to request to prefetch the instructions of the main path, and the instructions of the main path are the instructions corresponding to the prefetch address of the main path; the secondary path prefetch request is used to request to prefetch the instructions of the secondary path, and the instructions of the secondary path are the instructions corresponding to the prefetch address of the secondary path.

[0137] For example, in FIG1 , instruction requests are obtained from instruction fetch queue 130 and prefetch queue 140, and instruction fetch queue 130 and prefetch queue 140 send the instruction requests to the corresponding caches. For example, instruction fetch queue 130 sends instruction fetch requests to first cache 150 and second cache 160, instruction fetch queue 130 sends primary path prefetch requests to first cache 150, and prefetch queue 140 sends secondary path prefetch requests to first cache 150.

[0138] Step 3242: When the confidence classification is the first classification, the first caching method is adopted.

[0139] In some embodiments, the CPU includes a first cache, the first cache being configured to store prefetch addresses of a primary path and prefetch addresses of a secondary path, wherein the prefetch address of the primary path is the address of the primary path, and the prefetch address of the secondary path is the address of a subsequent execution path different from the primary path. The confidence classification includes a first classification and a second classification, wherein the second classification is a confidence classification in which the number of historical mispredictions is less than or equal to a confidence threshold. The first cache is further configured to store instructions corresponding to the prefetch addresses of the primary path and instructions corresponding to the prefetch addresses of the secondary path.

[0140] In some embodiments, the instruction request includes a main path prefetch request or a secondary path prefetch request, and the first caching method includes: based on the hit situation of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path, and the instruction of the main path is the instruction corresponding to the prefetch address of the main path; or, based on the hit situation of the secondary path prefetch request and the prefetch address of the secondary path, obtaining the instruction of the secondary path, and the instruction of the secondary path is the instruction corresponding to the prefetch address of the secondary path.

[0141] Instructions for the main path:

[0142] In some embodiments, the central processing unit further includes a third cache, which is a lower level cache of the first cache. Based on the hit of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path includes:

[0143] When the main path prefetch request hits the prefetch address of the main path, obtaining the instruction of the main path in the first cache;

[0144] In the case that the main path prefetch request does not hit the prefetch address of the main path, the first cache sends the main path prefetch request to the third cache, and the third cache stores the instruction of the main path into the first cache.

[0145] In some embodiments, if a prefetch request of the primary path hits a prefetch address of the secondary path, an instruction of the primary path is retrieved from the first cache;

[0146] In the case that the primary path prefetch request does not hit the prefetch address of the secondary path, the first cache sends the primary path prefetch request to the third cache, and the third cache stores the instruction of the primary path into the first cache.

[0147] In some embodiments, if the primary path prefetch request hits the address of the instruction fetch request, obtaining the primary path instruction in the first cache;

[0148] In the case that the main path prefetch request misses the address of the instruction fetch request, the first cache sends the main path prefetch request to the third cache, and the third cache stores the instruction of the main path into the first cache.

[0149] As shown in Figure 1, the instruction fetch queue 130 and the prefetch queue 140 send instruction requests to the corresponding caches respectively. The instruction requests include at least one of: instruction fetch requests, primary path prefetch requests, and secondary path prefetch requests. For example, the instruction fetch queue 130 sends the instruction fetch request to the first cache 150 and the second cache 160. The instruction fetch queue 130 sends the primary path prefetch request to the first cache 150, and the prefetch queue 140 sends the secondary path prefetch request to the first cache 150. The primary path prefetch request is used to request the prefetch of the instruction corresponding to the prefetch address of the primary path, and the secondary path prefetch request is used to request the prefetch of the instruction corresponding to the prefetch address of the secondary path. The three types of instruction requests each carry a corresponding request address. The first cache 150 compares the request address with the address stored in the first cache 150 to determine whether the instruction request is a hit. If the request address matches the stored address, the instruction request is a hit; if the request address does not match the stored address, the instruction request is a miss.

[0150] For missed instruction requests, a request to retrieve the instruction from the third cache is necessary. A missed instruction request includes at least one of an instruction fetch request, a primary path prefetch request, and a secondary path prefetch request. The third cache is a lower-level cache of the first cache, for example, a cache lower than the instruction cache. Optionally, for missed instruction requests, a request to retrieve the instruction from the main memory is necessary.

[0151] Based on the missed instruction request, the third cache returns the corresponding instruction. After the third cache returns the corresponding instruction, different instructions are stored in the corresponding memory respectively. The instruction includes at least one of the following: instruction fetch result, main path prefetch result, and secondary path prefetch result. Among them, the instruction fetch result includes the instruction that needs to be executed currently, the main path prefetch result includes the instruction of the main path (the instruction corresponding to the prefetch address of the main path), and the secondary path prefetch result includes the instruction of the secondary path (the instruction corresponding to the prefetch address of the secondary path). For example, the third cache stores the instruction of the main path in the first cache.

[0152] In some embodiments, when the CPU is first started, no address or instruction is stored in the first cache. 1. For example, in the order of other instruction A, branch instruction B, other instruction C, and other instruction D, when other instruction A needs to be executed, the instruction fetch queue sends a first instruction fetch request to the first cache. The first instruction fetch request carries the address of other instruction A, but there is no hit. The first cache then stores the address of other instruction A and sends the first instruction fetch request to the third cache. If there is a hit, the other instruction A is returned to the first cache.

[0153] 2. The instruction fetch queue sends a first main path prefetch request, which carries the address of the main path of branch instruction B. The request is sent to the first cache, but there is no hit. The first cache then stores the address of the main path and sends the first main path prefetch request to the third cache. After a hit, the instruction corresponding to the main path address is returned to the first cache.

[0154] 3. The instruction fetch queue sends a second primary path prefetch request, which carries the address of another instruction C, to the first cache. There is no hit, so the first cache stores the address of the other instruction C and sends the second primary path prefetch request to the third cache. After a hit, the instruction corresponding to the address of the other instruction C is returned to the first cache.

[0155] 4. The instruction fetch queue sends a third primary path prefetch request, which carries the address of another instruction D, to the first cache. However, the request does not hit the first cache, so the first cache stores the address of the other instruction D and sends the third primary path prefetch request to the third cache. If the request hits the first cache, the instruction corresponding to the address of the other instruction D is returned to the first cache.

[0156] 5. When the instruction fetch queue sends a main path prefetch request, the CPU continues to execute instructions. When the CPU executes branch instruction B, the instruction fetch queue sends a second instruction fetch request to the first cache. The second instruction fetch request carries the address of the main path of branch instruction B. The second instruction fetch request hits the address of the main path of branch instruction B in the first cache, and the main path of branch instruction B is executed, for example, jumping to other instruction D.

[0157] 6. When the CPU executes another instruction D, the instruction fetch queue sends a third instruction fetch request to the first cache. The third instruction fetch request carries the address of the other instruction D, hits the address of the other instruction D in the first cache, and obtains the other instruction D.

[0158] 7. The instruction fetch queue continues to send main path prefetch requests. If the subsequent main path prefetch requests carry the address of other instruction A, the address of the main path of branch instruction B, the address of other instruction C, and the address of other instruction D, the main path prefetch request can hit and directly obtain the corresponding instruction from the first cache without going to the third cache to obtain the corresponding instruction.

[0159] Instructions for the secondary path:

[0160] In some embodiments, the central processing unit further includes: a second cache and a third cache, wherein the third cache is a lower level cache of the first cache. Based on the hit of the secondary path prefetch request and the prefetch address of the secondary path, obtaining the instruction of the secondary path includes:

[0161] In the case where the secondary path prefetch request hits the prefetch address of the secondary path, the first cache obtains the instruction of the secondary path;

[0162] In the case that the secondary path prefetch request does not hit the prefetch address of the secondary path, the first cache sends the secondary path prefetch request to the third cache, and the third cache stores the instruction of the secondary path into the second cache.

[0163] In some embodiments, if a secondary path prefetch request hits a primary path prefetch address, the first cache retrieves an instruction of the secondary path;

[0164] In the case that the secondary path prefetch request does not hit the prefetch address of the primary path, the first cache sends the secondary path prefetch request to the third cache, and the third cache stores the instruction of the secondary path into the second cache.

[0165] In some embodiments, if the secondary path prefetch request hits the address of the instruction fetch request, the first cache retrieves the instruction of the secondary path;

[0166] In the case that the secondary path prefetch request does not hit the address of the instruction fetch request, the first cache sends the secondary path prefetch request to the third cache, and the third cache stores the instruction of the secondary path into the second cache.

[0167] As shown in Figure 1, the instruction fetch queue 130 and the prefetch queue 140 send instruction requests to the corresponding caches respectively. The instruction requests include at least one of: instruction fetch requests, primary path prefetch requests, and secondary path prefetch requests. For example, the instruction fetch queue 130 sends the instruction fetch request to the first cache 150 and the second cache 160. The instruction fetch queue 130 sends the primary path prefetch request to the first cache 150, and the prefetch queue 140 sends the secondary path prefetch request to the first cache 150. The primary path prefetch request is used to request the prefetch of the instruction corresponding to the prefetch address of the primary path, and the secondary path prefetch request is used to request the prefetch of the instruction corresponding to the prefetch address of the secondary path. The three types of instruction requests each carry a corresponding request address. The first cache 150 compares the request address with the address stored in the first cache 150 to determine whether the instruction request is a hit. If the request address matches the stored address, the instruction request is a hit; if the request address does not match the stored address, the instruction request is a miss.

[0168] For missed instruction requests, a request to retrieve the instruction from the third cache is necessary. A missed instruction request includes at least one of an instruction fetch request, a primary path prefetch request, and a secondary path prefetch request. The third cache is a lower-level cache of the first cache, for example, a cache lower than the instruction cache. Optionally, for missed instruction requests, a request to retrieve the instruction from the main memory is necessary.

[0169] Based on the missed instruction request, the third cache returns the corresponding instruction. After the third cache returns the corresponding instruction, different instructions are stored in the corresponding memory respectively. The instruction includes at least one of the following: instruction fetch result, main path prefetch result, and secondary path prefetch result. Among them, the instruction fetch result includes the instruction that needs to be executed currently, the main path prefetch result includes the instruction of the main path (the instruction corresponding to the prefetch address of the main path), and the secondary path prefetch result includes the instruction of the secondary path (the instruction corresponding to the prefetch address of the secondary path). For example, the third cache stores the instruction of the main path in the first cache and stores the instruction of the secondary path in the second cache.

[0170] In some embodiments, the instruction request further includes an instruction fetch request. When the instruction fetch request hits an instruction of the secondary path in the second cache, the second cache stores the instruction of the secondary path into the first cache.

[0171] In related art, direct storage of instructions from the secondary path into the first cache may result in the replacement of the currently executed instruction or other stored instructions, thereby overwriting instructions in the first cache. By first storing the instruction corresponding to the prefetch address of the secondary path into the second cache, and then storing the instruction corresponding to the prefetch address of the secondary path into the first cache when an instruction fetch request hits the instruction corresponding to the prefetch address of the secondary path, overwriting instructions in the first cache can be avoided.

[0172] Step 3244: When the confidence classification is the second classification, the second caching method is adopted.

[0173] In some embodiments, the second cache method includes: obtaining the instruction of the main path based on a hit condition between the main path prefetch request and the prefetch address of the main path.

[0174] The second cache method is the same as the part for the instructions of the main path in step 3242. For specific implementation details, please refer to step 3242 and will not be repeated here.

[0175] Step 330: Determine the confidence classification ratio.

[0176] The confidence classification ratio is the ratio of branch instructions corresponding to the first classification to the total instructions, and the first classification is a confidence classification in which the number of historical incorrect predictions is greater than the confidence threshold.

[0177] For example, the total number of instructions is 1000, and the number of branch instructions corresponding to the first category is 100, then the confidence classification ratio is 10%.

[0178] In some embodiments, the CPU includes a first storage unit, the first storage unit is used to store branch prediction information corresponding to the main path, each branch prediction information corresponds to a prediction counter, and the prediction counter is used to indicate the number of historical mispredictions corresponding to the branch prediction information;

[0179] In the case where the value of the prediction counter is greater than the confidence threshold, the confidence classification is the first classification;

[0180] In case the value of the prediction counter is less than or equal to the confidence threshold, the confidence classification is the second classification.

[0181] Step 340: Taking the confidence classification ratio as the desired ratio as the control target, adjust the confidence threshold.

[0182] In some embodiments, the expected ratio is a preset confidence classification ratio, which is used to represent an expected relatively stable confidence classification ratio.

[0183] For different workloads, if the fixed confidence threshold is too low, the confidence classification ratio will be too high. This will lead to an excessive number of prefetched instructions, which will result in insufficient instruction cache space for storing instructions. If the fixed confidence threshold is too high, the confidence classification ratio will be too low. This will result in an insufficient number of prefetched instructions. When the CPU needs to fetch an instruction, it may not be able to quickly find the instruction in the instruction cache, wasting instruction cache space. By adjusting the confidence threshold, these problems can be avoided or reduced.

[0184] For example, when the confidence classification ratio is greater than the expected ratio, the confidence threshold is increased, thereby reducing the confidence classification ratio; when the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered, thereby increasing the confidence classification ratio.

[0185] To sum up, the method provided in this embodiment adds a second cache to store the instructions corresponding to the prefetch address of the secondary path. When the instruction fetch request hits the instruction corresponding to the prefetch address of the secondary path, the instruction corresponding to the prefetch address of the secondary path is stored in the first cache, thereby avoiding overwriting of the instructions in the first cache.

[0186] In the above embodiments, steps with the same sequence number can be considered as the same step. The embodiment corresponding to FIG3 , the embodiment corresponding to FIG4 , and the embodiment corresponding to FIG5 can be implemented separately or in combination, and this application does not limit this.

[0187] An embodiment of the present application provides a central processing unit (CPU), the structure of which is shown in FIG1 , including:

[0188] A branch predictor 110 is configured to obtain a predicted primary path for each branch instruction. Each branch instruction corresponds to two candidate subsequent execution paths, and the primary path is the path predicted to be executed among the two subsequent execution paths.

[0189] The branch predictor 110 is configured to determine a confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and a confidence threshold, where the confidence classification indicates the likelihood that the prediction of the main path is accurate.

[0190] The branch predictor 110 is configured to determine a confidence classification ratio, where the confidence classification ratio is the ratio of branch instructions corresponding to a first classification to the total number of instructions, where the first classification is a confidence classification for which the number of historical mispredictions is greater than a confidence threshold;

[0191] The branch predictor 110 is configured to adjust a confidence threshold by taking the confidence classification ratio as a desired ratio as a control target.

[0192] In a possible design of this embodiment, the branch predictor 110 is configured to increase the confidence threshold when the confidence classification ratio is greater than the expected ratio; and to lower the confidence threshold when the confidence classification ratio is less than the expected ratio.

[0193] In one possible design of this embodiment, the branch predictor 110 is configured to, when the confidence classification ratio is greater than the expected ratio, increase the confidence threshold based on a predetermined step size, or increase the confidence threshold based on a dynamic step size determined based on a difference between the confidence classification ratio and the expected ratio;

[0194] The branch predictor 110 is configured to lower the confidence threshold based on a predetermined step size when the confidence classification ratio is less than an expected ratio, or to lower the confidence threshold based on a dynamic step size determined based on a difference between the confidence classification ratio and the expected ratio.

[0195] In one possible design of this embodiment, the central processing unit includes a first cache 150, and the first cache 150 is used to store prefetch addresses of a primary path and prefetch addresses of a secondary path. The prefetch address of the primary path is the address of the primary path, and the prefetch address of the secondary path is the address of a subsequent execution path different from the primary path. The confidence classification includes a first classification and a second classification. The second classification is a confidence classification in which the number of historical mispredictions is less than or equal to a confidence threshold.

[0196] The first cache 150 is also used to obtain instruction requests; when the confidence classification is the first classification, the first cache method is adopted; when the confidence classification is the second classification, the second cache method is adopted;

[0197] Among them, the instruction request includes a main path prefetch request or a secondary path prefetch request, and the first caching method includes: based on the hit situation of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path, and the instruction of the main path is the instruction corresponding to the prefetch address of the main path; or, based on the hit situation of the secondary path prefetch request and the prefetch address of the secondary path, obtaining the instruction of the secondary path, and the instruction of the secondary path is the instruction corresponding to the prefetch address of the secondary path; the second caching 160 method includes: based on the hit situation of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path.

[0198] In a possible design of this embodiment, the central processing unit further includes: a second cache 160 and a third cache 170, wherein the third cache 170 is a lower-level cache of the first cache;

[0199] In the case where the secondary path prefetch request hits the prefetch address of the secondary path, the first cache 150 is used to obtain the instruction of the secondary path;

[0200] When the secondary path prefetch request misses the prefetch address of the secondary path, the first cache 150 sends the secondary path prefetch request to the third cache 170 , and the third cache 170 stores the instruction of the secondary path into the second cache 160 .

[0201] In a possible design of this embodiment, the instruction request also includes an instruction fetch request, and the second cache 160 is further used to: when the instruction fetch request hits the instruction of the secondary path in the second cache 160, the second cache 160 stores the instruction of the secondary path into the first cache 150.

[0202] In a possible design of this embodiment, the central processing unit further includes a third cache 170 , which is a lower-level cache of the first cache 150 ;

[0203] When the primary path prefetch request hits the prefetch address of the primary path, the instruction of the primary path is obtained from the first cache 150 ;

[0204] When the main path prefetch request misses the prefetch address of the main path, the first cache 150 sends the main path prefetch request to the third cache 170 , and the third cache 170 stores the instruction of the main path into the first cache 150 .

[0205] The specific details of the central processing unit structure are shown in the embodiment of FIG1 and will not be repeated here.

[0206] An embodiment of the present application also provides a computer device, which includes: a processor and a memory, wherein at least one program is stored in the memory; the processor is used to execute at least one program in the memory to implement the instruction acquisition method provided by the above-mentioned method embodiments.

[0207] In some embodiments, the branch instruction corresponds to two candidate subsequent execution paths, the main path is the path predicted to be executed among the two subsequent execution paths, and the secondary path is a subsequent execution path different from the main path; the processor also includes a second cache, the second cache is used to obtain and store instructions corresponding to the address of the secondary path, and the processor is also used to execute at least one program in the memory to implement the instruction acquisition method as shown in the embodiment of Figure 5. The specific implementation details of the second cache refer to the embodiments of Figure 1 and Figure 5, and will not be repeated here.

[0208] FIG6 is a block diagram of a computer device 600 according to an exemplary embodiment of the present application. Generally, the computer device 600 includes a processor 601 and a memory 602 .

[0209] The processor 601 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 601 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 601 may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 601 may include a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 601 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0210] The memory 602 may include one or more computer-readable storage media, which may be non-transitory. The memory 602 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 602 is used to store at least one instruction, which is executed by the processor 601 to implement the instruction acquisition method provided in the method embodiment of the present application.

[0211] In some embodiments, the computer device 600 may optionally further include: an input interface 603 and an output interface 604. The processor 601, the memory 602, and the input interface 603 and the output interface 604 may be connected via a bus or a signal line. Each peripheral device may be connected to the input interface 603 and the output interface 604 via a bus, a signal line, or a circuit board. The input interface 603 and the output interface 604 may be used to connect at least one input / output-related peripheral device to the processor 601 and the memory 602. In some embodiments, the processor 601, the memory 602, and the input interface 603 and the output interface 604 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 601, the memory 602, and the input interface 603 and the output interface 604 may be implemented on a separate chip or circuit board, which is not limited in the embodiments of the present application.

[0212] Those skilled in the art will appreciate that the structure shown above does not limit the computer device 600 , and may include more or fewer components than shown, or combine certain components, or adopt a different component arrangement.

[0213] In an exemplary embodiment, a chip is also provided. The chip includes a programmable logic circuit and / or program instructions. When the chip runs on a computer device 600, it is used to implement the instruction acquisition method provided in the method embodiment of the present application.

[0214] In an exemplary embodiment, a computer program product is also provided, which includes computer instructions, which are stored in a computer-readable storage medium. A processor obtains the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to implement the instruction acquisition method provided in the method embodiment of the present application.

[0215] In an exemplary embodiment, a computer-readable storage medium is also provided, in which at least one program is stored. The at least one program is loaded and executed by a processor to implement the instruction acquisition method provided in the method embodiment of the present application.

[0216] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by a program instructing the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0217] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable storage medium or transmitted as one or more instructions or codes on a computer-readable storage medium. Computer-readable storage media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0218] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for obtaining an instruction, the method being executed by a central processing unit, the method comprising: Obtaining a main path predicted for each branch instruction, wherein each branch instruction corresponds to two candidate subsequent execution paths, and the main path is a path predicted to be executed in the two subsequent execution paths; Determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold, wherein the confidence classification is used to indicate the possibility classification of the accuracy of the prediction of the main path; Determining a confidence classification ratio, the confidence classification ratio being a ratio of branch instructions corresponding to a first classification to total instructions, the first classification being a confidence classification in which the number of historical mispredictions is greater than the confidence threshold; The confidence threshold is adjusted by taking the confidence classification ratio as the expected ratio as a control target.

2. The method according to claim 1, wherein: The adjusting the confidence threshold by taking the confidence classification ratio as the expected ratio as the control target includes: When the confidence classification ratio is greater than the expected ratio, increasing the confidence threshold; When the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered.

3. The method according to claim 2, wherein: When the confidence classification ratio is greater than the expected ratio, increasing the confidence threshold includes: In the case where the confidence classification ratio is greater than the expected ratio, the confidence threshold is increased based on a predetermined step size, or the confidence threshold is increased based on a dynamic step size determined based on a difference between the confidence classification ratio and the expected ratio; When the confidence classification ratio is less than the expected ratio, lowering the confidence threshold includes: In the case where the confidence classification ratio is less than the expected ratio, the confidence threshold is lowered based on the predetermined step size, or the confidence threshold is lowered based on the dynamic step size determined based on the difference between the confidence classification ratio and the expected ratio.

4. The method according to any one of claims 1 to 3, wherein: The central processing unit includes a first cache, the first cache is used to store a pre-fetch address of a primary path and a pre-fetch address of a secondary path, the pre-fetch address of the primary path is the address of the primary path, the pre-fetch address of the secondary path is the address of a subsequent execution path different from the primary path, the confidence classification includes the first classification and the second classification, the second classification is a confidence classification in which the number of historical mispredictions is less than or equal to the confidence threshold, and the method further includes: Obtaining an instruction request; when the confidence classification is the first classification, adopting a first cache method; when the confidence classification is the second classification, adopting a second cache method; Among them, the instruction request includes a main path prefetch request or a secondary path prefetch request, and the first caching method includes: based on the hit situation of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path, and the instruction of the main path is the instruction corresponding to the prefetch address of the main path; or, based on the hit situation of the secondary path prefetch request and the prefetch address of the secondary path, obtaining the instruction of the secondary path, and the instruction of the secondary path is the instruction corresponding to the prefetch address of the secondary path; the second caching method includes: based on the hit situation of the main path prefetch request and the prefetch address of the main path, obtaining the instruction of the main path.

5. The method according to claim 4, wherein: The central processor further includes: a second cache and a third cache, wherein the third cache is a lower level cache of the first cache; The obtaining of the instruction of the secondary path based on the hit condition of the secondary path prefetch request and the prefetch address of the secondary path comprises: In the case where the secondary path prefetch request hits the prefetch address of the secondary path, the first cache obtains the instruction of the secondary path; In the case that the secondary path prefetch request does not hit the prefetch address of the secondary path, the first cache sends the secondary path prefetch request to the third cache, and the third cache stores the instruction of the secondary path into the second cache.

6. The method according to claim 5, wherein: The instruction request further includes an instruction fetch request, and the method further includes: When the instruction fetch request hits the instruction of the secondary path in the second cache, the second cache stores the instruction of the secondary path into the first cache.

7. The method according to claim 4, wherein: The central processing unit further includes a third cache, which is a lower-level cache of the first cache; The obtaining of the main path instruction based on the main path prefetch request and the hit condition of the prefetch address of the main path includes: When the main path prefetch request hits the prefetch address of the main path, acquiring the instruction of the main path in the first cache; In the case that the main path prefetch request does not hit the prefetch address of the main path, the first cache sends the main path prefetch request to the third cache, and the third cache stores the instruction of the main path into the first cache.

8. A central processing unit, comprising: A branch predictor, used to obtain a main path predicted for each branch instruction, each branch instruction corresponding to two candidate subsequent execution paths, the main path being a path predicted to be executed among the two subsequent execution paths; The branch predictor is used to determine the confidence classification of the main path corresponding to each branch instruction based on the difference between the number of historical mispredictions of the main path of the same branch instruction and the confidence threshold, wherein the confidence classification is used to indicate the possibility classification of the prediction accuracy of the main path; The branch predictor is used to determine a confidence classification ratio, where the confidence classification ratio is a ratio of branch instructions corresponding to a first classification to total instructions, and the first classification is a confidence classification for which the number of historical mispredictions is greater than the confidence threshold; The branch predictor is used to adjust the confidence threshold by taking the confidence classification ratio as an expected ratio as a control target.

9. A computer device, comprising: A processor and a memory, wherein at least one program is stored in the memory; The processor is used to execute the at least one program in the memory to implement the instruction acquisition method according to any one of claims 1 to 4 or the instruction acquisition method according to claim 7.

10. The computer device according to claim 9, wherein: The branch instruction corresponds to two candidate subsequent execution paths, the primary path is a path predicted to be executed among the two subsequent execution paths, and the secondary path is a subsequent execution path different from the primary path; The processor also includes a second cache, which is used to obtain and store instructions corresponding to the address of the secondary path. The processor is also used to execute the at least one program in the memory to implement the instruction acquisition method as described in claim 5 or 6.

11. A computer-readable storage medium, wherein at least one program is stored in the computer-readable storage medium, and the at least one program is loaded and executed by a processor to implement the instruction acquisition method according to any one of claims 1 to 7.

12. A computer program product, comprising computer instructions, wherein the computer instructions are stored in a computer-readable storage medium, a processor obtains the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to implement the instruction acquisition method as described in any one of claims 1 to 7.

Images