Driver circuit for one or more power semiconductors

Abstract

The invention relates to a driver circuit for one or more power semiconductors (SD), the driver circuit comprising: at least one first switch (S1) and at least one second switch (S2), the driver circuit being connectable both to the lower switching potential and to the upper switching potential, a connection to the lower switching potential or to the upper switching potential being enabled by operation of the at least one first switch (S1) and of the at least one second switch (S2); a capacitor (Ctr) and a Zener diode (D0), the capacitor (Ctr) and the Zener diode (D0) being arranged in parallel branches, the parallel branches being connected on a first side to the connection of the switches (S1, S2), and the parallel branches being connected on a second side to the gate terminal of the power semiconductor (SD) to be driven, characterised in that the branch including the capacitor (Ctr) also comprises a resistor (RGon), and wherein in addition a protection circuit (OPT) comprising a further Zener diode and an antiserially connected diode is provided between the gate terminal (G) of the power semiconductor (SD) to be driven and the source terminal (S) of the power semiconductor (SD) to be driven.

Description

[0001] Driver circuit for one or more power semiconductors

[0002] background

[0003] Along with the so-called energy transition, there has been a great demand for power converters that preferably provide high power density with low weight and low costs.

[0004] This need stimulated the development of power converters whose power electronic components operate at high switching frequencies.

[0005] In addition to well-known silicon (Si) semiconductors, semiconductors with a wide band gap (WBG), e.g. based on silicon carbide (SiC) or gallium nitride (GaN), are now also being used in this power range.

[0006] Although these WBG power semiconductors can achieve switching frequencies up to the MHz range, the known driver circuits have demanding requirements. These include, for example, a low threshold voltage for turn-on, different current requirements during transition and in the steady state, negative potentials for safe turn-off, short breakdown times, and the maximum turn-on voltage.

[0007] Furthermore, it should be noted that existing driver circuits—especially for GaN power semiconductor switches—are complex and therefore expensive, as they are constructed from a large number of components that require careful selection and tuning depending on power, frequency, and application. Previous approaches, for example, aimed at reducing the capacitor in gate driver circuits. However, since a high inrush current (1000 times the continuous current) is required, a booster component is needed. This booster component is intended to supply the high transient current for a short duration through charging and discharging. However, charging an uncharged component leads to high dv / dt peaks, which can affect the lifetime of the connected GaN components.

[0008] GaN devices are used in systems designed to operate at high switching frequencies (several hundred kHz, sometimes even MHz). Since the turn-on threshold is low, a negative gate drive potential is preferred to ensure safe turn-off. Furthermore, the amplitude of the negative gate drive voltage affects the losses in GaN devices during switching, and limits for safe device operation have been proposed.

[0009] While negative gate drive voltages to establish the off state improve the components' immunity to external influences (e.g., dv / dt spikes via the Miller capacitance), they usually lead to higher switching and / or reverse conduction losses. The losses in a GaN component, in turn, determine, among other things, the size of the required heat sink; this size increases with increasing losses.

[0010] Two categories and several (sub)types of GaN power semiconductors are described in the literature.

[0011] For the understanding of the invention, the differences between the two main types, namely voltage-controlled components on the one hand and current-controlled components on the other, are important.

[0012] Examples of voltage-controlled devices include high-electron-mobility transistors (HEMTs), Schottky-gate GaN, and cascode GaN. A Schottky-gate GaN device physically alters the normally-on GaN HEMT structure to create a normally-off device. In these devices, also known as GaN E-HEMTs, the gate is sensitive to overvoltages and requires very precise control conditions to prevent unwanted / parasitic turn-on.

[0013] A cascode GaN device combines a higher-voltage GaN HEMT with a lower-voltage Si MOSFET that is normally off. Either gate drivers compatible with Si MOSFETs are used to switch the entire cascode structure, or the Si MOSFET is used as a safety on / off switch, while the normally-on GaN HEMT is directly driven at high frequencies.

[0014] Current-controlled components include gate injection transistors (GIT).

[0015] GaN GITs use a different manufacturing process than Schottky-gate GaNs to create a monolithic, normally-off device, but require a constant gate current to maintain the device in the on state. GaN GIT devices are considered more reliable and robust in operation than GaN HEMTs.

[0016] It should be noted that the gate drivers for cascode GaN and Schottky-gate GaN devices are quite similar, differing only in the control voltage levels and current requirements. However, GaN GIT devices have special requirements for continuous current (in the mA range) and require high transient currents, which necessitate capacitors.

[0017] The following presents and discusses a comprehensive overview (from research papers, technical reports, documents, and patents) of similar, state-of-the-art gate driver circuits. The article "A Resonant Drive Circuit for GaN Power MOSHFET" by B. Wang, N. Tipirneni, M. Riva, A. Monti, G. Simin, and E. Santi, published in the Conference Record of the 2006 IEEE Industry Applications Conference Forty-First IAS Annual Meeting, Tampa, FL, 2006, pages 364-368, introduces a first commonly used topology for gate driver circuits that can be used for Si, SiC, and GaN HEMT devices. In this topology, a resistor is placed between an (integrated) driver circuit and the GaN device to be driven. However, this topology is not suitable for GaN GIT devices.

[0018] Another topology is from the article “Design and Implementation of a GaN-Based, 100 kHz, 102 W / in3 Single-Phase Inverter" by authors C. Zhao et al., published in IEEE J. Emerg. Sci. Topics Power Electron., vol. 4, no. 3, pages 824-840, 2016, doi: 10.1109 / JESTPE.2016.2573758, is known, which can be understood as an extension of the previously listed topology. In this case, a capacitor is inserted into the circuit to attenuate crosstalk. This topology can be used for Si, SiC, and GaN HEMT devices, but is not suitable for GaN GIT devices.

[0019] Another topology is known from the article "Single-Phase T-Type Inverter Performance Benchmark Using Si IGBTs, SiC MOSFETs and GaN HEMTs" by E. Gurpinar and A. Castellazzi, published in IEEE Trans. Power Electron., page 1, 2015, doi: 10.1109 / TPEL.2015.2506400. This represents another common gate driver topology. It involves adding an additional diode (fast-switching Schottky diode) in series with a current-limiting resistor in parallel with the resistor (compared to the first topology listed) to enable different timings for the turn-on and turn-off processes. This topology is suitable for Si, SiC, and GaN HEMT devices, but does not meet the requirements of GaN GIT devices.

[0020] Another topology is known from the article "Gate driver for the active thermal control of a DC / DC GaN-based converter" by PK Prasobhu, G. Buticchi, S. Brueske, and M. Liserre, published in the 2016 IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI, USA, 2016, pages 1-8. This topology can be understood as an extension of the previously described topology. In this case, another fast-switching Schottky diode is inserted in the opposite direction, creating two parallel branches of a parallel circuit, each of which has its current limited by a resistor. The added fast-switching Schottky diode supports the device's fast turn-on process. This topology is also only suitable for Si, SiC, and GaN HEMT devices, but again does not meet the requirements of GaN GIT devices.

[0021] Another topology is known from the article "The 2018 GaN power electronics roadmap" by H. Amano et al., published in J. Phys. D: Appl. Phys., vol. 51, no. 16, page 163001, 2018, doi: 10.1088 / 1361-6463 / aaaf9d. This topology, which can be understood as an extension of the previously described topology, adds an additional clamping diode parallel to the gate and source or gate and emitter terminals on the driven component side. This clamping diode is used to protect the gate-source junction of the MOSFET. However, this topology also does not meet the requirements of GaN GIT devices; the circuit is only suitable for Si, SiC, and GaN HEMT devices.

[0022] Another topology is also known from the previously cited article "Single-Phase T-Type Inverter Performance Benchmark Using Si IGBTs, SiC MOSFETs and GaN HEMTs." In this topology, a parallel circuit is arranged between an (integrated) driver circuit and the GaN device to be driven. One branch of this circuit comprises a resistor and the other branch comprises a series connection of a capacitor and a resistor. This capacitor is a special requirement for GaN GIT devices. The capacitor contributes to accelerating the turn-on process by supplying a higher current during transient operation, which is limited to a safe level by the series resistor. The high-value parallel resistor helps maintain current flow in the steady state, so that the GIT gate diode remains forward-biased.

[0023] From the presentation "Gate driving solutions for GaN HEMT switches enabling robust and high power density designs" by the authors D. Varajao, available on ResearchGate, an extension of the previously mentioned topology is known, in which a series circuit comprising a fast switching Schottky diode and a current limiting

[0024] resistor is connected. This is intended to support the transient operation of the shutdown process.

[0025] The article "Comprehensive evaluation of GaN GIT in low- and high-frequency bridge leg applications" by authors D. Bortis, O. Knecht, D. Neumayr, and JW Kolar, published in 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia), Hefei, China, 2016, pages 21-30, shows some further topologies.

[0026] A first further topology shows a complex circuit consisting of two parallel circuits connected in series. The first parallel circuit has a resistor in a first branch and a series circuit consisting of a diode and a current-limiting resistor in a second branch. The second parallel circuit has three branches, with a first branch comprising a capacitor, a second branch comprising a diode, and a third branch comprising a series circuit consisting of a Schottky diode and a resistor. A clamping diode arrangement is also incorporated on the side of the component to be driven. The clamping diode arrangement comprises a series circuit consisting of a diode and a Schottky diode with opposite polarity. It can generally be assumed that the first parallel circuit can be used in particular for driving Si, SiC, and GaN HEMT components, while the second parallel circuit can be used for driving the GaN GIT component.

[0027] A modified topology reveals a significantly more complicated circuit. In this case, the second parallel circuit is placed in the path connecting the device's source, requiring an additional resistor. While this topology is also suitable for driving GaN GIT devices, the complexity of the circuit increases significantly when selecting the device values ​​and power levels.

[0028] Further topologies that could be suitable for GaN semiconductors are known from US patent US 10,348,286 B2. It should be noted that the applicants have not specified a specific type of GaN component, but only N-channel MOSFETs are shown in the figures. It is essential that two Zener diodes are connected in series in opposite directions on the side of the component to be driven as a clamping circuit. What all of the previously listed topologies have in common is that the circuit design is complex and requires the addition of multiple elements. It should be noted that adding capacitors, in particular, often solves one problem in order to add another.

[0029] Japanese patent application JP 2007 / 336694 A is also known from the prior art. Japanese patent application JP H08 / 149796 A is also known from the prior art.

[0030] Both documents show a driver circuit for an insulated-gate semiconductor. This circuit is designed to provide a reverse turn-off bias using a simple circuit while maintaining a single voltage supply.

[0031] Similar circuit concepts are also known from the Japanese patent application JP H02 / 197 293 A.

[0032] Based on this, it is an object of the invention to provide a driver circuit that is capable of driving GaN components, in particular GaN-GIT components.

[0033] Brief description of the invention

[0034] The object is achieved by a driver circuit according to claim 1. Further advantageous embodiments are the subject of the description, the figures and the dependent claims.

[0035] Brief description of the figures

[0036] The invention is explained in more detail below with reference to a drawing and exemplary embodiments. The drawing is a schematic representation and not to scale. The drawing does not limit the invention in any way. It shows:

[0037] Fig. 1-12 each show an exemplary schematic circuit diagram of a driver circuit according to the invention for one or more power semiconductors according to an embodiment of the invention.

[0038] Detailed description of the invention

[0039] The invention will be described in more detail below with reference to the figures. It should be noted that various aspects are described, each of which can be used individually or in combination. This means that any aspect can be used with different embodiments of the invention, unless explicitly presented as a mere alternative.

[0040] Furthermore, for the sake of simplicity, reference will generally be made to only one entity in the following. Unless explicitly stated, the invention may also comprise several of the entities in question. Therefore, the use of the words "a," "an," and "another" is to be understood merely as an indication that at least one entity is used in a simple embodiment.

[0041] Where procedures are described below, the individual steps of a procedure can be arranged and / or combined in any order, unless the context explicitly indicates otherwise. Furthermore, the procedures can be combined with one another, unless expressly indicated otherwise.

[0042] Numerical values ​​are generally not to be understood as exact values, but also include a tolerance of + / - 1% to + / - 10%. Where standards, specifications, or the like are mentioned in this application, reference is always made to the standards, specifications, or the like applicable on the filing date. This means that if a standard / specification, etc., is updated or replaced by a successor, the invention is also applicable to it.

[0043] For the sake of clarity, the invention described in this document is described below using GaN semiconductors as an example, but is in principle applicable to current and future semiconductor materials and technologies. Without limiting its generality, current semiconductor technologies for which this invention is applicable include, in particular, bipolar transistors, MOSFETs, IGBTs, JFETs, HEMTs, GITs, and cascode arrays.

[0044] According to the embodiments of the invention shown in Figures 1-12, a driver circuit is provided for one or more power semiconductors SD.

[0045] Each of these driver circuits has at least one first switch S1 and at least one second switch S2. The switches are preferably semiconductor switches.

[0046] The driver circuit is connectable both to a lower switching potential L and to an upper switching potential H, whereby the at least first switch S1 and the at least second switch S2 enable a connection of the lower switching potential L or the upper switching potential H. In some embodiments of the invention, the lower switching potential can also be provided together with a zero potential O.

[0047] The driver circuit also has a capacitor C trand a Zener diode Do, with the capacitor C tr and the Zener diode Do are arranged in parallel branches, wherein the parallel branches are connected on a first side to the junction of the switches Si, S2, and wherein the parallel branches are connected on a second side to the gate terminal G of the power semiconductor SD to be driven. The driver circuit of the invention is thus capable of meeting the requirements for the gate drive voltage and the gate drive current to control the switching on and off of the power semiconductor SD.

[0048] The current and voltage peaks that affect the operating time of the SD power semiconductor and the safety of the system can be minimized or even eliminated.

[0049] In addition, the user is able to limit the maximum gate drive voltages when switching the power semiconductor SD on and off (e.g. according to the limits specified by the manufacturer).

[0050] In these completely newly configured elements of the driver circuit, a Zener diode Do is connected in parallel to the transient capacitor C tr The driver circuits according to the invention are configured to translate the logical control signals into the necessary, usually higher amplitudes that control the switching on and off of the power semiconductor(s) SD.

[0051] The driver circuits presented according to the invention are simple to construct and dimension, as essentially only a few components (max. three components) need to be dimensioned. The driver circuits according to the invention allow the transient dv / dt peaks to be limited during the initial charging of the transient capacitor due to the parallel-connected voltage regulator / suppressor Zener diode.

[0052] For the operation of a single power semiconductor SD, only the size of the transient capacitor C tr to calculate. In general, the values ​​are easy to determine based on the required negative voltage control.

[0053] If multiple power semiconductors SD are to be driven by the driver circuits according to the invention, this may require the addition of a high-value resistor in parallel with the driver circuit, which is used in the case of a single switch, but does not require complex calculations. If a manufacturer specifies safety limits for the amplitude of the maximum negative and positive gate drive voltage, these can be ensured by the driver circuits according to the invention.

[0054] Overall, the driver circuits according to the invention represent a solution to transfer a complex design into a simple logical design that meets all requirements that can be defined for a GaN GIT gate driver circuit.

[0055] With regard to Figure 1, it should be noted that the driver circuits there require only three additional passive components in addition to the Zener diode Do and the optional diodes OPT (one Zener diode and one anti-serially connected diode), namely two resistors RGON, RGOFF and one capacitor Ctr.

[0056] The diodes marked OPT are optional and are not required for GaN GIT devices because they contain an inherent clamping diode.

[0057] The Zener diode D o can be selected based on a fixed Zener diode voltage - for example, 6.3 V to 6.8 V.

[0058] The values ​​of the two resistors RGON and RGOFF can be set appropriately. Common knowledge of gate driver circuit design is sufficient; otherwise, a value suggested in the driver IC's application notes can be used.

[0059] The value of the capacitor C trcan be determined based on the maximum required negative gate drive voltage.

[0060] The operation of the driver circuit shown in Figure 1 is based on the properties of the power semiconductor SD. The power semiconductor SD has a gate-source capacitor CGS, which must be charged to turn on the power semiconductor SD. Operation depends on the state of the two switches Si, S2 in the half-bridge between H and L / O. The half-bridge is usually part of commercially available gate driver ICs. The two switches Si, S2 are not turned on simultaneously. The operation of the power semiconductor SD can be divided into "turning on" and "turning off."

[0061] Turn on:

[0062] During switching on, the switch Si on the "H" side of the half-bridge is in the on state and the switch S2 on the "L" side of the half-bridge is in the off state.

[0063] The switching-on process can be divided into two phases, namely a transient process and continuous operation.

[0064] During the transient response, the current flows from the resistor RGON and charges the capacitor C tr and the capacitor CGS of the power semiconductor SD. After charging the capacitors C tr and CGS the transient process ends because the capacitor C tr does not conduct current at constant voltage.

[0065] In steady state, ie in continuous operation, the current consumption is very low and can be covered by the leakage current of the Zener diode D flowing through the resistor RGOFF o be covered.

[0066] The RGOFF resistor is only required for GaN HEMT devices if controlled turn-off is also required. If this is not necessary, the RGOFF resistor can be omitted.

[0067] Turn off:

[0068] During turn-off, switch S2 on the "L" side of the half-bridge is in the on state, and switch Si on the "H" side of the half-bridge is in the off state. The turn-off process can be divided into two phases: a transient operation and steady-state operation.

[0069] During the transient response, the two capacitors C tr and CGS are discharged. The diodes in the OPT and the connection between resistor RGOFF and Zener diode Do each provide paths for discharging the capacitors C tr and CGS- To ensure safe turn-off for GaN HEMT components, a negative gate drive is usually recommended, as these react very sensitively to coupled disturbances. However, the present invention also enables safe turn-off with a unipolar (non-negative) supply voltage, since the capacitor C tra negative pulse can be generated. With this invention, a negative gate voltage supply is not necessary for GaN GIT components, significantly reducing the effort and cost of generating the necessary gate voltage.

[0070] The discharge of capacitor C tr provides a negative gate drive based on the time constant of the discharge path. Once the capacitors C tr and CGS are discharged, ie in continuous operation, essentially no gate current flows through the gate drive circuit.

[0071] Without limiting the generality of the invention, the driver circuit is designed for differently shaped power semiconductors SD, in particular the power semiconductor(s) SD to be driven can be of the normally-on type (self-conducting) or of the normally-off type (self-blocking).

[0072] This means that the driver circuit can be used for different application scenarios.

[0073] Without limiting the generality of the invention, the lower switching potential L may be smaller than the upper switching potential H.

[0074] In embodiments of the driver circuit, a protection circuit OPT with a further Zener diode can be provided between the gate terminal G of the power semiconductor SD to be driven and the source terminal S of the power semiconductor SD to be driven. In embodiments of the invention, it can be provided that the branch with the Zener diode Do further comprises a resistor R Go ff (see Figures 1-3, 10-12).

[0075] Likewise, in embodiments of the invention, it can be provided that the branch with the capacitor C tr still has a resistance Rcon (see Figures 1, 4, 7 , 10).

[0076] In further embodiments of the invention, it can be provided that a further branch with a resistor RGS is arranged parallel to the branches (see Figure 7-12).

[0077] According to a further embodiment of the invention, it can be provided that the one or more power semiconductors SD comprise / comprise a gallium nitride gate injection transistor.

[0078] According to yet another embodiment of the invention, the driver circuit can be designed as an at least partially integrated circuit. Likewise, in some embodiments, the driver circuit can also be designed as a (fully or at least partially) discrete circuit.

[0079] Overall, it can be stated that the driver circuits according to the embodiments of the invention enable power semiconductors SD, especially GaN components, to be driven at high frequencies (in the MHz range), even for power electronics. This allows the challenges regarding low turn-on threshold voltages to be met, as well as requirements regarding symmetrical current distribution during transient and steady-state operating conditions, a negative gate potential for safe shutdown, the significantly reduced robustness of GaN semiconductors, which leads to significantly shorter times until component failure after fault situations, and the requirement to limit gate voltages within the limits defined by the manufacturer and the manufacturing process.Unlike previous approaches, the driver circuits according to the invention allow the maximum negative gate drive voltage to be taken into account. The driver circuits according to the invention also allow the effects of losses due to dead time and the amplitude of the negative gate drive voltage to be taken into account.

[0080] List of reference symbols

[0081] Si, S2 switch

[0082] H Upper switching potential / High-side gate drive voltage L Lower switching potential / Low-side gate drive voltage

[0083] 0 Zero potential / Zero potential to the gate drive high potential

[0084] RGON resistance / turn-on gate drive resistance

[0085] RGOFF resistance / turn-off gate drive resistance

[0086] RGS resistor / gate source pull-down resistance Do Zener diode

[0087] C tr Capacitor / Gate drive transient capacitor

[0088] GS gate source node / gate source junction node

[0089] G Gate

[0090] D Drain S Source

[0091] SD Power semiconductor / Semiconductor device

[0092] OPT optional circuit elements of a protection circuit / Optional circuit elements

Claims

Claims 1. Driver circuit for one or more power semiconductors (SD), comprising • at least one first switch (Si) and at least one second switch (S2), wherein the driver circuit is connectable both to the lower switching potential and to the upper switching potential, wherein the effect of the at least first switch (Si) and the at least second switch (S2) enables a connection of the lower switching potential or the upper switching potential, • a capacitor (C tr ) and • a Zener diode (Do), • where the capacitor (C tr ) and the Zener diode (Do) are arranged in parallel branches, • wherein the parallel branches are connected on a first side to the connection of the switches (Si, S2), and • the parallel branches are connected on a second side to the gate terminal of the power semiconductor (SD) to be driven, • characterized in that the branch with the capacitor (C tr ) still has a resistance (RG O n), • and wherein a protective circuit (OPT) with a further Zener diode and an anti-serially connected diode is further provided between the gate terminal (G) of the power semiconductor (SD) to be driven and the source terminal (S) of the power semiconductor (SD) to be driven.

2. Driver circuit according to claim 1, characterized in that the device to be driven Power semiconductor (SD) is of the normally-on type.

3. Driver circuit according to claim 1, characterized in that the device to be driven Power semiconductor (SD) is of the normally-off type.

4. Driver circuit according to one of the preceding claims, characterized in that the lower switching potential is smaller than the upper switching potential.

5. Driver circuit according to one of the preceding claims, characterized in that the driver circuit further comprises a protective circuit with a further Zener diode between the gate terminal of the power semiconductor (SD) to be driven and the source terminal of the power semiconductor (SD) to be driven.

6. Driver circuit according to one of the preceding claims, characterized in that the branch with the Zener diode (Do) further comprises a resistor (Rcoff).

7. Driver circuit according to one of the preceding claims, characterized in that a further branch with a resistor (RGS) is arranged parallel to the branches.

8. Driver circuit according to one of the preceding claims, characterized in that the one or more power semiconductors (SD) comprise a gallium nitride gate injection transistor.

9. Driver circuit according to one of the preceding claims, characterized in that the driver circuit is implemented as an integrated circuit.

10. Driver circuit according to one of the preceding claims 1 to 8, characterized in that the driver circuit is implemented as a discrete circuit.

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