Semiconductor device and multi-well plate

Abstract

The present technology relates to a semiconductor device and a multi-well plate that make it possible to reduce the number of connection terminals. The semiconductor device comprises: an MEA that has an electrode array part composed of a plurality of electrodes and outputs one or more pieces of first digital data obtained by measurement using the electrode array part; and a first multiplex part that multiplexes N pieces of the first digital data output from a plurality of MEAs and outputs M pieces of second digital data, M being smaller than N. The present technology can be applied to a multi-well plate.

Description

Semiconductor device and multi-well plate

[0001] The present technology relates to a semiconductor device and a multi-well plate, and in particular to a semiconductor device and a multi-well plate that enable a reduction in the number of connection terminals.

[0002] Microelectrode arrays (MEAs) are devices that can measure cellular action potentials and thereby provide insight into the response of cells to chemical compounds.

[0003] For example, a known MEA has multiple electrodes formed by depositing electrode material on an insulating substrate such as glass, and these electrodes capture the action potential of cells, and the signal is detected by an external amplifier and AD (Analog to Digital) converter. Hereinafter, an MEA with this configuration will be specifically referred to as a conventional MEA.

[0004] For example, as a conventional MEA technology, a technology has been proposed in which a plurality of transparent MEAs formed integrally with culture wells are arranged in an array to form a culture plate (see, for example, Patent Document 1).

[0005] In response to this, MEAs using so-called CMOS (Complementary Metal Oxide Semiconductor) technology (hereinafter also referred to as CMOS-MEAs) have been developed.

[0006] With conventional MEAs, it was difficult to narrow the pitch between electrodes, but with CMOS technology, by using semiconductor lithography technology, it is possible to form finer electrodes than with conventional MEAs.

[0007] Furthermore, by using CMOS technology, the action potential detected by the electrodes can be amplified and converted to analog form inside the chip, reducing the influence of external noise and enabling the creation of an MEA with more electrodes than conventional MEAs.

[0008] Special Publication No. 2016-529889

[0009] Incidentally, multi-well plates having a plurality of wells within the plate are known.

[0010] For example, consider a multi-well plate in which one MEA is provided per well.

[0011] In such a case, if a conventional MEA is installed in the well, the multi-well plate must be provided with connection terminals (output terminals) for each MEA, equal to the number of electrodes that the MEA has, to read out the signals resulting from the measurement at the electrodes.

[0012] Therefore, as the number of wells and electrodes increases, the number of connection terminals required on the multi-well plate increases, resulting in a narrower pitch between the connection terminals and a larger number of amplifiers and AD converters required on the external device connected to the multi-well plate.

[0013] Therefore, when using conventional MEAs, it was difficult to realize a multi-well plate with a large number of wells.

[0014] Similarly, even when a CMOS-MEA is provided for each well, the greater the number of wells and electrodes, the greater the number of connection terminals (output terminals) required on the multi-well plate. Therefore, it is desirable to reduce the number of connection terminals in multi-well plates that use CMOS-MEAs.

[0015] The present technology has been made in view of such circumstances, and makes it possible to reduce the number of connection terminals.

[0016] A semiconductor device according to a first aspect of the present technology includes an MEA having an electrode array section consisting of a plurality of electrodes and outputting one or more first digital data obtained by measurement using the electrode array section, and a first multiplex section that multiplexes the N pieces of first digital data output from the plurality of MEAs and outputs M pieces of second digital data, the M pieces being less than the N pieces.

[0017] In a first aspect of the present technology, a semiconductor device is provided with an MEA having an electrode array unit consisting of a plurality of electrodes and outputting one or more first digital data obtained by measurement using the electrode array unit, and a first multiplex unit that multiplexes N pieces of the first digital data output from the plurality of MEAs and outputs M pieces of second digital data, the M pieces being less than the N pieces.

[0018] A multi-well plate according to a second aspect of the present technology is a multi-well plate provided with the semiconductor device according to the first aspect of the present technology.

[0019] FIG. 1 is a diagram showing an example of the configuration of a conventional MEA. FIG. 2 is a conceptual diagram of a measurement system using a conventional MEA. FIG. 3 is a diagram showing an example of the configuration of a CMOS-MEA. FIG. 4 is a diagram showing an external appearance image of a CMOS-MEA. FIG. 5 is a diagram showing an example of an implementation of a CMOS-MEA. FIG. 6 is a conceptual diagram of a measurement system using a CMOS-MEA. FIG. 7 is a diagram showing an example of a multi-well plate. FIG. 8 is a diagram showing an image of a multi-well plate using a conventional MEA. FIG. 9 is a diagram explaining the present technology. FIG. 10 is a diagram showing an example of the configuration of a measurement system to which the present technology is applied. FIG. 11 is a diagram showing an example of the configuration of a semiconductor device. FIG. 12 is a diagram showing an example of the configuration of a CMOS-MEA chip. FIG. 13 is a diagram showing an example of the configuration of a multiplex IC. FIG. 14 is a diagram showing an example of the configuration of a semiconductor device.

[0020] Hereinafter, embodiments to which the present technology is applied will be described with reference to the drawings.

[0021] <First embodiment> <About the present technology> The present technology enables the reduction of the number of connection terminals in a multi-well plate by providing a multiplex function that multiplexes (integrates) digital data output from multiple CMOS-MEAs.

[0022] FIG. 1 is a diagram showing an example of the configuration of a conventional MEA.

[0023] In this example, a conventional MEA 11 has a substrate 21 such as glass, on which a total of 16 electrodes, including minute electrodes 22, are formed in a 4×4 arrangement.

[0024] Each electrode is electrically connected to a connection terminal (output terminal) via a wire. For example, electrode 22 is connected to connection terminal 24 via wire 23, and signals such as cellular action potentials detected by electrode 22 are output to an external device connected to connection terminal 24 via wire 23 and connection terminal 24.

[0025] In the following, for ease of understanding, the electrodes, wiring, and connection terminals provided on the conventional MEA 11 will also be referred to as electrodes 22, wiring 23, and connection terminals 24 without any particular distinction.

[0026] FIG. 2 is a conceptual diagram of a measurement system using the conventional MEA 11 shown in FIG.

[0027] In this example, the measurement system has a conventional MEA 11 connected to a housing 51 of the device, and a cell culture well 52 formed on the conventional MEA 11 .

[0028] In particular, here, each connection terminal 24 provided on the conventional MEA 11 is connected to each connection terminal 53 on the device side provided on the housing 51 .

[0029] In addition, in the measurement system, the conventional MEA 11 is placed on the bottom of the cell culture well 52 so that each electrode 22 of the conventional MEA 11 is contained within the cell culture well 52. Cells to be measured are cultured inside this cell culture well 52. In particular, the cells are cultured in the cell culture well 52 so that they come into contact with the electrodes 22.

[0030] In the measurement system, an external device 54 is electrically connected to an equipment housing 51 via a signal transmission line, and a data acquisition system 55 is further connected to the external device 54. The external device 54 is provided with an amplifier and an AD converter.

[0031] During measurement, the action potential of cells cultured in cell culture well 52 is detected by electrode 22. An analog signal indicating the detected action potential is then read out to housing 51 via wiring 23, connection terminal 24, and connection terminal 53, and the read signal is then transmitted from housing 51 to external device 54 via a signal transmission line.

[0032] The signal read out from the housing 51 is amplified and AD converted in an external device 54, and the resulting digital data is supplied to a data acquisition system 55 and recorded as the measurement result.

[0033] In the measurement system described above, the number of connection terminals 24 on the MEA 11 side and the number of connection terminals 53 on the device housing 51 side are required to be equal to the number of electrodes 22 provided on the conventional MEA 11. Similarly, the number of signal transmission lines connecting the device housing 51 and external devices 54 is also required to be equal to the number of electrodes 22 provided on the MEA 11.

[0034] Figure 3 shows an example of the configuration of a CMOS-MEA.

[0035] In this example, the CMOS-MEA 81 has a semiconductor substrate 91 on which an electrode array section 92, a row selection circuit 93, an AD conversion circuit 94, and an output circuit 95 are formed.

[0036] The electrode array section 92 has a plurality of electrodes, including minute electrodes 101, arranged in a row direction (horizontal direction in the drawing) and a column direction (vertical direction in the drawing), i.e., in a matrix. In this example, a total of 16 electrodes, 4 × 4, are formed on the semiconductor substrate 91, similar to the example shown in FIG.

[0037] Each electrode in the electrode array unit 92 is connected to a vertical signal line via an amplification transistor and a selection transistor. For example, the electrode 101 is connected to the gate of the amplification transistor 102. The amplification transistor 102 is connected to a vertical signal line 104 via a selection transistor 103. The vertical signal line 104 is connected to the AD conversion circuit 94.

[0038] In the following, for ease of understanding, the electrodes, amplification transistors, selection transistors, and vertical signal lines provided in the electrode array unit 92 will also be referred to without any particular distinction as electrodes 101, amplification transistors 102, selection transistors 103, and vertical signal lines 104. Furthermore, the plurality of electrodes 101 arranged in the row direction will also be referred to as electrode rows, and the plurality of electrodes 101 arranged in the column direction will also be referred to as electrode columns.

[0039] For example, when the row selection circuit 93 supplies a control signal to the selection transistors 103 connected to each electrode 101 in a specific electrode row, and the selection transistors 103 are turned on (conductive), the electrode row is selected.

[0040] Then, a signal indicating the action potential of the cell detected by each electrode 101 constituting the selected electrode row is output from the electrode 101 to the AD conversion circuit 94 via the amplification transistor 102, the selection transistor 103, and the vertical signal line 104.

[0041] The AD conversion circuit 94 performs AD conversion on the analog signal indicating the action potential of such cells, and outputs the resulting digital data to the outside of the CMOS-MEA 81 via the output circuit 95 .

[0042] Figure 4 shows an external image of the CMOS-MEA 81.

[0043] In this example, in addition to the electrode array portion 92, a plurality of pads including the pad 131 are provided on the surface of the semiconductor substrate 91 along the long sides of the semiconductor substrate 91. In the following, pads similar to the pad 131 provided on the semiconductor substrate 91 will also be referred to as the pad 131 without any particular distinction.

[0044] The pads 131 are used to supply power, clocks, control signals, etc. for operating the circuits such as the row selection circuit 93 provided inside the semiconductor substrate 91, and to output digital data output from the output circuit 95 to external devices. In other words, the circuits provided inside the semiconductor substrate 91 are connected to the pads 131 via wiring or the like (not shown). The pads 131 are also connected to a substrate or the like external to the CMOS-MEA 81 by gold wires or the like.

[0045] The CMOS-MEA 81 may be mounted on a substrate 161, for example, as shown in Fig. 5. In this example, a semiconductor substrate 91 on which an electrode array section 92 is formed is mounted on the substrate 161 to form a single package, and this package can be said to be a CMOS-MEA.

[0046] In the substrate 161, for example, the semiconductor substrate 91 is electrically connected to the substrate 161 by wire bonding or the like. Note that the semiconductor substrate 91 may be housed in some kind of package and mounted on the substrate 161.

[0047] A cell culture well 162 is formed on the semiconductor substrate 91. That is, the semiconductor substrate 91 is disposed on the bottom portion of the cell culture well 162 so that each electrode 101 of the electrode array section 92 is contained within the cell culture well 162.

[0048] Furthermore, the substrate 161 is provided with a plurality of connection terminals, including a connection terminal 163, as terminals for connecting to external devices, etc. Hereinafter, these connection terminals will be simply referred to as connection terminals 163 without any particular distinction.

[0049] Pads 131 provided on semiconductor substrate 91 are connected to connection terminals 163 via, for example, wiring formed in substrate 161. Therefore, digital data output from output circuit 95, for example, is output to an external device or the like via pads 131, the wiring in substrate 161, and connection terminals 163.

[0050] FIG. 6 is a conceptual diagram of a measurement system that uses a CMOS-MEA 81 to acquire digital data indicating the measurement results of action potentials.

[0051] 5 is mounted on a housing 191 of a predetermined device. In particular, the board 161 and the housing 191 (device) are electrically connected by connecting each connection terminal 163 of the board 161 to each connection terminal, including a connection terminal 192, provided on the housing 191. Hereinafter, the connection terminal on the housing 191 side will also be referred to as the connection terminal 192 without any particular distinction.

[0052] As described above, the semiconductor substrate 91 is mounted on the substrate 161, and the cell culture well 162 is formed in the portion of the semiconductor substrate 91 where the electrode array section 92 is located.

[0053] A data acquisition system 193 is connected to the device housing 191 via a transmission line.

[0054] For example, the data acquisition system 193 supplies clocks, power supplies, GND power supplies (ground power supplies), control signals, etc. to the semiconductor substrate 91 via transmission lines, wiring and circuits within the housing 191, connection terminals 192, connection terminals 163, wiring and circuits within the substrate 161, and pads 131.

[0055] Furthermore, various digital data, such as digital data indicating the measurement results of the action potential output from the semiconductor substrate 91, is supplied to the data acquisition system 193 via the wiring and circuits in the substrate 161, the connection terminal 163, the connection terminal 192, the wiring and circuits in the housing 191, and the transmission lines. The number of transmission lines connecting the housing 191 and the data acquisition system 193 varies depending on the number and format of the digital data to be transmitted.

[0056] As described above, conventional MEAs and CMOS-MEAs are used to measure the action potential of cells in cell culture wells.

[0057] Incidentally, experiments using cell culture wells are carried out for a variety of purposes and by a variety of methods.

[0058] In particular, what is called a multi-well plate is available for observing cell reactions under various conditions.

[0059] An example of a multi-well plate is shown in Figure 7. In this example, each cylindrical portion is a well, and the multi-well plate has a total of 96 wells, arranged in an 8 x 12 array.

[0060] Standard multi-well plates are available with 6, 12, 24, 48, 96, 384, and 1536 wells, and devices for administering chemical solutions into each well and observation devices are provided according to the size of the multi-well plate.

[0061] Therefore, multi-well plates have standard sizes defined by the ANSI (American National Standards Institute) / SBS (Society for Biomolecular Screening) standard: length 127.13mm to 83mm, width 85.23mm to 85.73mm, and height 14.1mm to 14.6mm.

[0062] Multi-well plates having MEAs are also required to have a size conforming to the above-mentioned standard sizes.

[0063] Therefore, when it comes to multi-well plates with MEAs, it is necessary to consider the technical issues assuming that they will be realized in standard sizes.

[0064] Regarding a well plate having wells in which MEAs are provided, we consider making it a multi-well plate.

[0065] First, let us consider the case where a conventional MEA is used.

[0066] For example, in the case of a multi-well plate with 96 wells, each well has 4 x 4 = 16 electrodes, and 16 x 96 = 1536 connection terminals (output terminals) are required to read out the electrical signals indicating the measurement results from the multi-well plate.

[0067] A standard well plate has a base of 127.5 mm x 85.5 mm, so the circumference of the base is 426 mm.

[0068] Therefore, the pitch between adjacent electrodes is 426 mm ÷ 1536 = 0.28 mm. If the electrodes are formed in two or three rows, the pitch will be doubled or tripled, but the pitch will still be very narrow (fine).

[0069] If the number of wells in a multi-well plate increases to 384, the pitch width becomes even more stringent. Increasing the number of electrodes in each well also narrows the pitch width, making multi-well plate implementation difficult.

[0070] Figure 8 shows an image of a multi-well plate constructed using a conventional MEA, with 16 electrodes per well and a total of 96 wells.

[0071] In this example, the portion indicated by the arrow Q11 is one conventional MEA shown in FIG. 1, and this MEA has 4×4 electrodes formed thereon.

[0072] In addition, connection terminals (output terminals) for reading out signals from each electrode are drawn along the sides of the multi-well plate, but since it is not possible to draw all of the connection terminals here, some of the connection terminals are omitted. In particular, each rectangle drawn on the side represents one connection terminal.

[0073] As can be seen from the example in Figure 8, when using a conventional MEA, it is difficult to realize a multi-well plate with a large number of wells.

[0074] Furthermore, when using a conventional MEA, the device connected to the multi-well plate also requires connection terminals for connecting to the connection terminals on the multi-well plate, as well as circuits for amplifying and A / D converting the signals read by the connection terminals. For example, in the example of Figure 8, 1536 connection terminals are required on the device side.

[0075] As described above, it is not easy, if not impossible, to realize a multi-well plate using a conventional MEA.

[0076] Furthermore, even if it were possible to create such a multi-well plate and an instrument to connect it, if the number of wells were to be changed, the number of connection terminals on the instrument would also have to be changed to accommodate that change, and it is not easy to increase the number of connection terminals.

[0077] As with the conventional MEAs described above, it is difficult to achieve multi-well configuration even when using CMOS-MEAs.

[0078] For example, if there are eight lanes of digital output (differential output) for one well having a CMOS-MEA, then 16 connection terminals are required for that one well.

[0079] If a multi-well plate has 96 such wells, the multi-well plate will require 16 x 96 = 1536 connection terminals (output terminals) for reading out the signals obtained by the electrodes.

[0080] When using a CMOS-MEA, terminals for power supply, clock, etc. are also required. Even if such terminals were common to all 96 wells, the situation would still require a large number of connection terminals.

[0081] Furthermore, even if a multi-well plate using a CMOS-MEA and an instrument connected to that multi-well plate are realized, if the number of wells in the multi-well plate is changed, the number of connection terminals on the instrument side must be changed to accommodate the change, just as in the case of conventional MEAs.

[0082] As described above, in order to realize a multi-well plate using CMOS-MEA, it was necessary to have as many connection terminals (output terminals) as there were wells to read out the signals (digital data) obtained from the electrodes, making it difficult to create multiple wells.

[0083] Therefore, this technology provides a function to multiplex the digital data output from the CMOS-MEA installed in each well, thereby reducing the number of connection terminals (output terminals) that previously needed to be multiplied by the number of multi-wells.

[0084] The present technology will be described with reference to Fig. 9. Note that Fig. 9 shows a simplified configuration for ease of understanding.

[0085] 9, the multi-well plate is provided with a total of four CMOS-MEAs, arranged in a 2 x 2 configuration. Specifically, the multi-well plate is provided with CMOS-MEAs 221-1 to 221-4.

[0086] In the following description, when there is no need to particularly distinguish between the CMOS-MEAs 221-1 to 221-4, they will also be simply referred to as CMOS-MEAs 221.

[0087] In this example, one CMOS-MEA 221 is placed at the bottom of one well formed in a multi-well plate.

[0088] Each CMOS-MEA 221 has multiple electrodes, similar to the example shown in Fig. 3, and outputs digital data obtained by measurements at these multiple electrodes as measurement data. In particular, the measurement data output from CMOS-MEA 221-1 to CMOS-MEA 221-4, respectively, will be referred to as measurement data D1 to measurement data D4.

[0089] The multi-well plate is also provided with a multiplex circuit 222 consisting of a multiplex IC (Integrated Circuit) or the like.

[0090] The measurement data D1 to D4 output from the CMOS-MEAs 221-1 to 221-4 are input to this multiplex circuit 222. The multiplex circuit 222 realizes a multiplex function for multiplexing (multiplexing) this measurement data.

[0091] That is, the multiplex circuit 222 multiplexes (integrates) the measurement data supplied from each CMOS-MEA 221, and outputs the resulting single digital data as measurement data to the subsequent stage.

[0092] Specifically, for example, the multiplex circuit 222 realizes the multiplex function by outputting each piece of measurement data to one signal line in the order of measurement data D1, measurement data D2, measurement data D3, and measurement data D4. In other words, the measurement data D1, measurement data D2, measurement data D3, and measurement data D4 are arranged in order and combined to form one piece of measurement data.

[0093] As an example, it is assumed that measurement data D1 to D4 are each output from the CMOS-MEA 221 at a data rate of N [bps].

[0094] In this case, the multiplex circuit 222 outputs one measurement data set consisting of measurement data D1 to D4 at a data rate of 4N [bps], which is four times N [bps], thereby reducing the number of connection terminals that would otherwise be required by one-fourth.

[0095] Note that the number of wires used to output digital data (measurement data) from each CMOS-MEA 221 is not necessarily one, and it is also possible that one CMOS-MEA 221 and the multiplex circuit 222 are connected by multiple wires.

[0096] In such a case, two or more pieces of digital data are input from one CMOS-MEA 221 to the multiplex circuit 222. However, if the number of pieces of data output from the multiplex circuit 222 is made smaller than the total number of pieces of digital data input to the multiplex circuit 222, the number of connection terminals can be reduced.

[0097] In general, M (in this example, M=4) pieces of digital data greater than or equal to N pieces are input to the multiplex circuit 222 from a plurality of N (in this example, N=4) CMOS-MEAs 221. The multiplex circuit 222 then multiplexes the M pieces of digital data input, and outputs the resulting M' pieces of digital data, which are less than M pieces of digital data.

[0098] Each CMOS-MEA 221 may be configured as an independent Si chip (silicon chip), that is, a semiconductor chip.

[0099] In such a case, each semiconductor chip, which is the CMOS-MEA 221, is die-bonded onto a substrate made of, for example, ceramic or organic material, and each semiconductor chip (CMOS-MEA 221) is connected to a multiplex circuit 222 provided on the substrate by wiring formed on the substrate.

[0100] Furthermore, for example, instead of each CMOS-MEA 221 being an independent semiconductor chip, several CMOS-MEAs 221 may be formed on the same semiconductor chip (Si chip). In other words, the CMOS-MEAs 221 provided in each of a plurality of wells may be formed (mounted) on the same single semiconductor chip.

[0101] As an example, it is conceivable that the CMOS-MEA 221-1 and the CMOS-MEA 221-2 are formed on one semiconductor chip, and the CMOS-MEA 221-3 and the CMOS-MEA 221-4 are formed on another semiconductor chip.

[0102] Also, for example, the CMOS-MEAs 221-1 to 221-4 may all be formed on a single semiconductor chip (Si chip).

[0103] In such a case, the multiplex circuit 222 may be provided within the semiconductor chip on which the entire CMOS-MEA 221 is provided, or may be provided outside the semiconductor chip on which the entire CMOS-MEA 221 is provided.

[0104] In FIG. 9, for ease of understanding, an example in which a total of four CMOS-MEAs (2×2) are provided on a multi-well plate has been described.

[0105] However, in reality, the number of wells is much greater. For example, a typical multi-well plate has 96 or 384 wells.

[0106] In such a case, there is an advantage to applying this technology if it is possible to reduce the number of connection terminals for transmitting digital data (measurement data) output from, for example, 96 wells, i.e., 96 CMOS-MEAs 221.

[0107] As a specific example, if eight multiplex circuits 222, each with one output for 12 inputs, are used, the number of connection terminals that would normally be required, which would be 96, can be reduced to eight.

[0108] Alternatively, for example, four multiplex circuits 222 each having one output for four inputs may be used, and another multiplex circuit 222 may be used that receives the outputs from these four multiplex circuits 222 as inputs and produces one output for those inputs. In this case, 4 x 4 = 16 inputs (digital data) can be used as one output (digital data).

[0109] When a plurality of CMOS-MEAs are combined with one or a plurality of multiplex circuits to reduce the number of connection terminals, the combination method can be set arbitrarily.

[0110] In other words, the combination of CMOS-MEA and multiplex circuit can be determined appropriately depending on the number and well arrangement of wells in the multi-well plate, the number and arrangement of connection terminals on the device connected to the multi-well plate, etc.

[0111] This not only reduces the number of connection terminals in the multi-well plate or device, but also makes it easy to accommodate changes in the number of wells, etc.

[0112] For example, it becomes possible to connect and use a plurality of multi-well plates each having a different number of wells or a different well arrangement to the same device, thereby improving convenience.

[0113] In addition, for example, in the example shown in Figure 9, if the outputs (measurement data) from many CMOS-MEAs 221 are combined into one measurement data by the multiplex circuit 222, it may become impossible to determine which data making up the measurement data is the measurement data for which well (CMOS-MEA 221).

[0114] To prevent this from happening, ID information specific to the well (CMOS-MEA 221 ) may be stored in the measurement data output from the CMOS-MEA 221 .

[0115] In other words, the measurement data output from the CMOS-MEA 221 may be assigned identification information such as an ID number (ID information) that can uniquely identify the well (CMOS-MEA 221) from which the measurement data is output.

[0116] In such a case, ID information specific to each well, i.e., ID information for identifying the well, is stored (assigned) in the header data portion at the beginning of measurement data for a predetermined period, such as one frame output from the CMOS-MEA 221. This makes it possible to identify which measurement data was obtained from which well (CMOS-MEA 221).

[0117] <Configuration Example of Measurement System> FIG. 10 is a diagram showing a configuration example of an embodiment of a measurement system to which the present technology is applied.

[0118] The measurement system shown in FIG. 10 includes a multi-well plate 251 , an external device 252 , and a data acquisition system 253 .

[0119] The multi-well plate 251 is a plate in which a plurality of wells including a well 261 are formed. The well 261 is, for example, a cell culture well (organism culture well) in which cells to be observed are cultured.

[0120] Here, the multi-well plate 251 is provided with a total of 96 wells, arranged in an 8×12 configuration, but the number of wells provided in the multi-well plate 251 may be any number.

[0121] Hereinafter, the wells provided in the multi-well plate 251 will be simply referred to as wells 261 without any particular distinction.

[0122] In addition, the multi-well plate 251 has a semiconductor device 262 made of a semiconductor substrate or the like, and the semiconductor device 262 is arranged on the bottom surface (bottom part) of the multi-well plate 251, i.e., the surface part of the multi-well plate 251 facing the external device 252.

[0123] The semiconductor device 262 is provided with a plurality of CMOS-MEAs (not shown), and the CMOS-MEAs are arranged so as to be contained within the well 261 .

[0124] More specifically, for example, one CMOS-MEA provided in semiconductor device 262 has one electrode array portion consisting of multiple electrodes, and is fixed to the bottom (bottom portion) of one well 261 so that the electrode array portion is contained within one well 261.

[0125] Here, an example in which a CMOS-MEA is provided as the MEA will be described, but the MEA provided in the semiconductor device 262 is not limited to this, and any MEA that outputs one or more digital data (measurement data) indicating the measurement result, in other words, that has an AD conversion function, may be used.

[0126] Cells to be measured (observed) are cultured in each well 261. At this time, the cells are cultured so that they are positioned on (in contact with) at least one electrode provided in the electrode array section.

[0127] In the following, an example will be described in which one CMOS-MEA is provided for one well 261, but one CMOS-MEA may be provided for multiple wells 261. In such a case, for example, multiple electrode array units, such as 2 x 2, are provided in one CMOS-MEA, and one electrode array unit is included in the bottom of one well 261.

[0128] In the measurement system, the multi-well plate 251 is placed on an external device 252, and a connection terminal (not shown) provided on the multi-well plate 251 is connected to a plurality of connection terminals including a connection terminal 263 on the external device 252. This electrically connects the multi-well plate 251 and the external device 252 via the connection terminals.

[0129] In the following description, the connection terminal provided on the external device 252 for connecting to the multi-well plate 251 will be simply referred to as the connection terminal 263 without any particular distinction.

[0130] Also, for ease of viewing, the figure shows the multi-well plate 251 not being placed on the external device 252, but in reality, the multi-well plate 251 is used in a state where it is placed on the external device 252.

[0131] A data acquisition system 253 is connected to the external device 252 via one or more transmission lines. For example, the data acquisition system 253 is configured by a computer or the like.

[0132] For example, the data acquisition system 253 supplies clocks, power, GND power (ground power), control signals, etc. to the semiconductor device 262 via transmission lines, wiring and circuits within the external device 252, and connection terminals 263.

[0133] Furthermore, various digital data, such as digital data indicating measurement results of action potentials and the like output from the semiconductor device 262, is supplied to the data acquisition system 253 via the connection terminal 263, wiring and circuits within the external device 252, and transmission lines. The number of transmission lines connecting the external device 252 and the data acquisition system 253 varies depending on the number and format of the digital data to be transmitted.

[0134] The semiconductor device 262 provided on the bottom of the multi-well plate 251 has, for example, the configuration shown in FIG.

[0135] 11, a plurality of CMOS-MEA chips arranged in an array, including a CMOS-MEA chip 292, are die-bonded (arranged) on a single substrate 291, such as a substrate made of ceramic or organic material, or a semiconductor substrate. Each CMOS-MEA chip is composed of an independent semiconductor chip.

[0136] In this example, 6 x 5 = 30 CMOS-MEA chips are shown for ease of viewing, but in reality, the number of CMOS-MEA chips provided in the entire semiconductor device 262 corresponds to the number of wells 261. For example, the number of CMOS-MEA chips provided in the entire semiconductor device 262 can be the same as the standard number of wells, such as 6, 12, 96, or 1536.

[0137] The CMOS-MEA chip 292 is a semiconductor chip made of, for example, a silicon substrate (semiconductor substrate) and functions as a CMOS-MEA. That is, the CMOS-MEA chip 292 has an electrode array unit made of multiple electrodes, and outputs one or more measurement data (digital data) obtained by measurement using the electrode array unit.

[0138] Note that the CMOS-MEA chip 292 may be mounted on the substrate 291 by any method. For example, the CMOS-MEA chip 292 may be wire-bonded to the substrate 291 by gold wires. That is, the CMOS-MEA chip 292 may be connected to the substrate 291 by wires such as gold wires. The CMOS-MEA chip 292 may also be connected to the substrate 291 by solder bumps or the like.

[0139] Hereinafter, the CMOS-MEA chip provided on the substrate 291 will also be referred to as a CMOS-MEA chip 292 without any particular distinction.

[0140] A multiplex IC 293 that functions as a multiplex circuit is also mounted on the substrate 291 , and each CMOS-MEA chip 292 and the multiplex IC 293 are connected by wiring 294 formed on the substrate 291 .

[0141] Therefore, measurement data, which is digital data obtained by measurement in each CMOS-MEA chip 292 , is supplied to the multiplex IC 293 via wiring 294 .

[0142] In addition, a circuit or the like that performs some kind of signal processing on the digital data output from the CMOS-MEA chip 292 may be connected between the CMOS-MEA chip 292 and the multiplex IC 293 .

[0143] One or more digital data (measurement data) obtained by measurement is supplied from one CMOS-MEA chip 292 to the multiplex IC 293. In other words, two or more digital data may be supplied from the CMOS-MEA chip 292 to the multiplex IC 293.

[0144] Basically, in the multi-well plate 251, one CMOS-MEA chip 292 is provided for one well 261. For example, the CMOS-MEA chip 292 is provided with one electrode array unit consisting of a plurality of electrodes, and the electrode array unit is disposed at the bottom portion (bottom) of the well 261 so that the electrode array unit is contained within the well 261. The electrode array unit referred to here is the electrode array unit 322 in FIG. 12 , which will be described later.

[0145] Alternatively, multiple electrode array units can be provided on one CMOS-MEA chip 292. In such a case, for example, each of the multiple electrode array units can be arranged in a plurality of different wells 261. In other words, one CMOS-MEA chip 292 can be arranged at the bottoms of a plurality of wells 261.

[0146] In this way, when a plurality of electrode array units are provided on the CMOS-MEA chip 292, digital data (measurement data) obtained by measurement can be output for each of these electrode array units from the CMOS-MEA chip 292 to the multiplex IC 293. In particular, in such a case, wiring 294 connecting the CMOS-MEA chip 292 and the multiplex IC 293 may be provided in the same number as the number of digital data to be output.

[0147] The multiplex IC 293 multiplexes the digital data (measurement data) supplied from each of the multiple CMOS-MEA chips 292 via wiring 294, and outputs the resulting digital data (measurement data) to a connection terminal 295 via wiring, etc.

[0148] In the example of FIG. 11, a CMOS-MEA chip 292 and a multiplex IC 293 correspond to the CMOS-MEA 221 and the multiplex circuit 222 shown in FIG.

[0149] The connection terminal 295 is a terminal (output terminal) formed on the substrate 291. For example, the connection terminal 295 is directly connected to the connection terminal 263 of the external device 252, or is indirectly connected to the connection terminal 263 via a circuit, wiring, or the like provided in the semiconductor device 262.

[0150] The connection terminal 295 supplies the digital data (measurement data) output from the multiplex IC 293 to the external device 252 via the connection terminal 263 .

[0151] A circuit for performing some kind of signal processing on the measurement data may be provided between the connection terminal 295 and the multiplex IC 293 .

[0152] The circuit that performs signal processing on the measurement data may be provided between the connection terminal 295 and the connection terminal 263 on the substrate 291, between the connection terminal 263 and the connection terminal 295 in the external device 252, or downstream of the connection terminal 263 in the external device 252, etc.

[0153] The digital data output from the multiplex IC 293 is not limited to being transmitted to the external device 252 via the connection terminal 295, and may be supplied to the external device 252 by other methods.

[0154] For example, the digital data (measurement data) output from the multiplex IC 293 may be transmitted to the external device 252 by an IC provided on the substrate 291 and having a transceiver function capable of transmitting digital data to the external device 252, i.e., capable of being connected to the external device 252.

[0155] Furthermore, although an example is shown here in which one piece of digital data (measurement data after multiplexing) is output from the multiplex IC 293 to the connection terminal 295, two or more pieces of digital data may be output from the multiplex IC 293. In such a case, for example, the substrate 291 is provided with connection terminals 295 equal to the number of digital data to be output, and the digital data is output from the multiplex IC 293 to each of the plurality of connection terminals 295.

[0156] In general, suppose that a total of N pieces of digital data (measurement data) are supplied (output) from multiple CMOS-MEA chips 292 to the multiplex IC 293. In this case, the multiplex IC 293 multiplexes the N pieces of input digital data to generate M pieces of digital data (where M is 1 or greater), which is less than N, and outputs each of the M pieces of digital data (measurement data) obtained by multiplexing to the connection terminal 295.

[0157] The semiconductor device 262 has at least one substrate 291 on which the above-described CMOS-MEA chip 292 and multiplex IC 293 are provided.

[0158] That is, the semiconductor device 262 may be configured from one substrate 291 or from two or more substrates 291 .

[0159] Furthermore, for example, multiple configurations each consisting of multiple CMOS-MEA chips 292, a multiplex IC 293 to which those CMOS-MEA chips 292 are connected, and a connection terminal 295 may be provided on one substrate 291.

[0160] In addition, multiple configurations each consisting of multiple CMOS-MEA chips 292 and multiplex ICs 293 to which these CMOS-MEA chips 292 are connected may be provided on the substrate 291, and a multiplex IC that multiplexes the digital data output from the multiple multiplex ICs 293 may be further provided.

[0161] In this case, the multiplex IC multiplexes a total of P (where P is 2 or more) pieces of digital data output from multiple multiplex ICs 293, and outputs Q (where Q is 1 or more) pieces of digital data, which is less than P, to connection terminals 295, etc.

[0162] A further multiplex IC may be provided that multiplexes measurement data (digital data) output from one or more multiplex ICs 293 with measurement data output from one or more CMOS-MEA chips 292, and outputs one or more multiplexed measurement data that are fewer than the number of input measurement data.

[0163] Alternatively, multiple boards 291 may be mounted on another board, and a multiplex IC that multiplexes the digital data (measurement data) output from the multiple boards 291 (multiplex IC 293) may be provided on the other board.

[0164] A CMOS-MEA chip 292 that functions as a CMOS-MEA is configured, for example, as shown in FIG.

[0165] In the example of Figure 12, the CMOS-MEA chip 292 has a semiconductor substrate 321, on which an electrode array section 322, a row selection circuit 323, an AD conversion circuit 324, an ID assignment section 325, and an output circuit 326 are formed.

[0166] The electrode array section 322 has a plurality of electrodes including minute electrodes 331 arranged in a row direction (horizontal direction in the drawing) and a column direction (vertical direction in the drawing), that is, in a matrix.

[0167] Here, a total of 16 electrodes in a 4×4 arrangement are formed on the semiconductor substrate 321, but the number of electrodes constituting the electrode array section 322 may be any number.

[0168] Each electrode in the electrode array section 322 is connected to a vertical signal line via an amplification transistor and a selection transistor. For example, the electrode 331 is connected to the gate of the amplification transistor 332. The amplification transistor 332 is connected to a vertical signal line 334 via a selection transistor 333. The vertical signal line 334 is connected to the AD conversion circuit 324.

[0169] Hereinafter, the electrodes, amplification transistors, selection transistors, and vertical signal lines provided in the electrode array section 322 will also be referred to as electrodes 331, amplification transistors 332, selection transistors 333, and vertical signal lines 334 without any particular distinction.

[0170] The electrode array unit 322 is placed at the bottom of one of the wells 261. For example, when cells are cultured in the well 261 so that they come into contact with the electrodes 331 of the electrode array unit 322, the action potential of the cells observed at the electrodes 331 changes due to the electrical activity of the cells.

[0171] Therefore, a signal corresponding to the action potential of the cell is supplied from the electrode 331 to the gate of the amplifying transistor 332. As a result, a signal corresponding to the signal supplied to the gate, i.e., a signal corresponding to the action potential of the cell, is output from the amplifying transistor 332 to the selecting transistor 333. The signal supplied from the amplifying transistor 332 to the selecting transistor 333 is an analog signal indicating the measurement result of the action potential, i.e., an analog signal obtained by measuring the action potential.

[0172] In the electrode array section 322, a selection transistor 333 is connected to each electrode 331 via an amplification transistor 332. The gate of the selection transistor 333 connected to each electrode 331 constituting an electrode row is connected to a signal line wired along the electrode row, and the end of the signal line is connected to the row selection circuit 323.

[0173] When the row selection circuit 323 supplies a control signal to the gate of each selection transistor 333 in an electrode row via a signal line to select the electrode row, the selection transistor 333 connected to the electrode 331 that constitutes that electrode row is turned on (conductive), i.e., selected.

[0174] When the selection transistor 333 is turned on, the analog signal indicating the measurement result output from the amplification transistor 332 is output (supplied) to the AD conversion circuit 324 via the selection transistor 333 and the vertical signal line 334 .

[0175] Selection transistors 333 connected to the electrodes 331 constituting the electrode column are connected to the vertical signal lines 334. For example, the row selection circuit 323 selects each electrode row in turn and turns on only the selection transistors 333 of the selected electrode row, whereby analog signals for the electrodes 331 constituting the selected electrode row are output in turn to the AD conversion circuit 324.

[0176] The AD conversion circuit 324 performs AD conversion on the analog signal supplied from the amplification transistor 332 via the vertical signal line 334 and the selection transistor 333, and supplies the resulting digital data to the ID assignment unit 325. The digital data thus supplied to the ID assignment unit 325 is measurement data obtained by measuring the action potential of the cell using the electrode 331 (electrode array unit 322).

[0177] The ID assigning section 325 is made up of a digital circuit having a memory, and holds (records) ID information that can uniquely identify the well 261 including the electrode array section 322 .

[0178] For example, the ID information held in the ID assigning unit 325 is identification information such as information indicating a well number specific to the well 261 including the electrode array unit 322 .

[0179] When measurement data (digital data) is supplied from the AD conversion circuit 324, the ID assignment unit 325 assigns (adds) the ID information it holds to the measurement data, and supplies the measurement data with the ID information assigned to it to the output circuit 326.

[0180] For example, the ID assigning unit 325 assigns ID information to one frame of measurement data. At this time, ID information specific to each well is stored (assigned) in the header data portion at the beginning of one frame of measurement data. This makes it possible to determine which CMOS-MEA chip 292 (semiconductor substrate 321) the measurement data output from the CMOS-MEA chip 292 (i.e., which well 261) represents the measurement results.

[0181] The output circuit 326 outputs the measurement data (digital data) supplied from the ID assignment unit 325, more specifically, the measurement data to which ID information has been assigned (measurement data to which ID information has been assigned), to the outside of the semiconductor substrate 321.

[0182] The measurement data output from the output circuit 326 is supplied to a multiplex IC 293 via a wiring 294, as shown in FIG. 11, for example.

[0183] As described above, ID information is added (stored) at the beginning of the measurement data. Therefore, by referring to the ID information in the multiplexed measurement data output from the multiplex IC 293, it is possible to identify which well 261 the data containing the ID information belongs to.

[0184] 12 has been described as an example in which one electrode array section 322 is formed on the semiconductor substrate 321 that constitutes the CMOS-MEA chip 292. However, this is not limiting, and two or more electrode array sections 322 may be formed on the semiconductor substrate 321.

[0185] In such a case, for example, one electrode array unit 322 is arranged in one well 261. Furthermore, when multiple electrode array units 322 are formed on the semiconductor substrate 321, a drive circuit for driving the electrode array unit 322, such as the row selection circuit 323, may be formed for each electrode array unit 322, or a drive circuit such as the row selection circuit 323 may be formed that is common to the multiple electrode array units 322. Furthermore, a circuit that performs some kind of signal processing on the measurement data may be provided before or after the ID assignment unit 325.

[0186] FIG. 13 shows an example of the configuration of the multiplex IC 293 shown in FIG.

[0187] In the example shown in FIG. 13, the multiplex IC 293 includes buffers 361-1 through 361-4 and a select circuit 362.

[0188] Measurement data (digital data) output from the CMOS-MEA chip 292 is supplied to the buffers 361-1 to 361-4 via the wiring 294.

[0189] Hereinafter, when there is no need to particularly distinguish between the buffers 361-1 to 361-4, they will also be simply referred to as buffers 361.

[0190] Each buffer 361 is supplied with measurement data to which ID information has been added, which is output from a different CMOS-MEA chip 292, more specifically, from a different output circuit 326.

[0191] The buffer 361 temporarily holds the measurement data supplied from the CMOS-MEA chip 292 (output circuit 326 ), and then supplies it to the select circuit 362 .

[0192] In particular, hereinafter, the measurement data supplied to the buffers 361-1 to 361-4 will also be referred to as measurement data DT1 to DT4.

[0193] In order to make the diagram easier to understand, the number of measurement data input to the multiplex IC 293 is set to four, but in reality, in the example of Figure 11, at least 30 measurement data are input to the multiplex IC 293.

[0194] The select circuit 362 selects and outputs the measurement data supplied from each of the plurality of buffers 361 in order, thereby realizing a multiplex function.

[0195] That is, the select circuit 362 multiplexes the supplied measurement data DT1 to DT4 and outputs one measurement data consisting of the measurement data DT1 to DT4 to the connection terminal 295. Therefore, in this example, a multiplex IC 293 with one output from four inputs is realized.

[0196] The select circuit 362 has switches 371-1 to 371-4.

[0197] The switches 371-1 to 371-4 are made up of, for example, transistors, and are turned on and off in response to a select signal supplied from a circuit or the like within the substrate 291. That is, the switches 371-1 to 371-4 are turned on (conductive) or off (non-conductive) in response to the select signal.

[0198] When the switches 371-1 to 371-4 are turned on, they output the measurement data DT1 to DT4 held in the buffers 361-1 to 361-4, respectively, to the connection terminal 295 in the subsequent stage.

[0199] For example, in the select circuit 362, the switches 371-1 to 371-4 are selected in order, and while one switch is turned on, the other three switches are turned off, thereby outputting the measurement data of each well 261 in order.

[0200] In the following description, when there is no need to particularly distinguish between the switches 371-1 to 371-4, they will also be simply referred to as switches 371.

[0201] A specific example of multiplexing the measurement data DT1 to DT4 will be described.

[0202] For example, assume that measurement data DT1 to DT4 are input simultaneously or approximately simultaneously to buffers 361-1 to 361-4 at D Hz, respectively. In this case, new measurement data is input to each buffer 361 every 1 / D seconds.

[0203] For example, first, the switch 371-1 is selected (turned on) by a select signal, and the measurement data DT1 held in the buffer 361-1 is output from the switch 371-1 at 4×D Hz. In this case, it takes 1 / (4×D) seconds to output the measurement data DT1.

[0204] Thereafter, the switches 371-2, 371-3, and 371-4 are selected in turn in the same manner by the select signal, and as a result, the measurement data DT2, DT3, and DT4 are output from each switch 371 in turn.

[0205] As in the case of the measurement data DT1, 1 / (4×D) seconds are required to output each of the measurement data DT2, DT3, and DT4.

[0206] By selecting the switches 371 in this order, one digital data obtained by arranging (combining) the measurement data DT1 to DT4 in order is output from the select circuit 362.

[0207] Since it takes 1 / (4×D) seconds to output each of the measurement data DT1 to DT4, it takes a total of 1 / D seconds to output all of the measurement data DT1 to DT4. In other words, output of all the measurement data is completed in 1 / D seconds. Therefore, it is possible to multiplex the four measurement data without causing delay and output them as one measurement data.

[0208] The configuration of the multiplex IC 293 is not limited to the configuration shown in FIG. 13, and any configuration may be used as long as it can realize the multiplex function.

[0209] In the above, an example in which the substrate 291 shown in FIG. 11 is provided has been described as an example of the semiconductor device 262 provided on the bottom of the multi-well plate 251 .

[0210] However, the configuration of the semiconductor device 262 is not limited to the example shown in Fig. 11 and may be any other configuration. As an example, the configuration of the semiconductor device 262 may be a configuration including a semiconductor substrate 401 shown in Fig. 14. Note that in Fig. 14, parts corresponding to those in Fig. 11 are assigned the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0211] In the example shown in FIG. 14, a plurality of CMOS-MEAs including a CMOS-MEA 402 are formed on a semiconductor substrate 401 made of a silicon substrate or the like.

[0212] In this example, as in Figure 11, 6 x 5 = 30 CMOS-MEAs are drawn to make the diagram easier to see, but in reality, the entire semiconductor device 262 is provided with CMOS-MEAs in numbers corresponding to the number of wells 261.

[0213] The CMOS-MEA 402 has, for example, the electrode array section 322, row selection circuit 323, AD conversion circuit 324, ID assignment section 325, and output circuit 326 shown in Figure 12, and the CMOS-MEA 402 is integrally formed within the semiconductor substrate 401.

[0214] Therefore, in this example, one semiconductor chip (silicon chip) is configured by one semiconductor substrate 401 on which multiple CMOS-MEAs, including the CMOS-MEA 402, are formed. In other words, multiple CMOS-MEAs are provided on one semiconductor chip.

[0215] Hereinafter, the CMOS-MEA formed on the semiconductor substrate 401 will also be referred to as a CMOS-MEA 402 without any particular distinction.

[0216] In the example shown in Figure 11, multiple CMOS-MEA chips 292, which are individual independent semiconductor chips, are mounted on a substrate 291, whereas in the example shown in Figure 14, each CMOS-MEA 402 is formed on a semiconductor substrate 401 that constitutes a single semiconductor chip.

[0217] A plurality of CMOS-MEAs 402 are formed in an array on a semiconductor substrate 401, and these CMOS-MEAs 402, particularly the output circuits 326 within the CMOS-MEAs 402, are connected to a multiplex IC 293 via wiring 294 formed on the semiconductor substrate 401. Furthermore, a connection terminal 295 is connected to the multiplex IC 293 via wiring on the semiconductor substrate 401, etc.

[0218] Therefore, in this example, the measurement data output from the output circuit 326 of each CMOS-MEA 402 is input to the multiplex IC 293 via the wiring 294. Then, the measurement data is multiplexed in the multiplex IC 293, and one measurement data obtained by the multiplexing is output from the multiplex IC 293 to the connection terminal 295.

[0219] The semiconductor device 262 has at least one semiconductor substrate 401, which is the semiconductor chip described above. That is, the semiconductor device 262 may be configured with one semiconductor substrate 401, or may be configured with two or more semiconductor substrates 401.

[0220] According to the present technology as described above, the number of connection terminals (output terminals) can be reduced even in the case of a multi-well configuration. In other words, even in the case of a multi-well configuration, it is not necessary to increase the number of connection terminals.

[0221] This eliminates the need for a measurement system to have circuits for receiving (acquiring) measurement data in multiples of the number of wells in the multi-well plate, and allows the multi-well plate to be installed with practical dimensions in an installation location with a fixed physical size.

[0222] Furthermore, according to the present technology, even when multi-well plates with different numbers of wells are used, the system can be configured with the same number of connection terminals for the multi-well plates with different numbers of wells and for external devices connected to the multi-well plates.

[0223] That is, in a system that uses multi-well plates with different numbers of wells depending on the application, the number of connection terminals on the system side can be made common regardless of the type of wells (number of wells, well arrangement, etc.).

[0224] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology.

[0225] Furthermore, the present technology can also be configured as follows.

[0226] (1) A semiconductor device comprising: an MEA having an electrode array unit consisting of a plurality of electrodes, the MEA outputting one or more first digital data obtained by measurement using the electrode array unit; and a first multiplex unit multiplexing N pieces of the first digital data output from the plurality of MEAs and outputting M pieces of second digital data, the M being less than N. (2) The semiconductor device according to (1), wherein the MEA is a CMOS-MEA. (3) The semiconductor device according to (1) or (2), wherein the electrode array unit is disposed in a well of a multi-well plate. (4) The semiconductor device according to (3), wherein the MEA outputs the first digital data provided with identification information capable of identifying the well. (5) The semiconductor device according to any one of (1) to (4), wherein each of the plurality of MEAs is constituted by a respective one of a plurality of semiconductor chips. (6) The semiconductor device according to (5), wherein a plurality of the semiconductor chips are disposed on a single substrate. (7) The semiconductor device according to (6), wherein the semiconductor chips are connected to the substrate by solder bumps or wires. (8) The semiconductor device according to any one of (1) to (4), wherein a plurality of the MEAs are provided on one semiconductor chip. (9) The semiconductor device according to any one of (1) to (8), wherein the MEA has a plurality of the electrode array units, and each of the plurality of electrode array units is arranged in a different well of a multi-well plate. (10) The semiconductor device according to any one of (1) to (9), further comprising a second multiplex unit that multiplexes P pieces of the second digital data output from a plurality of the first multiplex units and outputs Q pieces of third digital data, the Q pieces being less than the P pieces.(11) A multi-well plate having a plurality of wells, comprising a semiconductor device provided at the bottom of the multi-well plate, the semiconductor device comprising: an MEA having an electrode array section consisting of a plurality of electrodes arranged in the wells, which outputs one or more first digital data obtained by measurement using the electrode array section; and a multiplex section which multiplexes the N pieces of first digital data output from the plurality of MEAs and outputs M pieces of second digital data, the M pieces being less than the N pieces.

[0227] 251 Multi-well plate, 252 External device, 253 Data acquisition system, 261 Well, 262 Semiconductor device, 263 Connection terminal, 291 Substrate, 292 CMOS-MEA chip, 293 Multiplex IC, 295 Connection terminal, 322 Electrode array unit, 325 ID assignment unit, 401 Semiconductor substrate, 402 CMOS-MEA

Claims

1. A semiconductor device comprising: an MEA having an electrode array section consisting of a plurality of electrodes, which outputs one or more first digital data obtained by measurement using the electrode array section; and a first multiplex section which multiplexes N pieces of the first digital data output from the plurality of MEAs and outputs M pieces of second digital data, the M being less than the N pieces.

2. The semiconductor device according to claim 1, wherein the MEA is a CMOS-MEA.

3. The semiconductor device according to claim 1, wherein the electrode array portion is disposed within a well of a multi-well plate.

4. The semiconductor device according to claim 3, wherein the MEA outputs the first digital data to which identification information capable of identifying the well is added.

5. The semiconductor device according to claim 1, wherein each of the plurality of MEAs is constituted by a respective one of a plurality of semiconductor chips.

6. The semiconductor device according to claim 5, wherein a plurality of said semiconductor chips are arranged on one substrate.

7. The semiconductor device according to claim 6, wherein the semiconductor chip is connected to the substrate by solder bumps or wires.

8. The semiconductor device according to claim 1, wherein a plurality of said MEAs are provided on one semiconductor chip.

9. The semiconductor device according to claim 1, wherein the MEA has a plurality of the electrode array sections, each of the plurality of electrode array sections being arranged in a different well of a multi-well plate.

10. The semiconductor device according to claim 1, further comprising a second multiplex section that multiplexes P pieces of the second digital data output from a plurality of the first multiplex sections and outputs Q pieces of third digital data, the Q pieces being less than the P pieces.

11. A multi-well plate having a plurality of wells, comprising a semiconductor device provided at the bottom of the multi-well plate, the semiconductor device comprising: an MEA having an electrode array portion consisting of a plurality of electrodes arranged in the wells, which outputs one or more first digital data obtained by measurement using the electrode array portion; and a multiplex portion multiplexing the N pieces of first digital data output from the plurality of MEAs and outputting M pieces of second digital data, the M being less than the N pieces.

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