Processing-in-memory device for performing in-memory operation using refresh operation

Abstract

Provided is a processing-in-memory device performing an in-memory operation by using a refresh operation. The processing-in-memory device according to an embodiment of the present invention comprises: a memory cell that is refreshed at regular intervals; a row buffer that temporarily stores column data of the memory cell to be refreshed; and a calculator that stores, in the row buffer, a calculation result obtained by using the column data that has been stored in the row buffer during a refresh operation and causes the calculation result to be written to the memory cell. Accordingly, an in-memory operation can be performed by using a refresh operation, thereby enabling an energy-efficient operation, and a space-efficient processing-in-memory can be implemented by performing an in-memory operation by using a row buffer during a refresh operation.

Description

A processing-in-memory device that performs in-memory operations using refresh operations.

[0001] The present invention relates to processing-in-memory that performs operations within a memory, and more particularly, to a method for performing operations within a memory while minimizing power consumption and space overhead.

[0002] The DRAM-based processing-in-memory structure that has been studied so far performs operations by inserting additional vector registers and operation units (ALUs) into memory cells in addition to the DRAM circuit.

[0003] However, because the size of the vector register required for smooth operation is generally large, there is a problem that it is difficult to manufacture a processing-in-memory device using actual DRAM.

[0004] Additionally, separate time is required to issue commands and read data to perform operations in processing-in-memory, which reduces memory performance compared to existing DRAMs and increases power consumption due to increased number of DRAM operations.

[0005] The present invention has been devised to solve the above problems, and the purpose of the present invention is to provide a method for performing in-memory operations using a refresh operation and a processing-in-memory device applying the same as a method for implementing a processing-in-memory capable of energy-efficient operation.

[0006] In addition, another object of the present invention is to provide a method for performing in-memory operations using a row buffer during a refresh operation and a processing-in-memory device applying the method, as a means for implementing space-efficient processing-in-memory.

[0007] According to one embodiment of the present invention for achieving the above object, a processing-in-memory device includes: a memory cell that refreshes at regular intervals; a row buffer in which column data of a memory cell to be refreshed is temporarily stored; and an operator that stores an operation result using the column data stored in the row buffer during a refresh operation in the row buffer so that it is written to the memory cell.

[0008] When a refresh command for the Nth column arrives, the operator can perform an operation using the column data stored in the row buffer.

[0009] The operator can temporarily store the result of the operation in the output register.

[0010] When a refresh command for the N+1th column arrives, the operator can store the operation result temporarily stored in the output register in the Row buffer and write it to the memory cell.

[0011] When a refresh command for the Nth column data arrives, the row buffer can temporarily store the Nth column data stored in the memory cell and then write it back to the memory cell.

[0012] When a refresh command for the N+1th column arrives, the row buffer can write the operation result stored by the operator to the memory cell instead of temporarily storing the N+1th column data stored in the memory cell.

[0013] The row buffer may not be closed when a refresh command for the Nth column arrives.

[0014] The processing-in-memory device according to the present invention further includes a status register in which setting information for the processing-in-memory is stored, and the operator can perform an operation according to the setting information of the status register.

[0015] The row buffer can temporarily store the column data of the memory cells to be refreshed and then write them to the memory cells when the operator is not performing processing-in-memory operations.

[0016] According to another aspect of the present invention, a processing-in-memory method is provided, characterized by including: a step of temporarily storing column data of a memory cell to be refreshed in a row buffer; a step of storing an operation result using the column data stored in the row buffer during a refresh operation in the row buffer; and a step of writing the operation result stored in the row buffer to a memory cell.

[0017] According to another aspect of the present invention, a processing-in-memory device is provided, comprising: a memory cell that refreshes at regular intervals; a row buffer in which column data of a memory cell to be refreshed is temporarily stored; a status register in which setting information for processing-in-memory is stored; an output register in which an operation result of an operator is temporarily stored; and an operator that temporarily stores an operation result using column data stored in the row buffer based on the setting information stored in the status register during a refresh operation in an output register and then stores the result in the row buffer so that it is written to a memory cell.

[0018] According to another aspect of the present invention, a processing-in-memory method is provided, comprising: a step of storing setting information for processing-in-memory in a status register; a step of temporarily storing column data of a memory cell to be refreshed in a row buffer; a step of temporarily storing an operation result using the column data stored in the row buffer based on the setting information stored in the status register during a refresh operation in an output register; a step of storing the operation result temporarily stored in the output register in a row buffer; and a step of writing the operation result stored in the row buffer to a memory cell.

[0019] As described above, according to embodiments of the present invention, it is possible to perform in-memory operations using a refresh operation, thereby implementing processing-in-memory capable of energy-efficient operation.

[0020] In addition, according to embodiments of the present invention, space-efficient processing-in-memory can be implemented by performing in-memory operations using a row buffer during a refresh operation.

[0021] Figure 1. Computer system structure using DDRAM to which the present invention is applicable.

[0022] Figure 2. DRAM internal bank structure diagram

[0023] Figure 3. DRAM-based PIM structure diagram to which an embodiment of the present invention can be applied.

[0024] Figure 4. Structure diagram of a PIM device operating on a refresh basis according to one embodiment of the present invention.

[0025] Figure 5. Operation flowchart of a refresh-based PIM according to another embodiment of the present invention.

[0026] Hereinafter, the present invention will be described in more detail with reference to the drawings.

[0027] An embodiment of the present invention proposes a processing-in-memory device that performs in-memory operations using refresh operations. This technology utilizes the refresh operations of processing-in-memory to perform data operations while minimizing power consumption and space overhead.

[0028] By performing in-memory operations using refresh operations, it is possible to perform operations more energy-efficiently than conventional processing-in-memory, and by utilizing the row buffer, it is possible to implement in-memory operations with simplified logic compared to conventional processing-in-memory devices.

[0029] Figure 1 is a diagram illustrating the structure of a computer system using DRAM to which the present invention is applicable. The DRAM is configured in channel units that are independently controlled and operated by a memory controller within the processor, and each channel is configured with one or more DIMMs (Dual In-line Memory Modules).

[0030] A DIMM represents a single DRAM product mounted in a memory slot. Each channel consists of multiple ranks that operate independently but share a memory bus. A single DIMM can contain one or more ranks. Each rank is packaged with multiple DRAM chips, and during operation, it is divided into multiple banks, with each bank performing the same operation.

[0031] Figure 2 illustrates the internal bank structure of a DRAM. As illustrated, a bank comprises memory cells organized into columns and rows where actual data is stored, a row decoder for selecting a specific column, a column decoder for selecting a specific row within a column, and a row buffer for temporarily storing a designated column.

[0032] DRAM temporarily stores data from a selected column in a row buffer, uses a column decoder to select and read a specific row within the column, and then outputs the data to the bus. Once all data output is complete, the operation is completed by writing the data from the row buffer back to the column of DRAM cells.

[0033] Meanwhile, DRAM cells have a problem where data is lost after a certain period of time. To prevent data loss, the refresh command is used to read data into a low buffer and then write it back to the DRAM cells. This is called a refresh operation.

[0034] To prevent data corruption, all DRAM cells are typically refreshed once every 64ms, and normal data read and write operations cannot be performed on a bank that is undergoing a refresh operation.

[0035] Figure 3 illustrates a DRAM-based PIM structure to which an embodiment of the present invention can be applied. As illustrated, within the DRAM bank, there are memory cells, I / O circuits responsible for data input / output, and a processing unit for performing operations within the DRAM is added.

[0036] A processing unit may exist in all banks, but multiple banks may share a single processing unit. The detailed structure of the processing unit varies depending on the operations supported by the PIM, but generally, as illustrated on the right side of Figure 3, it consists of an input register that receives data from the I / O circuit of each bank and temporarily stores the data, a number of ALUs (Arithmetic Logic Units) where the actual operations are performed, and an output register that transfers the calculated data back to the bank I / O.

[0037] PIM is configured to receive PIM operation commands or instructions from the host or memory controller, perform the specified PIM operation, and write the result to a specified location to perform the operation within the memory.

[0038] FIG. 4 illustrates a structural diagram of a PIM device operating on a refresh basis according to one embodiment of the present invention. Unlike FIG. 3, where the Processing Unit for PIM operations was located next to the bank I / O circuit, in the embodiment of the present invention, the computational function of the Processing Unit is integrated within the bank I / O, and the input register existing in the Processing Unit is eliminated, thereby optimizing space efficiency for the PIM configuration.

[0039] The PIM Status Register (110) stores PIM settings received from the host or memory controller. The PIM Status Register (110) may be composed of multiple registers to store complex programs, or each bit of a single register may be used to specify PIM operations to support only simple operations.

[0040] The PIM ALU (130) operates in a designated manner according to the setting information stored in the PIM status register (110). At this time, the PIM ALU (130) does not have a separate register for temporarily storing the operation result, and operates by directly receiving data from the Row buffer (160) of the DRAM bank I / O, performing the operation, then temporarily storing the operation result in the output register (Output Register, 140) and then writing it back to the Row buffer (160).

[0041] FIG. 5 is an operation flowchart of a PIM that operates based on refresh according to another embodiment of the present invention.

[0042] Typically, DRAM performs a refresh operation at regular intervals, and when a refresh operation is introduced, all normal operations of the corresponding bank are stopped until the refresh is completed, and the refresh operation is performed.

[0043] As illustrated in FIG. 5, when a refresh command for the Nth column arrives (S205) and the PIM status register (110) is not set to indicate that PIM is operating (S210-N), the Nth column data is temporarily stored in the Row buffer (160) (S245), the temporarily stored data is rewritten to the memory cell (150) (S250), the Row buffer (160) is closed, and a refresh operation for the N+1th column is prepared (S255). Thereafter, when a refresh signal arrives from the memory controller or a self-refresh signal is generated, the refresh operation for the N+1th column is performed again. This corresponds to a general refresh operation.

[0044] Meanwhile, when a refresh command for the Nth column arrives (S205), if the PIM status register (110) is set to indicate that the PIM is operating (S210-Y), the Nth column data is first temporarily stored in the Row buffer (160) (S215), and the temporarily stored data is written back to the memory cell (150) (S220), thereby performing the same operation as a general Refresh operation.

[0045] However, without closing the Row buffer (160), the PIM ALU (130) is operated using the set value of the PIM status register (110) and the data of the Row buffer (160) to perform an operation (S225).

[0046] When the operation of the PIM ALU (130) is completed, the operation result is temporarily stored in the output register (140) (S230). Meanwhile, if a refresh command for the N+1th column occurs during this process, it is ignored, and the operation result temporarily stored in the output register (140) is stored in the Row buffer (160) and written to the N+1th column of the memory cell (150) (S235). Thereafter, the Row buffer (160) is closed, and a refresh operation for the N+2nd column is prepared (S240).

[0047] So far, a preferred embodiment of a processing-in-memory device that performs in-memory operations using a refresh operation has been described in detail.

[0048] The above embodiment implements energy-efficient processing-in-memory by enabling in-memory operations using refresh operations. Furthermore, space-efficient processing-in-memory is implemented by performing in-memory operations using a row buffer during refresh operations.

[0049] In addition, although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and various modifications can be made by a person having ordinary skill in the art to which the present invention pertains without departing from the gist of the present invention as claimed in the claims, and such modifications should not be understood individually from the technical idea or prospect of the present invention.

Claims

1. Memory cells that refresh at regular intervals; Row buffer where the column data of the memory cells to be refreshed are temporarily stored; A processing-in-memory device characterized by including an operator for storing an operation result using column data stored in a row buffer during a refresh operation in the row buffer and writing it to a memory cell.

2. In claim 1, The operator is, A processing-in-memory device characterized in that, when a refresh command for the Nth column arrives, an operation is performed using the column data stored in the row buffer.

3. In claim 2, The operator is, A processing-in-memory device characterized by temporarily storing the result of an operation in an output register.

4. In claim 3, The operator is, A processing-in-memory device characterized in that when a refresh command for the N+1th column arrives, the operation result temporarily stored in the output register is stored in the row buffer and written to the memory cell.

5. In claim 4, Row buffer is, A processing-in-memory device characterized in that, when a refresh command for the Nth column data arrives, the Nth column data stored in the memory cell is temporarily stored and then written to the memory cell again.

6. In claim 5, Row buffer is, A processing-in-memory device characterized in that, when a refresh command for the N+1th column arrives, the N+1th column data stored in the memory cell is not temporarily stored, but the operation result stored by the operator is written to the memory cell.

7. In claim 5, Row buffer is, A processing-in-memory device characterized in that it does not close when a refresh command for the Nth column arrives.

8. In claim 2, Further comprising a status register in which configuration information for processing-in-memory is stored; The operator is, A processing-in-memory device characterized by performing operations according to setting information of a status register.

9. In claim 8, Row buffer is, A processing-in-memory device characterized in that, when the operator is not performing a processing-in-memory operation, the column data of the memory cell to be refreshed is temporarily stored and then written to the memory cell.

10. Step of temporarily storing the column data of the memory cell to be refreshed in the Row buffer; A step of storing the operation result using the column data stored in the Row buffer during a refresh operation in the Row buffer; A processing-in-memory method, characterized by including a step of writing an operation result stored in a row buffer to a memory cell.

11. Memory cells that refresh at regular intervals; Row buffer where the column data of the memory cells to be refreshed are temporarily stored; A status register that stores configuration information for processing-in-memory; An output register where the results of a calculation are temporarily stored; A processing-in-memory device characterized by including an arithmetic unit that temporarily stores an operation result using column data stored in a row buffer based on setting information stored in a status register during a refresh operation in an output register and then stores it in the row buffer so that it can be written to a memory cell.

12. Step of storing configuration information for processing in memory in the status register; A step of temporarily storing the column data of the memory cell to be refreshed in the Row buffer; A step of temporarily storing the operation result using the column data stored in the row buffer based on the setting information stored in the status register during a refresh operation in the output register; A step of storing the operation result temporarily stored in the output register in the row buffer; A processing-in-memory method, characterized by including a step of writing an operation result stored in a row buffer to a memory cell.

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