Shift register unit and driving method therefor, gate driving circuit, and display panel

Abstract

A shift register unit and a driving method therefor, a gate driving circuit, and a display panel. The shift register unit comprises a node setting circuit, a preprocessing circuit, a gating circuit, an input circuit, a separation circuit and an output circuit. The gate driving circuit comprising the shift register unit can achieve the refresh frequency of a pixel driving circuit corresponding to any shift register unit.

Description

Shift register unit and driving method thereof, gate driving circuit, and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. Background Art

[0002] In the prior art, to balance display quality and power consumption, display panels typically divide the display area into multiple zones, with different refresh rates set for each zone. However, after the zones are divided, the positions of the zones cannot be changed, meaning the display panel cannot arbitrarily adjust the refresh rate of different zones as needed.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a shift register unit is provided, wherein the shift register unit includes:

[0006] a node setting circuit, connected to the third clock signal terminal and the first node, and configured to input a valid level to the first node in response to a signal from the third clock signal terminal;

[0007] a preprocessing circuit connected to the second clock signal terminal, the second node, and the third node, configured to input a valid level to the second node in response to a signal from the second clock signal terminal, and to transmit the signal from the second clock signal terminal to the second node in response to a signal from the third node;

[0008] a gating circuit connected to the third node, a third clock signal terminal, and one or more gating signal terminals, the gating circuit being configured to transmit the signal of the third clock signal terminal to the third node in response to a signal of any of the gating signal terminals;

[0009] an input circuit connected to the fourth clock signal terminal, the second node, and one or more control signal terminals, the input circuit being configured to transmit a signal from the fourth clock signal terminal to each of the control signal terminals in response to a signal from the second node;

[0010] a separation circuit connected to the first node, a plurality of control signal terminals, and a second power terminal, and configured to respond to a signal from the first node to transmit a signal from the second power terminal to each of the control signal terminals;

[0011] An output circuit is connected to multiple control signal terminals, multiple output clock signal terminals, multiple signal output terminals, and a second power supply terminal. The control signal terminal and the output clock signal terminal are correspondingly arranged, and the control signal terminal and the signal output terminal are correspondingly arranged. The output circuit is used to transmit the signal of the corresponding output clock signal terminal to the corresponding signal output terminal according to the signal of the control signal terminal, and is used to transmit the signal of the second power supply terminal to each signal output terminal in response to the signal of the first node.

[0012] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0013] The first pull-down circuit is connected to the third node and the second clock signal terminal, and is configured to input an invalid level to the third node in response to a signal from the second clock signal terminal.

[0014] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0015] The first storage circuit is connected to the third node, and is used to store the voltage of the third node.

[0016] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0017] A reset circuit is connected to the first power supply terminal, the first node, the second node, the second power supply terminal, and the reset signal terminal. The reset circuit is used to transmit the signal of the first power supply terminal to the first node in response to the signal of the reset signal terminal, and to transmit the signal of the second power supply terminal to the second node in response to the signal of the reset signal terminal.

[0018] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0019] The second pull-down circuit is connected to any one of the control signal terminals and the first node, and is configured to respond to a signal from the control signal terminal to input an invalid level to the first node.

[0020] In an exemplary embodiment of the present disclosure, the node setting circuit is further connected to a fourth clock signal terminal and a second node, and is configured to input an invalid level to the first node in response to signals from the fourth clock signal terminal and the second node.

[0021] In an exemplary embodiment of the present disclosure, the node setting circuit is configured to respond to a signal at the third clock signal terminal and utilize the third clock signal terminal to provide a valid level to the first node.

[0022] In an exemplary embodiment of the present disclosure, the node setting circuit is configured to respond to the fourth clock signal terminal and the signal of the second node and provide an invalid level to the first node using the third clock signal terminal.

[0023] In an exemplary embodiment of the present disclosure, the first pull-down circuit is further connected to a third clock signal terminal, and the first pull-down circuit is configured to input an invalid level to the third node via the third clock signal terminal in response to a signal at the second clock signal terminal.

[0024] In an exemplary embodiment of the present disclosure, the second pull-down circuit is further connected to a third clock signal terminal, and the second pull-down circuit is configured to input an invalid level to the first node using the third clock signal terminal in response to a signal from the control signal terminal.

[0025] In an exemplary embodiment of the present disclosure, the pre-processing circuit is configured to respond to a signal at the second clock signal terminal and provide a valid level to the second node using the second clock signal terminal.

[0026] In an exemplary embodiment of the present disclosure, the node setting circuit includes:

[0027] a first transistor, having a first electrode connected to the third clock signal terminal, a second electrode connected to the first node, and a gate connected to the third clock signal terminal;

[0028] a second transistor, having a first electrode connected to the first node and a gate connected to the second node;

[0029] a third transistor, a first electrode of which is connected to the second electrode of the second transistor, and a second electrode of which is connected to the third clock signal terminal;

[0030] The third capacitor has a first electrode connected to the first node and a second electrode connected to a stable voltage terminal.

[0031] In an exemplary embodiment of the present disclosure, the preprocessing circuit includes:

[0032] a fourth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the second node, and a gate connected to the second clock signal terminal;

[0033] a fifth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the second node, and a gate connected to the third node;

[0034] The second capacitor has a first electrode connected to the second node and a second electrode connected to a stable voltage terminal.

[0035] In an exemplary embodiment of the present disclosure, the gating circuit includes:

[0036] One or more gating transistors, the gating transistors and the gating signal terminals are correspondingly arranged, the first electrode of the gating transistor is connected to the third clock signal terminal, the second electrode of the gating transistor is connected to the third node, and the gate of the gating transistor is connected to the corresponding gating signal terminal.

[0037] In an exemplary embodiment of the present disclosure, the input circuit includes:

[0038] a sixth transistor, having a first electrode connected to the fourth clock signal terminal, a second electrode connected to the fourth node, and a gate connected to the second node;

[0039] One or more input transistors, the input transistors and the control signal terminal are correspondingly arranged, the first electrode of the input transistor is connected to the fourth node, the second electrode of the input transistor is connected to the corresponding control signal terminal, and the gate of the input transistor is connected to the fourth clock signal terminal.

[0040] In an exemplary embodiment of the present disclosure, the separation circuit includes:

[0041] One or more separation transistors, the separation transistors and the control signal terminal are correspondingly arranged, the first electrode of the separation transistor is connected to the second power supply terminal, the second electrode of the separation transistor is connected to the corresponding control signal terminal, and the gate of the separation transistor is connected to the first node.

[0042] In an exemplary embodiment of the present disclosure, the output circuit includes:

[0043] One or more first output transistors, each of the first output transistors and the control signal terminal being provided correspondingly, a gate of the first output transistor being connected to the corresponding control signal terminal, a first electrode of the first output transistor being connected to the corresponding output clock signal terminal, and a second electrode of the first output transistor being connected to the corresponding signal output terminal;

[0044] one or more second output transistors, each of the second output transistors being provided corresponding to the signal output terminal, a gate of the second output transistor being connected to the first node, a first electrode of the second output transistor being connected to the second power supply terminal, and a second electrode of the second output transistor being connected to the corresponding signal output terminal;

[0045] One or more output capacitors, each of the output capacitors being provided corresponding to the control signal terminal, a first electrode of the output capacitor being connected to the corresponding control signal terminal, and a second electrode of the output capacitor being connected to the corresponding signal output terminal;

[0046] Among them, the first output transistor and the output clock signal terminal corresponding to the same control signal terminal are correspondingly set, the first output transistor and the signal output terminal corresponding to the same control signal terminal are correspondingly set, and the output capacitor and the signal output terminal corresponding to the same control signal terminal are correspondingly set.

[0047] In an exemplary embodiment of the present disclosure, the first pull-down circuit includes:

[0048] A seventh transistor has a first electrode connected to the third clock signal terminal, a second electrode connected to the third node, and a gate connected to the second clock signal terminal.

[0049] In an exemplary embodiment of the present disclosure, the first storage circuit includes:

[0050] A first capacitor, wherein a first electrode of the first capacitor is connected to the third node, and a second electrode of the first capacitor is connected to a stable voltage terminal.

[0051] In an exemplary embodiment of the present disclosure, the reset circuit includes:

[0052] an eighth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first node, and a gate connected to the reset signal terminal;

[0053] A ninth transistor has a first electrode connected to the second power supply terminal, a second electrode connected to the second node, and a gate connected to the reset signal terminal.

[0054] In an exemplary embodiment of the present disclosure, the second pull-down circuit includes:

[0055] A tenth transistor has a first electrode connected to the third clock signal terminal, a second electrode connected to the first node, and a gate connected to any one of the control signal terminals.

[0056] In an exemplary embodiment of the present disclosure, in the same shift register unit, the types of the plurality of gate transistors are the same or different.

[0057] According to one aspect of the present disclosure, a shift register unit driving method is provided, for driving the above-mentioned shift register unit, wherein the driving method includes:

[0058] In the first stage: using the pre-processing circuit to input a valid level to the second node;

[0059] In the second stage: when the shift register unit is selected, the third clock signal terminal and the third node are turned off by the gating circuit; when the shift register unit is not selected, the third clock signal terminal and the third node are turned on by the gating circuit;

[0060] In the third stage, when the shift register unit is selected, the input circuit is used to transmit the signal of the fourth clock signal terminal to each control signal terminal, and when the shift register unit is not selected, the input circuit is used to turn off the fourth clock signal terminal and each control signal terminal;

[0061] In the fourth stage, when the shift register unit is selected, the output circuit transmits the signal of the corresponding output clock signal terminal to the corresponding signal output terminal according to the signal of the control signal terminal; when the shift register unit is not selected, the output circuit turns off the fourth clock signal terminal and each signal output terminal, and transmits the signal of the second power terminal to the signal output terminal by the output circuit;

[0062] In the fifth stage, the separation circuit is used to transmit the signal of the second power supply terminal to each control signal terminal, and the output circuit is used to transmit the signal of the second power supply terminal to each signal output terminal.

[0063] According to one aspect of the present disclosure, a gate driving circuit is provided, wherein the gate driving circuit includes a plurality of the above-mentioned shift register units.

[0064] In an exemplary embodiment of the present disclosure, the gate driving circuit includes a plurality of shift register groups, each of which includes one or more shift register units;

[0065] The gate drive circuit further includes:

[0066] A plurality of strobe signal lines, wherein different strobe signal terminals in the same shift register unit are respectively connected to a different strobe signal line;

[0067] In the same shift register group, the shift register units are connected to the same selection signal line;

[0068] In different shift register groups, at least one strobe signal line connected to the shift register units is different.

[0069] In an exemplary embodiment of the present disclosure, in different shift register groups, at least some of the shift register units are connected to the same selection signal line.

[0070] In an exemplary embodiment of the present disclosure, the shift register unit includes n selection signal terminals, and the gate drive circuit includes 2 n The shift register group and n groups of strobe signal line pairs are provided, each group of the strobe signal line pairs includes two strobe signal lines, and the two strobe signal lines in the same strobe signal line pair are connected to 2 n / 2 groups of shift registers;

[0071] The n selection signal terminals and n groups of selection signal line pairs in the shift register unit are arranged in a one-to-one correspondence, and one of the selection signal terminals is selectively connected to a selection signal line in the corresponding selection signal line pair;

[0072] The two strobe signal lines in the same strobe signal line pair have opposite polarities, and n is an integer greater than or equal to 1.

[0073] In an exemplary embodiment of the present disclosure, n is greater than or equal to 2;

[0074] The n groups of selection signal line pairs include the first selection signal line pair to the nth selection signal line pair. In the multiple shift register groups that are simultaneously connected to the same selection signal line in the first to i-th selection signal line pairs, half of the shift register groups are connected to one selection signal line in the i+1-th selection signal line pair, and the other half of the shift register groups are connected to the other selection signal line in the i+1-th selection signal line pair, where i is an integer greater than or equal to 1 and less than or equal to n-1.

[0075] In an exemplary embodiment of the present disclosure, the gating circuit includes:

[0076] One or more gating transistors, the gating transistors and the gating signal terminals are correspondingly provided, a first electrode of the gating transistor is connected to the third clock signal terminal, a second electrode of the gating transistor is connected to the third node, and a gate of the gating transistor is connected to the corresponding gating signal terminal;

[0077] The gate driving circuit includes a plurality of shift register groups, each of which includes one or more shift register units.

[0078] In different shift register groups, at least some of the shift register units have different combinations of types of gate transistors.

[0079] In an exemplary embodiment of the present disclosure, the shift register unit includes n selection signal terminals, and the gate drive circuit includes 2 n The shift register group and n strobe signal lines are arranged in a corresponding manner, and the strobe signal terminals are connected to the corresponding strobe signal lines;

[0080] In different shift register groups, the type combinations of the gate transistors in the shift register units are different.

[0081] In an exemplary embodiment of the present disclosure, the same selection signal line is connected to 2 n / 2 N-type transistors and 2 n / 2 P-type transistors;

[0082] In multiple shift register groups that are simultaneously connected to the first to i-th selection signal lines and have the same type of selection transistors connected to the same selection signal line, half of the selection transistors connected to the i+1-th selection signal line are N-type and half are P-type, and i is an integer greater than or equal to 1 and less than or equal to n-1.

[0083] In an exemplary embodiment of the present disclosure, the number of shift register units in different shift register groups is the same or different.

[0084] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes the above-mentioned gate driving circuit.

[0085] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0087] FIG1 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0088] FIG2 is a schematic structural diagram of an exemplary embodiment of a gate driving circuit disclosed herein;

[0089] FIG3 is a schematic structural diagram of an exemplary embodiment of a shift register unit disclosed herein;

[0090] FIG4 is a schematic diagram of a partial structure of a gate drive circuit disclosed in the present invention;

[0091] The timing diagram shown in FIG5 is a timing diagram when the first stage shift register unit in the gate drive circuit shown in FIG4 is selected;

[0092] FIG6 is a timing diagram of eight groups of strobe signal line pairs in the timing diagram shown in FIG5 ;

[0093] FIG7 is a schematic structural diagram of an exemplary embodiment of a shift register unit disclosed herein;

[0094] FIG8 is a schematic structural diagram of a node setting circuit in another exemplary embodiment of the shift register unit disclosed herein. DETAILED DESCRIPTION

[0095] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0096] In the description of this disclosure, unless otherwise expressly provided or limited, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance; the term "plurality" refers to two or more; and the term "and / or" includes any and all combinations of one or more of the associated listed items. In particular, reference to "the" or "an" object is also intended to mean one of a possible plurality of such objects.

[0097] As shown in Figure 1, it is a schematic diagram of the structure of an exemplary embodiment of the display panel of the present disclosure. The display panel may include a timing controller, a source driving circuit, a gate driving circuit and a pixel array. The timing controller is respectively connected to the source driving circuit and the gate driving circuit, and the source driving circuit is respectively connected to a plurality of data signal lines (Da1 to Dan). The gate driving circuit includes a scan driving circuit and a light-emitting driving circuit. The scan driving circuit is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driving circuit is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal line, the light-emitting signal line and the data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the source driver circuit to the source driver circuit, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver circuit to the scan driver circuit, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver circuit to the light-emitting driver circuit. The source driver circuit may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines Da1, Da2, Da3, ..., and Dan. For example, the source driver circuit may use the clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines Da1 to Dan in units of pixel rows, where n may be a natural number. The scan driver circuit may generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver circuit may sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan drive circuit can be constructed in the form of a shift register and can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal, and m can be a natural number. The light-emitting drive circuit can generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting drive circuit can sequentially provide an emission signal with an off-level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting drive circuit can be constructed in the form of a shift register and can generate an emission signal by sequentially transmitting an emission stop signal provided in the form of an off-level pulse to the next stage circuit under the control of a clock signal, and o can be a natural number.

[0098] This exemplary embodiment provides a gate drive circuit, as shown in FIG2 , which is a schematic structural diagram of an exemplary embodiment of the gate drive circuit disclosed herein. The gate drive circuit may include multiple shift register groups, and the shift register groups may include one or more shift register units. This exemplary embodiment is described using 16 shift register groups as an example, and the 16 shift register groups include shift register group 1 to shift register group 16. Accordingly, the gate drive circuit may include 4 groups of gate signal line pairs, each of which includes two gate signal lines. The first gate signal line pair may include gate signal lines D1 and D1e, the second gate signal line pair may include gate signal lines D2 and D2e, the third gate signal line pair may include gate signal lines D3 and D3e, and the fourth gate signal line pair may include gate signal lines D4 and D4e. The selection signal line D1 can be connected to the shift register group 9-shift register group 16, and the selection signal line D1e can be connected to the shift register group 1-shift register group 8; the selection signal line D2 can be connected to the shift register group 5-shift register group 8, the shift register group 13-shift register group 16, and the selection signal line D2e can be connected to the shift register group 1-shift register group 4, the shift register group 9-shift register group 12; the selection signal line D3 can be connected to the shift register group 3, the shift register group 4, the shift register group 7, the shift register group 8, the shift register group 11, the shift register group 12, the shift register group 15, and the shift register group 16, and the selection signal line D 3e can be connected to shift register group 1, shift register group 2, shift register group 5, shift register group 6, shift register group 9, shift register group 10, shift register group 13, and shift register group 14; the selection signal line D4 can be connected to shift register group 2, shift register group 4, shift register group 6, shift register group 8, shift register group 10, shift register group 12, shift register group 14, and shift register group 16; the selection signal line D4e can be connected to shift register group 1, shift register group 3, shift register group 5, shift register group 7, shift register group 9, shift register group 11, shift register group 13, and shift register group 15. In the same shift register group, the selection signal lines connected to the shift register units can be the same.

[0099] In this exemplary embodiment, each shift register group is connected to a different combination of select signal lines, meaning that different shift register groups are connected to at least one different select signal line. The polarity of the two select signal lines in the same select signal line pair is opposite. This exemplary embodiment allows any shift register group to be selected by controlling the polarity of the select signal lines in the four select signal line pairs. The selected shift register group can normally output gate drive signals, while unselected shift register groups do not output gate drive signals. This exemplary embodiment allows the refresh frequency of the pixel drive circuit connected to any shift register group to be controlled.

[0100] It should be understood that in other exemplary embodiments, the number of shift register groups can be other numbers, and n groups of strobe signal line pairs can achieve 2 n Arbitrary control of a shift register group, n is an integer greater than or equal to 1, for example, n can be equal to 1, 2, 3, 4, 5, 6, 7, 8, etc.

[0101] In this exemplary embodiment, n can be greater than or equal to 2, and the n groups of strobe signal line pairs include the first strobe signal line pair to the nth strobe signal line pair. In the multiple shift register groups that are simultaneously connected to the same strobe signal line in each of the first to i-th strobe signal line pairs, half of the shift register groups are connected to one strobe signal line in the (i+1)th strobe signal line pair, and the other half of the shift register groups are connected to the other strobe signal line in the (i+1)th strobe signal line pair, where i is an integer greater than or equal to 1 and less than or equal to n-1. For example, as shown in FIG2 , in shift register group 1 through shift register group 4 that are connected to strobe signal lines D1e and D2e, shift register group 1 through shift register group 2 are connected to D3e, and shift register group 3 through shift register group 4 are connected to D3.

[0102] It should be understood that in other exemplary embodiments, the number of gate signal lines in the gate drive circuit can be other numbers, and the gate signal lines and shift register groups can be connected in other ways. As long as at least one of the gate signal lines connected to different shift register groups is different, any shift register group can be selected based on the polarity of the gate signal line. In addition, among different shift register groups, at least some of the shift register groups can be connected to the same gate signal line. This arrangement can reduce the number of gate signal lines. FIG2 shows a specific method for shift register groups to share a gate signal line. The gate drive circuit provided by the present disclosure is not limited to this gate signal line sharing method.

[0103] The gate driving circuit provided by this exemplary embodiment may be used in the scanning driving circuit and the light emitting driving circuit in FIG. 1 .

[0104] This exemplary embodiment also provides a shift register unit, as shown in Figures 3 and 4. Figure 3 is a schematic diagram of the structure of an exemplary embodiment of the shift register unit disclosed herein, and Figure 4 is a schematic diagram of a portion of the structure of the gate drive circuit disclosed herein. The gate drive circuit shown in Figure 4 includes multiple shift register units shown in Figure 3. In this gate drive circuit, each shift register group GOAz can include four shift register units GOA. The shift register unit includes: a node setting circuit 1, a preprocessing circuit 2, a gating circuit 3, an input circuit 4, a separation circuit 5, and an output circuit 6. The node setting circuit 1 is connected to the third clock signal terminal CLK3 and the first node N1, and is used to input a valid level to the first node N1 in response to the signal of the third clock signal terminal CLK3; the preprocessing circuit 2 is connected to the second clock signal terminal CLK2, the second node N2, and the third node N3, and is used to input a valid level to the second node N2 in response to the signal of the second clock signal terminal CLK2, and is used to transmit the signal of the second clock signal terminal CLK2 to the second node N2 in response to the signal of the third node N3; the selection circuit 3 is connected to the third node N3, the third clock signal terminal CLK3, and 8 selection signal terminals d1-d8, and the selection circuit 3 is used to respond to the signal of any of the selection signal terminals to transmit the signal of the third clock signal terminal CLK3 to the third node N3; the input circuit 4 is connected to the fourth clock signal terminal CLK4, the second node N2, and the four control signal terminals Q1-Q4, and the input circuit 4 is used to respond to the signal of the second node N2 to transmit the signal of the fourth clock signal terminal CLK4 Transmitted to each of the control signal terminals Q1-Q4; the separation circuit 5 is connected to the first node N1, multiple control signal terminals Q1-Q4, and the second power supply terminal VGL, and is used to respond to the signal of the first node N1 to transmit the signal of the second power supply terminal VGL to each of the control signal terminals Q1-Q4; the output circuit 6 is connected to multiple control signal terminals Q1-Q4, multiple output clock signal terminals CK1-CK4, multiple signal output terminals OUT1-OUT4, and the second power supply terminal VGL, and the multiple control signal terminals Q1-Q4 and the multiple output clock signal terminals CK1-CK4 are set in one-to-one correspondence, and the multiple control signal terminals Q1-Q4 and the multiple signal output terminals OUT1-OUT4 are set in one-to-one correspondence, and the output circuit 6 is used to transmit the signal of the corresponding output clock signal terminal to the corresponding signal output terminal according to the signal of the control signal terminal, and to transmit the signal of the second power supply terminal VGL to each signal output terminal OUT1-OUT4 in response to the signal of the first node N1.

[0105] The shift register unit provided by this exemplary embodiment can, in the first stage: use the pre-processing circuit 2 to input a valid level to the second node N2; in the second stage: when the shift register unit is selected, use the gating circuit 3 to turn off the third clock signal terminal CLK3 and the third node N3; when the shift register unit is not selected, use the gating circuit 3 to turn on the third clock signal terminal CLK3 and the third node N3, so as to input a valid level to the third node N3 through the third clock signal terminal CLK3, and then transmit the invalid level of the second clock signal terminal CLK2 to the second node N2 through the pre-processing circuit 2; in the third stage, when the shift register unit is selected, the input circuit 4 transmits the valid level of the fourth clock signal terminal CLK4 to each control signal in response to the valid level of the second node N2. The fourth clock signal terminal Q1-Q4 is connected to the control signal terminal Q1-Q4. When the shift register unit is not selected, the input circuit 4 is used to turn off the fourth clock signal terminal CLK4 and each control signal terminal Q1-Q4. In the fourth stage, when the shift register unit is selected, the output circuit 6 transmits the signal of the corresponding output clock signal terminal to the corresponding signal output terminal in response to the active level of the control signal terminal. When the shift register unit is not selected, the output circuit is used to turn off the fourth clock signal terminal and each signal output terminal, and the output circuit 6 transmits the inactive level of the second power supply terminal VGL to the signal output terminal. In the fifth stage, the separation circuit 6 transmits the inactive level of the second power supply terminal VGL to each control signal terminal, and the output circuit 6 transmits the inactive level of the second power supply terminal VGL to each signal output terminal. In this exemplary embodiment, in the second stage, when any selection signal terminal in the shift register unit is at an active level, the shift register unit will not be selected. Only when all selection signal terminals in the shift register unit are at an inactive level is the shift register unit selected. Therefore, this exemplary embodiment can control whether the shift register unit is selected through multiple selection signal terminals.

[0106] It should be noted that the active level is a level that can turn on the target circuit, and the inactive level is a level that can turn off the target circuit. For example, the active level corresponding to an N-type transistor is a high level, and the inactive level corresponding to an N-type transistor is a low level.

[0107] In this exemplary embodiment, the selection signal terminals d1-d8 can be respectively connected to a selection signal line. Accordingly, the gate drive circuit can include 8 groups of selection signal line pairs. The selection signal terminals and the selection signal line pairs are correspondingly arranged, and one of the selection signal terminals is selectively connected to a selection signal line in the corresponding selection signal line pair.

[0108] It should be understood that in other exemplary embodiments, the shift register unit may also include other numbers of strobe signal terminals. For example, the shift register unit includes n strobe signal terminals, and the gate drive circuit includes 2 gate signal terminals. nThere are n shift register groups and n groups of strobe signal line pairs, each strobe signal line pair includes two strobe signal lines, and the two strobe signal lines in the same strobe signal line pair are connected to 2 n / 2 groups of shift register groups; n selection signal terminals and n groups of selection signal line pairs in the shift register unit are arranged in a one-to-one correspondence, and one of the selection signal terminals is selectively connected to a selection signal line in the selection signal line pair corresponding to it; wherein, the two selection signal lines in the same selection signal line pair have opposite polarities, and n is an integer greater than or equal to 1.

[0109] In this exemplary embodiment, the number of control signal terminals, signal output terminals, and output clock signal terminals can be the same, and the number of control signal terminals, signal output terminals, and output clock signal terminals can be four. It should be understood that in other exemplary embodiments, the number of control signal terminals, signal output terminals, and output clock signal terminals can also be other numbers. Each signal output terminal can be connected to a row of pixel driving circuits.

[0110] In this exemplary embodiment, as shown in Figure 3, the shift register unit may further include: a first pull-down circuit 7, the first pull-down circuit 7 is connected to the third node N3 and the second clock signal terminal CLK2, and is used to input an invalid level to the third node N3 in response to the signal of the second clock signal terminal CLK2.

[0111] In this exemplary embodiment, as shown in Figure 3, the shift register unit may further include: a reset circuit 9, the reset circuit 9 is connected to the first power supply terminal VGH, the first node N1, the second node N2, the second power supply terminal VGL, and the reset signal terminal, and the reset circuit 9 is used to respond to the signal of the reset signal terminal to transmit the signal of the first power supply terminal VGH to the first node N1, and to respond to the signal of the reset signal terminal to transmit the signal of the second power supply terminal VGL to the second node N2.

[0112] In this exemplary embodiment, as shown in Figure 3, the shift register unit may further include: a second pull-down circuit 10, the second pull-down circuit 10 is connected to any of the control signal terminals and the first node N1, and the second pull-down circuit 10 is used to respond to the signal of the control signal terminal to input an invalid level to the first node N1.

[0113] In this exemplary embodiment, as shown in FIG3 , the node setting circuit 1 can also be connected to the fourth clock signal terminal CLK4 and the second node N2. The node setting circuit 1 can be configured to input an inactive level to the first node N1 in response to the signals from the fourth clock signal terminal CLK4 and the second node N2. The node setting circuit 1 can also be configured to provide an active level to the first node N1 using the third clock signal terminal CLK3 in response to the signal from the third clock signal terminal CLK3. This configuration can reduce the voltage difference between the first node N1 and the third clock signal terminal CLK3 during at least a portion of the time period, thereby reducing leakage current of the first node N1.

[0114] In this exemplary embodiment, as shown in FIG3 , the first pull-down circuit 7 is further connected to the third clock signal terminal CLK3. The first pull-down circuit 7 is configured to respond to the signal of the second clock signal terminal CLK2 by inputting an inactive level to the third node N3 via the third clock signal terminal CLK3. The second pull-down circuit 10 is further connected to the third clock signal terminal CLK3. The second pull-down circuit 10 is configured to respond to the signal of the control signal terminal by inputting an inactive level to the first node N1 via the third clock signal terminal CLK3. The pre-processing circuit 2 is configured to respond to the signal of the second clock signal terminal CLK2 by providing an active level to the second node N2 via the second clock signal terminal CLK2.

[0115] In this exemplary embodiment, as shown in Figure 3, the node setting circuit 1 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a third capacitor C3. The first electrode of the first transistor T1 is connected to the third clock signal terminal CLK3, the second electrode is connected to the first node N1, and the gate is connected to the third clock signal terminal CLK3; the first electrode of the second transistor T2 is connected to the first node N1, and the gate is connected to the second node N2; the first electrode of the third transistor T3 is connected to the second electrode of the second transistor T2, and the second electrode is connected to the third clock signal terminal CLK3; the first electrode of the third capacitor C3 is connected to the first node N1, and the second electrode is connected to a stable voltage terminal. For example, the second electrode of the third capacitor C3 can be connected to the second power supply terminal VGL.

[0116] In this exemplary embodiment, as shown in Figure 3, the preprocessing circuit 2 may include: a fourth transistor T4, a fifth transistor T5, and a second capacitor C2, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CLK2, the second electrode is connected to the second node N2, and the gate is connected to the second clock signal terminal CLK2; the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CLK2, the second electrode is connected to the second node N2, and the gate is connected to the third node N3; the first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode is connected to a stable voltage terminal, for example, the second electrode of the second capacitor C2 can be connected to the first power supply terminal VGH.

[0117] In this exemplary embodiment, as shown in FIG3 , the gating circuit 3 may include eight gating transistors Td1-Td8, each of which is provided in a one-to-one correspondence with the gating signal terminal. A first electrode of each gating transistor is connected to the third clock signal terminal CLK3, a second electrode of each gating transistor is connected to the third node N3, and a gate of each gating transistor is connected to the corresponding gating signal terminal. The number of gating transistors may also be other, and the number of gating transistors is the same as the number of gating signal terminals.

[0118] In this exemplary embodiment, as shown in FIG3 , the input circuit 4 may include: a sixth transistor T6 and four input transistors Ti1-Ti4. The first electrode of the sixth transistor T6 is connected to the fourth clock signal terminal CLK4, the second electrode is connected to the fourth node N4, and the gate is connected to the second node N2. The input transistors and the control signal terminals are provided in a one-to-one correspondence, with the first electrode of the input transistor connected to the fourth node N4, the second electrode of the input transistor connected to the corresponding control signal terminal, and the gate of the input transistor connected to the fourth clock signal terminal CLK4. The number of input transistors may also be other, and the number of input transistors is the same as the number of control signal terminals.

[0119] In this exemplary embodiment, as shown in FIG3 , the separation circuit 5 includes four separation transistors Tp1-Tp4, each of which is provided in a one-to-one correspondence with the control signal terminal. A first electrode of each separation transistor is connected to the second power supply terminal VGL, a second electrode of each separation transistor is connected to the corresponding control signal terminal, and a gate of each separation transistor is connected to the first node N1. The number of separation transistors may also be other numbers, and the number of separation transistors is the same as the number of control signal terminals.

[0120] In this exemplary embodiment, as shown in FIG3 , the output circuit 6 includes: four first output transistors Thi1-Th4, four second output transistors Tl1-Tl4, and four output capacitors Cp1-Cp4. The first output transistors are arranged in a one-to-one correspondence with the control signal terminals, with the gate of the first output transistor connected to the corresponding control signal terminal, the first electrode of the first output transistor connected to the corresponding output clock signal terminal, and the second electrode of the first output transistor connected to the corresponding signal output terminal; the second output transistors are arranged in a one-to-one correspondence with the signal output terminal, with the gate of the second output transistor connected to the first node, the first electrode of the second output transistor connected to the second power supply terminal, and the second electrode of the second output transistor connected to the corresponding signal output terminal; the output capacitors are arranged in a one-to-one correspondence with the control signal terminals, with the first electrode of the output capacitor connected to the corresponding control signal terminal, and the second electrode of the output capacitor connected to the corresponding signal output terminal; wherein the first output transistor corresponding to the same control signal terminal is arranged in correspondence with the output clock signal terminal, the first output transistor corresponding to the same control signal terminal is arranged in correspondence with the signal output terminal, and the output capacitor corresponding to the same control signal terminal is arranged in correspondence with the signal output terminal.

[0121] In this exemplary embodiment, as shown in FIG3 , the first pull-down circuit 7 may include: a seventh transistor T7 , a first electrode of the seventh transistor T7 connected to the third clock signal terminal CLK3 , a second electrode connected to the third node N3 , and a gate connected to the second clock signal terminal CLK2 .

[0122] In this exemplary embodiment, as shown in Figure 3, the reset circuit 9 may include: an eighth transistor T8 and a ninth transistor T9, wherein a first electrode of the eighth transistor T8 is connected to the first power supply terminal VGH, a second electrode is connected to the first node N1, and a gate is connected to the reset signal terminal; a first electrode of the ninth transistor T9 is connected to the second power supply terminal VGL, a second electrode is connected to the second node N2, and a gate is connected to the reset signal terminal.

[0123] In this exemplary embodiment, as shown in FIG3 , the second pull-down circuit 10 includes: a tenth transistor T10 , a first electrode of the tenth transistor T10 connected to the third clock signal terminal CLK3 , a second electrode connected to the first node N1 , and a gate connected to any of the control signal terminals.

[0124] As shown in FIG3 and FIG4 , the gate driving circuit may further include four clock signal lines CLKq1 - CLKq4 , three of which provide signals to the second clock signal terminal CLK2 , the third clock signal terminal CLK3 , and the fourth clock signal terminal CLK4 , respectively. As shown in Figure 4, for the first-stage shift register unit GOA: the second clock signal terminal CLK2 is connected to the clock signal line CLKq2, the third clock signal terminal CLK3 is connected to the clock signal line CLKq3, and the fourth clock signal terminal CLK4 is connected to the clock signal line CLKq4; for the second-stage shift register unit GOA: the second clock signal terminal CLK2 is connected to the clock signal line CLKq3, the third clock signal terminal CLK3 is connected to the clock signal line CLKq4, and the fourth clock signal terminal CLK4 is connected to the clock signal line CLKq1; for the third-stage shift register unit GOA: the second clock signal terminal CLK2 is connected to the clock signal line CLKq4, the third clock signal terminal CLK3 is connected to the clock signal line CLKq1, and the fourth clock signal terminal CLK4 is connected to the clock signal line CLKq2; for the fourth-stage shift register unit GOA: the second clock signal terminal CLK2 is connected to the clock signal line CLKq1, the third clock signal terminal CLK3 is connected to the clock signal line CLKq2, and the fourth clock signal terminal CLK4 is connected to the clock signal line CLKq3. By analogy, for the fifth stage shift register unit GOA: the second clock signal terminal CLK2 is connected to the clock signal line CLKq2, the third clock signal terminal CLK3 is connected to the clock signal line CLKq3, and the fourth clock signal terminal CLK4 is connected to the clock signal line CLKq4.

[0125] As shown in Figures 3 and 4, the gate drive circuit may further include sixteen output clock signal lines CKq1-CKq16. In the shift register group GOAz, the sixteen output clock signal terminals in the four shift register units GOA are respectively connected to the sixteen output clock signal lines CKq1-CKq16. As shown in Figure 4, for the first-stage shift register unit GOA: the output clock signal terminal CK1 is connected to the output clock signal line CKq1, the output clock signal terminal CK2 is connected to the output clock signal line CKq2, the output clock signal terminal CK3 is connected to the output clock signal line CKq3, and the output clock signal terminal CK4 is connected to the output clock signal line CKq4; for the second-stage shift register unit GOA: the output clock signal terminal CK1 is connected to the output clock signal line CKq5, the output clock signal terminal CK2 is connected to the output clock signal line CKq6, the output clock signal terminal CK3 is connected to the output clock signal line CKq7, and the output clock signal terminal CK4 is connected to the output clock signal line CKq8; For the third-stage shift register unit GOA: the output clock signal terminal CK1 is connected to the output clock signal line CKq9, the output clock signal terminal CK2 is connected to the output clock signal line CKq10, the output clock signal terminal CK3 is connected to the output clock signal line CKq11, and the output clock signal terminal CK4 is connected to the output clock signal line CKq12. For the fourth-stage shift register unit GOA: the output clock signal terminal CK1 is connected to the output clock signal line CKq13, the output clock signal terminal CK2 is connected to the output clock signal line CKq14, the output clock signal terminal CK3 is connected to the output clock signal line CKq15, and the output clock signal terminal CK4 is connected to the output clock signal line CKq16. Similarly, for the fifth-stage shift register unit GOA: the output clock signal terminal CK1 is connected to the output clock signal line CKq1, the output clock signal terminal CK2 is connected to the output clock signal line CKq2, the output clock signal terminal CK3 is connected to the output clock signal line CKq3, and the output clock signal terminal CK4 is connected to the output clock signal line CKq4.

[0126] In this exemplary embodiment, all transistors in the shift register unit shown in FIG3 are N-type transistors, the first power supply terminal VGH may be a high-level power supply terminal, and the second power supply terminal VGL may be a low-level power supply terminal.

[0127] This exemplary embodiment provides a driving method for a shift register unit. As shown in FIG5 , it is a timing diagram of various signal lines and nodes in a driving method for a shift register unit disclosed in the present disclosure. The timing diagram shown in FIG5 is a timing diagram when the first-stage shift register unit in the gate driving circuit shown in FIG4 is selected. Re is a timing diagram of a reset signal terminal Re, CLKq1-CLKq4 are timing diagrams of clock signal lines CLKq1-CLKq4, CKq1-CKq16 are timing diagrams of output clock signal lines CKq1-CKq16, D1e-D8e are timing diagrams of selection signal lines D1e-D8e, N1 is a timing diagram of a first node, N2 is a timing diagram of a second node, N3 is a timing diagram of a third node, N4 is a timing diagram of a fourth node, Q1-Q4 are timing diagrams of control signal terminals Q1-Q4, and OUT1-OUT4 are timing diagrams of signal output terminals OUT1-OUT4.

[0128] The display panel may include a reset phase tre before the display period. In the reset phase tre: the reset signal terminal Re outputs a high-level signal, the eighth transistor T8 and the ninth transistor T9 are turned on, the high-level signal of the first power supply terminal VGH resets the first node N1, and the low-level signal of the second power supply terminal VGL resets the second node N2.

[0129] As shown in FIG. 5 , the display stage of the display panel may include a first stage t1 , a second stage t2 , a third stage t3 , a fourth stage t4 , and a fifth stage t5 .

[0130] During the first phase t1, the clock signal line CLKq2 outputs a high-level signal, the clock signal lines CLKq3 and CLKq4 output low-level signals, and the selection signal lines De1-De8 all output high-level signals. The clock signal line CLKq2 inputs a high-level signal to the second node N2, and the clock signal line CLKq3 inputs a low-level signal to the third node N3. The first node N1 maintains the high level of the previous phase. The second power supply terminal VGL outputs low-level signals to the signal output terminals OUT1-OUT4, respectively, through the second output transistors Tl1-Tl4. Simultaneously, the second power supply terminal VGL inputs low-level signals to the control signal terminals Q1-Q4, respectively, through the separation transistors Tp1-Tp4. Furthermore, the seventh transistor T7 is turned on, and the clock signal line CLKq3 inputs a low-level signal to the third node N3.

[0131] In the second phase t2, clock signal line CLKq3 outputs a high-level signal, while clock signal lines CLKq2 and CLKq4 output low-level signals. If the shift register unit is selected, selection signal lines De1-De8 all output low-level signals. Second node N2 maintains the high-level signal from the previous phase. Clock signal line CLKq3 writes a high-level signal to first node N1, and the second power supply terminal VGL outputs low-level signals to signal output terminals OUT1-OUT4 via second output transistors Tl1-Tl4, respectively. Simultaneously, the second power supply terminal VGL inputs low-level signals to control signal terminals Q1-Q4 via separation transistors Tp1-Tp4, respectively.

[0132] In the third phase t3, the clock signal line CLKq4 outputs a high-level signal, while the clock signal lines CLKq2 and CLKq3 output low-level signals. The clock signal line CLKq4 writes a high-level signal to the fourth node N4 via the sixth transistor T6. The fourth node N4 then inputs a high-level signal to the control signal terminals Q1-Q4 via the input transistors Ti1-Ti4, respectively. Simultaneously, the clock signal line CLKq3 inputs a low-level signal to the first node N1 via the tenth transistor T10. The clock signal line CLKq3 inputs a low-level signal to the first node N1 via the second transistor T2 and the third transistor T3.

[0133] In the fourth phase t4 , the control signal terminals Q1 - Q4 maintain a high level, and the output clock signal lines CKq1 - CKq4 sequentially output high level signals to the signal output terminals OUT1 - OUT4 through the first output transistors Th1 - Th4 .

[0134] In the fifth phase t5, the clock signal line CLKq3 outputs a high-level signal, while the clock signal lines CLKq2 and CLKq4 output low-level signals. The clock signal line CLKq3 inputs a high-level signal to the first node N1, turning on the separation transistors Tp1-Tp4. The second power supply terminal VGL inputs a low-level signal to the control signal terminals Q1-Q4 via the separation transistors Tp1-Tp4, respectively. Simultaneously, the second power supply terminal VGL outputs a low-level signal to the signal output terminals OUT1-OUT4 via the second output transistors Tl1-Tl4, respectively. Furthermore, the selection signal line De8 outputs a high-level signal, turning on the selection transistor Td8, and the clock signal line CLKq3 inputs a high-level signal to the third node N3.

[0135] If the shift register unit is not selected, in the second phase described above, at least one of the selection signal lines De1-De8 outputs a high-level signal, the clock signal line CLKq3 inputs a high-level signal to the third node N3, the fifth transistor T5 is turned on, and the clock signal line CLKq2 writes a low-level signal to the second node N2. Consequently, in the third phase, the clock signal line CLKq4 does not input a high-level signal to the fourth node, and consequently, in the fourth phase, the signal output terminal does not output a high-level signal.

[0136] Figure 6 shows the timing diagram for the eight strobe signal line pairs in the timing diagram shown in Figure 5 , where D1e-D8e are timing diagrams for strobe signal lines D1e-D8e, and D1-D8 are timing diagrams for strobe signal lines D1-D8. Die and Di form a strobe signal line pair, where i is an integer greater than or equal to 1 and less than or equal to 8. The two strobe signal lines in the same strobe signal line pair have opposite polarities. In this exemplary embodiment, the low-level pulse duration of strobe signal line Di is greater than the low-level pulse duration of strobe signal line Di+1. For example, the low-level pulse duration of strobe signal line Di is twice the low-level pulse duration of strobe signal line Di+1.

[0137] FIG7 is a schematic diagram illustrating the structure of an exemplary embodiment of a shift register unit according to the present disclosure. Compared to the shift register unit shown in FIG3 , the shift register unit shown in FIG7 does not include a first pull-down circuit 7 but instead includes a first storage circuit 8 . The first storage circuit 8 is connected to the third node N3 and is configured to store the voltage at the third node N3. The first storage circuit 8 can store the voltage at the third node N3, thereby maintaining the voltage at the third node N3 at the previous stage during the first stage t1. This configuration allows the first pull-down circuit 7 to be omitted.

[0138] In this exemplary embodiment, as shown in FIG7 , the first storage circuit 8 may include: a first capacitor C1, a first electrode of the first capacitor C1 being connected to the third node N3, and a second electrode of the first capacitor C1 being connected to a stable voltage terminal. For example, the second electrode of the first capacitor C1 may be connected to the first power supply terminal VGH. The driving method of the shift register unit shown in FIG7 may be the same as that of the shift register unit shown in FIG3 .

[0139] In this exemplary embodiment, the node setting circuit 1, preprocessing circuit 2, selection circuit 3, input circuit 4, separation circuit 5, output circuit 6, first pull-down circuit 7, reset circuit 9, and second pull-down circuit 10 in the shift register unit shown in Figures 3 and 7 can also be other connection methods or structures.

[0140] FIG8 is a schematic diagram illustrating the structure of a node setting circuit in another exemplary embodiment of a shift register unit according to the present disclosure. The node setting circuit 1 can be connected to a third power supply terminal VDD. In response to a signal from a third clock signal terminal CLK3, the node setting circuit 1 can utilize the third power supply terminal VDD to input a valid voltage level to the first node N1. The first power supply terminal VGH can be reused as the third power supply terminal VDD. Alternatively, the node setting circuit 1 can be connected to a second power supply terminal VGL. In response to signals from a second node N2 and a fourth clock signal terminal CLK4, the node setting circuit 1 can utilize the second power supply terminal VGL to input an inactive voltage level to the first node N1. Furthermore, the node setting circuit 1 can also be configured without the second transistor T2 and the third transistor T3.

[0141] In other exemplary embodiments, the first pull-down circuit 7 may be connected in other ways. For example, the first pull-down circuit 7 may be connected to the second power supply terminal VGL. The first pull-down circuit may be configured to respond to the signal of the second clock signal terminal and input an inactive level to the third node N3 using the second power supply terminal VGL. The second pull-down circuit 10 may be connected in other ways. For example, the second pull-down circuit 10 may be further connected to the second power supply terminal VGL. The second pull-down circuit may be configured to respond to the signal of the control signal terminal and input an inactive level to the first node N1 using the second power supply terminal VGL. The pre-processing circuit 2 may be connected in other ways. For example, the pre-processing circuit 2 may be configured to respond to the signal of the second clock signal terminal and provide an active level to the second node using the first power supply terminal VGH.

[0142] In this exemplary embodiment, in the same shift register unit, the gating transistors Td1-Td8 are of the same type. It should be understood that in other exemplary embodiments, the types of gating transistors Td1-Td8 may be at least partially different, for example, some gating transistors may be P-type transistors and some may be N-type transistors. Different shift register units can achieve different conduction combinations by setting the type of gating transistors while connected to the same gating signal line. A different conduction combination can be understood as having at least one transistor with a different conduction state. For example, in one shift register unit, gating transistors Td1-Td7 are N-type transistors and gating transistor Td8 is a P-type transistor; in another shift register unit, gating transistors Td1-Td8 are all N-type transistors. Even if the two shift register units are connected to the same eight gating signal lines, at least one of the gating transistors Td1-Td8 may have a different gating state. This arrangement allows for arbitrary positioning of the shift register group using fewer gating signal lines.

[0143] In this exemplary embodiment, in different shift register groups, at least some shift register units have different types of combinations of gate transistors. The shift register unit includes n gate signal terminals, and the gate drive circuit includes 2 n The shift register group and n selection signal lines are arranged in correspondence with each other, and the selection signal terminals are connected to the corresponding selection signal lines; in different shift register groups, the type combination of the selection transistors in the shift register units is different.

[0144] In this exemplary embodiment, the same strobe signal line is connected to two n / 2 N-type transistors and 2 n / 2 P-type transistors. In a plurality of shift register groups connected to the first to i-th selection signal lines at the same time, and the selection transistors connected to the same selection signal line are of the same type, the selection transistors connected to the i+1-th selection signal line are half N-type and half P-type. i is an integer greater than or equal to 1 and less than or equal to n-1. For example, the 1st to 2nd n Td1 in the / 2 shift register group is an N-type transistor, and the second n / 2+1 to 2nd n In the group shift register, Td1 is a P-type transistor; from 1st to 2nd n / 4 shift register groups, 2nd n / 2+1 to 3*2 n / 4 group of shift registers Td2 is an N-type transistor, the second n / 4+1 to 2nd n / 2 groups of shift registers, 3rd*2 n / 4+1 to 2nd n In the group shift register, Td2 is a P-type transistor; and by analogy, this setting can be implemented in different shift register groups, where the type combinations of the selection transistors in the shift register units are all different.

[0145] In this exemplary embodiment, the number of shift register units in different shift register groups may be the same or different.

[0146] This exemplary embodiment also provides a display panel, which may include the above-mentioned gate driving circuit. The display panel can be applied to display devices such as mobile phones, tablet computers, and televisions.

[0147] This exemplary embodiment also provides a display device including the above-mentioned display panel.

[0148] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0149] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0150] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A shift register unit, wherein: The shift register unit includes: a node setting circuit, connected to the third clock signal terminal and the first node, and configured to input a valid level to the first node in response to a signal from the third clock signal terminal; a preprocessing circuit connected to the second clock signal terminal, the second node, and the third node, configured to input a valid level to the second node in response to a signal from the second clock signal terminal, and to transmit the signal from the second clock signal terminal to the second node in response to a signal from the third node; a gating circuit connected to the third node, a third clock signal terminal, and one or more gating signal terminals, the gating circuit being configured to transmit the signal of the third clock signal terminal to the third node in response to a signal of any of the gating signal terminals; an input circuit connected to the fourth clock signal terminal, the second node, and one or more control signal terminals, the input circuit being configured to transmit a signal from the fourth clock signal terminal to each of the control signal terminals in response to a signal from the second node; a separation circuit connected to the first node, a plurality of control signal terminals, and a second power terminal, and configured to respond to a signal from the first node to transmit a signal from the second power terminal to each of the control signal terminals; An output circuit is connected to multiple control signal terminals, multiple output clock signal terminals, multiple signal output terminals, and a second power supply terminal. The control signal terminal and the output clock signal terminal are correspondingly arranged, and the control signal terminal and the signal output terminal are correspondingly arranged. The output circuit is used to transmit the signal of the corresponding output clock signal terminal to the corresponding signal output terminal according to the signal of the control signal terminal, and is used to transmit the signal of the second power supply terminal to each signal output terminal in response to the signal of the first node.

2. The shift register unit according to claim 1, wherein: The shift register unit further includes: The first pull-down circuit is connected to the third node and the second clock signal terminal, and is configured to input an invalid level to the third node in response to a signal from the second clock signal terminal.

3. The shift register unit according to claim 1, wherein: The shift register unit further includes: The first storage circuit is connected to the third node, and is used to store the voltage of the third node.

4. The shift register unit according to claim 1, wherein: The shift register unit further includes: A reset circuit is connected to a first power supply terminal, a first node, a second node, a second power supply terminal, and a reset signal terminal. The reset circuit is used to transmit the signal of the first power supply terminal to the first node in response to the signal of the reset signal terminal, and to transmit the signal of the second power supply terminal to the second node in response to the signal of the reset signal terminal.

5. The shift register unit according to claim 1, wherein: The shift register unit further includes: The second pull-down circuit is connected to any one of the control signal terminals and the first node, and is configured to respond to a signal from the control signal terminal to input an invalid level to the first node. The shift register unit according to claim 1 , wherein: The node setting circuit is further connected to a fourth clock signal terminal and a second node, and is configured to input an invalid level to the first node in response to signals from the fourth clock signal terminal and the second node.

7. The shift register unit according to claim 1, wherein: The node setting circuit is configured to respond to a signal at the third clock signal terminal and utilize the third clock signal terminal to provide a valid level to the first node.

8. The shift register unit according to claim 6, wherein: The node setting circuit is configured to respond to the fourth clock signal terminal and the signal of the second node by using the third clock signal terminal to provide an invalid level to the first node.

9. The shift register unit according to claim 2, wherein: The first pull-down circuit is further connected to a third clock signal terminal. The first pull-down circuit is configured to respond to a signal from the second clock signal terminal and input an invalid level to the third node using the third clock signal terminal.

10. The shift register unit according to claim 5, wherein: The second pull-down circuit is further connected to a third clock signal terminal. The second pull-down circuit is configured to respond to a signal from the control signal terminal and input an invalid level to the first node using the third clock signal terminal.

11. The shift register unit according to claim 1, wherein: The pre-processing circuit is configured to respond to a signal at the second clock signal terminal and utilize the second clock signal terminal to provide a valid level to the second node.

12. The shift register unit according to claim 1, wherein: The node setting circuit includes: a first transistor, having a first electrode connected to the third clock signal terminal, a second electrode connected to the first node, and a gate connected to the third clock signal terminal; a second transistor, having a first electrode connected to the first node and a gate connected to the second node; a third transistor, a first electrode of which is connected to the second electrode of the second transistor, and a second electrode of which is connected to the third clock signal terminal; The third capacitor has a first electrode connected to the first node and a second electrode connected to a stable voltage terminal.

13. The shift register unit according to claim 1, wherein: The preprocessing circuit comprises: a fourth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the second node, and a gate connected to the second clock signal terminal; a fifth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the second node, and a gate connected to the third node; The second capacitor has a first electrode connected to the second node and a second electrode connected to a stable voltage terminal.

14. The shift register unit according to claim 1, wherein: The gating circuit comprises: One or more gating transistors, the gating transistors and the gating signal terminals are correspondingly arranged, the first electrode of the gating transistor is connected to the third clock signal terminal, the second electrode of the gating transistor is connected to the third node, and the gate of the gating transistor is connected to the corresponding gating signal terminal.

15. The shift register unit according to claim 1, wherein: The input circuit comprises: a sixth transistor, having a first electrode connected to the fourth clock signal terminal, a second electrode connected to the fourth node, and a gate connected to the second node; One or more input transistors, the input transistors and the control signal terminal are correspondingly arranged, the first electrode of the input transistor is connected to the fourth node, the second electrode of the input transistor is connected to the corresponding control signal terminal, and the gate of the input transistor is connected to the fourth clock signal terminal.

16. The shift register unit according to claim 1, wherein: The separation circuit includes: One or more separation transistors, the separation transistors and the control signal terminal are correspondingly arranged, the first electrode of the separation transistor is connected to the second power supply terminal, the second electrode of the separation transistor is connected to the corresponding control signal terminal, and the gate of the separation transistor is connected to the first node.

17. The shift register unit according to claim 1, wherein: The output circuit includes: One or more first output transistors, each of the first output transistors and the control signal terminal being provided correspondingly, a gate of the first output transistor being connected to the corresponding control signal terminal, a first electrode of the first output transistor being connected to the corresponding output clock signal terminal, and a second electrode of the first output transistor being connected to the corresponding signal output terminal; one or more second output transistors, each of the second output transistors being provided corresponding to the signal output terminal, a gate of the second output transistor being connected to the first node, a first electrode of the second output transistor being connected to the second power supply terminal, and a second electrode of the second output transistor being connected to the corresponding signal output terminal; One or more output capacitors, each of the output capacitors being provided corresponding to the control signal terminal, a first electrode of the output capacitor being connected to the corresponding control signal terminal, and a second electrode of the output capacitor being connected to the corresponding signal output terminal; Among them, the first output transistor and the output clock signal terminal corresponding to the same control signal terminal are correspondingly set, the first output transistor and the signal output terminal corresponding to the same control signal terminal are correspondingly set, and the output capacitor and the signal output terminal corresponding to the same control signal terminal are correspondingly set.

18. The shift register unit according to claim 9, wherein: The first pull-down circuit comprises: A seventh transistor has a first electrode connected to the third clock signal terminal, a second electrode connected to the third node, and a gate connected to the second clock signal terminal.

19. The shift register unit according to claim 3, wherein: The first storage circuit includes: A first capacitor, wherein a first electrode of the first capacitor is connected to the third node, and a second electrode of the first capacitor is connected to a stable voltage terminal.

20. The shift register unit according to claim 4, wherein: The reset circuit comprises: an eighth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first node, and a gate connected to the reset signal terminal; A ninth transistor has a first electrode connected to the second power supply terminal, a second electrode connected to the second node, and a gate connected to the reset signal terminal.

21. The shift register unit according to claim 10, wherein: The second pull-down circuit includes: A tenth transistor has a first electrode connected to the third clock signal terminal, a second electrode connected to the first node, and a gate connected to any one of the control signal terminals.

22. The shift register unit according to claim 14, wherein: In the same shift register unit, the types of the plurality of gate transistors are the same or different.

23. A shift register unit driving method, for driving the shift register unit according to any one of claims 1 to 22, wherein: The driving method includes: In the first stage: using the pre-processing circuit to input a valid level to the second node; In the second stage: when the shift register unit is selected, the third clock signal terminal and the third node are turned off by the gating circuit; when the shift register unit is not selected, the third clock signal terminal and the third node are turned on by the gating circuit; In the third stage, when the shift register unit is selected, the input circuit is used to transmit the signal of the fourth clock signal terminal to each control signal terminal, and when the shift register unit is not selected, the input circuit is used to turn off the fourth clock signal terminal and each control signal terminal; In the fourth stage, when the shift register unit is selected, the output circuit transmits the signal of the corresponding output clock signal terminal to the corresponding signal output terminal according to the signal of the control signal terminal; when the shift register unit is not selected, the output circuit turns off the fourth clock signal terminal and each signal output terminal, and transmits the signal of the second power terminal to the signal output terminal by the output circuit; In the fifth stage, the separation circuit is used to transmit the signal of the second power supply terminal to each control signal terminal, and the output circuit is used to transmit the signal of the second power supply terminal to each signal output terminal.

24. A gate drive circuit, wherein: The gate driving circuit includes a plurality of shift register units according to any one of claims 1 to 21.

25. The gate driving circuit according to claim 24, wherein: The gate driving circuit includes a plurality of shift register groups, each of which includes one or more shift register units. The gate drive circuit further includes: A plurality of strobe signal lines, wherein different strobe signal terminals in the same shift register unit are respectively connected to a different strobe signal line; In the same shift register group, the shift register units are connected to the same selection signal line; In different shift register groups, at least one strobe signal line connected to the shift register units is different.

26. The gate driving circuit according to claim 25, wherein: In different shift register groups, at least some of the shift register units are connected to the same selection signal line.

27. The gate driving circuit according to claim 26, wherein: The shift register unit includes n selection signal terminals, and the gate drive circuit includes 2 n The shift register group and n groups of strobe signal line pairs are provided, each group of the strobe signal line pairs includes two strobe signal lines, and the two strobe signal lines in the same strobe signal line pair are connected to 2 n / 2 groups of shift registers; The n selection signal terminals and n groups of selection signal line pairs in the shift register unit are arranged in a one-to-one correspondence, and one of the selection signal terminals is selectively connected to a selection signal line in the corresponding selection signal line pair; The two strobe signal lines in the same strobe signal line pair have opposite polarities, and n is an integer greater than or equal to 1.

28. The gate driving circuit according to claim 27, wherein: n is greater than or equal to 2; The n groups of selection signal line pairs include the first selection signal line pair to the nth selection signal line pair. In the multiple shift register groups that are simultaneously connected to the same selection signal line in the first to i-th selection signal line pairs, half of the shift register groups are connected to one selection signal line in the i+1-th selection signal line pair, and the other half of the shift register groups are connected to the other selection signal line in the i+1-th selection signal line pair, where i is an integer greater than or equal to 1 and less than or equal to n-1.

29. The gate driving circuit according to claim 24, wherein: The gating circuit includes: One or more gating transistors, the gating transistors and the gating signal terminals are correspondingly provided, a first electrode of the gating transistor is connected to the third clock signal terminal, a second electrode of the gating transistor is connected to the third node, and a gate of the gating transistor is connected to the corresponding gating signal terminal; The gate driving circuit includes a plurality of shift register groups, each of which includes one or more shift register units. In different shift register groups, at least some of the shift register units have different combinations of types of gate transistors.

30. The gate driving circuit according to claim 29, wherein: The shift register unit includes n selection signal terminals, and the gate drive circuit includes 2 n The shift register group and n strobe signal lines are arranged in a corresponding manner, and the strobe signal terminals are connected to the corresponding strobe signal lines; In different shift register groups, the type combinations of the gate transistors in the shift register units are different.

31. The gate driving circuit according to claim 30, wherein: The same selection signal line is connected to 2 n / 2 N-type transistors and 2 n / 2 P-type transistors; In multiple shift register groups that are simultaneously connected to the first to i-th selection signal lines and have the same type of selection transistors connected to the same selection signal line, half of the selection transistors connected to the i+1-th selection signal line are N-type and half are P-type, and i is an integer greater than or equal to 1 and less than or equal to n-1.

32. The gate drive circuit according to claim 25 or 29, wherein: The number of shift register units in different shift register groups is the same or different.

33. A display panel, wherein: The display panel includes the gate driving circuit according to any one of claims 24 to 32.

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