Back contact cell and manufacturing method therefor

Abstract

The present application relates to the technical field of photovoltaics. Disclosed are a back contact cell and a manufacturing method therefor, aiming to prevent first doped semiconductor layers from being connected to second doped semiconductor layers and also shorten the movement distances of some carriers. The back contact cell comprises a silicon substrate, and first doped semiconductor layers and second doped semiconductor layers which are alternately distributed at intervals on the side of a shaded surface of the silicon substrate, wherein the first doped semiconductor layers and the second doped semiconductor layers have opposite conductivity types; in the shaded surface of the silicon substrate, regions corresponding to the first doped semiconductor layers are first regions, regions corresponding to the second doped semiconductor layers are second regions, and a region located between each first region and the second region adjacent to the first region is a spacing region; a surface of each second region is recessed into the silicon substrate relative to a surface of each first region; and a surface of each spacing region is recessed into the silicon substrate relative to the surface of each second region, and the depth by which the surface of each spacing region is recessed into the silicon substrate relative to the surface of each first region is less than 3000 nm.

Description

Back contact battery and manufacturing method thereof Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a method for manufacturing the same. Background Art

[0002] A back-contact cell is a solar cell with no electrodes on the light-facing side of the cell. Instead, both the positive and negative electrodes are located on the backside of the cell. This reduces shading of the cell by the electrodes, increases the cell's short-circuit current, and improves the cell's energy conversion efficiency. Furthermore, a surface passivation layer can be formed on the backside of the back-contact cell to reduce the carrier recombination rate on this side, thereby improving the cell's photoelectric conversion efficiency.

[0003] However, the carrier collection efficiency in existing back-contact batteries is low, which is not conducive to improving the working performance of back-contact batteries.

[0004] Summary of the Invention

[0005] The purpose of this application is to provide a back-contact battery and a manufacturing method thereof, which is used to shorten the movement distance of some carriers and improve the carrier collection efficiency while preventing the first doped semiconductor layer and the second doped semiconductor layer from being conductive, thereby improving the working performance of the back-contact battery.

[0006] In order to achieve the above-mentioned objectives, in a first aspect, the present application provides a back-contact battery, which includes: a silicon substrate, and a first doped semiconductor layer and a second doped semiconductor layer alternately distributed on the backlight side of the silicon substrate. The conductivity types of the first doped semiconductor layer and the second doped semiconductor layer are opposite. In the backlight side of the silicon substrate, the area corresponding to the first doped semiconductor layer is the first area, the area corresponding to the second doped semiconductor layer is the second area, and the area between the first area and the second area adjacent to itself is the spacing area. The surface of the second area is concave into the silicon substrate relative to the surface of the first area. The surface of the spacing area is concave into the silicon substrate relative to the surface of the second area, and the depth of the concave of the surface of the spacing area relative to the surface of the first area into the silicon substrate is less than 3000nm.

[0007] Using the above technical solution, the back-contact cell provided by this application comprises first and second doped semiconductor layers of opposite conductivity types alternately spaced on the backlit side of the silicon substrate. This spacing region on the backlit side of the silicon substrate can isolate the first and second doped semiconductor layers, reducing the carrier recombination rate at the lateral interface between the first and second doped semiconductor layers, thereby improving the photoelectric conversion efficiency of the back-contact cell. Secondly, the first doped semiconductor layer is formed on the first area of ​​the backlight surface, and the second doped semiconductor layer is formed on the second area of ​​the backlight surface. Therefore, when the surface of the second area is concave into the silicon substrate relative to the surface of the first area, and the surface of the spacing area is concave into the silicon substrate relative to the surface of the second area, it indicates that in the actual manufacturing process, after the entire layer of the first doped semiconductor layer covering one side of the backlight surface is selectively etched, not only the portion of the first doped semiconductor layer located on the second area and the spacing area is completely removed, but also part of the thickness of the silicon substrate is further etched to ensure that no first doped semiconductor layer remains on the second area and the spacing area to prevent short circuit; at the same time, it is also beneficial to at least partially stagger the first doped semiconductor layer and the second doped semiconductor layer, which are located on the backlight side of the silicon substrate and have opposite conductivity types, along the thickness direction of the silicon substrate, further reducing the leakage risk on the backlight side and improving the electrical reliability of the back-contact battery. Similarly, when the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, it indicates that in the actual manufacturing process, after the second doped semiconductor layer deposited on the first doped semiconductor layer, the second region and the spacing region is selectively etched, not only is the portion of the second doped semiconductor layer located on the first doped semiconductor layer and the spacing region completely removed, but also the etching continues to continue for part of the thickness of the silicon substrate corresponding to the spacing region, ensuring that no second doped semiconductor layer remains on the first doped semiconductor layer and the spacing region, thereby preventing short circuits.

[0008] In addition, it can be seen from the above that the depth of the recessed spacer region in the backlight surface of the silicon substrate into the silicon substrate is the largest, and the depth of the recessed spacer region into the silicon substrate relative to the surface of the first region is less than 3000nm. Based on this, compared with the depth of the recessed spacer region into the silicon substrate greater than 5μm in the related art, the depth of the recessed spacer region into the silicon substrate in the back-contact battery provided by the present application is smaller. At this time, carriers of the corresponding conductive type can be collected by the first doped semiconductor layer or the second doped semiconductor layer without having to bypass the deeper spacer region, thereby shortening the movement distance of some carriers, improving the carrier collection efficiency, and promoting the performance of the back-contact battery.

[0009] As a possible implementation, the surface of the aforementioned spacer region is planar. In this case, the surface of the spacer region is relatively flat. Based on this, when the back-contact cell also includes a surface passivation layer, the thickness of the surface passivation layer formed on the planar spacer region is greater than that formed on a suede surface. This can enhance the passivation effect of the surface passivation layer on the spacer region, reduce the carrier recombination rate on the surface of the spacer region, and thus improve the photoelectric conversion efficiency of the back-contact cell.

[0010] As a possible implementation, the roughness of the surface of the spacing region within every 10,000 square micrometers is less than or equal to 30 μm. The beneficial effects of this case are similar to those of the plane surface of the isolation region, and will not be repeated here.

[0011] As a possible implementation solution, along the arrangement direction of the first region and the second region, the length of the spacing region is greater than or equal to 20 μm and less than or equal to 110 μm.

[0012] When the above technical solution is adopted, the length of the spacing region is within the above range, which can prevent leakage between the first doped semiconductor layer and the second doped semiconductor layer due to the small spacing, thereby ensuring the high electrical reliability of the back-contact battery. In addition, it can also prevent the large spacing from causing the first doped semiconductor layer and / or the second doped semiconductor layer to form a smaller area on the backlight side, resulting in the inability of carriers on the backlight side to be collected by the first doped semiconductor layer and / or the second doped semiconductor layer in a timely manner and be conducted away by the corresponding electrodes, further reducing the carrier recombination rate on the backlight side.

[0013] As a possible implementation scheme, the surface of the second region is a plane. In this case, the surface of the second region is relatively flat, which is conducive to improving the formation quality of the second doped semiconductor layer formed on the second region. In addition, the surface of the second doped semiconductor layer formed on the second region has a similar degree of undulation to the surface of the second region. Therefore, when the surface of the second region is a plane, it is also conducive to improving the surface flatness of the second doped semiconductor layer on the side away from the silicon substrate. Based on this, when the back contact battery also includes a surface passivation layer, the thickness of the surface passivation layer formed on the second doped semiconductor layer with a higher surface flatness is greater than that of the velvet surface, which can improve the passivation effect of the surface passivation layer on the side of the second doped semiconductor layer away from the silicon substrate, further reduce the carrier recombination rate on the backlight side of the back contact battery, and help improve the photoelectric conversion efficiency of the back contact battery.

[0014] As a possible implementation solution, the depth of the surface of the second region recessed into the silicon substrate is greater than or equal to 100 nm and less than or equal to 1000 nm.

[0015] When the above technical solution is adopted, the depth of the second region's surface recessed into the silicon substrate is within the above range. This can prevent the first doped semiconductor layer and the second doped semiconductor layer, which are co-located on the backlight side of the silicon substrate and have opposite conductivity types, from being offset less along the thickness direction of the silicon substrate due to the smaller depth of the second region's surface recessed into the silicon substrate, thereby further reducing the risk of leakage on the backlight side. In addition, the spacer region is recessed into the silicon substrate relative to the second region, that is, the spacer region is recessed deeper into the silicon substrate than the second region. Therefore, the depth of the second region's surface recessed into the silicon substrate is within the above range. This can prevent the second region's surface recessed deeper into the silicon substrate, which would result in the spacer region recessing deeper into the silicon substrate, thereby ensuring that the distance traveled by some carriers bypassing the spacer region to the first doped semiconductor layer or the second doped semiconductor layer is shorter. At the same time, it can also prevent the need for a thicker silicon substrate due to the larger depth of the second region and the spacer region recessed into the silicon substrate, thereby reducing the manufacturing cost of the back-contact cell and facilitating the thin-film production of the back-contact cell.

[0016] As a possible implementation solution, the height difference between the surface of the second region and the surface of the spacing region is greater than or equal to 300 nm and less than 2000 nm.

[0017] When using the above technical solution, the height difference between the surface of the second region and the surface of the spacer region is within the above range. This can prevent the small height difference from requiring strict control of the etching time during the actual manufacturing process after completely removing the portion of the second doped semiconductor layer located above the spacer region, thereby ensuring that the etchant etches the spacer region of the silicon substrate to a small depth, thereby reducing the etching difficulty. It can also prevent the large height difference from causing a subtle reduction in the distance traveled by carriers of the corresponding conductivity type, thereby ensuring that carrier collection efficiency can be improved.

[0018] As a possible implementation, the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer near the gap region are both wavy. The amplitude of the fluctuation corresponding to the side surface of the second doped semiconductor layer near the gap region is greater than the amplitude of the fluctuation corresponding to the side surface of the first doped semiconductor layer near the gap region, and / or the frequency of the fluctuation corresponding to the side surface of the second doped semiconductor layer near the gap region is less than the frequency of the fluctuation corresponding to the side surface of the first doped semiconductor layer near the gap region.

[0019] When the above-mentioned technical solution is adopted, when the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer close to the gap region are both wavy, if the fluctuation amplitude corresponding to the side surface of the second doped semiconductor layer close to the gap region is greater than the fluctuation amplitude corresponding to the side surface of the first doped semiconductor layer close to the gap region, then the roughness of the local area of ​​the side surface of the second doped semiconductor layer close to the gap region is less than the roughness of the local area of ​​the side surface of the first doped semiconductor layer close to the gap region, which is beneficial to reducing the number of defects in the portion of the second doped semiconductor layer close to the gap region, thereby reducing the carrier recombination rate of the portion of the second doped semiconductor layer close to the gap region, and further improving the working performance of the back contact battery.

[0020] As a possible implementation, at least a portion of the sidewalls of the spacing region is tilted relative to the horizontal plane, so that the cross-sectional area of ​​at least a portion of the spacing region gradually increases from the light-facing surface to the backlight surface.

[0021] When using the above technical solution, the cross-sectional area of ​​the spacer region on the side facing the light is smaller than the cross-sectional area on the side facing the backlight, which helps increase the distance between the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity type, reduces the risk of leakage on the backlight side of the back-contact cell, and ensures the back-contact cell has high electrical reliability. In addition, the portion of the sidewall of the spacer region that is tilted relative to the plane also helps reflect light, allowing more light to enter the silicon substrate from the backlight side of the back-contact cell under the effect of the reflection effect of the portion of the sidewall of the spacer region that is tilted relative to the plane, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0022] As a possible implementation solution, the above-mentioned back-contact cell further includes a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer and the spacer region.

[0023] When using the above technical solution, the surface passivation layer can passivate the backlight side of the back-contact solar cell, reducing the carrier recombination rate on this side. Furthermore, the depth of the deepest recessed interval region into the silicon substrate is less than 3000nm, which helps to reduce the degree of undulation in various regions on the backlight side of the back-contact solar cell, thereby increasing the thickness of the surface passivation layer on this side and improving the passivation effect of the surface passivation layer on this side.

[0024] As a possible implementation solution, the back-contact cell further includes a first passivation layer located between the first region of the silicon substrate and the first doped semiconductor layer.

[0025] When adopting the above technical solution, the first passivation layer and the first doped semiconductor layer can form a selective contact structure to achieve chemical passivation of the first area on the backlight surface of the silicon substrate and selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on the backlight side, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

[0026] As a possible implementation solution, the back-contact cell further includes a second passivation layer located between the second region of the silicon substrate and the second doped semiconductor layer.

[0027] When adopting the above-mentioned technical solution, the second passivation layer and the second doped semiconductor layer can form a selective contact structure to achieve chemical passivation of the second area on the backlight surface of the silicon substrate and selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on the backlight side, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

[0028] As a possible implementation solution, when the back contact cell includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the first doped semiconductor layer is a doped polysilicon layer.

[0029] As a possible implementation solution, when the back contact cell includes a second passivation layer, and the second passivation layer is a tunneling passivation layer, the second doped semiconductor layer is a doped polysilicon layer.

[0030] In addition, the present application also provides a back contact cell, comprising: a silicon substrate, and a first doped semiconductor layer and a second doped semiconductor layer alternately distributed on the backlight side of the silicon substrate; wherein,

[0031] The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; on the backlight surface of the silicon substrate, the area corresponding to the first doped semiconductor layer is the first area, the area corresponding to the second doped semiconductor layer is the second area, and the area between the first area and the second area adjacent to itself is the spacing area; the side surfaces of the first doped semiconductor layer and / or the second doped semiconductor layer close to the spacing area are wavy.

[0032] Based on the above, as a possible implementation solution, the fluctuation amplitude corresponding to the side surface of the second doped semiconductor layer close to the spacing region is greater than the fluctuation amplitude corresponding to the side surface of the first doped semiconductor layer close to the spacing region.

[0033] As a possible implementation solution, the ripple frequency corresponding to the side surface of the second doped semiconductor layer close to the spacing region is smaller than the ripple frequency corresponding to the side surface of the first doped semiconductor layer close to the spacing region.

[0034] As a possible implementation solution, the surface of the second region is recessed into the silicon substrate relative to the surface of the first region; and the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region.

[0035] As a possible implementation, at least a portion of the sidewall of the spacing region is tilted relative to the horizontal plane, so that the cross-sectional area of ​​at least a portion of the spacing region gradually increases from the light-facing surface to the backlight surface.

[0036] In a second aspect, the present application provides a method for manufacturing a back-contact cell, comprising: first, providing a silicon substrate; the backlight surface of the silicon substrate having alternating first and second regions, and a spacer region between the first region and the adjacent second region. Next, forming a first doped semiconductor layer on the first region; and recessing the surfaces of both the spacer region and the second region into the silicon substrate relative to the surface of the first region. Then, forming a second doped semiconductor layer on the second region; and recessing the surface of the spacer region into the silicon substrate relative to the surface of the second region, with the depth of the recess of the spacer region into the silicon substrate relative to the surface of the first region being less than 3000 nm.

[0037] As a possible implementation, after providing a silicon substrate and before forming a second doped semiconductor layer on the second region, the method for manufacturing a back-contact cell includes: forming a first doped semiconductor layer disposed entirely on the backlight surface of the silicon substrate, and forming a first mask layer over the portion of the first doped semiconductor layer corresponding to the first region. Subsequently, under the masking action of the first mask layer, the portion of the first doped semiconductor layer located over the spacer region and the second region is selectively removed; and the surfaces of the spacer region and the second region are recessed into the silicon substrate relative to the surface of the first region.

[0038] As a possible implementation scheme, the material of the above-mentioned first doped semiconductor layer includes silicon. Furthermore, the above-mentioned formation of the first doped semiconductor layer as a whole layer on the backlight surface of the silicon substrate, and the first mask layer located on the portion of the first doped semiconductor layer corresponding to the first region, include: forming a first intrinsic semiconductor layer as a whole layer on the backlight surface of the silicon substrate. Next, the first intrinsic semiconductor layer is doped to form the first doped semiconductor layer from the first intrinsic semiconductor layer, and a first doped silicon glass layer as a whole layer is formed on the first doped semiconductor layer. Then, a laser etching process is used to heat-treat the portion of the first doped silicon glass layer corresponding to the spacing region and the second region, so that the portion of the first doped silicon glass layer that has not been heat-treated forms the first mask layer. Then, the heat-treated portion of the first doped silicon glass layer is removed.

[0039] When the above technical solution is employed, when the material of the first doped semiconductor layer includes silicon, the material of the first intrinsic semiconductor layer used to form the first doped semiconductor layer also includes silicon. Based on this, after doping the first intrinsic semiconductor layer, not only can the first doped semiconductor layer be obtained, but a first doped silica glass layer can also be formed entirely on the first doped semiconductor layer. Subsequently, a laser etching process is used to heat treat a portion of the first doped silica glass layer. During this process, the laser-treated portion of the first doped silica glass layer has reduced density and is easily removed. In contrast, the untreated portion of the first doped silica glass layer has a higher density and is not easily removed. Consequently, after the heat treatment, different portions of the first doped silica glass layer have different etching selectivities, resulting in a first mask layer for patterning the first doped semiconductor layer. This eliminates the need for additional mask materials or mask deposition steps to obtain the first mask layer, thereby reducing the manufacturing cost of back-contact solar cells and simplifying the manufacturing process for back-contact solar cells.

[0040] As a possible implementation scheme, a wet chemical process is used to selectively remove portions of the first doped semiconductor layer located on the spacer region and the second region under the masking action of a first mask layer, and the surfaces of the spacer region and the second region are recessed into the silicon substrate relative to the surface of the first region. The wet chemical process temperature is greater than or equal to 60°C and less than or equal to 80°C; and / or the wet chemical process time is greater than or equal to 40 seconds and less than or equal to 200 seconds; and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is greater than or equal to 2% and less than or equal to 20%; and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is greater than or equal to 0.5% and less than or equal to 5%.

[0041] When using the above technical solution, the process temperature and process time of the wet chemical process both affect the depth to which the surfaces of the spacer region and the second region are recessed into the silicon substrate relative to the surface of the first region. Therefore, keeping the process temperature within the above range can prevent the surfaces of the spacer region and the second region from recessing into the silicon substrate to a smaller depth relative to the surface of the first region due to a lower process temperature. Furthermore, it can also prevent the surfaces of the spacer region and the second region from recessing into the silicon substrate to a greater depth relative to the surface of the first region due to a higher process temperature. After this process, the depth to which the surfaces of the spacer region and the second region are recessed into the silicon substrate relative to the surface of the first region is equal to the depth to which the surface of the second region is recessed into the silicon substrate relative to the surface of the first region in the resulting back-contact cell. The beneficial effects of preventing the surface of the second region from recessing into the silicon substrate to a greater or lesser depth relative to the surface of the first region can be found in the previous discussion. Furthermore, the beneficial effects of maintaining the process time and the volume ratio of the alkaline component within the above range are similar to those of maintaining a process temperature greater than or equal to 60°C and less than or equal to 80°C, and are not further elaborated here. In addition, the volume ratio of the polishing additive in the wet chemical etching solution is within the above range, which can improve the flatness of the surface of the spacing area and the second area after the operation, and further improve the passivation effect of the surface passivation layer on the spacing area and the second doped semiconductor layer.

[0042] As a possible implementation, after the surfaces of the spacer region and the second region are recessed into the silicon substrate relative to the surface of the first region, the method for manufacturing a back-contact cell includes: depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacer region, and the second region; and forming a second mask layer on the portion of the second doped semiconductor layer corresponding to the second region. Next, under the masking effect of the second mask layer, selectively removing the portion of the second doped semiconductor layer corresponding to the first region and the spacer region; and recessing the surface of the spacer region relative to the surface of the second region into the silicon substrate.

[0043] As a possible implementation scheme, the material of the second doped semiconductor layer includes silicon. Furthermore, the above-mentioned steps of depositing the second doped semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region; and forming a second mask layer on the portion of the second doped semiconductor layer corresponding to the second region, include: depositing a second intrinsic semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region. Next, doping the second intrinsic semiconductor layer to form the second doped semiconductor layer, and forming a second doped silicon glass layer on the second doped semiconductor layer. Next, using a laser etching process, heat-treating the portion of the second doped silicon glass layer corresponding to the first region and the spacing region to form a second mask layer on the portion of the second doped silicon glass layer corresponding to the second region. Then, removing the heat-treated portion of the second doped silicon glass layer.

[0044] In the above technical solution, when the material of the second doped semiconductor layer includes silicon, the material of the second intrinsic semiconductor layer used to form the second doped semiconductor layer also includes silicon. Based on this, after doping the second intrinsic semiconductor layer, not only the second doped semiconductor layer is obtained, but also a second doped silica glass layer can be formed entirely on the second doped semiconductor layer. Then, a laser etching process is used to heat treat the portions of the second doped silica glass layer corresponding to the first region and the spacing region. During this process, the laser-treated portions of the second doped silica glass layer have reduced density and are easily removed. Meanwhile, the portions of the second doped silica glass layer corresponding to the second region are not laser-treated and have higher density, making them less easily removed. Consequently, after the heat treatment, different portions of the second doped silica glass layer have different etching selectivities, resulting in a second mask layer for patterning the second doped semiconductor layer. This eliminates the need for additional mask materials and mask deposition steps to obtain the second mask layer, thereby reducing the manufacturing cost of back-contact solar cells and simplifying the manufacturing process for back-contact solar cells.

[0045] As a possible implementation scheme, a wet chemical process is used, and under the masking action of a second mask layer, portions of the second doped semiconductor layer corresponding to the first region and the spacer region are selectively removed, and the surface of the spacer region is recessed into the silicon substrate relative to the surface of the second region. The wet chemical process temperature is greater than or equal to 60°C and less than or equal to 80°C; and / or the wet chemical process time is greater than or equal to 50 seconds and less than or equal to 300 seconds; and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is greater than or equal to 2% and less than or equal to 20%; and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is greater than or equal to 0.5% and less than or equal to 5%.

[0046] When the above technical solution is adopted, the process temperature and process time of the wet chemical process will affect the depth to which the surface of the spacer region is recessed into the silicon substrate relative to the surface of the second region through the wet chemical process. Based on this, if the process temperature of the wet chemical process is within the above range, it can prevent the surface of the spacer region from being recessed into the silicon substrate to a smaller depth relative to the surface of the second region due to a lower process temperature. In addition, it can also prevent the surface of the spacer region from being recessed into the silicon substrate to a greater depth relative to the surface of the second region due to a higher process temperature. The beneficial effects of preventing the surface of the spacer region from being recessed into the silicon substrate to a smaller or greater depth relative to the surface of the second region can be referred to above. Secondly, the beneficial effects of the process time and the volume ratio of the alkaline component within the above range are similar to the beneficial effects of the process temperature being greater than or equal to 60°C and less than or equal to 80°C, and will not be repeated here. In addition, if the volume ratio of the polishing additive in the wet chemical etching solution is within the above range, it can improve the flatness of the surface of the spacer region after the operation, further improving the passivation effect of the surface passivation layer on the spacer region.

[0047] As a possible implementation solution, after providing a silicon substrate and before forming a first doped semiconductor layer on the first region, the method for manufacturing a back-contact cell further includes: forming a first passivation layer on the first region.

[0048] As a possible implementation scheme, after the surfaces of the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region, and before forming a second doped semiconductor layer on part of the second region, the manufacturing method of the back contact battery also includes: forming a second passivation layer on the second region.

[0049] As a possible implementation scheme, after the surface of the spacer region is recessed into the silicon substrate relative to the surface of the second region, the manufacturing method of the back contact battery also includes: forming a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer and the spacer region.

[0050] The beneficial effects of the second aspect and its various implementations in this application can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0052] FIG1 is a longitudinal cross-sectional SEM image of the structure of a back contact battery in the related art;

[0053] FIG2 is a schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0054] FIG3 is a SEM image 1 of a partial structure of a back-contact battery provided in an embodiment of the present application;

[0055] FIG4 is a second SEM image of a partial structure of a back-contact battery provided in an embodiment of the present application;

[0056] FIG5 is a third SEM image of a partial structure of a back-contact battery provided in an embodiment of the present application;

[0057] FIG6 is a fourth SEM image of a partial structure of a back-contact battery provided in an embodiment of the present application;

[0058] FIG7 is a fifth SEM image of a partial structure of a back-contact battery provided in an embodiment of the present application;

[0059] FIG8 is a first structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0060] FIG9 is a second structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0061] FIG10 is a third structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0062] FIG11 is a fourth structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0063] FIG12 is a fifth structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0064] FIG13 is a sixth structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0065] FIG14 is a seventh structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0066] FIG15 is a structural schematic diagram eight of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0067] FIG16 is a ninth structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0068] FIG17 is a structural schematic diagram 10 of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0069] FIG18 is a structural schematic diagram 11 of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0070] FIG19 is a structural schematic diagram 12 of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0071] FIG20 is a thirteenth structural diagram of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0072] FIG21 is a structural schematic diagram 14 of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0073] FIG22 is a schematic top view of a back-contact battery provided in an embodiment of the present application.

[0074] Figure numerals: 11 is a silicon substrate, 12 is a first doped semiconductor layer, 13 is a second doped semiconductor layer, 14 is a first region, 15 is a second region, 16 is a spacing region, 17 is a surface passivation layer, 18 is a first passivation layer, 19 is a second passivation layer, 20 is a first mask layer, 21 is a second mask layer, 22 is a first intrinsic semiconductor layer, 23 is a first doped silicon glass layer, 24 is a second intrinsic semiconductor layer, and 25 is a second doped silicon glass layer. DETAILED DESCRIPTION

[0075] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0076] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0077] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application more clearly understood, the application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain this application and are not intended to limit this application.

[0078] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0079] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0080] Solar cells are increasingly being used as a new energy alternative. Photovoltaic solar cells convert sunlight into electricity. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, facilitating efficient use of the electrical energy.

[0081] Among them, when the positive and negative electrodes included in the solar cell are both located on the backlight side of the solar cell, the solar cell is a back-contact cell. The light-facing side of the back-contact cell is not affected by the obstruction of the metal electrode. Therefore, compared with solar cells with obstructed light-facing sides, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, and are one of the current technical directions for achieving high-efficiency crystalline silicon cells. Specifically, as shown in Figure 1, the existing back-contact cell generally includes a silicon substrate 11, and a first doped semiconductor layer 12 and a second doped semiconductor layer 13 alternately distributed on the backlight side of the silicon substrate 11. The first doped semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conductivity types.

[0082] In the actual manufacturing process, a first doped semiconductor layer is typically formed entirely on the backlight side. This first doped semiconductor layer is then selectively etched, leaving only the first doped semiconductor layer located on the backlight side. A second doped semiconductor layer is then formed on the first doped semiconductor layer and the portion of the backlight side exposed to the first doped semiconductor layer. This second doped semiconductor layer is then selectively etched, leaving the first doped semiconductor layer and the second doped semiconductor layer alternately spaced on the backlight side of the silicon substrate.

[0083] However, as shown in FIG1 , the first doped semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conductivity types. To prevent the first doped semiconductor layer 12 and the second doped semiconductor layer 13 from being conductive and causing a short circuit, existing manufacturing methods use wet chemical etching or other methods to form a spacing region 16 of a certain width between the two. However, in existing back-contact cells, the spacing region 16 between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 is recessed into the silicon substrate 11 to a large depth (e.g., greater than 5 μm). This requires carriers in the silicon substrate 11 to bypass the deep isolation region before they can be collected by the first doped semiconductor layer 12 and the second doped semiconductor layer 13, respectively. This results in a longer carrier movement distance, which in turn leads to lower carrier collection efficiency and a higher carrier recombination rate, which is not conducive to improving the operating performance of the back-contact cell.

[0084] To address the above-mentioned technical issues, in a first aspect, embodiments of the present application provide a back-contact cell. As shown in FIG2 , the back-contact cell provided by the embodiments of the present application includes: a silicon substrate 11, and first and second doped semiconductor layers 12, 13 alternately spaced on the backlight side of the silicon substrate 11. The first and second doped semiconductor layers 12, 13 have opposite conductivity types. On the backlight side of the silicon substrate 11, the region corresponding to the first doped semiconductor layer 12 is a first region 14, the region corresponding to the second doped semiconductor layer 13 is a second region 15, and the region between the first region 14 and the adjacent second region 15 is a spacer region 16. The surface of the second region 15 is recessed into the silicon substrate 11 relative to the surface of the first region 14. The surface of the spacer region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15, and the depth of the recess of the surface of the spacer region 16 relative to the surface of the first region 14 into the silicon substrate 11 is less than 3000 nm.

[0085] Using the above technical solution, as shown in FIG2 , in the back-contact cell provided in the embodiment of the present application, first doped semiconductor layers 12 and second doped semiconductor layers 13 of opposite conductivity types are alternately spaced on the backlight side of the silicon substrate 11. Based on this, the spacing region 16 on the backlight side of the silicon substrate 11 can isolate the first doped semiconductor layers 12 and the second doped semiconductor layers 13, reducing the carrier recombination rate at the lateral boundary between the first doped semiconductor layers 12 and the second doped semiconductor layers 13, thereby improving the photoelectric conversion efficiency of the back-contact cell. Secondly, the first doped semiconductor layer 12 is formed on the first region 14 on the backlight side, and the second doped semiconductor layer 13 is formed on the second region 15 on the backlight side. Therefore, when the surface of the second region 15 is concave into the silicon substrate 11 relative to the surface of the first region 14, and the surface of the spacer region 16 is concave into the silicon substrate 11 relative to the surface of the second region 15, it indicates that in the actual manufacturing process, after the entire layer of the first doped semiconductor layer 12 covering the backlight side is selectively etched, not only the portion of the first doped semiconductor layer 12 located on the second region 15 and the spacer region 16 is completely removed, but also a portion of the thickness of the silicon substrate 11 is further etched, ensuring that no first doped semiconductor layer 12 remains on the second region 15 and the spacer region 16, thereby preventing short circuit; at the same time, it is also beneficial to at least partially stagger the first doped semiconductor layer 12 and the second doped semiconductor layer 13, which are both located on the backlight side of the silicon substrate 11 and have opposite conductivity types, along the thickness direction of the silicon substrate 11, further reducing the leakage risk on the backlight side and improving the electrical reliability of the back-contact battery. Similarly, when the surface of the spacer region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15, this indicates that during the actual manufacturing process, the selective etching of the second doped semiconductor layer 13 deposited on the first doped semiconductor layer 12, the second region 15, and the spacer region 16 not only completely removes the portion of the second doped semiconductor layer 13 located on the first doped semiconductor layer 12 and the spacer region 16, but also further etches the thickness of the silicon substrate 11 corresponding to the spacer region 16, ensuring that no second doped semiconductor layer 13 remains on the first doped semiconductor layer 12 and the spacer region 16, thus preventing short circuits. Furthermore, as can be seen from the foregoing, the recessed depth of the spacer region 16 into the silicon substrate 11 is greatest on the backlight side of the silicon substrate 11, while the recessed depth of the spacer region 16 into the silicon substrate 11 relative to the surface of the first region 14 is less than 3000 nm. Based on this, compared with the prior art in which the depth of the recessed spacer region in the silicon substrate is greater than 5 μm, the depth of the recessed spacer region 16 in the silicon substrate 11 provided in the back contact battery provided by the embodiment of the present application is smaller. At this time, the carriers of the corresponding conductive type do not need to bypass the deeper spacer region 16 to be collected by the first doped semiconductor layer 12 or the second doped semiconductor layer 13, thereby shortening the movement distance of some carriers, improving the carrier collection efficiency, and helping to improve the working performance of the back contact battery.

[0086] In actual applications, as shown in Figure 2, the light-facing surface of the silicon substrate 11 can be flat or velvet-finished. Because velvet traps light, a velvet-finished surface can reduce the reflectivity of the light-facing surface, allowing more light to be refracted from the light-facing surface into the silicon substrate for absorption and utilization, thereby improving the photoelectric conversion efficiency of the back-contact solar cell.

[0087] In addition, in terms of scope, the boundaries of the first region, the second region, and the spacing region on the backlight side of the above-mentioned silicon substrate are virtual boundaries. As shown in Figure 2, the first doped semiconductor layer 12 is formed on the first region 14. Therefore, the scope of the first region 14 on the backlight side of the silicon substrate 11 can be determined based on the requirements for the formation scope of the first doped semiconductor layer 12 in the actual application scenario. Secondly, the second doped semiconductor layer 13 is formed on the second region 15. Therefore, the scope of the second region 15 on the backlight side of the silicon substrate 11 can be determined based on the requirements for the formation scope of the second doped semiconductor layer 13 in the actual application scenario. As for the spacing region 16, as mentioned above, the spacing region 16 can isolate the first doped semiconductor layer 12 and the second doped semiconductor layer 13 of opposite conductivity types to suppress leakage. Therefore, the scope of the spacing region 16 on the backlight side can be determined based on the requirements for the anti-leakage spacing between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 in the actual application scenario.

[0088] Exemplarily, along the arrangement direction of the first region and the second region, the length of the spacing region is greater than or equal to 20 μm and less than or equal to 110 μm. For example, the length of the spacing region can be 20 μm, 40 μm, 60 μm, 80 μm, 100 μm or 110 μm, etc. In this case, the length of the spacing region is within the above range, which can prevent leakage between the first doped semiconductor layer and the second doped semiconductor layer due to the small spacing, thereby ensuring that the back contact battery has high electrical reliability. In addition, it can also prevent the carriers on the backlight side from being collected by the first doped semiconductor layer and / or the second doped semiconductor layer in time and being led out by the corresponding electrode due to the large spacing, thereby further reducing the carrier recombination rate on the backlight side.

[0089] In terms of the depth of the recess, the depth of the second area and the spacing area on the backlight surface of the above-mentioned silicon substrate recessed into the silicon substrate, as well as the height difference between the second area and the surface of the spacing area can be determined according to the actual application scenario, as long as it is ensured that the second area is recessed inward relative to the surface of the first area, and the surface of the spacing area is recessed inward relative to the surface of the second area, and the depth of the recess of the surface of the spacing area relative to the surface of the first area into the silicon substrate is less than 3000nm.

[0090] Exemplarily, the depth of the surface of the second region recessed into the silicon substrate may be greater than or equal to 100 nm and less than or equal to 1000 nm. For example, the depth of the surface of the second region recessed into the silicon substrate may be 100 nm, 300 nm, 600 nm, 800 nm, 900 nm, or 1000 nm. In this case, the depth of the surface of the second region recessed into the silicon substrate is within the above-mentioned range, which can prevent the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types, which are co-located on the backlight side of the silicon substrate and have opposite conductivity types, from being offset to a smaller extent along the thickness direction of the silicon substrate due to the small depth of the surface of the second region recessed into the silicon substrate, thereby further reducing the risk of leakage on the backlight side. In addition, the spacing region is recessed into the silicon substrate relative to the second region, that is, compared with the second region, the spacing region is recessed deeper into the silicon substrate. Therefore, the depth of the surface of the second region recessed into the silicon substrate is within the above range, which can prevent the surface of the second region from being recessed deeper into the silicon substrate, resulting in the spacing region being recessed deeper into the silicon substrate, thereby ensuring that the movement distance of some carriers bypassing the spacing region to be transmitted to the first doped semiconductor layer or the second doped semiconductor layer is shorter; at the same time, it can also prevent the need to use a thicker silicon substrate due to the greater depth of the second region and the spacing region recessed into the silicon substrate, thereby reducing the manufacturing cost of the back-contact battery and facilitating the thin-film production of the back-contact battery.

[0091] Exemplarily, the height difference between the surface of the second region and the surface of the spacing region can be greater than or equal to 300nm and less than 2000nm. For example, the height difference between the surface of the second region and the surface of the spacing region can be 300nm, 600nm, 900nm, 1200nm, 1500nm, 1800nm ​​or 2000nm. In this case, the height difference between the surface of the second region and the surface of the spacing region is within the above range, which can prevent the etching time from being strictly controlled after the portion of the second doped semiconductor layer located on the spacing region is completely removed during the actual manufacturing process due to the small height difference, so that the etching depth of the etchant to the spacing region of the silicon substrate is small, thereby reducing the etching difficulty. It can also prevent the large height difference from causing the corresponding conductive type carrier movement distance to be reduced significantly, thereby ensuring that the carrier collection efficiency can be improved.

[0092] The depth of the recessed spacer region into the silicon substrate can be any value greater than the recessed depth of the second region surface into the silicon substrate and less than 3000 nm. For example, when the recessed depth of the second region surface into the silicon substrate is 500 nm, the recessed depth of the spacer region relative to the first region surface into the silicon substrate can be any value greater than 500 nm and less than 3000 nm (e.g., 1000 nm, 1500 nm, 1800 nm, 2000 nm, 2500 nm, 2800 nm, or 2900 nm).

[0093] In terms of surface morphology, as shown in FIG2 , in the backlight surface of the silicon substrate 11, the surface of the first region 14 is a plane. The surface of the second region 15 can be a plane or a velvet surface. Specifically, as shown in FIG2 to FIG7 , when the surface of the second region 15 is a plane, the surface of the second region 15 is relatively flat, which is beneficial to improving the formation quality of the second doped semiconductor layer 13 formed on the second region 15. In addition, the surface of the second doped semiconductor layer 13 formed on the second region 15 has a similar degree of undulation to that of the surface of the second region 15. Therefore, when the surface of the second region 15 is a plane, it is also beneficial to improve the surface flatness of the second doped semiconductor layer 13 on the side facing away from the silicon substrate 11. Based on this, when the back contact battery also includes a surface passivation layer 17, compared with the velvet surface, the thickness of the surface passivation layer 17 formed on the second doped semiconductor layer 13 with a higher surface flatness is larger, which can improve the passivation effect of the surface passivation layer 17 on the side of the second doped semiconductor layer 13 away from the silicon substrate 11, further reduce the carrier recombination rate on the backlight side of the back contact battery, and help improve the photoelectric conversion efficiency of the back contact battery.

[0094] As for the spacing region, as shown in Figures 2 to 7, the surface of the spacing region 16 can be a plane or a velvet surface. Among them, as shown in Figures 2 to 7, when the surface of the spacing region 16 is a plane, the surface of the spacing region 16 is relatively flat. Based on this, when the back contact battery also includes a surface passivation layer 17, the thickness of the portion of the surface passivation layer 17 formed on the spacing region 16 with a plane surface is larger than that of the velvet surface, which can improve the passivation effect of the surface passivation layer 17 on the spacing region 16, reduce the carrier recombination rate on the surface of the spacing region 16, and help improve the photoelectric conversion efficiency of the back contact battery. Specifically, the surface roughness of the spacing region 16 can be determined based on the requirements for the passivation effect of the surface passivation layer 17 on the spacing region 16 in the actual application scenario, as well as the actual manufacturing process, and is not specifically limited here.

[0095] When the spacing region is a velvet surface, the recessed depth of the spacing region may be the depth of the top position of the velvet surface of the spacing region recessed into the silicon substrate relative to the surface of the first region, or the depth of the bottom position of the velvet surface of the spacing region recessed into the silicon substrate relative to the surface of the first region; in at least one of the above cases, the recessed depth of the spacing region is less than 3000nm.

[0096] For example, the surface roughness of the spacer region within a range of 10,000 square microns (100 microns x 100 microns) may be less than or equal to 30 μm. For example, the surface roughness of the spacer region within a range of 10,000 square microns may be 5 μm, 10 μm, 12 μm, 15 μm, 18 μm, 20 μm, 22 μm, 25 μm, or 30 μm. The beneficial effects in this case are similar to those of the planar surface of the isolation region and are not further described here.

[0097] When the surface of the second region or the spacer region is a velvet surface, the size of the velvet structure on the surface can be determined based on the depth of the velvet surface recessed into the silicon substrate, and is not specifically limited here. It is understood that, within a certain range, the smaller the depth of the velvet surface recessed into the silicon substrate, the smaller the size of the velvet structure on its surface. In addition, it should be noted that when the surface of the second region or the spacer region is a velvet surface, the depth of the recessed surface of the second region or the spacer region into the silicon substrate is equal to the vertical distance from the middle of the velvet structure in the second region or the spacer region to the surface of the first region.

[0098] As for the sidewall morphology of the spacer region, as shown in FIG2 , the sidewall of the spacer region 16 can be perpendicular to the horizontal plane. Alternatively, as shown in FIG13 , at least a portion of the sidewall of the spacer region 16 can be inclined relative to the horizontal plane, such that the cross-sectional area of ​​at least a portion of the spacer region 16 gradually increases from the light-facing side to the backlight side. In this case, the cross-sectional area of ​​the spacer region 16 on the light-facing side is smaller than the cross-sectional area on the backlight side, which helps increase the distance between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 of opposite conductivity type, reduces the risk of leakage on the backlight side of the back-contact cell, and ensures high electrical reliability of the back-contact cell. Furthermore, the portion of the sidewall of the spacer region 16 that is inclined relative to the plane also helps reflect light, allowing more light to enter the silicon substrate 11 from the backlight side of the back-contact cell through reflection from the portion of the sidewall of the spacer region 16 that is inclined relative to the plane, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0099] In the above case, the angle between the portion of the side wall of the spacing region that is tilted relative to the horizontal plane and the horizontal plane can be determined according to the actual manufacturing process and the reflection requirements of the side wall, and is not specifically limited here.

[0100] Exemplarily, the angle between the portion of the sidewall of the spacer region that is tilted relative to the horizontal plane and the horizontal plane can be greater than or equal to 52° and less than or equal to 58°. For example, the angle between the portion of the sidewall of the spacer region that is tilted relative to the horizontal plane and the horizontal plane can be 52°, 53°, 54°, 55°, 56°, 57°, or 58°, etc. In this case, if the angle is within the above range, it can ensure that more light can enter the silicon substrate and be utilized by the silicon substrate due to the greater reflection effect of the portion of the sidewall of the spacer region that is tilted relative to the horizontal plane, thereby further improving the utilization rate of light by the back contact cell.

[0101] Regarding the above-mentioned first doped semiconductor layer and the second doped semiconductor layer, in terms of materials, the material of the above-mentioned first doped semiconductor layer or the second doped semiconductor layer can be a semiconductor material such as silicon, silicon germanium, germanium or gallium arsenide. In terms of the arrangement of the material, the crystal phase of the first doped semiconductor layer or the second doped semiconductor layer can be amorphous, microcrystalline, nanocrystalline, single crystal or polycrystalline, etc. In terms of conductivity type, the conductivity type of the first doped semiconductor layer or the second doped semiconductor layer can be opposite to the conductivity type of the silicon substrate, or can be the same as the conductivity type of the silicon substrate, as long as the conductivity types of the first doped semiconductor layer and the second doped semiconductor layer are opposite. As for the thickness of the first doped semiconductor layer and the second doped semiconductor layer, it can be set according to actual needs and is not specifically limited here. For example, the thickness of the first doped semiconductor layer or the second doped semiconductor layer can be greater than or equal to 100nm and less than or equal to 500nm.

[0102] In actual applications, the first doped semiconductor layer can be formed directly on the first region of the silicon substrate. Alternatively, as shown in FIG2 , the back-contact cell further includes a first passivation layer 18 located between the first region 14 of the silicon substrate 11 and the first doped semiconductor layer 12. In this case, the first passivation layer 18 and the first doped semiconductor layer 12 can form a selective contact structure to chemically passivate the first region 14 on the backlight side of the silicon substrate 11 and selectively collect carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the backlight side and improving the photoelectric conversion efficiency of the back-contact cell.

[0103] Specifically, the material of the first passivation layer can be determined according to the material of the first doped semiconductor layer and the type of the selective contact structure composed of the first passivation layer and the first doped semiconductor layer in actual application scenarios, and is not specifically limited here.

[0104] For example, when the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a tunneling passivation contact structure, the first doped semiconductor layer is a doped polysilicon layer, and the first passivation layer is a tunneling passivation layer. The material of the tunneling passivation layer may include silicon oxide, aluminum oxide, or titanium oxide.

[0105] For another example, when the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a heterogeneous contact structure, the first doped semiconductor layer is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the first passivation layer is an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0106] The thickness of the first passivation layer can be set according to actual needs and is not specifically limited here. For example, the thickness of the first passivation layer can be greater than or equal to 0.5 nm and less than or equal to 3 nm.

[0107] As for the second doped semiconductor layer mentioned above, the second doped semiconductor layer can be formed directly on the second region of the silicon substrate. Alternatively, as shown in Figure 2, the back-contact cell also includes a second passivation layer 19 located between the second region 15 of the silicon substrate 11 and the second doped semiconductor layer 13. In this case, the second passivation layer 19 and the second doped semiconductor layer 13 can form a selective contact structure to chemically passivate the second region 15 of the backlight side of the silicon substrate 11 and selectively collect carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the backlight side and improving the photoelectric conversion efficiency of the back-contact cell.

[0108] Specifically, the material and thickness of the second passivation layer may refer to the material and thickness of the first passivation layer described above, and will not be repeated here.

[0109] In terms of morphology, the embodiments of the present application do not impose any specific restrictions on the side morphology of the first doped semiconductor layer and the second doped semiconductor layer near the gap region, as long as they can be applied to the back-contact battery provided in the embodiments of the present application. For example, the side of the first doped semiconductor layer and / or the second doped semiconductor layer near the gap region can be in a straight line, a broken line, an arc shape, or a wavy shape. The side morphology of the first doped semiconductor layer near the gap region can be the same as or different from the side morphology of the second doped semiconductor layer near the gap region.

[0110] In actual applications, as shown in Figures 3 to 7 , the side surfaces of the first and second doped semiconductor layers 12 and 13 near the gap region 16 can both be wavy. Furthermore, the fluctuation amplitude corresponding to the side surface of the second doped semiconductor layer 13 near the gap region 16 can be greater than the fluctuation amplitude corresponding to the side surface of the first doped semiconductor layer 12 near the gap region 16. Furthermore, the fluctuation frequency corresponding to the side surface of the second doped semiconductor layer 13 near the gap region 16 can be less than the fluctuation frequency corresponding to the side surface of the first doped semiconductor layer 12 near the gap region 16. In this case, when the fluctuation amplitude corresponding to the side surface of the second doped semiconductor layer 13 near the gap region 16 is greater than the fluctuation amplitude corresponding to the side surface of the first doped semiconductor layer 12 near the gap region 16, the roughness of the local area of ​​the side surface of the second doped semiconductor layer 13 near the gap region 16 is less than the roughness of the local area of ​​the side surface of the first doped semiconductor layer 12 near the gap region 16. This helps reduce the number of defects in the portion of the second doped semiconductor layer 13 near the gap region 16, thereby reducing the carrier recombination rate in the portion of the second doped semiconductor layer 13 near the gap region 16 and further improving the performance of the back-contact battery.

[0111] The fluctuation amplitude corresponding to the side surface of the first doped semiconductor layer and the second doped semiconductor layer near the gap region refers to the fluctuation amplitude of the convex portion of the side surface relative to the lowest point of the concave portion of the side surface. Furthermore, the fluctuation frequency corresponding to the side surface of the first doped semiconductor layer and the second doped semiconductor layer near the gap region refers to the frequency with which different convex portions of the side surface appear. Specifically, when the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer near the gap region are both wavy, the fluctuation amplitude and fluctuation frequency of the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer near the gap region can be determined based on the actual manufacturing process and are not specifically limited here.

[0112] As a possible implementation scheme, as shown in FIG2 , the above-mentioned back-contact cell may further include a surface passivation layer 17 covering the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the spacer region 16. In this case, the surface passivation layer 17 can passivate the backlight side of the back-contact cell, reducing the carrier recombination rate on the backlight side. In addition, the spacer region 16, which is recessed the deepest into the silicon substrate 11, has a corresponding recess depth of less than 3000 nm, which is conducive to reducing the degree of undulation of various regions on the backlight side of the back-contact cell, increasing the thickness of the surface passivation layer 17 on the backlight side, and improving the passivation effect of the surface passivation layer 17 on the backlight side.

[0113] Specifically, the surface passivation layer may be made of any insulating material with a passivating effect, such as silicon oxide, aluminum oxide, or silicon nitride. The thickness of the surface passivation layer can be determined based on the actual application scenario and is not specifically limited here.

[0114] In a second aspect, embodiments of the present application provide a method for manufacturing a back-contact battery. The manufacturing process will be described below based on the cross-sectional views of the operations shown in Figures 2 to 21. Specifically, the method for manufacturing a back-contact battery includes the following steps:

[0115] First, a silicon substrate is provided; the backlight surface of the silicon substrate has first areas and second areas alternately distributed, and an interval area between the first area and the second area adjacent to the first area.

[0116] Specifically, the ranges of the first area, the second area, and the spacing area on one side of the backlight surface can be referred to above and will not be described in detail here.

[0117] Next, as shown in FIG. 12 to FIG. 14 , a first doped semiconductor layer 12 is formed on the first region 14 ; and the surfaces of the spacer region 16 and the second region 15 are recessed into the silicon substrate 11 relative to the surface of the first region 14 .

[0118] In an actual manufacturing process, as shown in FIG11 , after providing a silicon substrate 11, a first doped semiconductor layer 12 is formed entirely on the backlight surface of the silicon substrate 11, along with a first mask layer 20 located on the portion of the first doped semiconductor layer 12 corresponding to the first region 14. Next, as shown in FIG12 and FIG13 , under the masking action of the first mask layer 20, the portion of the first doped semiconductor layer 12 located on the spacing region 16 and the second region 15 is selectively removed, and the surfaces of the spacing region 16 and the second region 15 are recessed into the silicon substrate 11 relative to the surface of the first region 14.

[0119] The material and thickness of the first doped semiconductor layer, as well as the depth to which the surfaces of the spacer region and the second region are recessed into the silicon substrate after the operation, can be referenced above. Regarding the first mask layer, the material of the first mask layer can be any material that can function as a mask and is not specifically limited here. Secondly, the specific materials used for the first doped semiconductor layer and the first mask layer can determine the specific process for forming the doped semiconductor layer and the first mask layer.

[0120] For example, when the material of the first doped semiconductor layer includes silicon, the steps of forming the first doped semiconductor layer as a whole layer on the backlit surface of the silicon substrate and the first mask layer on the portion of the first doped semiconductor layer corresponding to the first region may include the following steps: as shown in FIG8 , forming a first intrinsic semiconductor layer 22 as a whole layer on the backlit surface of the silicon substrate 11. Next, as shown in FIG9 , the first intrinsic semiconductor layer 22 is doped to form the first doped semiconductor layer 12 from the first intrinsic semiconductor layer 22, and forming a first doped silicon glass layer 23 as a whole layer on the first doped semiconductor layer 12. Next, as shown in FIG10 , the portions of the first doped silicon glass layer 23 corresponding to the spacing regions 16 and the second regions 15 are heat-treated using a laser etching process to form the first mask layer 20 in the portions of the first doped silicon glass layer 23 that have not been heat-treated. Next, as shown in FIG11 , the heat-treated portions of the first doped silicon glass layer 23 are removed.

[0121] Specifically, the material of the first doped semiconductor layer includes silicon, which may mean that the material of the first doped semiconductor layer only includes silicon; or it may also mean that the material of the first doped semiconductor layer includes both silicon and other semiconductor materials such as germanium silicon. Secondly, in the actual manufacturing process, chemical vapor deposition and other processes can be used to form a first intrinsic semiconductor layer that is arranged on the backlight side as a whole layer. Next, the first intrinsic semiconductor layer can be doped using diffusion and other processes. After the above-mentioned doping treatment, not only the first doped semiconductor layer can be obtained, but also a first doped silicon glass layer that is arranged as a whole layer on the first doped semiconductor layer can be formed. Then, a laser etching process is used to heat-treat part of the first doped silicon glass layer. At this time, as shown in Figure 10, the density of the laser-treated portion of the first doped silicon glass layer becomes poorer, and it is easy to be removed. The portions of the first doped silica glass layer that have not been laser-treated are denser and less easily removed. Consequently, after heat treatment, different portions of the first doped silica glass layer have different etching selectivities, resulting in a first mask layer 20 for patterning the first doped semiconductor layer 12. This eliminates the need for forming additional mask materials or performing additional mask deposition steps to obtain the first mask layer 20, thereby reducing the manufacturing cost of back-contact cells and simplifying the manufacturing process for back-contact cells. The specific conditions for the laser etching process can be set based on the actual application scenario and are not specifically limited here.

[0122] For example, the laser used in the laser etching process may be a nanosecond laser, a picosecond laser, or a femtosecond laser, etc. The laser etching process may have a power greater than or equal to 10W and less than or equal to 100W, and the diameter of the laser spot may be greater than or equal to 50 μm and less than or equal to 300 μm.

[0123] Of course, when the material of the first doped semiconductor layer includes silicon, or when the material of the first doped semiconductor layer does not include silicon, chemical vapor deposition and doping processes can also be used to form the entire first doped semiconductor layer disposed on the backlight side. Then, chemical vapor deposition and etching processes can be used to form a first mask layer made of other materials such as silicon nitride that have a masking function.

[0124] Furthermore, after forming the first mask layer, a wet chemical process can be used to selectively remove the portion of the first doped semiconductor layer located above the spacer region and the second region under the masking effect of the first mask layer. The surfaces of the spacer region and the second region are recessed into the silicon substrate relative to the surface of the first region to prevent damage to the silicon substrate caused by the high-temperature laser, thereby improving the yield of back-contact cells. Specifically, the process conditions for selectively etching the first doped semiconductor layer can be determined based on the etching process used, the material of the first doped semiconductor layer, and the depth to which the surfaces of the spacer region and the second region are recessed into the silicon substrate after the operation, and are not specifically limited herein.

[0125] For example, when the wet chemical process selectively removes the portion of the first doped semiconductor layer located on the spacer region and the second region under the mask of the first mask layer, and causes the surfaces of the spacer region and the second region to be recessed into the silicon substrate relative to the surface of the first region, the process temperature of the wet chemical process can be greater than or equal to 60° C. and less than or equal to 80° C.; furthermore, the process time of the wet chemical process can be greater than or equal to 40 seconds and less than or equal to 200 seconds; furthermore, the wet chemical etching solution used in the wet chemical process can be an alkaline wet chemical etching solution, and the volume ratio of the alkaline component (such as NaOH or KOH) in the alkaline wet chemical etching solution can be greater than or equal to 2% and less than or equal to 20%. For example, the process temperature of the wet chemical process can be 60° C., 70° C., 75° C., 78° C., or 80° C., and the process time of the wet chemical process can be 40 seconds, 60 seconds, 80 seconds, 100 seconds, 150 seconds, or 200 seconds, etc. When the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, the volume ratio of the alkaline component in the alkaline wet chemical etching solution can be 2%, 3%, 6%, 9%, 12%, 15%, or 20%, etc. In this case, the process temperature and process time of the wet chemical process both affect the depth to which the surfaces of the spacer region and the second region are recessed relative to the surface of the first region into the silicon substrate during the wet chemical process. Therefore, keeping the process temperature within the above range can prevent the surfaces of the spacer region and the second region from recessing less deeply relative to the surface of the first region due to a lower process temperature. Furthermore, it can also prevent the surfaces of the spacer region and the second region from recessing more deeply relative to the surface of the first region due to a higher process temperature. After this process, the depth to which the surfaces of the spacer region and the second region are recessed relative to the surface of the first region into the silicon substrate is equal to the depth to which the surface of the second region is recessed relative to the surface of the first region in the resulting back-contact cell. The beneficial effects of preventing the surface of the second region from recessing more deeply relative to the surface of the first region into the silicon substrate can be found in the previous description. Secondly, the beneficial effects of the process time and the volume ratio of the alkaline component within the above ranges are similar to the beneficial effects of the process temperature being greater than or equal to 60° C. and less than or equal to 80° C., and will not be repeated here.

[0126] In addition, polishing additives can be added to the wet chemical etching solution to improve the flatness of the surface of the spacer region and the second region after the operation, and further improve the passivation effect of the surface passivation layer on the spacer region and the second doped semiconductor layer. Specifically, the composition of the polishing additive and the proportion of the polishing additive in the wet chemical etching solution can be determined according to the actual application scenario and are not specifically limited here. For example, the polishing additive may include sodium benzoate, a defoaming agent, and a surfactant. The volume ratio of the polishing additive in the wet chemical etching solution may be greater than or equal to 0.5% and less than or equal to 5%.

[0127] It should be noted that when the manufactured back-contact battery also includes a first passivation layer located between the first region and the first doped semiconductor layer, after providing a silicon substrate and before forming the first doped semiconductor layer on the first region, the manufacturing method of the back-contact battery also includes the steps of: using a deposition and etching process to first form a first passivation layer on the first region.

[0128] Alternatively, as shown in FIG8 , after providing a silicon substrate, a process such as chemical vapor deposition can be used to form a first passivation layer 18 entirely on the backlight side. Then, as shown in FIG11 to FIG13 , after forming a first mask layer 20 and selectively etching the first doped semiconductor layer 12 under the masking action of the first mask layer 20, the first passivation layer 18 is selectively etched. In this case, there is no need to form an additional mask layer for forming the first passivation layer 18, simplifying the manufacturing process of the back-contact cell.

[0129] Next, after the surfaces of the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region, as shown in FIG20 , a second doped semiconductor layer 13 is formed on the second region 15; and the surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15, and the depth of the recess of the surface of the spacing region 16 into the silicon substrate 11 relative to the surface of the first region 14 is less than 3000 nm.

[0130] In an actual manufacturing process, as shown in FIG18 , after the surfaces of the spacer region 16 and the second region 15 are recessed into the silicon substrate 11 relative to the surface of the first region 14, the second doped semiconductor layer 13 is deposited on the first doped semiconductor layer 12, the spacer region 16, and the second region 15. A second mask layer 21 is formed on the portion of the second doped semiconductor layer 13 corresponding to the second region 15. Next, as shown in FIG19 , under the masking action of the second mask layer 21, the portion of the second doped semiconductor layer 13 corresponding to the first region 14 and the spacer region 16 is selectively removed, and the surface of the spacer region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15.

[0131] Specifically, the material and thickness of the second doped semiconductor layer, as well as the depth of the recess of the surface of the spacer region into the silicon substrate after the operation, can be found in the previous section and will not be further elaborated here. The second mask layer can be made of any material that can function as a mask. In actual manufacturing, the formation process and specific steps of the second doped semiconductor layer and the second mask layer can be determined based on their materials.

[0132] For example, when the material of the second doped semiconductor layer includes silicon, the above-mentioned steps of depositing the second doped semiconductor layer on the first doped semiconductor layer, the spacer region, and the second region; and forming a second mask layer on the portion of the second doped semiconductor layer corresponding to the second region may include the following steps: as shown in FIG15 , depositing a second intrinsic semiconductor layer 24 on the first doped semiconductor layer 12, the spacer region 16, and the second region 15. Next, as shown in FIG16 , doping the second intrinsic semiconductor layer 24 to form the second doped semiconductor layer 13, and forming a second doped silicon glass layer 25 entirely on the second doped semiconductor layer 13. Next, as shown in FIG17 , heat-treating the portion of the second doped silicon glass layer 25 corresponding to the first region 14 and the spacer region 16 using a laser etching process to form a second mask layer 21 on the portion of the second doped silicon glass layer 25 corresponding to the second region 15. Then, as shown in FIG18 , removing the heat-treated portion of the second doped silicon glass layer 25.

[0133] Specifically, the material of the second doped semiconductor layer includes silicon, which may mean that the material of the second doped semiconductor layer only includes silicon; or it may also mean that the material of the second doped semiconductor layer includes both silicon and other semiconductor materials such as germanium silicon. Secondly, in the actual manufacturing process, chemical vapor deposition and other processes can be used to form a second intrinsic semiconductor layer that is arranged on the backlight side as a whole layer. Next, the second intrinsic semiconductor layer can be doped using diffusion and other processes. After the above-mentioned doping treatment, not only the second doped semiconductor layer can be obtained, but also a second doped silicon glass layer that is arranged as a whole layer can be formed on the second doped semiconductor layer. Then, a laser etching process is used to heat-treat the portion of the second doped silicon glass layer corresponding to the first region and the spacing region. At this time, the density of the laser-treated portion of the second doped silicon glass layer becomes poor, and it is easy to be removed. The portion of the second doped silica glass layer corresponding to the second region is not laser-treated. At this time, the portion of the second doped silica glass layer corresponding to the second region is highly dense and difficult to remove. Consequently, after heat treatment, different portions of the second doped silica glass layer have different etching selectivities, thereby obtaining a second mask layer for patterning the second doped semiconductor layer. This eliminates the need to form additional mask materials or perform additional mask deposition steps to obtain the second mask layer, thereby reducing the manufacturing cost of back-contact cells and simplifying the manufacturing process for back-contact cells. The specific conditions of the aforementioned laser etching process can be found in the previous text and are not specifically limited here.

[0134] Of course, when the material of the second doped semiconductor layer includes silicon, or when the material of the second doped semiconductor layer does not include silicon, chemical vapor deposition and doping processes can also be used to form a second doped semiconductor layer disposed entirely on the backlight side. Then, chemical vapor deposition and etching processes can be used to form a second mask layer made of other materials such as silicon nitride that have a masking function.

[0135] Furthermore, after forming the second mask layer, a wet chemical process or other process can be employed, and under the masking action of the second mask layer, the portion of the second doped semiconductor layer located on the spacer region and the first doped semiconductor layer can be selectively removed. Furthermore, the surface of the spacer region is recessed into the silicon substrate relative to the surface of the second region to prevent damage to the silicon substrate caused by the high-temperature laser, thereby improving the yield of the back-contact solar cell. Specifically, the process conditions for selectively etching the second doped semiconductor layer can be determined based on the etching process used, the material of the second doped semiconductor layer, and the depth of the recess of the spacer region surface into the silicon substrate, and are not specifically limited herein.

[0136] For example, when a wet chemical process is used under the mask of the second mask layer to selectively remove portions of the second doped semiconductor layer corresponding to the first region and the spacer region, and the surface of the spacer region is recessed into the silicon substrate relative to the surface of the second region, the process temperature of the wet chemical process can be greater than or equal to 60° C. and less than or equal to 80° C.; furthermore, the process time of the wet chemical process can be greater than or equal to 50 seconds and less than or equal to 300 seconds; furthermore, the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component (such as NaOH or KOH) in the alkaline wet chemical etching solution can be greater than or equal to 2% and less than or equal to 20%. For example, the process temperature of the wet chemical process can be 60° C., 70° C., 75° C., 78° C., or 80° C., and the process time of the wet chemical process can be 50 seconds, 55 seconds, 60 seconds, 100 seconds, 150 seconds, 200 seconds, or 300 seconds. When the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, the volume ratio of the alkaline component in the alkaline wet chemical etching solution can be 2%, 3%, 6%, 9%, 12%, 15%, or 20%, etc. In this case, the process temperature and process time of the wet chemical process both affect the depth to which the surface of the spacer region is recessed into the silicon substrate relative to the surface of the second region during the wet chemical process. Therefore, keeping the process temperature of the wet chemical process within the above range can prevent the spacer region's surface from recessing into the silicon substrate to a smaller depth relative to the surface of the second region due to a lower process temperature. Furthermore, keeping the process temperature within the above range can prevent the spacer region's surface from recessing into the silicon substrate to a greater depth relative to the surface of the second region due to a higher process temperature. The beneficial effects of preventing the spacer region's surface from recessing into the silicon substrate to a smaller or greater depth relative to the surface of the second region can be found in the previous description. Furthermore, the beneficial effects of keeping the process time and the volume ratio of the alkaline component within the above range are similar to those of keeping the process temperature greater than or equal to 60°C and less than or equal to 80°C, and will not be further elaborated here.

[0137] In addition, polishing additives can be added to the wet chemical etching solution to improve the flatness of the surface of the spacer area after the operation, and further improve the passivation effect of the surface passivation layer on the spacer area. Specifically, the composition of the polishing additive and the proportion of the polishing additive in the wet chemical etching solution can be determined according to the actual application scenario and are not specifically limited here. For example, the polishing additive may include sodium benzoate, a defoaming agent, and a surfactant. The volume ratio of the polishing additive in the wet chemical etching solution may be greater than or equal to 0.5% and less than or equal to 5%.

[0138] It should be noted that when the manufactured back-contact battery also includes a second passivation layer located between the second region and the second doped semiconductor layer, after the surfaces of the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region, and before the second doped semiconductor layer is formed on part of the second region, the manufacturing method of the back-contact battery also includes the step of: using a deposition and etching process to first form a second passivation layer on the second region.

[0139] Alternatively, as shown in FIG15 , after the surfaces of the spacer region and the second region are recessed into the silicon substrate relative to the surface of the first region, and before and after the second doped semiconductor layer is formed on a portion of the second region, a second passivation layer 19 can be deposited on the first doped semiconductor layer, the second region, and the spacer region using a process such as chemical vapor deposition. Then, as shown in FIG18 and FIG19 , after forming a second mask layer 21 and selectively etching the second doped semiconductor layer under the masking action of the second mask layer 21, the second passivation layer 19 is selectively etched. In this case, there is no need to form an additional mask layer to form the second passivation layer 19, simplifying the manufacturing process of the back-contact cell.

[0140] In addition, when the manufactured back-contact cell further includes a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer, and the spacer region, after the surface of the spacer region is recessed into the silicon substrate relative to the surface of the second region, as shown in FIG21 , a process such as chemical vapor deposition can be used to form a surface passivation layer 17 covering the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the spacer region 16. The material and thickness of the surface passivation layer 17 can be referred to above.

[0141] The beneficial effects of the second aspect and its various implementations in the embodiments of the present application can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0142] In addition, the present invention also provides a comparative example and an example to illustrate the manufacturing process and working performance of the back-contact battery provided in the present invention. Table 1 shows the test results of the back-contact battery corresponding to Example 1 and Comparative Example 1.

[0143] Example 1

[0144] In the first step, the single crystal silicon wafer is subjected to alkaline polishing treatment using an alkaline solution having a concentration of 15% to form a smooth and clean silicon surface.

[0145] In the second step, a tunnel oxide layer and an intrinsic polysilicon layer are sequentially deposited on the surface of the single crystal silicon wafer, wherein the thickness of the tunnel oxide layer is 1.8 nm and the thickness of the intrinsic polysilicon layer is 350 nm.

[0146] The third step is to perform boron doping on the deposited intrinsic polysilicon layer to form a P-type doped polysilicon layer; and to form a borosilicate glass layer on the P-type doped polysilicon layer. The boron doping concentration is 8×10 19 / cm 3 .

[0147] The fourth step is to heat-treat the borosilicate glass layer using a laser etching process to prepare a mask layer with a specific pattern. The laser can be a picosecond laser with a processing power of 40W and a spot diameter of 200μm.

[0148] In the fifth step, under the masking effect of the mask layer, portions of the P-type doped polysilicon layer are selectively removed. The surface of the single-crystal silicon wafer is then etched to form a groove structure. The etching solution used mainly consists of an alkali and a polishing additive. The alkali concentration in the etching solution is 5%, the etching temperature is 82°C, the process time is 300 seconds, and the polishing additive is 2% by volume. The polishing additive mainly includes sodium benzoate, a defoaming agent, and a surfactant.

[0149] Step 6: Form a tunneling oxide layer and an N-type doped polysilicon layer stacked in sequence at the bottom of the groove structure; and recess the portion of the single crystal silicon wafer between the P-type doped polysilicon layer and the N-type doped polysilicon layer into the silicon substrate relative to the bottom surface of the groove structure. The thickness of the N-type doped polysilicon layer is greater than or equal to 150 nm and less than or equal to 180 nm. The thickness of the tunneling oxide layer is greater than or equal to 0.5 nm and less than or equal to 3 nm. The portion of the single crystal silicon wafer between the P-type doped polysilicon layer and the N-type doped polysilicon layer recessed into the silicon substrate to a depth of less than 3000 nm.

[0150] Step 7: forming a surface passivation layer covering the single crystal silicon wafer, the P-type doped polysilicon layer and the N-type doped polysilicon layer.

[0151] Comparative Example 1

[0152] The manufacturing method corresponding to Comparative Example 1 is identical to the manufacturing process of Example 1, except for step 6. In the manufacturing method provided in Comparative Example 1, after forming a tunneling oxide layer and an N-type doped polysilicon layer stacked in sequence at the bottom of the groove structure, the portion of the single crystal silicon wafer located between the P-type doped polysilicon layer and the N-type doped polysilicon layer is recessed into the silicon substrate to a depth greater than 5 μm, and the surface of the portion of the single crystal silicon wafer located between the P-type doped polysilicon layer and the N-type doped polysilicon layer is textured.

[0153] Table 1 Test results of back contact cells corresponding to Example 1 and Comparative Example 1

[0154] It can be seen from the data shown in Table 1 that in the back-contact battery formed by the manufacturing method provided in Example 1, the carrier movement distance can be shortened because the depth of the spacer region recessed into the silicon substrate is small; and when the back-contact battery also includes a surface passivation layer, the passivation effect of the surface passivation layer on the spacer region can be improved, thereby achieving higher working efficiency, open-circuit voltage, short-circuit current and fill factor than the back-contact battery obtained by the corresponding manufacturing method of Comparative Example 1, that is, the back-contact battery provided in the embodiment of the present application has higher working performance.

[0155] On the other hand, as shown in Figure 22, in some other embodiments, the back-contact battery disclosed in the present invention includes a silicon substrate 11, and a first doped semiconductor layer 12 and a second doped semiconductor layer 13 alternately distributed on the backlight side of the silicon substrate 11. The first doped semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conductivity types, the first doped semiconductor layer 12 is a P-type doped polycrystalline silicon layer, and the second doped semiconductor layer 13 is an N-type doped polycrystalline silicon layer.

[0156] On the backlight surface of the silicon substrate 11, the area corresponding to the first doped semiconductor layer 12 is the first area 14, the area corresponding to the second doped semiconductor layer 13 is the second area 15, and the area between the first area 14 and the second area 15 adjacent to itself is the spacing area 16; the side surfaces (sidewall surfaces) of the first doped semiconductor layer 12 or the second doped semiconductor layer 13 close to the spacing area 16 both present a quasi-wavy structure; it is easy to understand that the corresponding silicon substrate 11 also presents a quasi-wavy structure on the side surfaces (sidewall surfaces) close to the spacing area 16 corresponding to the first area 14 and the second area 15.

[0157] A first passivation layer (tunneling passivation layer, not shown in the figure) is provided between the first doped semiconductor layer 12 and the silicon substrate 11 ; a second passivation layer (tunneling oxide layer, not shown in the figure) is provided between the second doped semiconductor layer 13 and the silicon substrate 11 .

[0158] Among them, the side wall of the P-type doped polysilicon layer has a wavy structure. In the wavy structure, its amplitude A (the distance from the peak to the trough in the direction from the P-type doped polysilicon layer to the N-type doped polysilicon layer) is: 3-15μm; the step length L (the distance between each two adjacent peaks along the extension direction of the spacing region 16) is: 3-15μm.

[0159] The sidewall of the N-type doped polysilicon layer has a wavy structure. In the direction from the P-type doped polysilicon layer to the N-type doped polysilicon layer, in the wavy structure, the amplitude A (the distance from the peak to the valley) is: 10-70 μm, preferably: 30-60 μm; the step length L (the distance between each two adjacent peaks along the extension direction of the spacing region 16) is: 10-40 μm;

[0160] In addition, in the above-mentioned wavy structure, the wavy curve is not completely smooth, but has a sawtooth shape, which can increase the probability of light scattering and scatter more light into the spacing area 16.

[0161] Example 2

[0162] This embodiment is a further improved embodiment based on the above embodiment (illustrated in FIG22 ), with the difference being that the fluctuation amplitude A of the second doped semiconductor layer 13 (N-type doped polysilicon layer) is different from the fluctuation amplitude of the first doped semiconductor layer 12 (P-type doped polysilicon layer). Specifically, the fluctuation amplitude of the second doped semiconductor layer 13 is greater than that of the first doped semiconductor layer 12, and the sum of the amplitude A of the first doped semiconductor layer 12 and the amplitude A of the second doped semiconductor layer 13 is less than 50% of the average width of the spacing region 16. To ensure effective isolation between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 and avoid leakage risks, the width of the spacing region 16 is 100 μm, the amplitude A of the first doped semiconductor layer 12 is 3 μm, and the amplitude A of the second doped semiconductor layer 13 is 35 μm.

[0163] Generally speaking, in order to ensure effective isolation between the P-type doped polysilicon layer and the N-type doped polysilicon layer, the spacing region 16 needs to ensure a certain effective width. Therefore, the sum of the amplitude A of the first doped semiconductor layer 12 and the amplitude A of the second doped semiconductor layer 13 is less than 50% of the average width of the spacing region 16; and because the side walls of the first doped semiconductor layer 12 and the first region 14 facing the spacing region 16 are higher, and the side walls of the second doped semiconductor layer 13 and the second region 15 facing the spacing region 16 are lower; the leakage risk on the side with the higher side wall (P-type doped polysilicon layer) is greater, and the process control of the fluctuation shape is more difficult to achieve. Therefore, the amplitude A of the first doped semiconductor layer 12 is set to be relatively small, and the amplitude A of the second doped semiconductor layer 13 is set to be relatively large, so as to control the leakage risk and facilitate process control.

[0164] Example 3

[0165] This embodiment is a further improved embodiment based on the above embodiment (illustrated in FIG22 ). The difference is that the first doped semiconductor layer 12 and the second doped semiconductor layer 13 have different frequencies of undulation structures; specifically, the undulation frequency of the second doped semiconductor layer 13 is less than the undulation frequency of the first doped semiconductor layer 12. The step length L (the distance between two adjacent wave peaks along the extension direction of the spacing region 16) of the first doped semiconductor layer 12 is set to 5 μm, and the step length L (the distance between two adjacent wave peaks along the extension direction of the spacing region 16) of the second doped semiconductor layer 13 is set to 20 μm.

[0166] It should be understood that the larger the step length L of the wave structure, the smaller the wave frequency of the corresponding wave structure; conversely, the smaller the step length L of the wave structure, the larger the wave frequency of the corresponding wave structure.

[0167] In practical applications, when a large number of peaks face each other, this reduces the effective gap isolation spacing and creates a large number of leakage risk points. In this embodiment, because the first doped semiconductor layer 12 and the second doped semiconductor layer 13 have different oscillation frequencies, it is possible to avoid a large number of peaks facing each other at the same frequency in the direction facing the gap region. This leakage risk point is overcome by setting the oscillation frequency.

[0168] Example 4

[0169] This embodiment is a further improved embodiment based on the above embodiment (shown in FIG22 ), and the difference is that:

[0170] In this embodiment, in the wavy structure of the sidewall of the P-type doped polysilicon layer, the amplitude A (the distance from the peak to the trough in the direction from the P-type doped polysilicon layer to the N-type doped polysilicon layer) is 5 μm; the step length L (the distance between each two adjacent peaks along the extension direction of the spacing region 16) is 8 μm; in the wavy structure of the sidewall of the N-type doped polysilicon layer, the amplitude A (the distance from the peak to the trough in the direction from the P-type doped polysilicon layer to the N-type doped polysilicon layer) is 20 μm; the step length L (the distance between each two adjacent peaks along the extension direction of the spacing region 16) is 30 μm.

[0171] By optimizing the fluctuation amplitude and fluctuation frequency (indicated by the step length L) of the first doped semiconductor layer 12 and the second doped semiconductor layer 13 in the above embodiment, it is possible to avoid the situation where a large number of peaks appear relative to each other in the direction facing the spacing area, and the amplitude A of the first doped semiconductor layer 12 is set to be relatively small, while the amplitude A of the second doped semiconductor layer 13 is set to be relatively large, so as to synergistically overcome the risk points of leakage and easily achieve process control on the higher side of the side wall (P-type doped polysilicon layer).

[0172] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0173] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A back contact battery, wherein: include: A silicon substrate, and a first doped semiconductor layer and a second doped semiconductor layer alternately distributed on a backlight side of the silicon substrate; wherein, The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; in the backlight surface of the silicon substrate, the area corresponding to the first doped semiconductor layer is the first area, the area corresponding to the second doped semiconductor layer is the second area, and the area between the first area and the second area adjacent to the first area is the spacing area; The surface of the second region is recessed into the silicon substrate relative to the surface of the first region; the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, and the depth of the recess of the surface of the spacing region into the silicon substrate relative to the surface of the first region is less than 3000nm.

2. The back contact cell according to claim 1, wherein: The roughness of the surface of the spacing area within a range of 10,000 square micrometers is less than or equal to 30 μm; and / or, Along the arrangement direction of the first region and the second region, the length of the spacing region is greater than or equal to 20 μm and less than or equal to 110 μm.

3. The back contact cell according to claim 1, wherein: The surface of the second region is a plane; and / or, The depth of the surface of the second region recessed into the silicon substrate is greater than or equal to 100 nm and less than or equal to 1000 nm; and / or, A height difference between a surface of the second region and a surface of the spacing region is greater than or equal to 300 nm and less than 2000 nm.

4. The back contact cell according to claim 1, wherein: The side surfaces of the first doped semiconductor layer and the second doped semiconductor layer close to the spacing region are both wavy; wherein the fluctuation amplitude corresponding to the side surface of the second doped semiconductor layer close to the spacing region is greater than the fluctuation amplitude corresponding to the side surface of the first doped semiconductor layer close to the spacing region, and / or the fluctuation frequency corresponding to the side surface of the second doped semiconductor layer close to the spacing region is less than the fluctuation frequency corresponding to the side surface of the first doped semiconductor layer close to the spacing region; and / or, At least part of the surface of the side wall of the spacing area is inclined relative to the horizontal plane, so that the cross-sectional area of ​​at least part of the spacing area gradually increases from the light-facing surface to the backlight surface.

5. The back contact battery according to any one of claims 1 to 4, wherein: The back contact cell further comprises a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer and the spacing region; and / or, The back contact cell further comprises a first passivation layer located between the first region of the silicon substrate and the first doped semiconductor layer; and / or, The back contact cell further includes a second passivation layer located between the second region of the silicon substrate and the second doped semiconductor layer.

6. The back contact cell according to claim 5, wherein: In the case where the back contact cell includes the first passivation layer, and the first passivation layer is a tunnel passivation layer, the first doped semiconductor layer is a doped polysilicon layer; and / or, In the case that the back contact cell comprises the second passivation layer, and the second passivation layer is a tunnel passivation layer, the second doped semiconductor layer is a doped polysilicon layer.

7. A back contact battery, wherein: include: A silicon substrate, and a first doped semiconductor layer and a second doped semiconductor layer alternately distributed on a backlight side of the silicon substrate; wherein, The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; in the backlight surface of the silicon substrate, the area corresponding to the first doped semiconductor layer is the first area, the area corresponding to the second doped semiconductor layer is the second area, and the area between the first area and the second area adjacent to the first area is the spacing area; The side surface of the first doped semiconductor layer and / or the second doped semiconductor layer close to the spacing region is wavy.

8. The back contact cell according to claim 7, wherein: The fluctuation amplitude corresponding to the side surface of the second doped semiconductor layer close to the spacing region is greater than the fluctuation amplitude corresponding to the side surface of the first doped semiconductor layer close to the spacing region.

9. The back contact cell according to claim 7 or 8, wherein: The fluctuation frequency corresponding to the side surface of the second doped semiconductor layer close to the spacing region is smaller than the fluctuation frequency corresponding to the side surface of the first doped semiconductor layer close to the spacing region.

10. The back contact cell according to claim 9, wherein: The surface of the second region is concave toward the silicon substrate relative to the surface of the first region; and the surface of the spacing region is concave toward the silicon substrate relative to the surface of the second region.

11. The back contact cell according to claim 10, wherein: At least part of the surface of the side wall of the spacing area is inclined relative to the horizontal plane, so that the cross-sectional area of ​​at least part of the spacing area gradually increases from the light-facing surface to the backlight surface.

12. A method for manufacturing a back contact battery, wherein: include: Providing a silicon substrate; The backlight surface of the silicon substrate has first areas and second areas that are alternately spaced and arranged, and a spacing area between the first area and the second area adjacent to the first area; forming a first doped semiconductor layer on the first region; and making the surfaces of the spacing region and the second region both concave into the silicon substrate relative to the surface of the first region; A second doped semiconductor layer is formed on the second region; and a surface of the spacing region is recessed into the silicon substrate relative to a surface of the second region, and a depth of the recessed surface of the spacing region relative to a surface of the first region into the silicon substrate is less than 3000 nm.

13. The method for manufacturing a back contact battery according to claim 12, wherein: After providing a silicon substrate and before forming a second doped semiconductor layer on the second region, the method for manufacturing a back contact cell includes: forming a first doped semiconductor layer disposed entirely on the backlight surface of the silicon substrate, and a first mask layer located on a portion of the first doped semiconductor layer corresponding to the first region; Under the masking effect of the first mask layer, the first doped semiconductor layer located in the spacing area and the The surface of the spacer region and the second region are both recessed into the silicon substrate relative to the surface of the first region.

14. The method for manufacturing a back contact battery according to claim 13, wherein: The material of the first doped semiconductor layer includes silicon; The first doped semiconductor layer formed as a whole layer on the backlight surface of the silicon substrate, and the first mask layer located on the portion of the first doped semiconductor layer corresponding to the first region, include: Forming a first intrinsic semiconductor layer disposed entirely on the backlight surface of the silicon substrate; Performing a doping treatment on the first intrinsic semiconductor layer so that the first intrinsic semiconductor layer forms the first doped semiconductor layer, and forming a first doped silicon glass layer disposed entirely on the first doped semiconductor layer; Using a laser etching process, heat-treating the portion of the first doped silicon glass layer corresponding to the spacing region and the second region, so that the portion of the first doped silicon glass layer that has not been heat-treated forms the first mask layer; The heat-treated portion of the first doped silicon glass layer is removed.

15. The method for manufacturing a back contact battery according to claim 13, wherein: A wet chemical process is used to selectively remove the portion of the first doped semiconductor layer located on the spacing region and the second region under the masking action of the first mask layer; and the surfaces of the spacing region and the second region are both recessed into the silicon substrate relative to the surface of the first region; wherein, The process temperature of the wet chemical process is greater than or equal to 60°C and less than or equal to 80°C; and / or, the process time of the wet chemical process is greater than or equal to 40s and less than or equal to 200s; and / or, the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is greater than or equal to 2% and less than or equal to 20%; and / or, the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is greater than or equal to 0.5% and less than or equal to 5%.

16. The method for manufacturing a back contact battery according to claim 12, wherein: After the surfaces of the spacing region and the second region are both recessed into the silicon substrate relative to the surface of the first region, the method for manufacturing the back contact cell comprises: Depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacer region and the second region; and forming a second mask layer on a portion of the second doped semiconductor layer corresponding to the second region; Under the masking effect of the second mask layer, the portion of the second doped semiconductor layer corresponding to the first region and the spacing region is selectively removed; and the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region.

17. The method for manufacturing a back contact battery according to claim 16, wherein: The material of the second doped semiconductor layer includes silicon; Depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacing region and the second region; and forming a second mask layer on a portion of the second doped semiconductor layer corresponding to the second region, comprising: depositing a second intrinsic semiconductor layer on the first doped semiconductor layer, the spacer region and the second region; Performing a doping treatment on the second intrinsic semiconductor layer so that the second intrinsic semiconductor layer forms the second doped semiconductor layer, and forming a second doped silicon glass layer disposed entirely on the second doped semiconductor layer; Using a laser etching process, heat-treating the portion of the second doped silicon glass layer corresponding to the first region and the spacing region, so that the portion of the second doped silicon glass layer corresponding to the second region forms the second mask layer; The heat-treated portion of the second doped silicon glass layer is removed.

18. The method for manufacturing a back contact battery according to claim 16, wherein: A wet chemical process is used, and under the masking effect of the second mask layer, the portion of the second doped semiconductor layer corresponding to the first region and the spacing region is selectively removed, and the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region; wherein, The process temperature of the wet chemical process is greater than or equal to 60°C and less than or equal to 80°C; and / or, the process time of the wet chemical process is greater than or equal to 50s and less than or equal to 300s; and / or, the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is greater than or equal to 2% and less than or equal to 20%; and / or, the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is greater than or equal to 0.5% and less than or equal to 5%.

19. The method for manufacturing a back contact battery according to any one of claims 12 to 18, wherein: After providing a silicon substrate and before forming a first doped semiconductor layer on the first region, the method for manufacturing a back contact battery further includes: forming a first passivation layer on the first region; and / or, After the surfaces of the spacing region and the second region are both recessed into the silicon substrate relative to the surface of the first region, and before the second doped semiconductor layer is formed on part of the second region, the method for manufacturing a back contact battery further includes: forming a second passivation layer on the second region; and / or, After making the surface of the spacing region concave into the silicon substrate relative to the surface of the second region, the method for manufacturing the back contact battery further includes: forming a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer and the spacing region.

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