Multi-core synchronization method, apparatus, system and storage medium

Abstract

The present application belongs to the technical field of data processing. Provided are a multi-core synchronization method, an apparatus, a system and a storage medium. The method comprises: receiving from a first processing unit a first synchronization request, the first synchronization request indicating that a synchronization task of the first processing unit has been completed, and the first synchronization request carrying a target synchronization domain identifier of the synchronization task executed by the first processing unit; according to the first synchronization request, adding 1 to a first numerical value of a target counter corresponding to the target synchronization domain identifier to obtain a second numerical value; if the second numerical value is less than a preset numerical value of processing units processing the synchronization task and corresponding to the target synchronization domain identifier, giving no response; and, if the second numerical value is equal to the preset numerical value, sending first response information, the first response information being used for instructing a second processing unit among a plurality of processing units that is corresponding to the target synchronization domain identifier to execute a subsequent task. In the present solution, a multi-core synchronization apparatus determines whether synchronization is completed without the need of frequent polling of common resources, thereby improving the synchronization efficiency.

Description

Multi-core synchronization method, device, system and storage medium

[0001] This application claims priority to the patent application filed with the China Patent Office on December 20, 2023, with application number 202311765209.2 and invention name “Multi-core synchronization method, device, system and storage medium”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the field of data processing technology, and in particular relates to a multi-core synchronization method, device, system and storage medium. Background Art

[0003] With the development of data processing technology, multi-core processors are often used to improve data processing efficiency. Multi-core processors include multiple processing units, which can access the same data cache area to perform synchronous tasks.

[0004] In related technologies, semaphores are used to synchronize processing units. A semaphore is a non-negative counter. By setting a semaphore in a data cache area, a processing unit's access to the data cache area is restricted. Specifically, the semaphore's value is used to determine whether a processing unit has permission to access the data cache area. For example, if the semaphore's value is greater than 0, the processing unit is allowed to access the data cache area; otherwise, access to the cache area is denied.

[0005] Summary of the Invention

[0006] The purpose of this application is to provide a multi-core synchronization method, device, system and storage medium, aiming to solve the problem of low synchronization efficiency in traditional synchronization processes.

[0007] A first aspect of an embodiment of the present application provides a multi-core synchronization method, which is applied to a system including multiple processing units, wherein the multiple processing units include a first processing unit. The method includes:

[0008] receiving a first synchronization request from the first processing unit, where the first synchronization request is used to indicate that a synchronization task of the first processing unit has been completed, and the first synchronization request carries a target synchronization domain identifier, where the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit;

[0009] Adjusting a value of a target counter from a first value to a second value according to the first synchronization request, where the second value is greater than the first value, and a difference between the second value and the first value is 1, and the target counter is a counter corresponding to the target synchronization domain identifier;

[0010] If the second value is smaller than the preset value corresponding to the target synchronization domain identifier, determine not to send the first response information; or,

[0011] If the second value is equal to the preset value corresponding to the target synchronization domain identifier, sending a first response message;

[0012] The first response information is used to instruct the processing unit corresponding to the target synchronization domain identifier among the multiple processing units to execute subsequent tasks, and the preset value is the number of processing units that process the synchronization task.

[0013] In an embodiment of the present application, a multi-core synchronization device is set up for multiple processing units, and the processing units that need to be synchronized are recorded by the multi-core synchronization device. When the processing unit completes the current synchronization task, it sends a synchronization request to the multi-core synchronization device. The multi-core synchronization device adjusts the count value of the target counter corresponding to the synchronization domain according to the synchronization domain identifier carried by the synchronization request. When the count value of the target counter is equal to the preset data corresponding to the synchronization domain identifier, it indicates that the processing units executing the current synchronization task have completed synchronization. In this way, the multi-core synchronization device sends a first response message to the multiple processing units corresponding to the synchronization domain, so that the processing units continue to execute the next task. In this way, the multi-core synchronization device is used to determine whether the synchronization is completed, without the need to frequently poll public resources, thereby improving the synchronization efficiency.

[0014] In some embodiments, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, sending the first response information includes:

[0015] If the second value is equal to the preset value corresponding to the target synchronization domain identifier, determine the unit identifier of at least one second processing unit from the multiple processing unit information tables based on the target synchronization domain identifier, where the second processing unit is a processing unit among the multiple processing units that has sent a synchronization request carrying the target synchronization domain identifier;

[0016] The first response information is sent to the second processing unit according to the unit identifier of the second processing unit.

[0017] By recording the unit identifiers of the synchronized processing units in the processing unit information table, it is easy to search for all processing units corresponding to the same synchronization domain identifier, saving the time of searching for the processing units and further improving the synchronization efficiency.

[0018] In some embodiments, the method further comprises:

[0019] Switching the state of the processing unit information table of the second processing unit from a running state to a waiting state;

[0020] The sending the first response information to the second processing unit according to the unit identifier of the second processing unit includes:

[0021] Determining the status of the plurality of processing unit information tables at predetermined intervals;

[0022] If the states of the plurality of processing unit information tables include the waiting state, the first response information is sent to the processing units corresponding to the processing unit information tables in the waiting state in the plurality of processing unit information tables.

[0023] Since the multi-core synchronization device can be connected to multiple processing units, in order to avoid the blocking problem caused by sending the first response information to multiple processing units at the same time, in an embodiment of the present application, the state of the processing unit information table is first switched from the running state to the waiting state, and the first response information is sent to the processing unit in the processing unit information table in the waiting state every preset time. This ensures that the processing unit is notified in time of the completion of synchronization while preventing blocking caused by excessive information content.

[0024] In some embodiments, the first synchronization request further carries a unit identifier of the first processing unit;

[0025] After receiving the first synchronization request from the first processing unit, the method further includes:

[0026] Storing the unit identifier of the first processing unit and the target synchronization domain identifier in a first processing unit information table in correspondence;

[0027] The state of the first processing unit information table is switched from an idle state to a running state.

[0028] The multi-core synchronization device stores the unit identification and synchronization domain identification of the first processing unit in the processing unit information table, and switches the state of the processing unit information table from idle state to running state, so as to record the unit identification of the processing unit corresponding to the same synchronization domain identification through the processing unit information table, so that when the synchronization is completed, the first response information can be sent to all processing units corresponding to the target synchronization domain identification.

[0029] In some embodiments, the first synchronization request includes a status field, and the storing the unit identifier of the first processing unit and the target synchronization domain identifier in the first processing unit information table includes:

[0030] If the status field indicates that the first synchronization request is a record request, the unit identifier of the first processing unit and the target synchronization domain identifier are stored in the first processing unit information table in a corresponding manner;

[0031] The method further comprises:

[0032] If the status field indicates that the first synchronization request is a cache request, cache the synchronization request;

[0033] Second response information is sent to the first processing unit, where the second response information is used to indicate that the first synchronization request has been cached.

[0034] By adding a status field in the synchronization request, different types of synchronization requests can be sent to different bypasses. In this way, there is no need to wait until all processing units corresponding to the synchronization domain identifier complete synchronization, and the processing unit can continue to perform subsequent tasks, thereby improving the synchronization efficiency and the efficiency of the processing unit itself.

[0035] A second aspect of an embodiment of the present application provides a multi-core synchronization device, the multi-core synchronization device comprising: a synchronization domain status recording module and a processing unit information recording module;

[0036] The synchronization domain status recording module stores target counters corresponding to multiple synchronization domain identifiers, which are used to receive a first synchronization request from the first processing unit, where the first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed, and the first synchronization request carries a target synchronization domain identifier, which is an identifier of the synchronization task executed by the first processing unit; according to the first synchronization request, the value of the target counter is adjusted from a first value to a second value, where the second value is greater than the first value, and the difference between the second value and the first value is 1, and the target counter is a counter corresponding to the target synchronization domain identifier; if the second value is less than the preset value corresponding to the target synchronization domain identifier, it is determined not to send a first response message; or, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, a release message is sent to the processing unit information recording module, where the release message carries the target synchronization domain identifier;

[0037] The processing unit information recording module stores multiple processing unit information tables, which are used to respond to the release information sent by the synchronization domain status recording module, determine the unit identifiers of the multiple processing units corresponding to the target synchronization domain identifier from the multiple processing unit information tables according to the target synchronization domain identifier carried by the release information, and send a first response information to the processing unit corresponding to the target synchronization domain identifier according to the unit identifier.

[0038] In some embodiments, the processing unit information recording module is used to store the unit identifier of the first processing unit and the target synchronization domain identifier correspondingly in the first processing unit information table in response to receiving a first synchronization request sent by the first processing unit; and switch the state of the first processing unit information table from an idle state to a running state.

[0039] In some embodiments, the first synchronization request includes a status field, and the multi-core synchronization apparatus further includes a cache module;

[0040] The multi-core synchronization device is further configured to parse the first synchronization request to obtain a status field; if the status field indicates that the first synchronization request is a cache request, send the first synchronization request to the multi-core synchronization device; if the status field indicates that the first synchronization request is a record request, send the first synchronization request to the processing unit information recording module;

[0041] The cache module is used to cache the first synchronization request in response to receiving the first synchronization request, and send a second response message to the first processing unit corresponding to the first synchronization request, where the second response message is used to indicate that the synchronization request of the first processing unit has been cached.

[0042] In some embodiments, the processing unit information recording module is further configured to, in response to receiving a first synchronization request sent by a first processing unit, store the unit identifier of the first processing unit and the target synchronization domain identifier in a processing unit information table; and switch the state of the processing unit information table from an idle state to a running state;

[0043] The processing unit information recording module is also used to switch the status of the processing unit information tables of the first processing unit and the second processing unit from a running state to a waiting state after receiving the release information; determine the status of the multiple processing unit information tables every preset time period; if the status of the multiple processing unit information tables includes the waiting state, send the first response information to the processing unit corresponding to the processing unit information table in the waiting state in the multiple processing unit information tables; and switch the status of the processing unit information table corresponding to the processing unit that has sent the first response information from a waiting state to an idle state.

[0044] A third aspect of the embodiments of the present application provides a multi-core synchronization system, the multi-core synchronization system comprising a plurality of processing units and the multi-core synchronization device described in any one of the second aspects of the embodiments of the present application;

[0045] For any processing unit, the processing unit is used to send a synchronization request to the multi-core synchronization device in response to the processing unit completing the task to be synchronized, the synchronization request is used to indicate that the synchronization task of the processing unit has been completed, and the first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit;

[0046] The multi-core synchronization device is used to execute the multi-core synchronization method as described in any one of the first aspects of the present application.

[0047] The fourth aspect of an embodiment of the present application provides a multi-core synchronization device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the multi-core synchronization method described above when executing the computer program.

[0048] A fifth aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the multi-core synchronization method described above is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 shows a schematic diagram of a multi-core synchronization system provided by an exemplary embodiment;

[0050] FIG2 shows a functional schematic diagram of a multi-core synchronization device provided by an exemplary embodiment;

[0051] FIG3 shows a functional schematic diagram of a multi-core synchronization device provided by an exemplary embodiment;

[0052] FIG4 shows a schematic flow chart of a multi-core synchronization method provided by an exemplary embodiment;

[0053] FIG5 is a schematic flow chart showing a multi-core synchronization method provided by an exemplary embodiment;

[0054] FIG6 shows a schematic flow chart of a multi-core synchronization method provided by an exemplary embodiment;

[0055] FIG7 is a schematic flow chart showing a multi-core synchronization method provided by an exemplary embodiment;

[0056] FIG8 is a schematic diagram showing a synchronization model applied by a multi-core synchronization method provided by an exemplary embodiment;

[0057] FIG9 is a schematic diagram showing a synchronization model applied by a multi-core synchronization method provided by an exemplary embodiment;

[0058] FIG10 shows a schematic structural diagram of a multi-core synchronization device provided by an exemplary embodiment. DETAILED DESCRIPTION

[0059] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0061] To improve data processing efficiency, multi-core processors are often used for data processing. Multi-core refers to multiple processing units. To complete the same task, several processing units need to coordinate with each other to achieve synchronization. This means that before one processing unit can begin executing an operation, another processing unit must have completed it; otherwise, the processing unit must wait. Therefore, communication between the processing units is necessary to keep track of the operations being executed. For example, if two processing units need to use the same data cache, one processing unit writes processed data to the data cache, while the other reads the data from the data cache and further processes it. Only after the first processing unit has completed writing data to the data cache can the other processing unit read data from the data cache for processing. Therefore, after the first processing unit has completed writing data to the data cache, it needs to notify the other processing unit that the data write is complete. Various synchronization schemes between processing units exist in the related art, but each scheme has its shortcomings. The following describes several common multi-core synchronization methods.

[0062] In some implementations, semaphores are used to achieve synchronization between processing units. A semaphore is a non-negative counter. By setting a semaphore in the data cache area, the processing unit's access to the data cache area is restricted. That is, the value of the semaphore is used to determine whether the processing unit has permission to access the data cache area. For example, when the value of the semaphore is greater than 0, the processing unit can access the data cache area, otherwise it is not allowed to access the data cache area. In this technical solution, when accessing the data cache area, it is necessary to frequently perform read and write polling on the semaphore in the data cache area, which affects the access efficiency of the data cache area and thus affects the multi-core synchronization efficiency.

[0063] In other implementations, asynchronous communication between processing units is achieved by setting up a mailbox area. That is, a processing unit can write a message corresponding to the execution status of a task into the mailbox area, and then continue to execute other tasks. When other processing units need to know the execution status of the previous processing unit, they can read the execution status of other processing units from the mailbox area. In this implementation, a shared buffer needs to be set up to store messages. When multiple processing units synchronize with the same processing unit, multiple processing units send a large number of messages to the buffer corresponding to the same processing unit, resulting in buffer overflow or performance degradation. In addition, mailbox area communication requires that the processing units comply with the same communication protocol, so the requirements for the processing units are relatively high.

[0064] In summary, the multi-core synchronization methods in related technologies have many deficiencies, which affect the efficiency of multi-core synchronization. Therefore, a new multi-core synchronization solution is urgently needed to address the deficiencies in related technologies and improve the efficiency of synchronization between processing units.

[0065] In an embodiment of the present application, to address the aforementioned process synchronization issues, a multi-core synchronization method, device, and system are provided. Synchronization devices are provided between multiple processing units, and the synchronization devices coordinate the processing units to achieve synchronization between the processing units. FIG1 shows a multi-core synchronization system provided by an exemplary embodiment. The multi-core synchronization system includes a multi-core synchronization device 10 and multiple processing units 20.

[0066] The multi-core synchronization device 10 is respectively connected to the plurality of processing units 20. The plurality of processing units 20 are used to process the operations in the process to implement the tasks corresponding to the process. The plurality of processing units 20 can be divided into different synchronization domains as needed, wherein the processing units corresponding to the same synchronization domain need to perform synchronization tasks. The plurality of processing units 20 are connected to a storage system outside the multi-core synchronization system, and the storage system is used to store data written by each processing unit 20 and provide readable data to each processing unit 20.

[0067] For any processing unit 20, the processing unit 20 is used to send a synchronization request to the multi-core synchronization device 10 in response to the processing unit 20 completing the task to be synchronized. The synchronization request is used to indicate that the synchronization task of the processing unit has been completed. The synchronization request includes the synchronization domain identifier corresponding to the synchronization task and the unit identifier of the processing unit 20. The synchronization domain identifier is the identifier corresponding to the synchronization task executed by the processing unit 20.

[0068] When executing a task, the processing unit 20 loads the instruction corresponding to the task. In an embodiment of the present application, the last instruction of the synchronization task is set as a synchronization request instruction. When the synchronization task is loaded into the synchronization request instruction at the instruction level, the processing unit 20 sends a synchronization request to the multi-core synchronization device 10. The synchronization request instruction carries a variety of information. For example, the synchronization request carries information such as the synchronization domain identifier, the unit identifier of the processing unit 20, the status field of the synchronization request, and the pre-designed value corresponding to the synchronization domain identifier. The synchronization request can be any type of instruction. For example, the synchronization request can be a bar instruction, etc.

[0069] The multi-core synchronization device 10 is configured to, in response to receiving a synchronization request from any processing unit 20, adjust the value of a target counter from a first value to a second value based on a synchronization domain identifier in the synchronization request, wherein the second value is greater than the first value, and the difference between the second value and the first value is 1, and the target counter is the counter corresponding to the target synchronization domain identifier. Accordingly, upon receiving a synchronization request from any processing unit 20, the multi-core synchronization device 10 parses the synchronization request to obtain the synchronization domain identifier carried in the synchronization request and a pre-designed value corresponding to the synchronization domain identifier, wherein the pre-designed value represents the number of processing units 20 processing the synchronization task. Based on the synchronization domain identifier, the multi-core synchronization device 10 queries an existing counter for the synchronization domain identifier. If a target counter exists among the existing counters whose synchronization domain identifier is the same as the target synchronization domain identifier, the count value of the target counter is adjusted. If a target counter does not exist among the existing counters whose synchronization domain identifier is the same as the target synchronization domain identifier, a target counter corresponding to the synchronization domain identifier is created and the count value of the target counter is adjusted.

[0070] One point that needs to be explained is that the multi-core synchronization device can adjust the count value of the target counter according to any preset adjustment method. In the embodiment of the present application, the counting method of the target counter is not specifically limited. For example, the adjustment method can be to add one to the count value of the target counter, and then the initial value of the target counter can be set to 0. For another example, the adjustment method can also be to subtract one from the count value of the target counter, and accordingly, the initial value of the target counter can be set to a pre-designed value. Correspondingly, when the count value of the target counter is 0, the multi-core synchronization device 10 determines that the synchronization is completed and performs subsequent operations.

[0071] After the multi-core synchronization device 10 adjusts the count value of the target counter corresponding to the synchronization domain identifier, it determines whether the adjusted second value is less than the pre-designed value corresponding to the target synchronization domain identifier. If the second value is less than the pre-designed value corresponding to the synchronization domain identifier, the multi-core synchronization device 10 determines not to send the first response information and no longer makes other responses. If the second value is equal to the pre-designed value corresponding to the target synchronization domain identifier, the multi-core synchronization device 10 sends the first response information. Accordingly, the multiple processing units 20 that perform the synchronization task receive the first response information, wherein the first response information is used to indicate that the processing unit corresponding to the target synchronization domain identifier among the multiple processing units performs subsequent tasks, and the preset value is the number of processing units that process the synchronization task. The first response information is used to indicate to the processing unit 20 that the current synchronization task has been completed. When any synchronization unit determines that the current synchronization is completed, it continues to execute the next task.

[0072] Taking the processing unit currently sending the synchronization request as the first processing unit and the processing unit corresponding to the target synchronization area as the second unit as an example for explanation, the multi-core synchronization device is used to receive a first synchronization request from the first processing unit, and the first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed. The first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is the identifier of the synchronization task executed by the first processing unit; according to the first synchronization request, the value of the target counter is adjusted from the first value to the second value, and the second value is greater than the first value, and the difference between the second value and the first value is 1, and the target counter is the counter corresponding to the target synchronization domain identifier; if the second value is less than the preset value corresponding to the target synchronization domain identifier, it is determined not to send a first response message; or, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, a first response message is sent; wherein, the first response message is used to instruct the second processing unit corresponding to the target synchronization domain identifier among the multiple processing units to perform subsequent tasks, and the preset value is the number of processing units that process the synchronization task.

[0073] There is at least one second processing unit, and the second processing unit includes the first processing unit.

[0074] One point that needs to be explained is that when the multi-core synchronization device 10 receives a synchronization request, it can also store the synchronization domain identifier carried by the synchronization request and the unit identifier of the processing unit 20 in correspondence, so that when receiving the first response information from the multiple processing units 20 that perform the synchronization task, it can determine the multiple unit identifiers corresponding to the synchronization domain identifier carried by the synchronization request received this time from the stored correspondence between the synchronization domain identifier and the unit identifier, and thus send the first response information to the multiple processing units 20 corresponding to the synchronization domain identifier based on the multiple unit identifiers. Accordingly, the first synchronization request also carries the unit identifier of the first processing unit; after receiving the first synchronization request from the first processing unit, the multi-core synchronization device stores the unit identifier of the first processing unit and the target synchronization domain identifier in the first processing unit information table; and switches the state of the first processing unit information table from the idle state to the running state.

[0075] In this implementation, by recording the unit identifier and target synchronization domain identifier in the synchronization request, the multi-core synchronization device can quickly find the unit identifier corresponding to the target synchronization domain identifier, thereby improving the efficiency of determining the unit identifier and further improving the synchronization efficiency.

[0076] Another point worth noting is that the multi-core synchronization system provided in the embodiments of the present application also supports parallel synchronization of multiple synchronization domains. Different synchronization domain identifiers are set for different synchronization domains. Accordingly, the multiple processing units 20 connected to the multi-core synchronization device 10 are divided into different synchronization domains. Each synchronization domain can operate independently without interfering with each other. In addition, the number of processing units 20 in the multi-core synchronization system can be set as needed. Therefore, it can flexibly adapt to changes in chip specifications, making the application scenarios of the multi-core synchronization system more extensive.

[0077] The multi-core synchronization device 10 is described below, and the principle of the multi-core synchronization device 10 to achieve the above functions is further explained.

[0078] In some embodiments, referring to FIG. 2 , the multi-core synchronization device 10 includes a synchronization domain status recording module 11 and a processing unit information recording module 12 .

[0079] The synchronization domain status recording module 11 stores counters corresponding to multiple synchronization domain identifiers. In some embodiments, the multiple counters and the synchronization domain identifiers corresponding to the counters are stored in a processing unit information table. The processing unit information table can be set as an information table corresponding to each processing unit, or as an information table corresponding to multiple processing units. In the embodiment of the present application, this is not specifically limited. In response to receiving a synchronization request sent by any processing unit 20, the synchronization domain status recording module 11 determines the target counter corresponding to the target synchronization domain identifier from the processing unit information table according to the synchronization domain identifier carried by the synchronization request, and adjusts the value of the target counter from the first value to the second value according to the first synchronization request. The second value is greater than the first value, and the difference between the second value and the first value is 1. The target counter is the counter corresponding to the target synchronization domain identifier; if the second value is less than the preset value corresponding to the target synchronization domain identifier, it is determined not to send the first response information; or if the second value is equal to the preset value corresponding to the target synchronization domain identifier, a release message is sent to the processing unit information recording module, and the release message carries the target synchronization domain identifier.

[0080] If the adjusted count value is less than the pre-set value corresponding to the synchronization domain identifier, the synchronization domain status recording module 11 will not make any other response. If the adjusted count value is equal to the pre-set value corresponding to the synchronization domain identifier, the synchronization domain status recording module 11 sends a release message to the processing unit information recording module 12.

[0081] The processing unit information recording module 12 stores multiple processing unit information tables, each of which stores a synchronization domain identifier, a unit identifier, and the status of the processing unit information table. The processing unit information recording module 12 is configured to receive the release message sent by the synchronization domain status recording module 11, determine, from the multiple processing unit information tables, the multiple processing unit 20 information tables corresponding to the synchronization domain identifier based on the synchronization domain identifier carried in the release message, and send a first response message to the processing units corresponding to the multiple unit identifiers based on the unit identifiers recorded in the multiple processing unit information tables corresponding to the synchronization domain identifier.

[0082] Take the synchronization domain status recording module receiving the first synchronization request of the first processing unit as an example for explanation. The synchronization domain status recording module stores a plurality of target counters corresponding to synchronization domain identifiers, which are used to receive the first synchronization request from the first processing unit. The first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed. The first synchronization request carries the target synchronization domain identifier, which is the identifier of the synchronization task executed by the first processing unit; according to the first synchronization request, the value of the target counter is adjusted from the first value to the second value, the second value is greater than the first value, and the difference between the second value and the first value is 1, and the target counter is the counter corresponding to the target synchronization domain identifier; if the second value is less than the preset value corresponding to the target synchronization domain identifier, it is determined not to send the first response information; or, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, a release message is sent to the processing unit information recording module, and the release message carries the target synchronization domain identifier.

[0083] The processing unit information recording module stores multiple processing unit information tables, which are used to respond to the release information sent by the synchronization domain status recording module, determine the unit identifier of the second processing unit corresponding to the target synchronization domain identifier from the multiple processing unit information tables according to the target synchronization domain identifier carried by the release information, and send a first response information to the second processing unit according to the unit identifier.

[0084] One point that needs to be explained is that before the first processing unit sends the first synchronization request, or after the first processing unit sends the first synchronization request, and when the second count value is less than the pre-designed value, the multi-core synchronization device 10 also receives the second synchronization request sent by other processing units for processing the synchronization task identified by the target synchronization domain, and records the relevant information of the second synchronization request according to the above process. In the embodiment of the present application, this will not be repeated.

[0085] The status in the information table of the processing unit 20 is adjusted as the synchronization process progresses. In some embodiments, upon receiving the release message, the processing unit information recording module 12 switches the status of the information table of the processing unit 20 corresponding to the multiple processing units 20 corresponding to the synchronization domain identifiers carried in the release message from the running state (RUN) to the waiting state (WAIT); after the processing unit information recording module 12 sends the first response message to the multiple processing units 20, the processing unit information recording module 12 switches the status of the table of the multiple processing units 20 from the waiting state to the idle state (IDLE).

[0086] In some embodiments, the processing unit information recording module 12 is also used to, in response to receiving a first synchronization request sent by the first processing unit, store the unit identifier of the first processing unit and the target synchronization domain identifier in the processing unit information table; switch the state of the processing unit information table from an idle state to a running state; the processing unit information recording module 12 is also used to, after receiving the release information, switch the state of the processing unit information tables of the first processing unit and the second processing unit from a running state to a waiting state; determine the state of the multiple processing unit information tables at preset time intervals; if the state of the multiple processing unit information tables includes the waiting state, send the first response information to the processing unit corresponding to the processing unit information table in the waiting state in the multiple processing unit information tables; switch the state of the processing unit information table corresponding to the processing unit that has sent the first response information from a waiting state to an idle state.

[0087] Since the multi-core synchronization device 10 can be connected to multiple processing units 20, in order to avoid the blocking problem caused by sending the first response information to multiple processing units 20 at the same time, in the embodiment of the present application, the state of the processing unit 20 information table is first switched from the running state to the waiting state, and the first response information is sent to the processing unit 20 in the information table of the processing unit 20 in the waiting state every preset time. This ensures that the processing unit 20 is notified in time of the completion of synchronization while preventing blocking caused by excessive information content.

[0088] The preset duration can be set as needed, and in the embodiment of the present application, the preset duration is not specifically limited. For example, the preset duration can be 1 clock cycle.

[0089] Prior to this, the multi-core synchronization device 10 needs to record the processing units 20 that have completed synchronization in the processing unit information recording module 12. Accordingly, in response to receiving a synchronization request, the multi-core synchronization device 10 sends the synchronization request to the processing unit information recording module 12. The processing unit information recording module 12 associates the synchronization domain identifier carried by the multi-core synchronization request with the unit identifier of the processing unit 20 and stores it in the processing unit information table, and switches the state of the synchronization unit information table from the idle state to the running state.

[0090] In some embodiments, referring to FIG3 , the multi-core synchronization device 10 further includes a cache module 13. The multi-core synchronization device 10 is further configured to parse the first synchronization request and obtain a status field; if the status field indicates that the first synchronization request is a cache request, the first synchronization request is sent to the cache module 13; if the status field indicates that the first synchronization request is a record request, the first synchronization request is sent to the processing unit information recording module 12; the cache module 13 is configured to cache the first synchronization request in response to receiving the first synchronization request, and send a second response message to the first processing unit corresponding to the first synchronization request, the second response message being used to indicate that the synchronization request of the first processing unit has been cached. The processing unit 20 receives the second response message and does not further respond to the second response message.

[0091] It should be noted that, after receiving the synchronization request, the cache module 13 can send the second response information to the corresponding processing unit 20 in real time. The cache module 13 can also send the second response information to the corresponding processing unit 20 at preset intervals. In the embodiment of the present application, this is not specifically limited.

[0092] After the processing unit 20 sends a synchronization request of the cache request type to the multi-core synchronization device 10, since there is no need to respond to the second response information returned by the cache module 13, there is no need to wait for the cache module 13 to return the second response information. After sending the synchronization request of the cache request type, the processing unit 20 can continue to execute subsequent tasks. It can be seen from this that the identification of the processing unit 20 at this time does not need to be recorded in the processing unit information recording module 12. Because, in an embodiment of the present application, synchronization requests can be classified so that different modules in the multi-core synchronization device 10 process different types of synchronization requests respectively. In some embodiments, a status field indicating the status is added to the synchronization request, and the type of the synchronization request is indicated by the status field. The type of the synchronization request includes a cache request and a record request. For example, the status field is a sync field, indicating that the type of the synchronization request is a record request. The status field is a pass field, indicating that the type of the synchronization request is a cache type.

[0093] Correspondingly, the multi-core synchronization device 10 is also used to parse the received synchronization request to obtain a status field; if the status field indicates that the synchronization request is a cache request, the synchronization request is sent to the multi-core synchronization device 10; if the status field indicates that the synchronization request is a recording request, the synchronization request is sent to the processing unit information recording module 12.

[0094] In this implementation, by adding a status field in the synchronization request, different types of synchronization requests can be sent to different bypasses. In this way, there is no need to wait until all processing units 20 corresponding to the synchronization domain identifier complete synchronization, and the processing unit 20 can continue to perform subsequent tasks, thereby improving the synchronization efficiency and the efficiency of the processing unit 20 itself in processing data.

[0095] In an embodiment of the present application, a multi-core synchronization device 10 is set for multiple processing units 20, and the processing units 20 that need to be synchronized are recorded through the multi-core synchronization device 10. When the processing unit 20 completes the current synchronization task, it sends a synchronization request to the multi-core synchronization device 10. The multi-core synchronization device 10 adjusts the count value of the target counter corresponding to the synchronization domain according to the synchronization domain identifier carried by the synchronization request. When the count value of the synchronization domain counter is equal to the preset data corresponding to the synchronization domain identifier, it indicates that the processing units 20 executing the current synchronization task have completed synchronization. In this way, the multi-core synchronization device 10 sends a first response message to the multiple processing units 20 corresponding to the synchronization domain, so that the processing unit 20 continues to execute the next task. In this way, the multi-core synchronization device 10 is used to determine whether the synchronization is completed, without the need to frequently poll public resources, thereby improving the synchronization efficiency.

[0096] Furthermore, by communicating with the multiple processing units 20 respectively through the multi-core synchronization device 10, there is no need for collaborative communication between the multiple processing units 20. Therefore, there is no need to limit the communication protocol between the multiple processing units 20, which reduces the difficulty of synchronization.

[0097] Moreover, the synchronous processing unit 20 can be divided only by designing the synchronization domain identifier in the synchronization request at the processing level, so that the multi-core processing unit 20 can realize any one-to-many, many-to-one, and many-to-many synchronization processing.

[0098] Among the multiple processing units corresponding to the same synchronization domain identifier, only after the last processing unit that completes synchronization sends a synchronization request to the multi-core synchronization unit, the processing method of the multi-core processing unit is different. After the other processing units except the last processing unit that completes synchronization complete synchronization and send a synchronization request to the multi-core synchronization device, the processing method of the multi-core synchronization device is the same. In the embodiment of the present application, the currently received synchronization request is taken as an example of the synchronization request sent by the first processing unit. The first synchronization request can be any processing unit in the above-mentioned multi-core synchronization system. See Figure 4, which shows a flowchart of a multi-core synchronization method provided by the present application. As an example and not a limitation, the method is applied in the above-mentioned multi-core synchronization device.

[0099] S401, the multi-core synchronization device receives a first synchronization request from the first processing unit, and the first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed. The first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit.

[0100] After the first processing unit completes processing the current synchronization task, it generates a first synchronization request based on the target synchronization domain identifier corresponding to the synchronization task, the pre-designed value corresponding to the target synchronization domain identifier, and the unit identifier of the first processing unit, and sends the first synchronization request to the multi-core synchronization device.

[0101] In some embodiments, after receiving the first synchronization request, the multi-core synchronization device further stores the synchronization domain identifier in the first synchronization request and the unit identifier of the processing unit in a corresponding manner. Accordingly, the multi-core synchronization device stores the unit identifier of the first processing unit and the target synchronization domain identifier in a first processing unit information table in a corresponding manner, and switches the state of the first processing unit information table from an idle state to a running state.

[0102] In this implementation, the multi-core synchronization device stores the unit identifier and synchronization domain identifier of the first processing unit in the processing unit information table, and switches the state of the processing unit information table from idle state to running state, thereby recording the unit identifier of the processing unit corresponding to the same synchronization domain identifier through the processing unit information table, so that when the synchronization is completed, the first response information can be sent to all processing units corresponding to the target synchronization domain identifier.

[0103] S402, the multi-core synchronization device adjusts the value of the target counter from a first value to a second value according to the first synchronization request, the second value is greater than the first value, and the difference between the second value and the first value is 1, and the target counter is the counter corresponding to the target synchronization domain identifier.

[0104] In response to receiving the first synchronization request sent by the first processing unit, the multi-core synchronization device adjusts the count value of the target counter corresponding to the target synchronization domain identifier according to the target synchronization domain identifier in the first synchronization request.

[0105] In some embodiments, after receiving the first synchronization request, the multi-core synchronization device parses the first synchronization request to obtain the target synchronization domain identifier carried by the first synchronization request and a pre-designed value corresponding to the target synchronization domain identifier, where the pre-designed value is the number of processing units that handle the synchronization task. The multi-core synchronization device queries the synchronization domain identifier corresponding to the existing counter based on the target synchronization domain identifier. If there is a target counter with the same synchronization domain identifier as the target synchronization domain identifier in the existing counters, the count value of the target counter is adjusted. If there is no counter with the same synchronization domain identifier as the target synchronization domain identifier in the existing counters, a target counter corresponding to the target synchronization domain identifier is created, and the count value of the target counter is adjusted.

[0106] In the embodiment of the present application, the count value of the target counter can be adjusted according to any preset adjustment method. In the embodiment of the present application, the counting method of the target counter is not specifically limited. For example, the adjustment method can be to add one to the count value of the target counter, and the initial value of the target counter can be set to 0. For another example, the adjustment method can also be to subtract one from the count value of the target counter, and accordingly, the initial value of the target counter can be set to a pre-designed value. Correspondingly, when the count value of the target counter is 0, the multi-core synchronization device determines that the synchronization is completed and performs subsequent operations.

[0107] After the multi-core synchronization device adjusts the count value of the target counter corresponding to the synchronization domain identifier, it determines whether the adjusted count value (second value) is less than the pre-designed value corresponding to the synchronization domain identifier. If the adjusted count value (second value) is less than the pre-designed value corresponding to the synchronization domain identifier, the multi-core synchronization device executes step S403, makes no other response, and then continues to execute steps S401-S402. If the adjusted count value (second value) is equal to the pre-designed value corresponding to the synchronization domain identifier, the multi-core synchronization device executes step S404.

[0108] S403: If the second value is smaller than the preset value corresponding to the target synchronization domain identifier, the multi-core synchronization device determines not to send the first response information.

[0109] If the second value is smaller than the preset value corresponding to the target synchronization domain identifier, the multi-core synchronization device continues to receive the second synchronization request sent by the third processing unit among the multiple processing units, parses the second synchronization request, and obtains the synchronization domain identifier carried by the second synchronization request. If the synchronization domain identifier carried by the second synchronization request is the same as the target synchronization domain identifier, the count value of the target counter continues to be adjusted; until the count value of the adjusted target counter is equal to the pre-designed value, step S404 is executed.

[0110] S404: If the second value is equal to the preset value corresponding to the target synchronization domain identifier, the multi-core synchronization device sends a first response message.

[0111] Wherein, the first response information is used to instruct the second processing unit corresponding to the target synchronization domain identifier among the multiple processing units to perform subsequent tasks, and the preset value is the number of processing units that process the synchronization task. The first response information includes information such as the unit identifier of the second processing unit, which is used to indicate that the current synchronization of the second processing unit has been completed and other tasks can continue to be performed. Wherein, the second processing unit is a processing unit for processing the synchronization task corresponding to the target synchronization domain identifier, the number of the second processing unit is at least one, and the second processing unit includes the first processing unit.

[0112] One point that needs to be explained is that when the multi-core synchronization device receives a synchronization request, it can also store the synchronization domain identifier carried by the synchronization request and the unit identifier of the processing unit in correspondence, so that when receiving the first response information from multiple processing units that execute the synchronization task, it can determine the multiple unit identifiers corresponding to the synchronization domain identifier carried by the synchronization request received this time from the stored correspondence between the synchronization domain identifier and the unit identifier, and thus send the first response information to the multiple processing units corresponding to the synchronization domain identifier based on the multiple unit identifiers.

[0113] In some embodiments, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, the multi-core synchronization device determines the unit identifier of the at least one second processing unit from multiple processing unit information tables based on the target synchronization domain identifier, and the second processing unit is the processing unit among the multiple processing units that has sent a synchronization request carrying the target synchronization domain identifier; and sends the first response information to the second processing unit based on the unit identifier of the second processing unit.

[0114] The multi-core synchronization device determines the multiple unit identifiers corresponding to the target synchronization domain identifier based on the correspondence between the synchronization domain identifiers and unit identifiers stored in multiple processing unit information tables, and thus sends a first response message to the processing unit corresponding to the multi-core unit identifier. In this way, the unit identifier of the processing unit that has completed synchronization is recorded in the processing unit information table, which facilitates the search for all processing units corresponding to the same synchronization domain identifier, saves the time for searching the processing unit, and further improves the synchronization efficiency.

[0115] In some embodiments, after the multi-core synchronization device determines that synchronization is complete, it first adjusts the status of the processing unit information table and then sends a first response message to the processing unit in the waiting state. The process is as follows: the multi-core synchronization device switches the status of the processing unit information table of the second processing unit from the running state to the waiting state; determines the status of the multiple processing unit information tables at predetermined intervals; and if the status of the multiple processing unit information tables includes the waiting state, sends the first response message to the processing unit corresponding to the processing unit information table in the waiting state in the multiple processing unit information tables.

[0116] Since the multi-core synchronization device can be connected to multiple processing units, in order to avoid the blocking problem caused by sending the first response information to multiple processing units at the same time, in an embodiment of the present application, the state of the processing unit information table is first switched from the running state to the waiting state, and the first response information is sent to the processing unit in the processing unit information table in the waiting state every preset time. This ensures that the processing unit is notified in time of the completion of synchronization while preventing blocking caused by excessive information content.

[0117] The preset duration can be set as needed, and in the embodiment of the present application, the preset duration is not specifically limited. For example, the preset duration can be 1 clock cycle.

[0118] In an embodiment of the present application, a multi-core synchronization device is set up for multiple processing units, and the processing units that need to be synchronized are recorded by the multi-core synchronization device. When the processing unit completes the current synchronization task, it sends a synchronization request to the multi-core synchronization device. The multi-core synchronization device adjusts the count value of the target counter corresponding to the synchronization domain according to the synchronization domain identifier carried by the synchronization request. When the count value of the target counter is equal to the preset data corresponding to the synchronization domain identifier, it indicates that the processing units executing the current synchronization task have completed synchronization. In this way, the multi-core synchronization device sends a first response message to the multiple processing units corresponding to the synchronization domain, so that the processing units continue to execute the next task. In this way, the multi-core synchronization device is used to determine whether the synchronization is completed, without the need to frequently poll public resources, thereby improving the synchronization efficiency.

[0119] Furthermore, by communicating with multiple processing units separately through the multi-core synchronization device, there is no need for collaborative communication between the multiple processing units. Therefore, there is no need to limit the communication protocol between the multiple processing units, which reduces the difficulty of synchronization.

[0120] Moreover, by only designing the synchronization domain identifier in the synchronization request at the processing level, the synchronized processing units can be divided, so that the multi-core processing units can achieve any one-to-many, many-to-one, and many-to-many synchronization processing.

[0121] In actual applications, some processing units can continue to execute without waiting for the multi-core synchronization device to return a response message. In order to achieve this synchronization process, in an embodiment of the present application, the synchronization requests are classified. The classification processing method is described below using the first synchronization request as an example. In fact, the classification processing method for the second synchronization request is the same, and it will not be repeated in the embodiment of the present application. See Figure 5, which shows a flowchart of a multi-core synchronization method provided by the present application. As an example and not a limitation, this method is applied in the above-mentioned multi-core synchronization device.

[0122] S501 : In response to receiving a first synchronization request sent by a first processing unit, a multi-core synchronization apparatus parses the first synchronization request to obtain a status field.

[0123] The type of the synchronization request includes a cache request and a record request. For example, if the status field is a sync field, it indicates that the type of the synchronization request is a record request. If the status field is a pass field, it indicates that the type of the synchronization request is a cache type.

[0124] If the status field indicates that the first synchronization request is a cache request, step S502 is executed; if the status field indicates that the first synchronization request is a record request, step S504 is executed.

[0125] S502: If the status field indicates that the first synchronization request is a cache request, the multi-core synchronization device caches the synchronization request.

[0126] S503: The multi-core synchronization device sends a second response message to the first processing unit, where the second response message is used to indicate that the first synchronization request has been cached.

[0127] Referring to Figure 6, if the status field carried by the first synchronization request issued by the first processing unit indicates that the first synchronization request is a cache request, the multi-core synchronization device bypasses the cache of the first synchronization request and sends a second response message to the first processing unit. After the first processing unit sends the first synchronization request, it continues to execute subsequent tasks and does not perform any other processing after receiving the second response message.

[0128] S504: If the status field indicates that the first synchronization request is a record request, the multi-core synchronization device stores the unit identifier of the first processing unit and the target synchronization domain identifier in the first processing unit information table in a corresponding manner.

[0129] Referring to Figure 7, if the status field carried by the first synchronization request sent by the first processing unit indicates that the first synchronization request is a cache request, the first processing unit suspends and blocks after sending the first synchronization request, waiting for the multi-core synchronization device to respond. The multi-core synchronization device receives the first synchronization request and stores the synchronization domain identifier and unit identifier carried by the first synchronization request in the processing unit information table. Then, the count value of the target counter is adjusted according to the first synchronization request. If the count value is less than the pre-designed value, other synchronization requests are continued to be received. If the count value is equal to the pre-designed value, the multi-core synchronization device sends a first response message to the first processing unit and the second processing unit corresponding to the target synchronization domain identifier according to the synchronization domain identifier and the unit identifier of the processing unit recorded in the processing unit information table. Accordingly, after receiving the first response message, the processing unit and the second processing unit release the suspension and continue to run.

[0130] In an embodiment of the present application, by adding a status field in the synchronization request, different types of synchronization requests can be sent to different bypasses. In this way, there is no need to wait until all processing units corresponding to the synchronization domain identifier complete synchronization, and the processing unit can continue to perform subsequent tasks, thereby improving the synchronization efficiency and the efficiency of the processing unit itself.

[0131] In an embodiment of the present application, a multi-core synchronization device is set up for multiple processing units, and the processing units that need to be synchronized are recorded by the multi-core synchronization device. When the processing unit completes the current synchronization task, it sends a synchronization request to the multi-core synchronization device. The multi-core synchronization device adjusts the count value of the target counter corresponding to the synchronization domain according to the synchronization domain identifier carried by the synchronization request. When the count value of the target counter is equal to the preset data corresponding to the synchronization domain identifier, it indicates that the processing units executing the current synchronization task have completed synchronization. In this way, the multi-core synchronization device sends a first response message to the multiple processing units corresponding to the synchronization domain, so that the processing units continue to execute the next task. In this way, the multi-core synchronization device is used to determine whether the synchronization is completed, without the need to frequently poll public resources, thereby improving the synchronization efficiency.

[0132] The multi-core synchronization method, device, and system provided in the embodiments of this application can be applied in a variety of multi-core synchronization models. For example, they can be applied in a producer-consumer model or a barrier model. The following uses these two models as examples to introduce how this solution is used in practical applications.

[0133] In one implementation, it is applied in a producer-consumer model.

[0134] Referring to Figure 8 , initially, the producers include processing units 0 and 1, and the consumers include processing units 2 and 3. For any producer processing unit, after producing the first batch of data, it writes that data to address A. Because there's no need to wait for the consumer, the synchronization request type used is a cache request (with a pass field). After the producer sends a synchronization request to complete the first batch of data, it can prepare the next batch of data. At this point, the consumer has completed the previous batch of data, so it sends a synchronization request and then suspends the wait.

[0135] In this relational model, both the producer and the consumer can be any processing unit connected to the multi-core synchronization device, and the synchronization requests sent by the producer and consumer carry the same synchronization domain identifier. The identities of the processing units corresponding to the producers and consumers can be flexibly changed. For example, when it is necessary to produce data to the same physical address, in order to avoid overwriting (duplicate writing) of the data, it is necessary to wait for the consumer to consume all the previous batch of data. At this time, the relationship between the producer and the consumer is swapped. The original producer needs to send a synchronization request of the type record request (carrying the sync field), while the original consumer only needs to send a synchronization request of the type cache request (carrying the pass field) to cooperate with the synchronization device to complete the second synchronization.

[0136] For example, in the synchronization process shown in FIG8 , during the first synchronization, the synchronization request carries a synchronization domain identifier ID=1. Processing units 0 and 1, acting as producers, first produce data and write data A. At this point, processing units 2 and 3, acting as consumers, send synchronization requests of the record request type (carrying the sync field) and wait in a suspended state. Processing units 0 and 1 send synchronization requests of the cache request type (carrying the pass field) and continue producing data until processing units 0 and 1 complete data production in this synchronization process. Since both the producer and consumer have sent synchronization requests at this point, synchronization is complete. The consumer begins consuming data, reading data from address A for processing. After each set of data is processed, it can send a synchronization request of the cache request type (carrying the pass field) and continue consuming data. The producer corresponding to this process sends a synchronization request of the record request type (carrying the sync field) and waits in a suspended state. Since the data production process and the data consumption process are two different synchronization processes, although the same processing unit is used, different synchronization domain identifiers are used.

[0137] In one implementation, it is applied to a barrier model.

[0138] Referring to Figure 9, when multiple processing units need to be executed to the same position, the processing units participating in the synchronization can send a synchronization request of the record request type (carrying a sync field) and then enter a suspended state until the multi-core synchronization device returns a response message and releases the suspension.

[0139] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0140] Figure 10 is a schematic diagram of a multi-core synchronization device provided by an exemplary embodiment of the present application. As shown in Figure 10, the vehicle controller 10 of this embodiment includes: a processor 100, a memory 101, and a computer program 102 stored in the memory 101 and executable on the processor 100, such as a multi-core synchronization program. When the processor 100 executes the computer program 102, it implements the steps in the above-mentioned various multi-core synchronization method embodiments, such as steps S401 to S405 shown in Figure 4. Alternatively, when the processor 100 executes the computer program 102, it implements the functions of each unit in the above-mentioned device embodiments, such as the functions of the synchronization domain status recording module and the processing unit information recording module shown in Figure 3.

[0141] Exemplarily, the computer program 102 may be divided into one or more units, which are stored in the memory 101 and executed by the processor 100 to implement the present application. The one or more units may be a series of computer program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the computer program 102 in the multi-core synchronization device 10. For example, the computer program 102 may be divided into a synchronization domain status recording module and a processing unit information recording module, and the specific functions of each module are as described in the above embodiment.

[0142] The multi-core synchronization device 10 can be any synchronization controller with synchronization functions. The multi-core synchronization device 10 can include, but is not limited to, a processor 100 and a memory 101. Those skilled in the art will understand that Figure 10 is merely an example of a multi-core synchronization device 10 and does not constitute a limitation of the multi-core synchronization device 10. The multi-core synchronization device 10 can include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the multi-core synchronization device 10 can also include input and output devices, network access devices, buses, etc.

[0143] The processor 100 may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0144] The memory 101 may be an internal storage unit of the multi-core synchronization device 10, such as a hard disk or memory of the multi-core synchronization device 10. The memory 101 may also be an external storage device of the multi-core synchronization device 10, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the multi-core synchronization device 10. Furthermore, the memory 101 may also include both an internal storage unit of the multi-core synchronization device 10 and an external storage device. The memory 101 is used to store the computer program and other programs and data required by the terminal device. The memory 101 may also be used to temporarily store data that has been output or is to be output.

[0145] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0146] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0147] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0148] In the embodiments provided in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0149] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0150] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0151] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by the processor, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0152] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0153] The embodiments of the present application further provide a computer program product, which, when executed on a mobile terminal, enables the mobile terminal to implement the steps of the above-mentioned method embodiments.

[0154] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A multi-core synchronization method, characterized in that: Applied in a multi-core synchronization device, the multi-core synchronization device is a device in a multi-core synchronization system, the multi-core synchronization system also includes a plurality of processing units, the plurality of processing units include a first processing unit, the method includes: receiving a first synchronization request from the first processing unit, where the first synchronization request is used to indicate that a synchronization task of the first processing unit has been completed, and the first synchronization request carries a target synchronization domain identifier, where the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit; According to the first synchronization request, adjusting the value of the target counter from a first value to a second value, where the second value is greater than the first value, and a difference between the second value and the first value is 1, and the target counter is a counter corresponding to the target synchronization domain identifier; If the second value is smaller than the preset value corresponding to the target synchronization domain identifier, determine not to send the first response information; or, If the second value is equal to the preset value corresponding to the target synchronization domain identifier, sending a first response message; The first response information is used to instruct the second processing unit corresponding to the target synchronization domain identifier among the multiple processing units to execute a subsequent task, and the preset value is the number of processing units that process the synchronization task.

2. The method according to claim 1, characterized in that If the second value is equal to the preset value corresponding to the target synchronization domain identifier, sending the first response information includes: If the second value is equal to the preset value corresponding to the target synchronization domain identifier, determine the unit identifier of at least one of the second processing units from multiple processing unit information tables according to the target synchronization domain identifier, and the second processing unit is a processing unit among the multiple processing units that has sent a synchronization request carrying the target synchronization domain identifier; The first response information is sent to the second processing unit according to the unit identification of the second processing unit.

3. The method according to claim 2, characterized in that The method further comprises: Switching the state of the processing unit information table of the second processing unit from a running state to a waiting state; The sending the first response information to the second processing unit according to the unit identifier of the second processing unit includes: Determining the status of the plurality of processing unit information tables at preset time intervals; If the states of the plurality of processing unit information tables include the waiting state, the first response information is sent to the processing unit corresponding to the processing unit information table in the plurality of processing unit information tables that is in the waiting state.

4. The method according to any one of claims 1 to 3, characterized in that The first synchronization request also carries a unit identifier of the first processing unit; After receiving the first synchronization request from the first processing unit, the method further includes: The unit identifier of the first processing unit and the target synchronization domain identifier are stored in a first processing unit information table in correspondence; The state of the first processing unit information table is switched from an idle state to a running state.

5. The method according to claim 4, characterized in that The first synchronization request includes a status field, and the corresponding storage of the unit identifier of the first processing unit and the target synchronization domain identifier in the first processing unit information table includes: If the status field indicates that the first synchronization request is a record request, the unit identifier of the first processing unit and the target synchronization domain identifier are stored in the first processing unit information table in correspondence; The method further comprises: If the status field indicates that the first synchronization request is a cache request, cache the synchronization request; Sending second response information to the first processing unit, where the second response information is used to indicate that the first synchronization request has been cached.

6. A multi-core synchronization device, characterized in that: The multi-core synchronization device includes: a synchronization domain status recording module and a processing unit information recording module; The synchronization domain status recording module stores target counters corresponding to multiple synchronization domain identifiers, which are used to receive a first synchronization request from a first processing unit, wherein the first synchronization request is used to indicate that the synchronization task of the first processing unit has been completed, and the first synchronization request carries a target synchronization domain identifier, which is an identifier of the synchronization task executed by the first processing unit; according to the first synchronization request, the value of the target counter is adjusted from a first value to a second value, wherein the second value is greater than the first value, and the difference between the second value and the first value is 1, and the target counter is a counter corresponding to the target synchronization domain identifier; if the second value is less than a preset value corresponding to the target synchronization domain identifier, it is determined not to send a first response message; or, if the second value is equal to the preset value corresponding to the target synchronization domain identifier, a release message is sent to the processing unit information recording module, and the release message carries the target synchronization domain identifier; The processing unit information recording module stores multiple processing unit information tables, which are used to respond to the release information sent by the synchronization domain status recording module, determine the unit identifier of the second processing unit corresponding to the target synchronization domain identifier from the multiple processing unit information tables according to the target synchronization domain identifier carried by the release information, and send a first response information to the second processing unit according to the unit identifier.

7. The multi-core synchronization device according to claim 6, characterized in that: The first synchronization request includes a status field, and the multi-core synchronization device also includes a cache module; The multi-core synchronization device is further configured to parse the first synchronization request to obtain a status field; if the status field indicates that the first synchronization request is a cache request, send the first synchronization request to the cache module; If the status field indicates that the first synchronization request is a record request, sending the first synchronization request to the processing unit information record module; The cache module is used to cache the first synchronization request in response to receiving the first synchronization request, and send second response information to the first processing unit corresponding to the first synchronization request, wherein the second response information is used to indicate that the synchronization request of the first processing unit has been cached.

8. The multi-core synchronization device according to claim 6, characterized in that: The processing unit information recording module is further used to store the unit identifier of the first processing unit and the target synchronization domain identifier in the processing unit information table in response to receiving the first synchronization request sent by the first processing unit; and switch the state of the processing unit information table from an idle state to a running state; The processing unit information recording module is also used to switch the status of the processing unit information tables of the first processing unit and the second processing unit from a running status to a waiting status after receiving the release information; determine the status of the multiple processing unit information tables at preset time intervals; if the status of the multiple processing unit information tables includes the waiting status, send the first response information to the processing unit corresponding to the processing unit information table in the waiting status among the multiple processing unit information tables; switch the status of the processing unit information table corresponding to the processing unit that has sent the first response information from a waiting status to an idle status.

9. A multi-core synchronization system, characterized in that: The multi-core synchronization system comprises a plurality of processing units and the multi-core synchronization device according to any one of claims 6 to 8; For any processing unit, the processing unit is used to send a synchronization request to the multi-core synchronization device in response to the processing unit completing the task to be synchronized, the synchronization request is used to indicate that the synchronization task of the processing unit has been completed, and the first synchronization request carries a target synchronization domain identifier, and the target synchronization domain identifier is an identifier of the synchronization task executed by the first processing unit; The multi-core synchronization device is used to execute the multi-core synchronization method described in any one of claims 1-5.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the multi-core synchronization method according to any one of claims 1 to 5.

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