DMA (Direct Memory Access) communication device for computing network integration computing architecture and working method of DMA communication device

Abstract

The invention discloses a direct memory access (DMA) communication device for a computing network convergence computing architecture and a working method of the DMA communication device. The DMA communication device comprises a DMA transaction processing module and a protocol conversion module; the DMA transaction processing module is used for analyzing related DMA read-write requests, realizing processing of the DMA read-write requests and receiving of response data of the DMA read requests and completing processing of interrupt requests at the same time, and the protocol conversion module is used for completing conversion of read-write requests between a DMA interface and an AXI interface and mapping of response states. The invention aims to realize efficient protocol conversion between AXI and DMA interfaces, avoid the problem of DMA read request starvation caused by resource competition and ensure the consistency of DMA data access so as to improve the performance of an accelerator in high-performance calculation and artificial intelligence application, reduce transmission delay and improve data transmission bandwidth and energy efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer communication technology, and in particular to a DMA communication device for a computer-network fusion computing architecture and a working method thereof. Background Art

[0002] To meet the explosive growth in computing power and diverse converged support requirements for high-performance computing (HPC) and artificial intelligence (AI) applications, traditional CPU+GPU heterogeneous computing architectures, which use the PCIe bus to interconnect the CPU, GPU, and network interface card (NIC), face limitations in data transmission bandwidth and energy efficiency. Against this backdrop, heterogeneous computing architectures that integrate computing and network components using on-chip heterogeneous integration or multi-chip integration have become a significant development trend. These converged computing and network architectures use AXI interfaces to integrate computing and network components on-chip, reducing transmission latency and improving data transmission bandwidth and energy efficiency. Direct Memory Access (DMA) allows certain hardware subsystems to directly access system memory without CPU control. In HPC and AI applications, this can be used by GPUs to directly access system memory without CPU control, potentially improving GPU performance. Therefore, implementing DMA communication technology for converged computing and network architectures has become a key technical challenge that needs to be addressed. Summary of the Invention

[0003] Technical problem to be solved by the present invention: In response to the above-mentioned problems of the prior art, a DMA communication device and a working method thereof are provided for a computing-network fusion computing architecture. The present invention aims to achieve efficient protocol conversion between the AXI interface and the DMA interface, avoid the DMA read request starvation problem caused by resource competition, and ensure the consistency of DMA data access, so as to improve the performance of accelerators in high-performance computing and artificial intelligence applications, reduce transmission delays and improve data transmission bandwidth and energy efficiency.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A DMA communication device for a computing-network fusion computing architecture comprises two interconnected modules, a DMA transaction processing module and a protocol conversion module. The protocol conversion module is connected to a computing component and a memory connected to an on-chip network NoC via an AXI interface. The DMA transaction processing module is connected to a network protocol processing component. When the network protocol processing component initiates a DMA read / write request, the DMA transaction processing module is used to parse the relevant DMA read / write request, implement the processing of the DMA read / write request and receive the DMA read request response data, and complete the processing of the interrupt request at the same time. The protocol conversion module is used to complete the conversion of the read / write request and the mapping of the response status between the DMA interface and the AXI interface. The protocol conversion module includes a read Request FIFO, request conversion unit, data FIFO, data conversion unit and state conversion unit, the read request FIFO is used to cache DMA read request information received by the protocol conversion module to ensure the smooth execution of continuous read request operations; the request conversion unit parses DMA read and write requests, converts DMA read and write requests into AXI read and write requests and converts the request address and data length; the data FIFO is responsible for caching DMA write request data and DMA read response data; the data conversion unit converts the big and small end of the data to achieve cross-protocol data consistency; the state conversion unit is responsible for converting the AXI response signal into the transaction processing status of the DMA read and write request, and the transaction processing status includes success or failure.

[0005] Optionally, the DMA transaction processing module includes a DMA write request processing module and a DMA read request processing module for processing DMA write requests and DMA read requests from the network protocol processing component. The DMA write request processing module is used to cache the DMA write requests initiated by the network protocol processing component, parse the target address and data length of the request, and transmit the target address, data length and write data to the protocol conversion module; the DMA read request processing module receives requests from each read request source in parallel through a one-to-one correspondence between the request queue and the read request source; at the same time, the DMA read request processing module arbitrates the read request according to the available credit and whether there is a read-write conflict, and after receiving the response data of the read request, transmits it to the corresponding read request source. The DMA transaction processing module uses an interrupt line to trigger an interrupt after the DMA data transmission is completed, notifying the CPU to release memory access rights, thereby realizing alternating memory access between the CPU and DMA and reducing resource competition.

[0006] Optionally, the DMA write request processing module is composed of a DMA write request FIFO, a DMA write data FIFO, a DMA write control unit and an interrupt request unit. The DMA write request FIFO is used to cache write requests initiated by the network protocol processing component, and the DMA write data FIFO is used to cache write data of write requests initiated by the network protocol processing component. When the DMA write control unit detects the write request channel ready signal, it reads the write request and write data from the DMA write request FIFO and the DMA write data FIFO respectively, parses the target address and data length of the request, and transmits the address, data length and write data to the protocol conversion module; after the data transmission is completed, the DMA write control unit marks that the write request has been successfully sent, and triggers the interrupt request unit to perform the interrupt request and clear operation through the interrupt enable signal. The DMA read request processing module includes a DMA read request FIFO allocated to each read request source, a read request arbitration unit and a DMA read control unit. The DMA read request FIFO is used to cache the read requests initiated by the network protocol processing component. The read request arbitration unit is used to determine whether each read request FIFO has the processing conditions based on the available credits and whether there is a read-write conflict, and to perform polling arbitration on the request FIFOs that meet the conditions to determine the DMA read requests to be processed. When the DMA read control unit detects the read request channel ready signal, it receives and parses the DMA read request determined by the read arbitration unit, transmits the corresponding DMA read request information to the protocol conversion module, and receives its response data at the same time. After feeding back the response data to the corresponding read request source, the DMA transaction processing module performs credit recovery and resource release operations.

[0007] Optionally, the DMA write control unit has a built-in write request receiving counter and a write request sending counter for controlling the execution order between DMA read requests and DMA write requests. The value wreq_count of the write request receiving counter is used to record the number of write requests initiated by the network protocol processing component. Whenever the DMA write control unit receives a new write request, the counter is incremented. The value wsent_count of the write request sending counter indicates the number of write requests that have completed data transmission. The counter is incremented each time a write request is sent to the protocol conversion module. When the DMA read request processing module receives a new read request, the value wreq_count of the current write request receiving counter is incremented. unt is merged with the read request and stored in the corresponding DMA read request FIFO; in the arbitration stage, the read request arbitration unit compares the value wreq_count of the write request receiving counter carried in the read request with the value wsent_count of the write request sending counter of the current DMA write control unit to determine whether there is an unfinished preceding write request for the read request: if the value wsent_count of the write request sending counter is greater than or equal to the value wreq_count of the write request receiving counter, it means that all write requests received before the read request have been sent to the protocol conversion module, and there is no read-write conflict at this time, and the read request can be processed; otherwise, the read request will not be processed for the time being.

[0008] Optionally, the read request arbitration unit is used to determine whether each read request FIFO has processing conditions based on available credits and whether there is a read-write conflict. The basis for determining whether each read request FIFO has processing conditions includes: (1) the read request FIFO of the request source is not empty and there are unprocessed read requests; (2) the reserved credits of the request source are not exhausted or the total credit resources used have not reached the system upper limit; (3) there is no situation where "write first, read later" is mistakenly processed as "read first, write later".

[0009] Optionally, the working state flow of the protocol conversion module includes four stages: initial state IDLE, address resolution state ADDR_PARSE, data transmission state DATA_XFER and response adaptation state RESP_ADAPT. After power-on reset, the protocol conversion module is in the initial state IDLE, waiting for the DMA request signal; when the DMA read and write request enable signal is detected, the module enters the address resolution state ADDR_PARSE and completes the AXI request conversion; in the address resolution state ADDR_PARSE, the DMA request conversion unit will cache the DMA read request information and convert the DMA read and write request into an AXI read and write request, and at the same time generate AXI address information, calculate the AXI bit width and Burst, and generate a byte valid signal; after the conversion is completed, the module enters the data transmission state DATA_XFER state , realizing DMA data conversion and transmission; in the data transmission state DATA_XFER, the DMA data conversion unit caches the DMA request data and performs data endian conversion according to the request type: if it is a write request, the protocol conversion module waits for the DMA write data to be valid, stores the DMA write request data in the data FIFO and sends it to the AXI interface after endian conversion; if it is a read request, the protocol conversion module waits for the AXI read data feedback to be valid, performs endian conversion and stores it in the data FIFO; after the transmission is completed, the protocol conversion module enters the response adaptation state RESP_ADAPT and feeds back the processing status of the DMA request; in the response adaptation state RESP_ADAPT, the protocol conversion module generates an AXI response request signal, parses the DMA processing result and feeds it back to the DMA transaction processing module, and then returns to the initial state IDLE.

[0010] In addition, the present invention also provides a computing chip for fusion of computing and network, comprising a computing component, an on-chip network NoC, a DMA communication device and a network protocol processing component connected in sequence, wherein the DMA communication device is the DMA communication device for the computing and network fusion computing architecture.

[0011] In addition, the present invention also provides a working method of the aforementioned DMA communication device for the computing-network fusion computing architecture, including a request conversion unit performing DMA request conversion: including AXI transaction request generation, address information conversion, AXI Burst length calculation and write byte valid signal generation; when the network protocol processing component initiates a DMA transaction request, if it is a read request, the request conversion unit caches the read request to the read request FIFO and converts it into an AXI read request in sequence; if it is a write request, the request conversion unit directly converts it; then the request conversion unit sends the converted AXI read and write request to the processor, and performs address information conversion operation at the same time; when the address information is converted, the request conversion unit maps the DMA request address to an AXI physical address, and generates a write byte valid signal for the write request, the AXI interface data bit width is 256 bits, the offset of the DMA write request address is represented by ADDR[4:0], and the request conversion unit judges and generates the corresponding byte valid signal based on whether the address is aligned: for the case of address alignment, if the total data length is If the address is less than or equal to 32 bytes, a single-beat byte valid signal is generated according to the data length; if it exceeds 32 bytes, the first several beats transmitted in Burst mode are all valid, and the last beat generates the corresponding byte valid signal according to the remaining data length; and for the case of unaligned addresses, if the total data length is If the total data length is less than or equal to 32-ADDR[4:0], a single-byte valid signal is generated by combining the address offset and data length; If it exceeds 32-ADDR[4:0], the first beat generates a partial byte valid signal according to the address offset, the middle beat is fully valid, and the last beat generates a corresponding byte valid signal according to the remaining data length; when calculating the AXI Burst length, the request conversion unit calculates the AXI Burst length according to the data length of the DMA request, and its calculation function expression is:

[0012] in, is the AXI Burst length, is the total data length, The offset of the DMA write request address. is the ceiling operator.

[0013] Optionally, a data conversion unit is also included to perform DMA data conversion: after receiving the DMA data enable signal, the data conversion unit will cache the DMA write request data in the data FIFO and initiate an AXI write data request. At the same time, the data conversion unit will perform big-endian and small-endian format conversion, and use a counter to count the amount of data transmitted to ensure the accuracy of data transmission. If the length of the data to be transmitted is less than the data bus bit width, the data conversion unit sets the last beat data signal to be valid, notifying the processor that the data transmission is over; during the DMA read request processing, when the data conversion unit receives the AXI read response data enable signal, it converts the response data into big-endian and small-endian formats, and caches the converted DMA response data into the data FIFO. If the length of the data to be transmitted is less than the data bus bit width, the data conversion unit sets the last beat data signal to be valid, notifying the network protocol processing component that the data transmission is over.

[0014] Optionally, a state conversion unit is also included to perform DMA state conversion: during the write request processing, after the write data request is responded to, the state conversion unit waits for the data transmission to be completed, and then converts the AXI write request response into a DMA transaction processing state. During the read request processing, the AXI read data feedback is completed and the AXI response request is parsed into a DMA transaction processing state. The transaction processing state includes success or failure.

[0015] Compared with the prior art, the present invention can mainly achieve the following beneficial effects: in the computing-network fusion computing architecture, the network protocol processing component accesses the storage space through DMA requests. Based on this architecture, the device of the present invention can complete the DMA communication conversion and processing between the network protocol processing component and the computing component, and realize efficient DMA communication between the computing component and the network component. The device of the present invention completes efficient protocol conversion between the AXI interface and the DMA interface through the decoupling design of the address, data and response channels. At the same time, the device of the present invention reserves a certain credit for each DMA read request, and avoids the starvation problem of DMA read requests caused by resource competition through a fair round-robin scheduling strategy. The device of the present invention ensures the consistency of DMA data access by controlling the execution order between DMA read requests and DMA write requests. The device of the present invention can improve the performance of computing components in high-performance computing and artificial intelligence applications, reduce transmission delays, and improve data transmission bandwidth and energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the structure of a DMA communication device in an embodiment of the present invention.

[0017] Figure 2 Schematic diagram of the structure of the DMA transaction processing module in an embodiment of the present invention.

[0018] Figure 3Schematic diagram of the principles of the three conversion functions of the protocol conversion module in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In a converged computing architecture, network protocol processing components access storage space through DMA requests. Based on this architecture, the present invention proposes an AXI interface DMA communication device to perform DMA communication conversion and processing between the network protocol processing component and the computing component. To facilitate a better understanding of the technical solution of the present invention by those skilled in the art, the following detailed description of the technical solution is provided in conjunction with the accompanying drawings illustrating embodiments of the present invention.

[0020] like Figure 1 As shown, this embodiment provides a DMA communication device for a computing-network fusion computing architecture, including two modules: a DMA transaction processing module and a protocol conversion module that are interconnected. The protocol conversion module is connected to a computing component (such as a general computing component, an accelerated computing component, etc.) and a memory connected to an on-chip network NoC through an AXI interface. The DMA transaction processing module is connected to a network protocol processing component. When the network protocol processing component initiates a DMA read / write request, the DMA transaction processing module is used to parse the relevant DMA read / write request, implement the processing of DMA read / write requests and the reception of DMA read request response data, and complete the processing of interrupt requests at the same time. The protocol conversion module is used to complete the conversion of read / write requests and the mapping of response status between the DMA interface and the AXI interface.

[0021] like Figure 1 As shown, the DMA transaction processing module in this embodiment includes a DMA write request processing module and a DMA read request processing module for processing DMA write requests and DMA read requests from the network protocol processing component. The DMA write request processing module is used to cache the DMA write requests initiated by the network protocol processing component, parse the target address and data length of the request, and transmit the target address, data length and write data to the protocol conversion module; the DMA read request processing module receives requests from each read request source in parallel through a one-to-one correspondence between the request queue and the read request source; at the same time, the DMA read request processing module arbitrates the read request based on the available credit and whether there is a read-write conflict, and after receiving the response data of the read request, transmits it to the corresponding read request source. The DMA transaction processing module uses an interrupt line to trigger an interrupt after the DMA data transmission is completed, notifying the CPU to release the memory access permission, thereby realizing alternating memory access between the CPU and DMA and reducing resource contention.

[0022] like Figure 1As shown, the protocol conversion module in this embodiment includes a read request FIFO, a request conversion unit, a data FIFO, a data conversion unit and a state conversion unit. The read request FIFO is used to cache the DMA read request information received by the protocol conversion module to ensure the smooth execution of continuous read request operations; the request conversion unit parses the DMA read and write requests, converts the DMA read and write requests into AXI read and write requests, and converts the request address and data length; the data FIFO is responsible for caching DMA write request data and DMA read response data; the data conversion unit converts the big / little endian of the data to achieve cross-protocol data consistency; the state conversion unit is responsible for converting the AXI response signal into the transaction processing status of the DMA read and write request, and the transaction processing status includes success or failure.

[0023] like Figure 2 As shown, the DMA write request processing module in this embodiment is composed of a DMA write request FIFO, a DMA write data FIFO, a DMA write control unit and an interrupt request unit. The DMA write request FIFO is used to cache write requests initiated by the network protocol processing component, and the DMA write data FIFO is used to cache write data of write requests initiated by the network protocol processing component. When the DMA write control unit detects the write request channel ready signal, it reads the write request and write data from the DMA write request FIFO and the DMA write data FIFO respectively, parses the target address and data length of the request, and transmits the address, data length and write data to the protocol conversion module; after the data transmission is completed, the DMA write control unit marks that the write request has been successfully sent, and triggers the interrupt request unit to perform interrupt request and clear operations through the interrupt enable signal.

[0024] like Figure 2 As shown, the DMA read request processing module in this embodiment includes a DMA read request FIFO allocated to each read request source, a read request arbitration unit and a DMA read control unit. The DMA read request FIFO is used to cache read requests initiated by the network protocol processing component. The read request arbitration unit is used to determine whether each read request FIFO has processing conditions based on available credits and whether there is a read-write conflict, and to perform polling arbitration on the request FIFOs that meet the conditions to determine the DMA read request to be processed; when the DMA read control unit detects a read request channel ready signal, it receives and parses the DMA read request determined by the read arbitration unit, and transmits the corresponding DMA read request information to the protocol conversion module, and receives its response data at the same time; after feeding back the response data to the corresponding read request source, the DMA transaction processing module performs credit recovery and resource release operations.

[0025] In this embodiment, the DMA write request FIFO and the DMA write data FIFO are used to cache the write requests and corresponding write data initiated by the network protocol processing component, respectively. Specifically, when the DMA transaction processing module receives the DMA write request enable signal from the network protocol processing component, it increments the value of the write request reception counter wreq_count, stores the write request in the DMA write request FIFO, assigns a unique number to each write request, and returns a request response signal at the same time. After receiving the DMA write data enable signal from the network protocol processing component, the data is stored in the DMA write data FIFO, and a reception response signal is returned. The DMA transaction processing module prevents "write first, read later" from being mistakenly processed as "read first, write later" by controlling the execution order between the DMA read request and the DMA write request, thereby ensuring the consistency of read and write access. In order to ensure the consistency of read and write access, the DMA write control unit in this embodiment has built-in write request receiving counter and write request sending counter to control the execution order between DMA read request and DMA write request. The value wreq_count of the write request receiving counter is used to record the number of write requests initiated by the network protocol processing component. Whenever the DMA write control unit receives a new write request, the counter is incremented. The value wsent_count of the write request sending counter represents the number of write requests that have completed data transmission. The counter is incremented after each write request is sent to the protocol conversion module. When the DMA read request processing module receives a new read request, the value wreq_count of the current write request receiving counter is compared with the read request. After the requests are merged, they are stored in the corresponding DMA read request FIFO. In the arbitration stage, the read request arbitration unit compares the value of the write request receiving counter wreq_count carried in the read request with the value of the write request sending counter wsent_count of the current DMA write control unit to determine whether the read request has an unfinished preceding write request: if the value of the write request sending counter wsent_count is greater than or equal to the value of the write request receiving counter wreq_count (i.e., wsent_count ≥ wreq_count), it means that all write requests received before the read request have been sent to the protocol conversion module. At this time, there is no read-write conflict and the read request can be processed. Otherwise, the read request will not be processed for the time being.

[0026] In this embodiment, the DMA write control unit is responsible for managing the processing of DMA write requests, and its control logic is as follows: when the DMA write request channel of the protocol conversion module is ready and there is a pending request in the DMA write request FIFO, the DMA write control unit sends a read enable signal to the DMA write request FIFO, reads a write request and parses the write data address and data length, then sends the parsed result to the protocol conversion module and triggers the DMA write request enable signal, and then performs data transmission. The DMA write control unit sends a read enable signal to the DMA write data FIFO, reads the requested write data and sends it to the protocol conversion module, and at the same time triggers the DMA write data enable signal. After the transmission is completed, the DMA write control unit triggers the DMA write data completion signal, increments the value of the write request sending counter to mark that the current write request has been successfully sent to the protocol conversion module, and prepares to process the next write request. If an interrupt request is parsed during the request processing, the DMA transaction processing module sends an interrupt enable signal to the interrupt request unit to trigger interrupt processing, and at the same time suspends the processing of the current write request, and continues the DMA write request processing after the interrupt processing is completed.

[0027] In this embodiment, the interrupt request unit is responsible for interrupt request and clear operations. When the interrupt request unit detects the interrupt enable signal from the DMA read control unit, it sends an interrupt request signal to the processor via the interrupt line and suspends the current DMA transaction processing to ensure data consistency. After the interrupt processing is completed, the status flag clearing mechanism resumes the DMA transaction request processing flow.

[0028] In this embodiment, the DMA read request FIFO caches read requests initiated by the network protocol processing component. Specifically, the DMA transaction processing module allocates an independent DMA read request FIFO to each read request source of the network protocol processing component, ensuring that each DMA read request FIFO corresponds to a read request source. When the DMA transaction processing module receives the DMA read request enable signal from the network protocol processing component, it obtains the value wreq_count of the write request reception counter in the current write request processing module, concatenates it with the read request to form a single data, and then stores it in the corresponding DMA read request FIFO based on its source. A unique number is assigned to the read request, and a read request response signal is returned to the network protocol processing component.

[0029] In this embodiment, the read request arbitration unit is responsible for polling arbitration of the DMA read request FIFOs of each read request source. The unit independently maintains credit for each DMA read request source and reserves a certain credit value to prevent a single request source from excessively occupying system resources. The arbitration logic takes the larger value of the actual used credit and the reserved credit of each request source as its effective used credit; and judges whether the credit resources have been exhausted based on the sum of the effective used credits of all request sources and the preset threshold. The read request arbitration unit is used to judge whether each read request FIFO has the processing conditions based on the available credits and whether there is a read-write conflict. The judgment basis for judging whether each read request FIFO has the processing conditions includes: (1) the read request FIFO of the request source is not empty and there are unprocessed read requests; (2) the reserved credit of the request source is not exhausted or the total used credit resources have not reached the system upper limit; (3) there is no situation where "write first, read later" is mistakenly processed as "read first, write later". Subsequently, the read request arbitration unit adopts a polling strategy to read requests from the qualified read request FIFOs and hands them over to the DMA read control unit for processing. During the request processing, the DMA transaction processing module updates the credit usage in real time.

[0030] In this embodiment, the DMA read control unit is responsible for coordinating the processing of DMA read requests and receiving response data. During the DMA read request processing phase, upon detecting the DMA read request channel ready signal from the protocol conversion module, the DMA read control unit retrieves the pending read request from the read request arbitration unit and decrements the credit of the corresponding request source. The DMA read control unit then parses the target address and data length information in the read request, stores the parsed request in the response request queue, and sends the DMA read request ID, DMA read data address, and DMA read data length to the protocol conversion module. Simultaneously, it triggers the DMA read request enable signal to complete the submission of the DMA read request. Upon receiving the read response enable signal from the protocol conversion module, the DMA read control unit enters the response data reception process. First, the read control unit determines whether the receive buffer space of the request source corresponding to the read response ID is sufficient to accommodate the current response data. If the receive buffer space of the request source is sufficient to accommodate the response data, the DMA read control unit sends a DMA read data enable signal to the protocol conversion module and receives the response data; otherwise, data reception is suspended. Upon data reception completion, the response data reception completion signal and the response data enable signal are asserted, and the response data is forwarded to the corresponding request source. Finally, the DMA read control unit releases the credit resources occupied by the read request, marks the read transaction as complete, and prepares to process subsequent requests.

[0031] like Figure 3 As shown, the protocol conversion module of the DMA communication device in this embodiment mainly realizes the functions of DMA request conversion, DMA data conversion and DMA state conversion. Figure 3As shown, the DMA request conversion performed by the request conversion unit is responsible for buffering DMA read request information, converting DMA read / write requests into AXI read / write requests, and sending them to the processor via the AXI bus. It also parses DMA address information to generate corresponding AXI address information, parses DMA data length to calculate the AXI bit width and burst parameters, and generates a write request byte valid signal. The DMA data conversion performed by the data conversion unit is responsible for buffering DMA request data, converting between DMA data and AXI data through big / little endian format conversion, and converting between DMA data enable signals and AXI data valid signals. The DMA state conversion performed by the state conversion unit is used to monitor the processing progress of DMA requests, generate corresponding AXI response requests, and, after the AXI response handshake signal is parsed and converted into a DMA transaction processing state, feed it back to the network protocol processing component. In this embodiment, the working state flow of the protocol conversion module includes four stages: initial state IDLE, address resolution state ADDR_PARSE, data transmission state DATA_XFER, and response adaptation state RESP_ADAPT. After power-on reset, the protocol conversion module is in the initial state IDLE, awaiting DMA request signals. Upon detecting the DMA read / write request enable signal, the module enters the address resolution state ADDR_PARSE to complete AXI request conversion. In the ADDR_PARSE state, the DMA request conversion unit buffers DMA read request information and converts DMA read / write requests into AXI read / write requests. It also generates AXI address information, calculates the AXI bit width and burst, and generates a byte valid signal. After the conversion is complete, the module enters the DATA_XFER state to perform DMA data conversion and transmission. In the DATA_XFER state, the DMA data conversion unit buffers the DMA request data and performs endian conversion based on the request type. If it's a write request, the protocol conversion module waits for the DMA write data to be valid before storing the DMA write request data in the data FIFO and performing endian conversion before sending it to the AXI interface. If it's a read request, the protocol conversion module waits for the AXI read data to be valid before performing endian conversion and storing it in the data FIFO. After the transfer is complete, the protocol conversion module enters the RESP_ADAPT state to provide feedback on the DMA request processing status. In the response adaptation state RESP_ADAPT, the protocol conversion module generates an AXI response request signal, parses the DMA processing result and feeds it back to the DMA transaction processing module, and then returns to the initial state IDLE.

[0032] In summary, the DMA communication device of this embodiment includes a DMA transaction processing module and a protocol conversion module. When the network protocol processing component initiates a DMA read / write request, the DMA transaction processing module is used to parse the relevant DMA read / write request, implement the processing of the DMA read / write request and the reception of the DMA read request response data, and simultaneously complete the processing of the interrupt request. The protocol conversion module is used to complete the conversion of the read / write request and the mapping of the response status between the DMA interface and the AXI interface. The DMA communication device of this embodiment can realize efficient protocol conversion between the AXI interface and the DMA interface, avoid the problem of DMA read request starvation caused by resource competition, ensure the consistency of DMA data access, thereby improving the performance of the accelerator in high-performance computing and artificial intelligence applications, reducing transmission delay and improving data transmission bandwidth and energy efficiency.

[0033] In addition, this embodiment also provides a computing chip for fusion of computing and network, including a computing component, an on-chip network NoC, a DMA communication device and a network protocol processing component connected in sequence, and the DMA communication device is the DMA communication device used for the computing and network fusion computing architecture.

[0034] In addition, this embodiment also provides a working method of the DMA communication device for the computing network fusion computing architecture mentioned above, including a request conversion unit performing DMA request conversion (converting DMA read and write requests into AXI read and write requests): including AXI transaction request generation, address information conversion, AXI Burst length calculation and write byte valid signal generation; when the network protocol processing component initiates a DMA transaction request, if it is a read request, the request conversion unit caches the read request to the read request FIFO and converts it into an AXI read request in sequence; if it is a write request, the request conversion unit directly converts it; then the request conversion unit sends the converted AXI read and write request to the processor and performs an address information conversion operation at the same time; when the address information is converted, the request conversion unit maps the DMA request address to an AXI physical address and generates a write byte valid signal for the write request, the AXI interface data bit width is 256 bits (i.e. 32 bytes), the offset of the DMA write request address is represented by ADDR[4:0], and the request conversion unit judges and generates a corresponding byte valid signal based on whether the address is aligned: for the case of address alignment, if the total data length is If the address is less than or equal to 32 bytes, a single-beat byte valid signal is generated according to the data length; if it exceeds 32 bytes, the first several beats transmitted in Burst mode are all valid, and the last beat generates the corresponding byte valid signal according to the remaining data length; and for the case of unaligned addresses, if the total data length is Less than or equal to 32-ADDR[4:0], that is: , then combine the address offset and data length to generate a single-byte valid signal; if the total data length If it exceeds 32-ADDR[4:0], the first beat generates a partial byte valid signal according to the address offset, the middle beat is fully valid, and the last beat generates a corresponding byte valid signal according to the remaining data length; when calculating the AXI Burst length, the request conversion unit calculates the AXI Burst length according to the data length of the DMA request, and its calculation function expression is:

[0035] in, is the AXI Burst length, is the total data length, The offset of the DMA write request address. is a ceiling operator. Furthermore, in this embodiment, each AXI request carries a unique ID to ensure the independence of multiple request operations. After receiving the AXI request response signal, DMA data conversion is performed and DMA read / write transaction requests are responded to via the system bus.

[0036] The method of this embodiment also includes a data conversion unit performing DMA data conversion: after receiving a DMA data enable signal, the data conversion unit will cache the DMA write request data in the data FIFO and initiate an AXI write data request. At the same time, the data conversion unit will perform big-endian and small-endian format conversion, and use a counter to count the amount of data transmitted to ensure the accuracy of data transmission. If the length of the data to be transmitted is less than the data bus width, the data conversion unit will set the last beat data signal to be valid, notifying the processor that the data transmission is completed; during the DMA read request processing, when the data conversion unit receives the AXI read response data enable signal, it will convert the response data into big-endian and small-endian formats, and cache the converted DMA response data into the data FIFO. If the length of the data to be transmitted is less than the data bus width, the data conversion unit will set the last beat data signal to be valid, notifying the network protocol processing component that the data transmission is completed.

[0037] The method of this embodiment further includes a state conversion unit performing DMA state conversion: during the write request processing, after the write data request is responded to, the state conversion unit waits for the data transmission to be completed, and then converts the AXI write request response to the DMA transaction processing state. During the read request processing, when the AXI read data feedback is completed, the AXI response request is parsed into the DMA transaction processing state, and the transaction processing state includes success or failure.

[0038] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A DMA communication device for a computing-network fusion computing architecture, characterized in that: It includes two modules, a DMA transaction processing module and a protocol conversion module, which are interconnected. The protocol conversion module is connected to the computing component and memory connected to the on-chip network NoC through an AXI interface. The DMA transaction processing module is connected to the network protocol processing component. When the network protocol processing component initiates a DMA read / write request, the DMA transaction processing module is used to parse the relevant DMA read / write request, implement the processing of the DMA read / write request and the reception of the DMA read request response data, and simultaneously complete the processing of the interrupt request. The protocol conversion module is used to complete the conversion of the read / write request and the mapping of the response status between the DMA interface and the AXI interface; the protocol conversion module includes a read request FIFO, a request conversion unit, a data FIFO, a data conversion unit and a state conversion unit; the read request FIFO is used to cache the DMA read request information received by the protocol conversion module to ensure the smooth execution of continuous read request operations; the request conversion unit parses the DMA read / write request, converts the DMA read / write request into an AXI read / write request and converts the request address and data length; the data FIFO is responsible for caching the DMA write request data and the DMA read response data; The data conversion unit achieves cross-protocol data consistency by converting the big-endian and small-endian data. The state conversion unit is responsible for converting the AXI response signal into the transaction processing status of the DMA read and write request, and the transaction processing status includes success or failure.

2. The DMA communication device for computing-network fusion computing architecture according to claim 1, characterized in that: The DMA transaction processing module includes a DMA write request processing module and a DMA read request processing module for processing DMA write requests and DMA read requests from the network protocol processing component. The DMA write request processing module is used to cache the DMA write requests initiated by the network protocol processing component, parse the target address and data length of the request, and transmit the target address, data length and write data to the protocol conversion module; the DMA read request processing module receives requests from each read request source in parallel through a one-to-one correspondence between the request queue and the read request source; at the same time, the DMA read request processing module arbitrates the read request based on the available credit and whether there is a read-write conflict, and after receiving the response data of the read request, transmits it to the corresponding read request source. The DMA transaction processing module uses an interrupt line to trigger an interrupt after the DMA data transmission is completed, notifying the CPU to release memory access rights, thereby realizing alternating memory access between the CPU and DMA and reducing resource contention.

3. The DMA communication device for computing-network fusion computing architecture according to claim 2, characterized in that: The DMA write request processing module is composed of a DMA write request FIFO, a DMA write data FIFO, a DMA write control unit, and an interrupt request unit. The DMA write request FIFO is used to cache write requests initiated by the network protocol processing component, and the DMA write data FIFO is used to cache write data of write requests initiated by the network protocol processing component. When the DMA write control unit detects a write request channel ready signal, it reads the write request and write data from the DMA write request FIFO and the DMA write data FIFO respectively, parses the target address and data length of the request, and transmits the address, data length, and write data to the protocol conversion module; After the data transmission is completed, the DMA write control unit marks that the write request has been successfully sent, and triggers the interrupt request unit to perform interrupt request and clear operations through the interrupt enable signal; the DMA read request processing module includes a DMA read request FIFO allocated to each read request source, a read request arbitration unit and a DMA read control unit, the DMA read request FIFO is used to buffer the read request initiated by the network protocol processing component, and the read request arbitration unit is used to determine whether each read request FIFO meets the processing conditions based on available credits and whether there is a read-write conflict, and polls and arbitrates the request FIFOs that meet the conditions to determine the DMA read request to be processed; When the DMA read control unit detects the read request channel ready signal, it receives and analyzes the DMA read request determined by the read arbitration unit, transmits the corresponding DMA read request information to the protocol conversion module, and receives its response data at the same time; After feeding back the response data to the corresponding read request source, the DMA transaction processing module performs credit recovery and resource release operations.

4. The DMA communication device for computing-network fusion computing architecture according to claim 3, characterized in that: The DMA write control unit has a built-in write request receiving counter and a write request sending counter for controlling the execution order between DMA read requests and DMA write requests. The value wreq_count of the write request receiving counter is used to record the number of write requests initiated by the network protocol processing component. Whenever the DMA write control unit receives a new write request, the counter is incremented. The value wsent_count of the write request sending counter represents the number of write requests that have completed data transmission. The counter is incremented after each write request is sent to the protocol conversion module. When the DMA read request processing module receives a new read request, the value wreq_count of the current write request receiving counter is combined with the read request and stored in the corresponding DMA read request FIFO. During the arbitration stage, the read request arbitration unit compares the value wreq_count of the write request receiving counter carried in the read request with the value wsent_count of the write request sending counter of the current DMA write control unit to determine whether the read request has an unfinished preceding write request: if the value wsent_count of the write request sending counter is greater than or equal to the value wreq_count of the write request receiving counter, it means that all write requests received before the read request have been sent to the protocol conversion module, and there is no read-write conflict at this time, and the read request can be processed; otherwise, the read request will not be processed for the time being.

5. The DMA communication device for computing-network fusion computing architecture according to claim 4, characterized in that: The read request arbitration unit is used to determine whether each read request FIFO has processing conditions based on available credits and whether there is a read-write conflict. The basis for determining whether each read request FIFO has processing conditions includes: (1) the read request FIFO of the request source is not empty and there are unprocessed read requests; (2) the reserved credits of the request source are not exhausted or the total credit resources used have not reached the system upper limit; (3) there is no situation where "write first, read later" is mistakenly processed as "read first, write later".

6. The DMA communication device for computing-network fusion computing architecture according to claim 2, characterized in that: The working state flow of the protocol conversion module includes four stages: initial state IDLE, address resolution state ADDR_PARSE, data transmission state DATA_XFER and response adaptation state RESP_ADAPT. After power-on reset, the protocol conversion module is in the initial state IDLE, waiting for the DMA request signal; when the DMA read and write request enable signal is detected, the module enters the address resolution state ADDR_PARSE and completes the AXI request conversion; in the address resolution state ADDR_PARSE, the DMA request conversion unit caches the DMA read request information and converts the DMA read and write request into an AXI read and write request, and at the same time generates AXI address information, calculates the AXI bit width and Burst, and generates a byte valid signal; after the conversion is completed, the module enters the data transmission state DATA_XFER state, and realizes DMA data conversion and transmission are now performed; in the data transmission state DATA_XFER, the DMA data conversion unit caches the DMA request data and performs data endian conversion according to the request type: if it is a write request, the protocol conversion module waits for the DMA write data to be valid, stores the DMA write request data in the data FIFO and sends it to the AXI interface after endian conversion; if it is a read request, the protocol conversion module waits for the AXI read data feedback to be valid, performs endian conversion and stores it in the data FIFO; after the transmission is completed, the protocol conversion module enters the response adaptation state RESP_ADAPT and feeds back the processing status of the DMA request; in the response adaptation state RESP_ADAPT, the protocol conversion module generates an AXI response request signal, parses the DMA processing result and feeds it back to the DMA transaction processing module, and then returns to the initial state IDLE.

7. A computing chip integrating computing and network, comprising a computing component, a network on chip (NoC), a DMA communication device and a network protocol processing component connected in sequence, characterized in that: The DMA communication device is a DMA communication device for a computing-network fusion computing architecture as described in any one of claims 1 to 6.

8. A method for operating a DMA communication device for a computing-network fusion computing architecture according to any one of claims 1 to 6, characterized in that: Including a request conversion unit to perform DMA request conversion: including AXI transaction request generation, address information conversion, AXI Burst length calculation and write byte valid signal generation; when the network protocol processing component initiates a DMA transaction request, if it is a read request, the request conversion unit caches the read request to the read request FIFO and converts it into an AXI read request in sequence; if it is a write request, the request conversion unit directly converts it; then the request conversion unit sends the converted AXI read and write request to the processor, and performs address information conversion operation at the same time; when the address information is converted, the request conversion unit maps the DMA request address to an AXI physical address, and generates a write byte valid signal for the write request, the AXI interface data bit width is 256 bits, the offset of the DMA write request address is represented by ADDR[4:0], the request conversion unit judges and generates the corresponding byte valid signal based on whether the address is aligned: for the case of address alignment, if the total data length If the address is less than or equal to 32 bytes, a single-beat byte valid signal is generated according to the data length; if it exceeds 32 bytes, the first several beats transmitted in Burst mode are all valid, and the last beat generates the corresponding byte valid signal according to the remaining data length; and for the case of unaligned addresses, if the total data length is If the total data length is less than or equal to 32-ADDR[4:0], a single-byte valid signal is generated by combining the address offset and data length; If it exceeds 32-ADDR[4:0], the first beat generates a partial byte valid signal according to the address offset, the middle beat is fully valid, and the last beat generates a corresponding byte valid signal according to the remaining data length; when calculating the AXIBurst length, the request conversion unit calculates the AXI Burst length according to the data length of the DMA request, and its calculation function expression is: in, is the AXI Burst length, is the total data length, The offset of the DMA write request address. is the ceiling operator.

9. The working method of the DMA communication device for computing-network fusion computing architecture according to claim 8, characterized in that: It also includes a data conversion unit that performs DMA data conversion: after receiving the DMA data enable signal, the data conversion unit will cache the DMA write request data in the data FIFO and initiate an AXI write data request. At the same time, the data conversion unit will perform big-endian and small-endian format conversion, and use a counter to count the amount of data transmitted to ensure the accuracy of data transmission. If the length of the data to be transmitted is less than the data bus width, the data conversion unit sets the last beat data signal to be valid, notifying the processor that the data transmission is over; during the DMA read request processing, when the data conversion unit receives the AXI read response data enable signal, it converts the response data into big-endian and small-endian formats, and caches the converted DMA response data into the data FIFO. If the length of the data to be transmitted is less than the data bus width, the data conversion unit sets the last beat data signal to be valid, notifying the network protocol processing component that the data transmission is over.

10. The working method of the DMA communication device for computing-network fusion computing architecture according to claim 9, characterized in that: It also includes a state conversion unit that performs DMA state conversion: during the write request processing, after the write data request is answered, the state conversion unit waits for the data transmission to be completed, and then converts the AXI write request response into a DMA transaction processing state. During the read request processing, when the AXI read data feedback is completed, the AXI response request is parsed into a DMA transaction processing state, and the transaction processing state includes success or failure.

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