Back-contact solar cell and photovoltaic module

Abstract

The present application relates to the technical field of photovoltaics. Provided are a back-contact solar cell and a photovoltaic module. The back-contact solar cell comprises a silicon substrate, a P-type doped polysilicon layer and an N-type doped polysilicon layer, wherein the silicon substrate has a first side and a second side which are opposite each other; the P-type doped polysilicon layer is located in a first region of the first side of the silicon substrate; the N-type doped polysilicon layer is located in a second region of the first side of the silicon substrate, and the first region is different from the second region; and the ratio of the thickness of the P-type doped polysilicon layer to the thickness of the N-type doped polycrystalline silicon layer is 1-2. In the present application, the thickness of a P-type doped polysilicon layer is larger, such that a passivation effect of the P-type doped polycrystalline silicon layer can be improved. Corresponding thicknesses can respectively be set for the P-type doped polysilicon layer and an N-type doped polysilicon layer in respect of the doping concentrations, passivation effects, etc., that correspond thereto, such that not only can a good effect be achieved in terms of passivation effect and doping concentration, but also materials can be saved on.

Description

Back contact solar cell and photovoltaic module

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese application No. 2024101098208, filed on January 26, 2024, the contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a back-contact solar cell and a photovoltaic module. Background Art

[0004] The biggest feature of back contact (BC) solar cells is that the emitter and metal contact are both on the back of the cell, and there is no metal electrode blocking the front, so it has a higher short-circuit current Jsc. At the same time, the back can allow for wider metal grid lines to reduce the series resistance Rs, thereby increasing the fill factor FF. Moreover, this type of cell with no obstruction on the front not only has high conversion efficiency, but also looks more beautiful. At the same time, photovoltaic modules with full back electrodes are easier to assemble, so it has broad development prospects. For example, the interdigitated back contact (IBC) solar cell in the BC cell is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0005] However, in current back-contact solar cells, the coordination and optimization between the P-region and N-region structures has not been fully considered to reduce losses while ensuring the passivation effect, so the performance of current back-contact solar cells is poor. Summary of the Invention

[0006] The present application provides a back-contact solar cell and a photovoltaic module, aiming to solve the problem of poor performance of existing back-contact solar cells.

[0007] In a first aspect of the present application, a back-contact solar cell is provided, comprising:

[0008] a silicon substrate having opposing first and second sides;

[0009] A P-type doped polysilicon layer, the P-type doped polysilicon layer being located in a first region of a first side of the silicon substrate;

[0010] An N-type doped polysilicon layer, the N-type doped polysilicon layer being located in a second region of a first side of the silicon substrate, the first region being different from the second region;

[0011] Wherein, the ratio of the thickness of the P-type doped polysilicon layer to the thickness of the N-type doped polysilicon layer is 1 to 2.

[0012] In the embodiments of the present application, the thickness of the P-type doped polysilicon layer is relatively large, which can enhance the passivation effect of the P-type doped polysilicon layer while ensuring minimal metallization damage and low contact resistance. When the thickness of the P-type doped polysilicon layer is slightly greater than that of the N-type doped polysilicon layer, the P-type doped polysilicon layer and the N-type doped polysilicon layer can each be configured with corresponding thicknesses based on their corresponding doping concentrations, passivation effects, and the like. This not only achieves optimal passivation effects and doping concentrations, but also saves material.

[0013] Optionally, a surface of the P-type doped polysilicon layer close to the silicon substrate is farther away from the second side of the silicon substrate than a surface of the N-type doped polysilicon layer facing away from the silicon substrate; and a height difference between a surface of the P-type doped polysilicon layer close to the silicon substrate and a surface of the N-type doped polysilicon layer facing away from the silicon substrate is greater than 0 and less than or equal to 4.85 microns.

[0014] Alternatively, a surface of the P-type doped polysilicon layer close to the silicon substrate is flush with a surface of the N-type doped polysilicon layer away from the silicon substrate;

[0015] Or, the surface of the P-type doped polysilicon layer close to the silicon substrate is closer to the second side of the silicon substrate than the surface of the N-type doped polysilicon layer away from the silicon substrate; the height difference between the surface of the P-type doped polysilicon layer close to the silicon substrate and the surface of the N-type doped polysilicon layer away from the silicon substrate is greater than 0 and less than or equal to 0.3 microns.

[0016] Optionally, a surface of the P-type doped polysilicon layer close to the silicon substrate is farther away from the second side of the silicon substrate than a surface of the N-type doped polysilicon layer away from the silicon substrate; and a height difference between a surface of the P-type doped polysilicon layer close to the silicon substrate and a surface of the N-type doped polysilicon layer away from the silicon substrate is greater than 0 and less than or equal to 1.6 microns.

[0017] Optionally, the back contact solar cell further comprises:

[0018] A first dielectric layer is located between the P-type doped polysilicon layer and a first region on the first side of the silicon substrate.

[0019] Optionally, a surface of the first dielectric layer close to the silicon substrate is farther away from the second side of the silicon substrate than a surface of the N-type doped polysilicon layer facing away from the silicon substrate; a height difference between a surface of the first dielectric layer close to the silicon substrate and a surface of the N-type doped polysilicon layer facing away from the silicon substrate is greater than 0 and less than or equal to 4.85 microns;

[0020] Alternatively, a surface of the first dielectric layer close to the silicon substrate is flush with a surface of the N-type doped polysilicon layer away from the silicon substrate;

[0021] Alternatively, a surface of the first dielectric layer close to the silicon substrate is closer to the second side of the silicon substrate than a surface of the N-type doped polysilicon layer facing away from the silicon substrate; and a height difference between a surface of the first dielectric layer close to the silicon substrate and a surface of the N-type doped polysilicon layer facing away from the silicon substrate is greater than 0 and less than or equal to 0.3 microns.

[0022] Optionally, a surface of the first dielectric layer close to the silicon substrate is farther away from the second side of the silicon substrate than a surface of the N-type doped polysilicon layer facing away from the silicon substrate; a height difference between a surface of the first dielectric layer close to the silicon substrate and a surface of the N-type doped polysilicon layer facing away from the silicon substrate is greater than 0 and less than or equal to 1.6 microns.

[0023] Optionally, the silicon substrate has N-type doping; the P-type doped polysilicon layer includes multiple P-type collector regions; the N-type doped polysilicon layer includes multiple N-type collector regions, and wherein the N-type collector regions and the P-type collector regions are alternately distributed along the first direction and both extend along the second direction; the ratio of the width of one N-type collector region to the width of one P-type collector region is 0.5 to 1.5; the direction of the width of the N-type collector region and the direction of the width of the P-type collector region are both parallel to the first direction.

[0024] Optionally, the silicon substrate has N-type doping; the P-type doped polysilicon layer includes multiple P-type collector regions; the N-type doped polysilicon layer includes multiple N-type collector regions; and wherein the N-type collector regions and the P-type collector regions are alternately distributed along the first direction and both extend along the second direction; the ratio of the volume of one P-type collector region to the volume of one N-type collector region is 0.5 to 4.

[0025] Optionally, the silicon substrate has P-type doping; the P-type doped polysilicon layer includes multiple P-type collector regions; the N-type doped polysilicon layer includes multiple N-type collector regions; and wherein the N-type collector regions and the P-type collector regions are alternately distributed along the first direction and both extend along the second direction; the volume of one of the P-type collector regions is smaller than the volume of one of the N-type collector regions.

[0026] Optionally, the ratio of the volume of one of the P-type collector regions to the volume of one of the N-type collector regions is 0.1 to 0.8.

[0027] Optionally, the silicon substrate has P-type doping; the P-type doped polysilicon layer includes multiple P-type collector regions; the N-type doped polysilicon layer includes multiple N-type collector regions; and wherein the N-type collector regions and the P-type collector regions are alternately distributed along the first direction and both extend along the second direction; the width of one N-type collector region is greater than the width of one P-type collector region; the direction in which the width of the N-type collector region lies and the direction in which the width of the P-type collector region lies are both parallel to the first direction.

[0028] Optionally, the ratio of the width of one of the N-type collector regions to the width of one of the P-type collector regions is 2.5 to 8.

[0029] Optionally, the P-type doped polysilicon layer further includes a plurality of P-type bus regions; the N-type doped polysilicon layer further includes a plurality of N-type bus regions; and wherein the N-type bus regions and the P-type bus regions are alternately distributed along the second direction and both extend along the first direction; the first direction is different from the second direction and both are perpendicular to the direction of the thickness; each of the N-type collector regions located between an N-type bus region and an adjacent P-type bus region is connected to the N-type bus region; each of the P-type collector regions located between an N-type bus region and an adjacent P-type bus region is connected to the P-type bus region; the ratio of the length of a collector region to the width of a bus region is 22 to 64; the collector region is the P-type collector region or the N-type collector region; the bus region is the P-type bus region or the N-type bus region; the direction of the length of the collector region and the direction of the width of the bus region are both parallel to the second direction.

[0030] Optionally, the P-type doped polysilicon layer includes a plurality of P-type collector regions and a plurality of P-type bus regions;

[0031] The N-type doped polysilicon layer includes a plurality of N-type collector regions and a plurality of N-type bus regions;

[0032] The N-type collector region and the P-type collector region are alternately distributed along a first direction and both extend along a second direction; the N-type bus region and the P-type bus region are alternately distributed along the second direction and both extend along the first direction; the first direction is different from the second direction and both are perpendicular to the direction of the thickness;

[0033] Each of the N-type collector regions located between an N-type bus region and an adjacent P-type bus region is connected to the N-type bus region;

[0034] Each of the P-type collector regions located between an N-type bus region and an adjacent P-type bus region is connected to the P-type bus region;

[0035] The ratio of the length of a collector region to the width of a bus region is 22 to 64; the collector region is the P-type collector region or the N-type collector region; the bus region is the P-type bus region or the N-type bus region; the direction of the length of the collector region and the direction of the width of the bus region are both parallel to the second direction.

[0036] There is a first gap between the adjacent N-type collector region and the adjacent P-type collector region;

[0037] There is a second gap between the collector area and the special-shaped bus area;

[0038] A size of the second gap in the second direction is greater than or equal to a size of the first gap in the first direction.

[0039] Optionally, a ratio of a size of the second gap in the second direction to a size of the first gap in the first direction is 1 to 4.

[0040] Optionally, the volume of one of the P-type bus regions is greater than or equal to the volume of one of the N-type bus regions.

[0041] Optionally, the ratio of the volume of one of the P-type bus regions to the volume of one of the N-type bus regions is 1 to 2.

[0042] Optionally, the silicon substrate has N-type doping;

[0043] The ratio of the width of one N-type collector region to the width of one P-type collector region is 0.5 to 1.5; the direction of the width of the N-type collector region and the direction of the width of the P-type collector region are both parallel to the first direction.

[0044] Optionally, a ratio of a width of the N-type collector region to a width of the P-type collector region is 0.85 to 1.2.

[0045] Optionally, the silicon substrate has N-type doping, and a ratio of a volume of the P-type collector region to a volume of the N-type collector region is 0.5 to 4.

[0046] Optionally, the ratio of the volume of one of the P-type collector regions to the volume of one of the N-type collector regions is 0.8 to 2.4.

[0047] Optionally, the silicon substrate has P-type doping, and the volume of one of the P-type collector regions is smaller than the volume of one of the N-type collector regions.

[0048] Optionally, the ratio of the volume of one of the P-type collector regions to the volume of one of the N-type collector regions is 0.1 to 0.8.

[0049] Optionally, the silicon substrate has P-type doping, the width of one N-type collector region is greater than the width of one P-type collector region; the direction of the width of the N-type collector region and the direction of the width of the P-type collector region are both parallel to the first direction.

[0050] Optionally, the ratio of the width of one of the N-type collector regions to the width of one of the P-type collector regions is 2.5 to 8.

[0051] Optionally, a ratio of a width of the P-type bus region to a width of the N-type bus region is 0.95 to 1.05;

[0052] Alternatively, a ratio of a length of the P-type collector region to a length of the N-type collector region is 0.95 to 1.05.

[0053] Optionally, the back contact solar cell further comprises:

[0054] A P-type collector gate line, the P-type collector gate line is located on the P-type collector region;

[0055] A P-type bus gate line, the P-type bus gate line being located on the P-type bus region;

[0056] An N-type collector gate line, the N-type collector gate line is located on the N-type collector region;

[0057] an N-type bus gate line, the N-type bus gate line being located on the N-type bus region;

[0058] Each of the N-type collector gate lines located between an N-type bus gate line and an adjacent P-type bus gate line is electrically connected to the N-type bus gate line, and each of the P-type collector gate lines located between an N-type bus gate line and an adjacent P-type bus gate line is electrically connected to the P-type bus gate line.

[0059] Optionally, the ratio of the length of a collector gate line to the width of a bus gate line is 22 to 64; the collector gate line is the P-type collector gate line or the N-type collector gate line; the bus gate line is the P-type bus gate line or the N-type bus gate line; the direction of the length of the collector gate line and the direction of the width of the bus gate line are both parallel to the second direction.

[0060] In a second aspect of the present application, a photovoltaic module is provided, comprising one or more back-contact solar cells as described above.

[0061] The above-mentioned back-contact solar cells and photovoltaic modules have the same or similar beneficial effects, and to avoid repetition, they are not described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0063] FIG1 shows a front view schematic structural diagram of a back-contact solar cell in an embodiment of the present application;

[0064] FIG2 shows a schematic top view of a back-contact solar cell according to an embodiment of the present application;

[0065] FIG3 shows a schematic diagram of a partial top view of a back-contact solar cell according to an embodiment of the present application;

[0066] FIG4 shows a schematic diagram of a first partial front view structure of a back-contact solar cell in an embodiment of the present application;

[0067] FIG5 shows a schematic diagram of a second partial front view structure of a back contact solar cell in an embodiment of the present application;

[0068] FIG6 shows a third partial front view structural diagram of a back-contact solar cell in an embodiment of the present application;

[0069] FIG7 shows a schematic diagram of a fourth partial front view structure of a back-contact solar cell in an embodiment of the present application.

[0070] Explanation of the accompanying drawings: 1-silicon substrate, 11-texture structure, 2-P-type doped polysilicon layer, 21-P-type collector region, 22-P-type bus region, 3-N-type doped polysilicon layer, 31-N-type collector region, 32-N-type bus region, 4-positive electrode, 41-P-type collector grid line, 42-P-type bus grid line, 5-negative electrode, 51-N-type collector grid line, 52-N-type bus grid line, 6-front passivation anti-reflection film layer, 7-back composite passivation film layer, 8-first dielectric layer, 9-second dielectric layer. d1-thickness of the P-type doped polysilicon layer 2, d2-thickness of the N-type doped polysilicon layer 3, d3-length of a P-type collector region 21, d4-width of an N-type bus region 32, d5-width of a P-type bus region 22, d6-dimension of the first gap in the first direction L3, d7-dimension of the second gap in the second direction L4, d8-width of an N-type collector region 31, d9-width of a P-type collector region 21. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0072] In existing technologies, the main reason for poor passivation performance in back-contact solar cells is that, due to process limitations and other factors, it is difficult to prepare a high-concentration P-type doped polysilicon layer. In existing technologies, the thickness of the P-type doped polysilicon layer in back-contact solar cells is relatively small, resulting in excessive metallization damage or excessive contact resistance. For example, boron has a relatively low solid solubility, making high doping concentrations difficult to achieve. An overly thin polysilicon layer can increase metallization damage in the P region, reducing the ablation capability of the metal slurry. This, in turn, can lead to excessive metal-silicon contact resistance, resulting in efficiency loss.

[0073] Figure 1 shows a schematic diagram of the front view structure of a back-contact solar cell in an embodiment of the present application. Figure 2 shows a schematic diagram of the top view structure of a back-contact solar cell in an embodiment of the present application. Figure 3 shows a schematic diagram of a partial top view structure of a back-contact solar cell in an embodiment of the present application. Figure 4 shows a schematic diagram of the first partial front view structure of the back-contact solar cell in an embodiment of the present application. Figure 5 shows a schematic diagram of the second partial front view structure of the back-contact solar cell in an embodiment of the present application. Figure 6 shows a schematic diagram of the third partial front view structure of the back-contact solar cell in an embodiment of the present application. Figure 7 shows a schematic diagram of the fourth partial front view structure of the back-contact solar cell in an embodiment of the present application. Figure 3 is a schematic diagram of the portion between the two special-shaped busbar lines in Figure 2. It should be noted that the dimension markings in Figures 1 to 3 are only schematic dimensions and do not represent the actual relative size relationship of the dimensions.

[0074] The present application provides a back-contact solar cell. Referring to FIG1 , the back-contact solar cell may include a silicon substrate 1 having a first side and a second side opposite to each other, where the first side is a side close to an electrode. For example, the first side of the silicon substrate 1 in FIG1 is a lower side, and the second side is an upper side.

[0075] In Figure 1, the dashed lines L1 and L2 are used only to distinguish the first and second regions and do not actually exist in the back-contact solar cell. Referring to Figure 1 , the back-contact solar cell also includes a P-type doped polysilicon layer 2 located in a first region on the first side of the silicon substrate 1. On the first side of the silicon substrate 1, the area to the left of the dashed line L1 is the first region, and the area to the right of the dashed line L2 is the second region. The P-type doped polysilicon layer 2 is located in the area to the left of the dashed line L1 on the first side of the silicon substrate 1.

[0076] The N-type doped polysilicon layer 3 is located in the second region of the first side of the silicon substrate 1. The first region is different from the second region. As shown in FIG1 , the N-type doped polysilicon layer 3 is located in the region to the right of the dotted line L2 on the first side of the silicon substrate 1.

[0077] The ratio of the thickness d1 of the P-type doped polysilicon layer 2 to the thickness d2 of the N-type doped polysilicon layer 3 is 1 to 2. That is, the thickness d1 of the P-type doped polysilicon layer 2 is equal to the thickness d2 of the N-type doped polysilicon layer 3, that is, the ratio of the two is equal to 1; or, the thickness d1 of the P-type doped polysilicon layer 2 is slightly larger than the thickness d2 of the N-type doped polysilicon layer 3, that is, the ratio of the two is greater than 1 and less than or equal to 2, and can be any value in the set (1, 2]. When the thickness d1 of the P-type doped polysilicon layer 2 is larger, the passivation effect of the P-type doped polysilicon layer 2 can be improved, while ensuring that the metallization damage and the contact resistance are small. When the thickness d1 of the P-type doped polysilicon layer 2 is slightly larger than the thickness d2 of the N-type doped polysilicon layer 3, the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 can each be set to a corresponding thickness according to their corresponding doping concentrations, passivation effects, etc., which not only can achieve better passivation effects and doping concentrations, but also can save materials.

[0078] For example, the ratio of the thickness d1 of the P-type doped polysilicon layer 2 to the thickness d2 of the N-type doped polysilicon layer 3 can be 1, or 1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.

[0079] It should be noted that the directions of the thicknesses mentioned throughout the text are consistent with the stacking direction of the silicon substrate 1 and the P-type doped polysilicon layer 2 .

[0080] Optionally, when the ratio of d1 to d2 is any value between 1 and 2, the thickness d1 of the P-type doped polysilicon layer 2 is between 100 nm (nanometers) and 500 nm, and the thickness d2 of the N-type doped polysilicon layer 3 can be between 50 nm and 300 nm. When d1 and d2 are within the above ranges, on the one hand, it is easy to achieve good doping effects for both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, and on the other hand, both layers have good passivation effects, while ensuring minimal metallization damage and low contact resistance, and at relatively low cost.

[0081] For example, the thickness d1 of the P-type doped polysilicon layer 2 can be 100nm, or 103nm, or 130nm, or 143nm, or 172nm, or 190nm, or 205nm, or 250nm, or 283nm, or 300nm, or 301nm, or 342nm, or 367nm, or 370nm, or 420nm, or 456nm, or 482nm, or 500nm. For example, the thickness d2 of the N-type doped polysilicon layer 3 can be 50nm, or 52nm, or 60nm, or 66.7nm, or 73nm, or 81nm, or 90nm, or 92nm, or 100nm, or 112nm, or 133nm, or 144nm, or 175nm, or 190nm, or 211nm, or 243nm, or 270nm, or 282nm, or 296nm, or 300nm.

[0082] Optionally, the P-type doped polysilicon layer 2 includes a plurality of P-type collector regions 21, and the N-type doped polysilicon layer 3 includes a plurality of N-type collector regions 31. The up-down direction indicated by the dotted line L3 is the first direction, and the left-right direction indicated by the dotted line L4 is the second direction. The N-type collector regions 31 and the P-type collector regions 21 are alternately distributed along the first direction L3 and both extend along the second direction L4. That is, the N-type collector regions 31 and the P-type collector regions 21 both extend along the second direction L4. Simultaneously, in the first direction L3, an N-type collector region 31, followed by a P-type collector region 21, then another N-type collector region 31, and then another P-type collector region 21 are alternately distributed. The first direction L3 is different from the second direction L4, and both are perpendicular to the thickness direction. The angle between the first direction L3 and the second direction L4 is not specifically limited; for example, the first direction L3 and the second direction L4 are perpendicular.

[0083] Optionally, the ratio of the length d3 of a P-type collector region 21 to the length of an N-type collector region 31 is 0.95 to 1.05, and the length d3 of a P-type collector region 21 is equal to or approximately equal to the length of an N-type collector region 31, which makes the process simple, easy to prepare, and has a good effect on carrier convergence.

[0084] For example, the ratio of the length d3 of a P-type collector region 21 to the length of an N-type collector region 31 can be 0.95, or 0.951, or 0.962, or 0.985, or 0.99, or 0.993, or 1.0, or 1.01, or 1.017, or 1.02, or 1.028, or 1.03, or 1.04, or 1.047, or 1.05.

[0085] Optionally, the silicon substrate 1 has N-type doping, and the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 is 0.5 to 1.5. Here, the direction in which the width d8 of the N-type collector region 31 and the direction in which the width d9 of the P-type collector region 21 are located are both parallel to the first direction L3. Specifically, the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 is 0.5 to 1.5. This setting ensures a reasonable junction area ratio, ensures better current, balances the passivation of the P and N regions, ensures better battery start-up voltage, and thus ensures a good collection effect on both holes and electrons, thereby improving the efficiency of the battery.

[0086] For example, the silicon substrate 1 has N-type doping, and the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 can be 0.5, or 0.53, or 0.61, or 0.67, or 0.7, or 0.76, or 0.79, or 0.85, or 0.863, or 0.87, or 0.89, or 0.9, or 0.93, or 0.97, or 1.0, or 1.09, or 1.15, or 1.23, or 1.3, or 1.46, or 1.5.

[0087] Optionally, the silicon substrate 1 has N-type doping, and the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 is 0.85 to 1.2. Here, the direction of the width d8 of the N-type collector region 31 and the direction of the width d9 of the P-type collector region 21 are both parallel to the first direction L3. Specifically, the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 is 0.85 to 1.2. With this setting, a reasonable junction area ratio can be guaranteed, the current is better, the passivation of the P and N regions is balanced, and the battery start-up voltage is better, thereby ensuring a good collection effect on both holes and electrons, thereby improving the efficiency of the battery.

[0088] For example, the silicon substrate 1 has N-type doping, and the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 can be 0.85, or 0.859, or 0.86, or 0.862, or 0.868, or 0.87, or 0.876, or 0.88, or 0.896, or 0.9, or 0.92, or 0.935, or 0.961, or 0.973, or 0.98, or 1.0, or 1.06, or 1.08, or 1.139, or 1.15, or 1.199, or 1.2.

[0089] Optionally, the silicon substrate 1 has N-type doping, the width d8 of an N-type collector region 31 is 380μm to 500μm, and the width d9 of a P-type collector region 21 is 300μm to 450μm. This setting can ensure a reasonable junction area ratio, ensure better current, balance the passivation of the P and N regions, and ensure better battery start-up voltage, thereby ensuring a good collection effect on both holes and electrons, thereby improving the efficiency of the battery.

[0090] For example, the silicon substrate 1 has N-type doping, and the width d8 of an N-type collector region 31 can be 380μm, or 387μm, or 394.3μm, or 401μm, or 406μm, or 410μm, or 427μm, or 430μm, or 440μm, or 446.5μm, or 453.1μm, or 466μm, or 472μm, or 479μm, or 483μm, or 493μm, or 500μm. For example, the silicon substrate 1 has N-type doping, and the width d9 of a P-type collector region 21 can be 300μm, or 301μm, or 323μm, or 352.1μm, or 363μm, or 369μm, or 375μm, or 379.2μm, or 380μm, or 390μm, or 395.4μm, or 413μm, or 415.1μm, or 420.3μm, or 427.3μm, or 435μm, or 440μm, or 443μm, or 450μm.

[0091] Optionally, the silicon substrate 1 has N-type doping, and the ratio of the volume of a P-type collector region 21 to the volume of an N-type collector region 31 is 0.5 to 4. This setting can ensure a reasonable junction area ratio, ensure better current, and balance the passivation of the P and N regions, thereby improving the passivation effect and ensuring a better battery start-up voltage. At the same time, it ensures that the metallization damage is small and the contact resistance is small, which can ensure a good collection effect for both holes and electrons, thereby improving the efficiency of the battery.

[0092] For example, the silicon substrate 1 has N-type doping, and the ratio of the volume of a P-type collector region 21 to the volume of an N-type collector region 31 can be 0.5, or 0.52, or 0.57, or 0.61, or 0.68, or 0.7, or 0.79, or 0.85, or 0.97, or 0.985, or 1.07, or 1.13, or 1.25, or 1.37, or 1.45, or 1.57, or 1.61, or 1.72, or 1.83, or 1.93, or 2.11, or 2.27, or 2.4, or 2.77, or 2.885, or 2.97, or 3, or 3.1, or 3.37, or 3.45, or 3.57, or 3.61, or 3.72, or 3.83, or 3.93, or 4.

[0093] Optionally, the silicon substrate 1 has N-type doping, and the ratio of the volume of a P-type collector region 21 to the volume of an N-type collector region 31 is 0.8 to 2.4. This setting can ensure a reasonable junction area ratio, ensure better current, and balance the passivation of the P and N regions, thereby improving the passivation effect and ensuring a better battery start-up voltage. At the same time, it ensures that the metallization damage is small and the contact resistance is small, which can ensure a good collection effect for both holes and electrons, thereby improving the efficiency of the battery.

[0094] For example, the silicon substrate 1 has N-type doping, and the ratio of the volume of a P-type collector region 21 to the volume of an N-type collector region 31 can be 0.8, or 0.82, or 0.87, or 0.91, or 0.93, or 0.975, or 1.01, or 1.16, or 1.25, or 1.35, or 1.45, or 1.53, or 1.64, or 1.72, or 1.83, or 1.91, or 2.11, or 2.29, or 2.4.

[0095] Optionally, the silicon substrate 1 has P-type doping, and the volume of a P-type collector region 21 is smaller than the volume of an N-type collector region 31. This arrangement ensures a reasonable junction area ratio, better current, improved passivation effect, better battery start-up voltage, and less metallization damage and contact resistance, thereby ensuring a good collection effect for both holes and electrons and improving battery efficiency.

[0096] Optionally, the silicon substrate 1 has P-type doping, and the ratio of the volume of a P-type collector region 21 to the volume of an N-type collector region 31 is 0.1 to 0.8. In this case, the electrons collected by the N-type collector region 31 are minority carriers, and the ratio of the volumes of the two is appropriate, which can ensure a good collection effect for both holes and electrons, and can improve the efficiency of the battery.

[0097] For example, the silicon substrate 1 has P-type doping, and the ratio of the volume of a P-type collector region 21 to the volume of an N-type collector region 31 can be 0.1, or 0.17, or 0.27, or 0.31, or 0.38, or 0.41, or 0.43, or 0.45, or 0.5, or 0.57, or 0.63, or 0.67, or 0.69, or 0.72, or 0.77, or 0.79, or 0.8.

[0098] Optionally, the silicon substrate 1 has a P-type doping structure, and the width d8 of an N-type collector region 31 is greater than the width d9 of a P-type collector region 21. In this case, the electrons collected by the N-type collector region 31 are minority carriers. The larger width d8 of the N-type collector region 31 facilitates the collection of minority carriers, thereby improving the efficiency of the back-contact solar cell. It should be noted that the direction of the width d8 of the N-type collector region 31 and the direction of the width d9 of the P-type collector region 21 are both parallel to the first direction L3.

[0099] Optionally, the silicon substrate 1 has P-type doping, and the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 is 2.5 to 8. The ratio is set relatively appropriately. With this setting, a reasonable junction area ratio can be guaranteed, the current can be better, and the passivation of the P and N regions can be balanced, thereby improving the passivation effect, ensuring a better battery start-up voltage, ensuring a good collection effect for both holes and electrons, and improving the efficiency of the battery.

[0100] For example, the silicon substrate 1 has P-type doping, and the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 can be 2.5, or 2.69, or 2.72, or 2.89, or 2.93, or 3.1, or 3.3, or 3.89, or 4.0, or 4.56, or 4.99, or 5.15, or 5.25, or 5.5, or 6.64, or 6.87, or 7.32, or 7.59, or 8.

[0101] Optionally, the silicon substrate 1 has P-type doping, the width d8 of an N-type collector region 31 is 500μm to 800μm, and the width d9 of a P-type collector region 21 is 100μm to 200μm. This setting can ensure a reasonable junction area ratio, ensure better current, and balance the passivation of the P and N regions, thereby improving the passivation effect, ensuring a better battery start-up voltage, ensuring a good collection effect for both holes and electrons, and improving the efficiency of the battery.

[0102] For example, the silicon substrate 1 has P-type doping, and the width d8 of an N-type collector region 31 can be 500μm, or 522μm, or 531.3μm, or 541.3μm, or 588μm, or 601μm, or 623μm, or 647μm, or 650μm, or 666μm, or 683.1μm, or 672μm, or 694μm, or 713μm, or 756μm, or 783.2μm, or 800μm. For example, the silicon substrate 1 has P-type doping, and the width d9 of a P-type collector region 21 can be 100μm, or 101μm, or 111.3μm, or 125μm, or 133μm, or 146μm, or 150μm, or 158.7μm, or 161μm, or 169μm, or 173μm, or 180.3μm, or 187.7μm, or 191μm, or 193μm, or 199.7μm, or 200μm.

[0103] Optionally, referring to Figures 2 and 3, the P-type doped polysilicon layer 2 includes a plurality of P-type collector regions 21 and a plurality of P-type bus regions 22. The N-type doped polysilicon layer 3 includes a plurality of N-type collector regions 31 and a plurality of N-type bus regions 32. In Figures 2 and 3, the up-down direction indicated by the dotted line L3 is the first direction, and the left-right direction indicated by the dotted line L4 is the second direction. The N-type collector regions 31 and the P-type collector regions 21 are alternately distributed along the first direction L3, and both extend along the second direction L4. That is, the N-type collector regions 31 and the P-type collector regions 21 both extend along the second direction L4. At the same time, in the first direction L3, an N-type collector region 31, followed by a P-type collector region 21, then an N-type collector region 31, and then another P-type collector region 21 are alternately distributed. As shown in Figure 2, the length of a P-type collector region 21 is d3. Typically, the length d3 of a P-type collector region 21 is equal to or approximately equal to the length of an N-type collector region 31. In the presence of a bus region, the P-type bus region 22 is positioned approximately at the center of the corresponding P-type collector region 21 along the first direction L3, and the N-type bus region 32 is positioned approximately at the center of the corresponding N-type collector region 31 along the first direction L3. Typically, the projections of adjacent N-type and P-type collector regions 31 in the first direction L3 at least partially overlap. In addition, the length of a P-type bus region 22 is equal to or approximately equal to the length of an N-type bus region 32, and the projections of adjacent P-type and N-type bus regions 22 and 32 in the second direction L4 at least partially overlap or approximately overlap. It should be noted that the first direction L3 is different from the second direction L4, and both are perpendicular to the thickness direction. There is no specific limitation on the included angle between the first direction L3 and the second direction L4. For example, in FIG. 2 and FIG. 3 , the first direction L3 and the second direction L4 are perpendicular.

[0104] The N-type bus regions 32 and the P-type bus regions 22 are alternately distributed along the second direction L4 and both extend along the first direction L3. That is, the N-type bus regions 32 and the P-type bus regions 22 both extend along the first direction L3. Meanwhile, in the second direction L4, an N-type bus region 32 is alternately distributed, followed by a P-type bus region 22, then another N-type bus region 32, and then another P-type bus region 22.

[0105] 3 , each N-type collector region 31 located between an N-type bus region 32 and an adjacent P-type bus region 22 is connected to the N-type bus region 32, and each P-type collector region 21 located between an N-type bus region 32 and an adjacent P-type bus region 22 is connected to the P-type bus region 22. The back-contact solar cell formed in this way is an IBC solar cell.

[0106] The P-type collector region 21 and the N-type collector region 31 are collectively referred to as collector regions. The N-type bus region 32 and the P-type bus region 22 are collectively referred to as bus regions. The ratio of the length of a collector region to the width of a bus region is 22 to 64. The direction of the length of the collector region and the direction of the width of the bus region are both parallel to the second direction L4. Typically, the length d3 of a P-type collector region 21 is equal to or approximately equal to the length of an N-type collector region 31, and the width d4 of an N-type bus region 32 is equal to or approximately equal to the width d5 ​​of a P-type bus region 22. Therefore, the ratio of the length of a collector region to the width of a bus region is 22 to 64, corresponding to four cases: first, the ratio of the length d3 of a P-type collector region 21 to the width d5 ​​of a P-type bus region 22 is 22 to 64; second, the ratio of the length d3 of an N-type collector region 31 to the width d5 ​​of a P-type bus region 22 is 22 to 64; third, the ratio of the length d3 of a P-type collector region 21 to the width d4 of an N-type bus region 32 is 22 to 64; and fourth, the ratio of the length of an N-type collector region 31 to the width d4 of an N-type bus region 32 is 22 to 64. A ratio that is too small for the length of a collector region to the width of a bus region will result in a loss of battery efficiency, while a ratio that is too large may increase the battery series resistance. The ratio of the length of a collector region to the width of a bus region is 22 to 64, which is a relatively appropriate ratio that not only ensures better battery performance but also avoids material waste.

[0107] For example, the ratio of the length of a collector region to the width of a bus region may be 22, or 22.4, or 27, or 29, or 31.2, or 33, or 36, or 38, or 40, or 45.4, or 48.7, or 51.2, or 53.7, or 57.3, or 60, or 62.4, or 64.

[0108] Optionally, the ratio of the width d5 ​​of a P-type bus region 22 to the width d4 of an N-type bus region 32 is 0.95 to 1.05, and the width d5 ​​of a P-type bus region 22 is equal to or approximately equal to the width d4 of an N-type bus region 32, which makes the process simple, easy to prepare, and has a good effect on carrier convergence.

[0109] For example, the ratio of the width d5 ​​of a P-type bus region 22 to the width d4 of an N-type bus region 32 can be 0.95, or 0.96, or 0.968, or 0.977, or 0.986, or 0.99, or 0.993, or 1.0, or 1.01, or 1.016, or 1.02, or 1.03, or 1.04, or 1.043, or 1.05.

[0110] Optionally, the width d5 ​​of a P-type bus region 22 is 300 μm (micrometers) to 800 μm, and the width d4 of an N-type bus region 32 is 300 μm to 800 μm. Both have good carrier convergence effects and avoid material waste.

[0111] For example, the width d5 ​​of a P-type bus region 22 can be 300μm, or 312μm, or 343μm, or 350μm, or 362μm, or 391μm, or 410μm, or 442μm, or 467μm, or 492μm, or 500μm, or 532μm, or 550μm, or 589.2μm, or 632.3μm, or 662μm, or 711μm, or 753.2μm, or 763μm, or 788μm, or 800μm. For example, the width d4 of an N-type bus region 32 may be 300 μm, or 333 μm, or 351 μm, or 360.1 μm, or 374 μm, or 391 μm, or 423 μm, or 451 μm, or 499 μm, or 513 μm, or 531 μm, or 550 μm, or 591 μm, or 625 μm, or 678.1 μm, or 743 μm, or 762.1 μm, or 777 μm, or 800 μm.

[0112] Optionally, the volume of a P-type bus region 22 is greater than or equal to the volume of an N-type bus region 32. The larger volume of the P-type bus region 22 can improve the passivation effect of the P-type bus region 22 while ensuring that the metallization damage is small and the contact resistance is small.

[0113] Optionally, the ratio of the volume of one P-type bus region 22 to the volume of one N-type bus region 32 is 1 to 2. Specifically, the length of one P-type bus region 22 is substantially equal to the length of one N-type bus region 32, the width d5 ​​of one P-type bus region 22 is substantially equal to the width d4 of one N-type bus region 32, and the ratio of the thickness of one P-type bus region 22 to the thickness of one N-type bus region 32 is 1 to 2. Therefore, the ratio of the volume of one P-type bus region 22 to the volume of one N-type bus region 32 is 1 to 2. The two volumes are equal, that is, the ratio between the two is equal to 1; or, the volume of a P-type bus region 22 is slightly larger than the volume of an N-type bus region 32, that is, the ratio between the two is greater than 1 and less than or equal to 2, and can be any value in the set (1, 2]. When the volume of the P-type bus region 22 is larger, the passivation effect of the P-type bus region 22 can be improved, while ensuring that the metallization damage and the contact resistance are small. When the volume of the P-type bus region 22 is slightly larger than that of the N-type bus region 32, the P-type bus region 22 and the N-type bus region 32 can each be set with corresponding thicknesses according to their corresponding doping concentrations, passivation effects, etc., which not only can achieve better passivation effects and doping concentrations, but also can save materials.

[0114] For example, the ratio of the volume of a P-type bus region 22 to the volume of an N-type bus region 32 can be 1, or 1.01, or 1.1, or 1.21, or 1.32, or 1.37, or 1.44, or 1.46, or 1.5, or 1.58, or 1.63, or 1.71, or 1.79, or 1.8, or 1.86, or 1.92, or 1.96, or 2.

[0115] Optionally, a first gap exists between adjacent N-type collector regions 31 and P-type collector regions 21, and the dimension of the first gap in the first direction L3 is d6. A second gap exists between the collector region and the heterogeneous bus region, and the dimension of the second gap in the second direction L4 is d7. The P-type collector region 21 and the N-type collector region 31 are collectively referred to as collector regions. The N-type bus region 32 and the P-type bus region 22 are collectively referred to as bus regions. That is, a second gap exists between the P-type collector region 21 and the N-type bus region 32. A second gap exists between the N-type collector region 31 and the P-type bus region 22. The dimension d7 of a second gap in the second direction L4 is greater than or equal to the dimension d6 of a first gap in the first direction L3. Specifically, under normal circumstances, the current passing through the bus area is large, and the dimension d7 of the second gap between the collector area and the heterotype bus area in the second direction L4 is greater than or equal to the dimension d6 of the first gap between the adjacent N-type collector area 31 and the P-type collector area 21 in the first direction L3, so that the probability of short circuit is lower and a higher yield and reliability can be maintained.

[0116] Optionally, the ratio of the dimension d7 of a second gap in the second direction L4 to the dimension d6 of a first gap in the first direction L3 is 1 to 4. A ratio range that is too large may result in space waste, and a ratio range that is too small may result in a short circuit risk. A ratio range between 1 and 4 is appropriate, so that not only the probability of short circuit is low, but also there is basically no space waste.

[0117] For example, the ratio of the dimension d7 of the second gap in the second direction L4 to the dimension d6 of the first gap in the first direction L3 can be 1, or the ratio of the two can be any value in the set (1, 4]. For example, the ratio of the two can be 1.01, or 1.05, or 1.09, or 1.095, or 1.1, or 1.12, or 1.143, or 1.16, or 1.17, or 1.19, or 1.20, or 1.24, or 1.28, or 1.3, or 1.32, or 1.329, or 1.34, or 1.45, or 1.62, or 1.95, or 2.1, or 2.32, or 2.66, or 2.93, or 3.16, or 3.57, or 3.71, or 3.89, or 4.

[0118] Optionally, a dimension d6 of a first gap in the first direction L3 is 50 μm to 150 μm, and a dimension d7 of a second gap in the second direction L4 is 50 μm to 200 μm. The two gaps are arranged in the manner described above, which not only reduces the probability of short circuit, but also eliminates basically no space waste.

[0119] For example, the dimension d6 of a first gap in the first direction L3 may be 50 μm, or 58 μm, or 69 μm, or 72 μm, or 78 μm, or 81 μm, or 86 μm, or 93 μm, or 97.2 μm, or 99 μm, or 100 μm, or 100.3 μm, or 102 μm, or 105.7 μm, or 109.2 μm, or 111 μm, or 117 μm, or 123 μm, or 130 μm, or 142.2 μm, or 147.3 μm, or 150 μm. For example, the dimension d7 of a second gap in the second direction L4 may be 50 μm, or 53.2 μm, or 58 μm, or 61 μm, or 63 μm, or 74 μm, or 75.2 μm, or 80 μm, or 83 μm, or 86 μm, or 99 μm, or 101 μm, or 109 μm, or 113 μm, or 118 μm, or 120.3 μm, or 125 μm, or 131 μm, or 137 μm, or 143 μm, or 155 μm, or 161 μm, or 177 μm, or 185 μm, or 200 μm.

[0120] Optionally, the silicon substrate 1 has an N-type doping function, and the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 is 0.5 to 1.5. Here, the direction of the width d8 of the N-type collector region 31 and the direction of the width d9 of the P-type collector region 21 are both parallel to the first direction L3. The specific ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 or the specific values ​​of the collector region widths are described above.

[0121] Optionally, the silicon substrate 1 has N-type doping, and the ratio of the volume of one P-type collector region 21 to the volume of one N-type collector region 31 is 0.5 to 4. The specific ratio of the volume of one P-type collector region 21 to the volume of one N-type collector region 31 is described in detail above.

[0122] Optionally, the silicon substrate 1 has P-type doping, and the volume of a P-type collector region 21 is smaller than the volume of an N-type collector region 31 .

[0123] Optionally, the silicon substrate 1 has a P-type doping, and the ratio of the volume of a P-type collector region 21 to the volume of an N-type collector region 31 is 0.1 to 0.8. The specific ratio of the volume of a P-type collector region 21 to the volume of an N-type collector region 31 is described in detail above.

[0124] Optionally, the silicon substrate 1 has P-type doping, and a width d8 of an N-type collector region 31 is greater than a width d9 of a P-type collector region 21 .

[0125] Optionally, the silicon substrate 1 has a P-type doping, and the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 is 2.5 to 8. The specific ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 or the specific numerical value of the collector region width is described above.

[0126] Optionally, referring to Figures 2 and 3, the back-contact solar cell further includes a P-type collector grid line 41 and a P-type bus grid line 42, wherein the P-type collector grid line 41 is located on the P-type collector region 21, the P-type bus grid line 42 is located on the P-type bus region 22, the P-type collector grid line 41 is used to collect holes in the P-type collector region 21, and the P-type bus grid line 42 and the P-type collector grid line 41 constitute a positive electrode 4. The back-contact solar cell further includes an N-type collector grid line 51 and an N-type bus grid line 52, wherein the N-type collector grid line 51 is located on the N-type collector region 31, the N-type bus grid line 52 is located on the N-type bus region 32, the N-type collector grid line 51 is used to collect electrons in the N-type collector region 31, and the N-type bus grid line 52 and the N-type collector grid line 51 constitute a negative electrode 5. Each N-type collector grid line 51 located between an N-type bus grid line 52 and an adjacent P-type bus grid line 42 is electrically connected to the N-type bus grid line 52. The N-type bus grid line 52 is used to conduct electrons on each N-type collector grid line 51 electrically connected thereto. Each P-type collector grid line 41 is electrically connected to the P-type bus grid line 42. The P-type bus grid line 42 is used to conduct holes on each P-type collector grid line 41 electrically connected thereto. The back-contact solar cell is an IBC solar cell, which not only has a high conversion efficiency but also looks more beautiful. At the same time, it is easier to assemble to form a photovoltaic module.

[0127] The P-type collector grid line 41 and the N-type collector grid line 51 are collectively referred to as collector grid lines. The N-type bus grid line 52 and the P-type bus grid line 42 are collectively referred to as bus grid lines. The ratio of the length of a collector grid line to the width of a bus grid line is 22 to 64. The direction in which the length of the collector grid line and the direction in which the width of the bus grid line are located are both parallel to the second direction L4. Normally, the length of a P-type collector grid line 41 is equal to or approximately equal to the length of an N-type collector grid line 51, and the width of an N-type bus grid line 52 is equal to or approximately equal to the width of a P-type bus grid line 42. Therefore, the ratio of the length of a collector gate line to the width of a bus gate line is 22 to 64, corresponding to four cases: first, the ratio of the length of a P-type collector gate line 41 to the width of a P-type bus gate line 42 is 22 to 64; second, the ratio of the length of an N-type collector gate line 51 to the width of a P-type bus gate line 42 is 22 to 64; third, the ratio of the length of a P-type collector gate line 41 to the width of an N-type bus gate line 52 is 22 to 64; and fourth, the ratio of the length of an N-type collector gate line 51 to the width of an N-type bus gate line 52 is 22 to 64. A ratio of too small a collector gate line length to a bus gate line width will result in a loss of battery efficiency, while a ratio that is too large may increase the series resistance. The ratio of the length of a collector gate line to the width of a bus gate line is 22 to 64, which is a relatively appropriate ratio that not only ensures better battery performance but also avoids material waste.

[0128] For example, the ratio of the length of a collector grid line to the width of a bus grid line can be 22, or 23.1, or 24.7, or 27, or 28, or 29, or 30.1, or 31.2, or 32.7, or 33, or 33.6, or 37, or 39.2, or 40, or 42.7, or 44.8, or 45.4, or 49.1, or 51.2, or 53.7, or 57.3, or 58.1, or 60, or 62.4, or 63, or 64.

[0129] Optionally, the second side surface of the silicon substrate 1 has a velvet structure 11 , which brings about a good light trapping effect and improves the conversion efficiency of the back-contact solar cell.

[0130] Optionally, the back-contact solar cell further includes a front passivation anti-reflection film layer 6 located on the second side surface of the silicon substrate 1 and a back composite passivation film layer 7 located on the surfaces of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 .

[0131] In Figures 4 through 7, dashed lines L1 and L2 are used only to distinguish the first and second regions and do not actually exist in the back-contact solar cell. In Figures 4 through 7, the area to the left of dashed line L1 on the first side of the silicon substrate 1 is the first region, and the area to the right of dashed line L2 is the second region. The P-type doped polysilicon layer 2 is located to the left of dashed line L1 on the first side of the silicon substrate 1. The N-type doped polysilicon layer 3 is located in the second region on the first side of the silicon substrate 1. The first region is distinct from the second region. The N-type doped polysilicon layer 3 is located to the right of dashed line L2 on the first side of the silicon substrate 1.

[0132] Optionally, referring to FIG4 , the surface of the P-type doped polysilicon layer 2 near the silicon substrate 1 is further away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. A height difference H1 between the surface of the P-type doped polysilicon layer 2 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is greater than 0 and less than or equal to 4.85 micrometers (μm). Optionally, the surface of the P-type doped polysilicon layer 2 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 are flush with each other. The flush distribution herein means that the height difference between the surface of the P-type doped polysilicon layer 2 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is zero. Optionally, referring to FIG5 , the surface of the P-type doped polysilicon layer 2 near the silicon substrate 1 is closer to the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. A height difference H2 between a surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 and a surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1 is greater than 0 and less than or equal to 0.3 micrometers. When the relative positional relationship between the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1 is one of the three aforementioned situations, the following beneficial technical effects can be achieved: First, in the process of making the latter doped polysilicon layer, the previously made doped polysilicon layer can be used as a position reference, and the thickness of the latter doped polysilicon layer is easy to control, which reduces the process difficulty; second, before the latter doped polysilicon layer is made, the part of the previously made doped polysilicon layer that needs to be etched is etched more cleanly, and the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 in the gap between the first area and the second area are both etched more cleanly, with better electrical performance and good electrical isolation effect, and low risk of short circuit or leakage; third, the silicon substrate 1 will not be over-etched, and the back-contact solar cell is not prone to hidden cracks, etc., and has good mechanical properties.

[0133] For example, referring to Figures 4 and 5 , the surface of the P-type doped polysilicon layer 2 that is close to the silicon substrate 1 is the lower surface of the P-type doped polysilicon layer 2, and the surface of the N-type doped polysilicon layer 3 that is away from the silicon substrate 1 is the upper surface of the N-type doped polysilicon layer 3. The second side of the silicon substrate 1 is the lower side of the silicon substrate 1. In Figure 4 , the lower surface of the P-type doped polysilicon layer 2 is higher than the upper surface of the N-type doped polysilicon layer 3. In other words, the surface of the P-type doped polysilicon layer 2 that is close to the silicon substrate 1 is farther away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 that is away from the silicon substrate 1. In FIG4 , the height difference H1 between the lower surface of the P-type doped polysilicon layer 2 and the upper surface of the N-type doped polysilicon layer 3 can be any value in the set (0, 4.85 μm]. For example, in FIG4 , the height difference H1 between the lower surface of the P-type doped polysilicon layer 2 and the upper surface of the N-type doped polysilicon layer 3 can be 0.02 μm, or 0.05 μm, or 0.08 μm, or 0.1 μm, or 0.42 μm, or 0.92 μm, or 1.02 μm, or 1.4 6μm, or 1.57μm, or 1.83μm, or 1.95μm, or 2.03μm, or 2.21μm, or 2.37μm, or 2.42μm, or 2.64μm, or 2.97μm, or 3.11μm, or 3.53μm, or 3.69μm, or 3.92μm, or 4.07μm, or 4.26μm, or 4.37μm, or 4.62μm, or 4.85μm.

[0134] In FIG5 , the lower surface of the P-type doped polysilicon layer 2 is lower than the upper surface of the N-type doped polysilicon layer 3, that is, the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 is closer to the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. In FIG5 , the height difference H2 between the lower surface of the P-type doped polysilicon layer 2 and the upper surface of the N-type doped polysilicon layer 3 can be any value in the set (0, 0.3 μm]. For example, in FIG5 , the height difference H2 between the lower surface of the P-type doped polysilicon layer 2 and the upper surface of the N-type doped polysilicon layer 3 can be 0.01 μm, or 0.02 μm, or 0.04 μm, or 0.07 μm, or 0.09 μm, or 0.1 μm, or 0.12 μm, or 0.1 5μm, or 0.16μm, or 0.17μm, or 0.19μm, or 0.2μm, or 0.21μm, or 0.24μm, or 0.246μm, or 0.251μm, or 0.253μm, or 0.261μm, or 0.273μm, or 0.281μm, or 0.287μm, or 0.290μm, or 0.293μm, or 0.296μm, or 0.3μm.

[0135] Optionally, referring to FIG4 , the surface of the P-type doped polysilicon layer 2 proximal to the silicon substrate 1 is further away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. A height difference H1 between the surface of the P-type doped polysilicon layer 2 proximal to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is greater than 0 and less than or equal to 1.6 μm. This configuration allows for more precise control of the relative position of the two surfaces, providing a more accurate position reference. Prior to fabricating the subsequent doped polysilicon layer, the portion of the previously fabricated doped polysilicon layer that needs to be etched can be etched more cleanly. Furthermore, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 in the gap between the first region and the second region can be etched more cleanly, resulting in better electrical performance and electrical isolation, a lower risk of short circuits or leakage, and a lower risk of hidden cracks in the back-contact solar cell, all resulting in better mechanical performance.

[0136] In FIG4 , the height difference H1 between the lower surface of the P-type doped polysilicon layer 2 and the upper surface of the N-type doped polysilicon layer 3 can be any value in the set (0, 1.6 μm]. For example, in FIG4 , the height difference H1 between the lower surface of the P-type doped polysilicon layer 2 and the upper surface of the N-type doped polysilicon layer 3 can be 0.02 μm, or 0.03 μm, or 0.04 μm, or 0.05 μm, or 0.07 μm, or 0.08 μm. .08μm, or 0.1μm, or 0.15μm, or 0.22μm, or 0.34μm, or 0.41μm, or 0.52μm, or 0.63μm, or 0.72μm, or 0.8μm, or 0.95μm, or 1.02μm, or 1.22μm, or 1.34μm, or 1.46μm, or 1.57μm, or 1.6μm.

[0137] Optionally, referring to Figures 6 and 7, the back-contact solar cell further includes a first dielectric layer 8, which is located between the P-type doped polysilicon layer 2 and the first region on the first side of the silicon substrate 1. There is no specific limitation on whether the back-contact solar cell further includes a second dielectric layer. For example, in Figures 6 and 7, the back-contact solar cell further includes a second dielectric layer 9, which is located between the N-type doped polysilicon layer 3 and the second region on the first side of the silicon substrate 1. Here, the thickness of the first dielectric layer 8 and the second dielectric layer 9 can both be 1nm to 2nm, and the materials of the first dielectric layer 8 and the second dielectric layer 9 can be silicon oxide, silicon nitride, silicon oxynitride, etc. Here, the first dielectric layer 8 and the second dielectric layer 9 can both play the role of tunneling and passivation.

[0138] Optionally, referring to FIG6 , the surface of the first dielectric layer 8 near the silicon substrate 1 is further away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1, and a height difference H3 between the surface of the first dielectric layer 8 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is greater than 0 and less than or equal to 4.85 microns. Optionally, the surface of the first dielectric layer 8 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 are flush. Here, flush distribution means that the height difference between the surface of the first dielectric layer 8 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is zero. Optionally, referring to FIG7 , the surface of the first dielectric layer 8 near the silicon substrate 1 is closer to the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1, and a height difference H4 between the surface of the first dielectric layer 8 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is greater than 0 and less than or equal to 0.3 microns. When the relative positional relationship between the surface of the first dielectric layer 8 close to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1 is one of the three aforementioned situations, the following beneficial technical effects can be achieved: First, the first dielectric layer 8 or the N-type doped polysilicon layer 3 can play a certain position reference role, which can appropriately reduce the process difficulty; second, before the latter doped polysilicon layer is made, the part that needs to be etched in the previous doped polysilicon layer is etched more cleanly, and the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 in the gap between the first area and the second area are both etched more cleanly, with better electrical performance and good electrical isolation effect, and low risk of short circuit or leakage; third, the silicon substrate 1 will not be over-etched, and the back-contact solar cell is not prone to hidden cracks, etc., and has good mechanical properties.

[0139] For example, referring to Figures 6 and 7 , the surface of the first dielectric layer 8 close to the silicon substrate 1 is the lower surface of the first dielectric layer 8, and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is the upper surface of the N-type doped polysilicon layer 3. The second side of the silicon substrate 1 is the lower side of the silicon substrate 1. In Figure 6 , the lower surface of the first dielectric layer 8 is higher than the upper surface of the N-type doped polysilicon layer 3. In other words, the surface of the first dielectric layer 8 close to the silicon substrate 1 is farther away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. In FIG6 , the height difference H3 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polysilicon layer 3 can be any value in the set [0, 4.85 μm]. For example, in FIG6 , the height difference H3 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polysilicon layer 3 can be 0.02 μm, or 0.05 μm, or 0.072 μm, or 0.1 μm, or 0.42 μm, or 0.92 μm, or 1.02 μm, or 1.46 μm, or 1.57μm, or 1.84μm, or 1.95μm, or 2.03μm, or 2.21μm, or 2.37μm, or 2.42μm, or 2.64μm, or 2.97μm, or 3.11μm, or 3.53μm, or 3.69μm, or 3.92μm, or 4.07μm, or 4.26μm, or 4.37μm, or 4.62μm, or 4.85μm.

[0140] In FIG7 , the lower surface of the first dielectric layer 8 is lower than the upper surface of the N-type doped polysilicon layer 3. That is, the surface of the first dielectric layer 8 close to the silicon substrate 1 is closer to the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. In FIG7 , the height difference H4 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polysilicon layer 3 can be any value in the set [0, 0.3 μm]. For example, in FIG7 , the height difference H4 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polysilicon layer 3 can be 0.01 μm, or 0.02 μm, or 0.04 μm, or 0.07 μm, or 0.09 μm, or 0.1 μm, or 0.12 μm, or 0.15 μm. m, or 0.16μm, or 0.17μm, or 0.19μm, or 0.2μm, or 0.21μm, or 0.24μm, or 0.246μm, or 0.251μm, or 0.253μm, or 0.261μm, or 0.273μm, or 0.281μm, or 0.287μm, or 0.290μm, or 0.293μm, or 0.296μm, or 0.3μm.

[0141] Optionally, referring to FIG6 , the surface of the first dielectric layer 8 proximal to the silicon substrate 1 is further away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. A height difference H3 between the surface of the first dielectric layer 8 proximal to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is greater than 0 and less than or equal to 1.6 microns. This configuration allows for more precise control of the relative position of the two surfaces, providing a more accurate position reference. Prior to forming a subsequent doped polysilicon layer, the portion of the previously formed doped polysilicon layer requiring etching can be more cleanly etched. Furthermore, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 in the gap between the first and second regions can be more cleanly etched, resulting in better electrical performance and electrical isolation, a lower risk of short circuits or leakage, and a lower risk of micro-cracks in the back-contact solar cell, all resulting in improved mechanical properties.

[0142] For example, referring to Figure 6, the lower surface of the first dielectric layer 8 is higher than the upper surface of the N-type doped polysilicon layer 3, that is, the surface of the first dielectric layer 8 close to the silicon substrate 1 is farther away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. In FIG6 , the height difference H3 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polysilicon layer 3 can be any value in the set [0, 1.6 μm]. For example, in FIG6 , the height difference H3 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polysilicon layer 3 can be 0.01 μm, or 0.02 μm, or 0.05 μm, or 0.09 μm, or 0.1 μm, or 0.12 μm, or 0.23 μm, or 0.46 μm, or 0.57 μm, or 0.8 μm, or 0.84 μm, or 0.95 μm, or 1.03 μm, or 1.13 μm, or 1.21 μm, or 1.37 μm, or 1.40 μm, or 1.42 μm, or 1.51 μm, or 1.6 μm.

[0143] The present application also provides a photovoltaic module comprising one or more of any of the aforementioned back-contact solar cells. The photovoltaic module also includes an encapsulation film located on opposite sides of the back-contact solar cell. The specific structure of the photovoltaic module is not limited herein.

[0144] It should be noted that photovoltaic modules and back-contact solar cells have the same or similar beneficial effects, and the relevant aspects between the two can be referenced to each other. In order to avoid repetition, they will not be described here.

[0145] The present application will be further explained below with reference to specific embodiments. It should be noted that pitch mentioned below = width d9 of the P-type collector region 21 + width d8 of the N-type collector region 31 + 2×dimension d6 of the first gap in the first direction L3.

[0146] Example 1

[0147] 1 , the silicon substrate 1 is an N-type silicon substrate. The second side surface of the silicon substrate 1 has a velvet structure 11. A front passivation anti-reflection film layer 6 is also provided on the second side surface of the silicon substrate 1. A P-type doped polysilicon layer 2 is provided in the first region of the first side of the silicon substrate 1, and an N-type doped polysilicon layer 3 is provided in the second region of the first side. A gap is provided between the first region and the second region. The P-type doped polysilicon layer 2, the N-type doped polysilicon layer 3, and the gap are covered with a back composite passivation film layer 7. By utilizing effective process means such as mask preparation and laser film opening, through mask patterning line width and line length control and laser film opening line width and line length control, the P-type collector region 21, the P-type bus region 22, the N-type collector region 31, the N-type bus region 32, the gap, etc. are made to reach the following sizes and proportions.

[0148] Referring to Figures 2 and 3 , the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 is 0.5 to 1.5. The width d8 of an N-type collector region 31 is 380 μm to 500 μm, and the width d9 of a P-type collector region 21 is 300 μm to 450 μm. In the first direction L3, a first gap is defined between adjacent N-type collector regions 31 and P-type collector regions 21. The dimension d6 of the first gap in the first direction L3 is 50 μm to 150 μm.

[0149] The ratio of the width d4 of an N-type bus region 32 to the width d5 ​​of a P-type bus region 22 is approximately 1. The width d4 of an N-type bus region 32 and the width d5 ​​of a P-type bus region 22 are both 300 μm to 800 μm. The ratio of the length of a collector region to the width of a collector region is 22 to 64. The collector region here is the P-type collector region 21 or the N-type collector region 31, and the bus region here is the N-type bus region 32 or the P-type bus region 22. In the second direction L4, a second gap exists between the collector region and the heterotype bus region. The dimension d7 of the second gap in the second direction L4 is 50 μm to 200 μm. The ratio of the length of a collector gate line to the width of a bus gate line is 22 to 64. The collector gate line is P-type collector gate line 41 or N-type collector gate line 51, and the bus gate line is P-type bus gate line 42 or N-type bus gate line 52. The direction of the collector gate line length and the direction of the bus gate line width are both parallel to the second direction L4. The ratio of the volume of a P-type collector region 21 to the volume of an N-type collector region 31 is 0.5 to 4.

[0150] 1 , the ratio of the thickness d1 of the P-type doped polysilicon layer 2 to the thickness d2 of the N-type doped polysilicon layer 3 is 1 to 2. The thickness d1 of the P-type doped polysilicon layer 2 is 100 nm to 500 nm, and the thickness d2 of the N-type doped polysilicon layer 3 is 50 nm to 300 nm.

[0151] The preparation method of the back-contact solar cell corresponding to Example 1 is roughly as follows.

[0152] S1: Select an N-type single crystal silicon wafer and perform double-side polishing on the N-type single crystal silicon wafer to remove a damaged layer to obtain an N-type silicon substrate.

[0153] S2: preparing a tunneling oxide layer and a polysilicon layer in a first area of ​​a first side surface of the N-type silicon substrate, wherein the oxide layer has a thickness of 1 nm to 3 nm, and the polysilicon layer has a thickness of 100 nm to 500 nm.

[0154] S3: performing boron deposition and diffusion on the polysilicon layer to form a P-type doped polysilicon layer 2.

[0155] S4: Design a barrier layer or laser opening, wherein the barrier layer is designed so that the width d9 of a P-type collector region 21 is designed to be 300μm to 450μm (or the width of the laser opening is designed to be 550μm to 700μm) (the width is designed here based on: adjacent same-type regions pitch = 1000μm), the length of the collector region is 18.3mm to 19.1mm (or the length of the laser opening is 18.7mm to 19.2mm), and the barrier layer is designed so that the width of the bus region is 300μm to 800μm (or the width of the laser opening in the bus region is 400μm to 1200μm), and then use alkaline etching to perform interval etching to etch and remove the P-type doped polysilicon layer 2 until it reaches the silicon substrate, with an etching depth of 0.1μm to 5μm, so that the high layer and the middle layer are arranged adjacent to each other.

[0156] S5: On the first side surface of the silicon substrate 1 and the first side surface of the remaining P-type doped polysilicon layer 2, an N-region tunneling oxide layer and a polysilicon layer are prepared. The thickness of the oxide layer is 1 nm to 3 nm, and the thickness of the polysilicon layer is 50 nm to 300 nm.

[0157] S6: performing phosphorus deposition and diffusion on the polysilicon layer after step S5 to form an N-type doped polysilicon layer 3.

[0158] S7: After step S6, the P-type doped polysilicon layer 2 left after the above-mentioned step S4 is subjected to printed etching or laser film opening, wherein the etching width of the collector gate line or the width of the laser film opening is 400μm to 750μm, and the etching width of the bus gate line or the width of the laser film opening is 400μm to 1200μm.

[0159] S8: After step S7, the second side of the N-type silicon substrate is acid-etched and then alkaline texturing is performed to form a velvet structure 11 with a light-trapping effect on the front side. The velvet structure 11 may include a pyramid structure, and the back side forms staggered high-level areas, low-level areas, and middle-level areas to isolate the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. The dimension d6 of the first gap in the first direction L3 is 50μm to 150μm, and the dimension d7 of the second gap in the second direction L4 is 50μm to 200μm. The etching depth is 0.05μm to 5μm (compared with the middle N-type doped polysilicon layer 3).

[0160] S9: passivating the structure after step S8 so that the front side is covered with a multi-layer front passivation anti-reflection film layer 6 and the back side is covered with a multi-layer passivation film, thereby forming a back side composite passivation film layer 7 on the back side.

[0161] S10: Electrodes are printed at intervals on the back composite passivation film layer 7, and positive electrodes 4 and negative electrodes 5 are formed on the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 respectively, and a low-layer gap area is set on the back, between the high layer and the middle layer.

[0162] In Example 1, both the first dielectric layer 8 and the second dielectric layer 9 are tunneling oxide layers. In Example 1, the surface of the first dielectric layer 8 near the silicon substrate 1 is farther away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. This embodiment corresponds to Figure 6. Here, the height difference H3 between the surface of the first dielectric layer 8 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is greater than 0 and less than or equal to 4.85 μm. This Example 1 can significantly reduce the risk of leakage while ensuring the passivation effect and electrical performance, reasonably design various dimensions, improve the mechanical properties of the battery, and improve the battery conversion efficiency.

[0163] Example 2

[0164] The only difference between Example 2 and Example 1 is that in step S4, the etching depth is 0.5 μm to 2 μm, and in step S8, the etching depth is 0.5 μm to 3 μm. The remaining steps of Example 2 are the same as the corresponding steps of Example 1.

[0165] In Example 2, the first dielectric layer 8 and the second dielectric layer 9 are both tunneling oxide layers. In Example 2, the surface of the first dielectric layer 8 close to the silicon substrate 1 is farther away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. This embodiment corresponds to Figure 6, where the height difference H3 between the surface of the first dielectric layer 8 close to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is greater than 0 and less than or equal to 1.6μm. This Example 2 can also greatly reduce the risk of leakage while ensuring the passivation effect and electrical performance, reasonably design various dimensions, and improve the battery conversion efficiency. At the same time, compared with Example 1, Example 2 has better electrical performance and good electrical isolation effect, lower risk of short circuit or leakage, and the back-contact solar cell is less prone to hidden cracks, etc., and has better mechanical properties.

[0166] Example 3

[0167] 1 , the silicon substrate 1 is a P-type silicon substrate. The second side surface of the silicon substrate 1 has a velvet structure 11. A front passivation anti-reflection film layer 6 is also provided on the second side surface of the silicon substrate 1. A P-type doped polysilicon layer 2 is provided in the first region of the first side of the silicon substrate 1, and an N-type doped polysilicon layer 3 is provided in the second region of the first side. There is a gap between the first region and the second region. The P-type doped polysilicon layer 2, the N-type doped polysilicon layer 3, and the gap are covered with a back composite passivation film layer 7. By utilizing effective process means such as mask preparation and laser film opening, through mask patterning line width and line length control and laser film opening line width and line length control, the P-type collector region 21, the P-type bus region 22, the N-type collector region 31, the N-type bus region 32, the gap, etc. are made to reach the following sizes and proportions.

[0168] 2 and 3 , the ratio of the width d8 of an N-type collector region 31 to the width d9 of a P-type collector region 21 is 2.5 to 8. The width d8 of an N-type collector region 31 is 500 μm to 800 μm, and the width d9 of a P-type collector region 21 is 100 μm to 200 μm. In the first direction L3, a first gap is defined between adjacent N-type collector regions 31 and P-type collector regions 21. The dimension d6 of the first gap in the first direction L3 is 50 μm to 150 μm.

[0169] The ratio of the width d4 of an N-type bus region 32 to the width d5 ​​of a P-type bus region 22 is approximately 1. The width d4 of an N-type bus region 32 and the width d5 ​​of a P-type bus region 22 are both 300 μm to 800 μm. The ratio of the length of a collector region to the width of a collector region is 22 to 64. The collector region here is the P-type collector region 21 or the N-type collector region 31, and the bus region here is the N-type bus region 32 or the P-type bus region 22. In the second direction L4, a second gap exists between the collector region and the heterotype bus region. The dimension d7 of the second gap in the second direction L4 is 50 μm to 200 μm. The ratio of the length of a collector gate line to the width of a bus gate line is 22 to 64. The collector gate line is P-type collector gate line 41 or N-type collector gate line 51, and the bus gate line is P-type bus gate line 42 or N-type bus gate line 52. The direction of the collector gate line length and the direction of the bus gate line width are both parallel to the second direction L4. The ratio of the volume of a P-type collector region 21 to the volume of an N-type collector region 31 is 0.1 to 0.8.

[0170] 1 , the ratio of the thickness d1 of the P-type doped polysilicon layer 2 to the thickness d2 of the N-type doped polysilicon layer 3 is 1 to 2. The thickness d1 of the P-type doped polysilicon layer 2 is 100 nm to 500 nm, and the thickness d2 of the N-type doped polysilicon layer 3 is 50 nm to 300 nm.

[0171] The preparation method of the back-contact solar cell corresponding to Example 3 is roughly as follows.

[0172] S1: Select a P-type single crystal silicon wafer and perform double-sided polishing on the P-type single crystal silicon wafer to remove a damaged layer to obtain a P-type silicon substrate.

[0173] S2: preparing a tunneling oxide layer and a polysilicon layer in a first area of ​​a first side surface of a P-type silicon substrate, wherein the oxide layer has a thickness of 1 nm to 3 nm, and the polysilicon layer has a thickness of 100 nm to 500 nm.

[0174] S3: performing boron deposition and diffusion on the polysilicon layer to form a P-type doped polysilicon layer 2.

[0175] S4: Design a barrier layer or laser opening, wherein the barrier layer is designed so that the width d9 of a P-type collector region 21 is designed to be 100μm to 200μm (or the width of the laser opening is designed to be 800μm to 900μm) (the width is designed here based on: adjacent same-type regions pitch = 1000μm), the length of the collector region is 18.3mm to 19.1mm (or the length of the laser opening is 18.7mm to 19.2mm), and the barrier layer is designed so that the width of the bus region is 300μm to 800μm (or the width of the laser opening in the bus region is 400μm to 1200μm), and then use alkaline etching to perform interval etching to etch and remove the P-type doped polysilicon layer 2 until it reaches the silicon substrate, with an etching depth of 0.1μm to 5μm, so that the high layer and the middle layer are arranged adjacent to each other.

[0176] S5: On the first side surface of the silicon substrate 1 and the first side surface of the remaining P-type doped polysilicon layer 2, an N-region tunneling oxide layer and a polysilicon layer are prepared. The thickness of the oxide layer is 1 nm to 3 nm, and the thickness of the polysilicon layer is 50 nm to 300 nm.

[0177] S6: performing phosphorus deposition and diffusion on the polysilicon layer after step S5 to form an N-type doped polysilicon layer 3.

[0178] S7: After step S6, the P-type doped polysilicon layer 2 left after the above-mentioned step S4 is subjected to printed etching or laser film opening, wherein the width of the collector grid line etching or the width of the laser film opening is 200μm to 500μm, and the width of the bus grid line etching or the width of the laser film opening is 400μm to 1200μm.

[0179] S8: After step S7, the second side of the N-type silicon substrate 1 is acid-etched and then alkaline-textured to form a velvet structure 11 with a light-trapping effect on the front side. The velvet structure 11 may include a pyramid structure, and the back side forms staggered high-level areas, low-level areas, and middle areas to isolate the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. The dimension d6 of the first gap in the first direction L3 is 50μm to 150μm, and the dimension d7 of the second gap in the second direction L4 is 50μm to 200μm, and the etching depth is 0.05μm to 5μm (compared with the middle N-type doped polysilicon layer 3).

[0180] S9: passivating the structure after step S8 so that the front side is covered with a multi-layer front passivation anti-reflection film layer 6 and the back side is covered with a multi-layer passivation film, thereby forming a back side composite passivation film layer 7 on the back side.

[0181] S10: Electrodes are printed at intervals on the back composite passivation film layer 7, and positive electrodes 4 and negative electrodes 5 are formed on the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 respectively, and a low-layer gap area is set on the back, between the high layer and the middle layer.

[0182] In Example 3, both the first dielectric layer 8 and the second dielectric layer 9 are tunneling oxide layers. In Example 3, the surface of the first dielectric layer 8 near the silicon substrate 1 is farther away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1. This embodiment corresponds to Figure 6. Here, the height difference H3 between the surface of the first dielectric layer 8 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 facing away from the silicon substrate 1 is greater than 0 and less than or equal to 4.85 μm. This Example 3 can significantly reduce the risk of leakage while ensuring the passivation effect and electrical performance, reasonably design various dimensions, improve the mechanical properties of the battery, and improve the battery conversion efficiency.

[0183] Example 4

[0184] The only difference between Example 4 and Example 3 is that in step S4, the etching depth is 0.5 μm to 2 μm, and in step S8, the etching depth is 0.5 μm to 3 μm. The remaining steps of Example 4 are the same as the corresponding steps of Example 3.

[0185] In Example 4, the first dielectric layer 8 and the second dielectric layer 9 are both tunneling oxide layers. In Example 4, the surface of the first dielectric layer 8 close to the silicon substrate 1 is farther away from the second side of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1. This embodiment corresponds to Figure 6. Here, the height difference H3 between the surface of the first dielectric layer 8 close to the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1 is greater than 0 and less than or equal to 1.6μm. This Example 4 can also greatly reduce the risk of leakage while ensuring the passivation effect and electrical performance, reasonably design various dimensions, and improve the battery conversion efficiency. At the same time, compared with Example 3, Example 4 has better electrical performance and good electrical isolation effect, lower risk of short circuit or leakage, and the back contact solar cell is less prone to cracking, etc., and has better mechanical properties.

[0186] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0187] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0188] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are protected by this application.

Claims

1. A back contact solar cell, wherein: include: a silicon substrate having opposing first and second sides; A P-type doped polysilicon layer, wherein the P-type doped polysilicon layer is located in a first region of a first side of the silicon substrate; An N-type doped polysilicon layer, wherein the N-type doped polysilicon layer is located in a second region of a first side of the silicon substrate, the first region being different from the second region; Wherein, the ratio of the thickness of the P-type doped polysilicon layer to the thickness of the N-type doped polysilicon layer is 1 to 2.

2. The back contact solar cell according to claim 1, wherein: A surface of the P-type doped polysilicon layer close to the silicon substrate is further away from the second side of the silicon substrate than a surface of the N-type doped polysilicon layer away from the silicon substrate; a height difference between a surface of the P-type doped polysilicon layer close to the silicon substrate and a surface of the N-type doped polysilicon layer away from the silicon substrate is greater than 0 and less than or equal to 4.85 micrometers; Or, a surface of the P-type doped polysilicon layer close to the silicon substrate is flush with a surface of the N-type doped polysilicon layer away from the silicon substrate; Or, a surface of the P-type doped polysilicon layer close to the silicon substrate is closer to the second side of the silicon substrate than a surface of the N-type doped polysilicon layer away from the silicon substrate; a height difference between a surface of the P-type doped polysilicon layer close to the silicon substrate and a surface of the N-type doped polysilicon layer away from the silicon substrate is greater than 0 and less than or equal to 0.3 microns.

3. The back contact solar cell according to claim 2, wherein: A surface of the P-type doped polysilicon layer close to the silicon substrate is farther away from the second side of the silicon substrate than a surface of the N-type doped polysilicon layer away from the silicon substrate; a height difference between a surface of the P-type doped polysilicon layer close to the silicon substrate and a surface of the N-type doped polysilicon layer away from the silicon substrate is greater than 0 and less than or equal to 1.6 microns.

4. The back contact solar cell according to claim 1, wherein: The back contact solar cell further comprises: A first dielectric layer is disposed between the P-type doped polysilicon layer and the first region of the first side of the silicon substrate.

5. The back contact solar cell according to claim 4, wherein: A surface of the first dielectric layer close to the silicon substrate is farther away from the second side of the silicon substrate than a surface of the N-type doped polysilicon layer away from the silicon substrate; a height difference between a surface of the first dielectric layer close to the silicon substrate and a surface of the N-type doped polysilicon layer away from the silicon substrate is greater than 0 and less than or equal to 4.85 micrometers; Or, a surface of the first dielectric layer close to the silicon substrate is flush with a surface of the N-type doped polysilicon layer away from the silicon substrate; Or, a surface of the first dielectric layer close to the silicon substrate is closer to the second side of the silicon substrate than a surface of the N-type doped polysilicon layer facing away from the silicon substrate; a height difference between a surface of the first dielectric layer close to the silicon substrate and a surface of the N-type doped polysilicon layer facing away from the silicon substrate is greater than 0 and less than or equal to 0.3 microns.

6. The back contact solar cell according to claim 5, wherein: A surface of the first dielectric layer close to the silicon substrate is farther away from the second side of the silicon substrate than a surface of the N-type doped polysilicon layer away from the silicon substrate; a height difference between a surface of the first dielectric layer close to the silicon substrate and a surface of the N-type doped polysilicon layer away from the silicon substrate is greater than 0 and less than or equal to 1.6 microns.

7. The back contact solar cell according to claim 1, wherein: The silicon substrate has N-type doping; the P-type doped polysilicon layer includes a plurality of P-type collector regions; the N-type doped polysilicon layer includes a plurality of N-type collector regions; And wherein the N-type collector region and the P-type collector region are alternately distributed along the first direction and both extend along the second direction; the ratio of the width of one N-type collector region to the width of one P-type collector region is 0.5 to 1.5; the direction where the width of the N-type collector region is located and the direction where the width of the P-type collector region is located are both parallel to the first direction.

8. The back contact solar cell according to claim 1, wherein: The silicon substrate has N-type doping; the P-type doped polysilicon layer includes a plurality of P-type collector regions; the N-type doped polysilicon layer includes a plurality of N-type collector regions; And wherein the N-type collector region and the P-type collector region are alternately distributed along the first direction and both extend along the second direction; the ratio of the volume of one P-type collector region to the volume of one N-type collector region is 0.5 to 4.

9. The back contact solar cell according to claim 1, wherein: The silicon substrate has P-type doping; the P-type doped polysilicon layer includes a plurality of P-type collector regions; the N-type doped polysilicon layer includes a plurality of N-type collector regions; And wherein, the N-type collector regions and the P-type collector regions are alternately distributed along the first direction and both extend along the second direction; the volume of one of the P-type collector regions is smaller than the volume of one of the N-type collector regions.

10. The back contact solar cell according to claim 9, wherein: The ratio of the volume of one of the P-type collector regions to the volume of one of the N-type collector regions is 0.1 to 0.

8.

11. The back contact solar cell according to claim 1, wherein: The silicon substrate has P-type doping; the P-type doped polysilicon layer includes a plurality of P-type collector regions; the N-type doped polysilicon layer includes a plurality of N-type collector regions; And wherein, the N-type collector region and the P-type collector region are alternately distributed along the first direction and both extend along the second direction; the width of one of the N-type collector regions is greater than the width of one of the P-type collector regions; the direction where the width of the N-type collector region is located and the direction where the width of the P-type collector region is located are both parallel to the first direction.

12. The back contact solar cell according to claim 11, wherein: A ratio of a width of the N-type collector region to a width of the P-type collector region is 2.5 to 8.

13. The back contact solar cell according to any one of claims 7 to 12, wherein: The P-type doped polysilicon layer further includes a plurality of P-type bus regions; The N-type doped polysilicon layer further includes a plurality of N-type bus regions; And wherein the N-type bus region and the P-type bus region are alternately distributed along the second direction and both extend along the first direction; the first direction is different from the second direction and both are perpendicular to the direction where the thickness is located; Each of the N-type collector regions located between one of the N-type bus regions and one of the P-type bus regions adjacent thereto is connected to the N-type bus region; Each of the P-type collector regions located between one of the N-type bus regions and one of the P-type bus regions adjacent thereto is connected to the P-type bus region; The ratio of the length of a collector region to the width of a bus region is 22 to 64; the collector region is the P-type collector region or the N-type collector region; the bus region is the P-type bus region or the N-type bus region; the direction of the length of the collector region and the direction of the width of the bus region are both parallel to the second direction.

14. The back contact solar cell according to claim 13, wherein: There is a first gap between the adjacent N-type collector region and the adjacent P-type collector region; A second gap is provided between the collector area and the special-shaped bus area; A size of one of the second gaps in the second direction is greater than or equal to a size of one of the first gaps in the first direction.

15. The back contact solar cell according to claim 14, wherein: A ratio of a size of one of the second gaps in the second direction to a size of one of the first gaps in the first direction is 1 to 4.

16. The back contact solar cell according to claim 13, wherein: The volume of one of the P-type bus regions is greater than or equal to the volume of one of the N-type bus regions.

17. The back contact solar cell according to claim 16, wherein: The ratio of the volume of one of the P-type bus regions to the volume of one of the N-type bus regions is 1 to 2.

18. The back contact solar cell according to claim 13, wherein: The ratio of the width of one of the P-type bus regions to the width of one of the N-type bus regions is 0.95 to 1.05; Alternatively, a ratio of a length of the P-type collector region to a length of the N-type collector region is 0.95 to 1.

05.

19. A photovoltaic module, wherein: A back-contact solar cell comprising one or more of claims 1 to 18.

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