Chiplet-based microprocessor system, architecture method, chip, and electronic device

Abstract

The present application discloses a chiplet-based microprocessor system, an architecture method, a chip, and an electronic device. The microprocessor system is based on a chiplet architecture, and comprises: a plurality of computing dies having a computing function; a data die coupled to the plurality of computing dies, wherein the data die is provided with an external interface unit, a memory read-write unit, and a plurality of co-processing units for data acceleration processing; and a plurality of memory units arranged close to the data die. According to the microprocessor system provided by the present application, the co-processing units are arranged on the data die, thereby effectively utilizing the space on the data die, achieving computation offloading, and achieving high performance of the microprocessor system.

Description

Chiplet-based microprocessor system, architecture method, chip and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 22, 2023, with application number 202311795291.3 and application name “Microprocessor system, architecture method, chip and electronic device based on chiplet”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of chip design technology, and in particular to a chiplet-based microprocessor (CPU) system, architecture method, chip, and electronic device. Background Art

[0004] As the semiconductor industry's process upgrades become increasingly difficult and Moore's Law gradually becomes ineffective, achieving chips with better performance and higher integration requires the use of more advanced packaging processes, with chiplets becoming the current dominant technology. Industry vendors using chiplet technology can achieve the following chip solutions:

[0005] 1. Reduce implementation costs. During chip manufacturing, the larger the die area, the more difficult it is to manufacture. Furthermore, due to the existence of manufacturing defects (randomly distributed), the larger the die area, the higher the probability of defects on the die, which means a sharp drop in yield. Therefore, chiplet technology can achieve an appropriate die area and thus achieve optimal cost control.

[0006] 2. A reasonable chiplet solution allows analog IP and digital IP to be implemented using different wafers with different processes. For example, various high-speed IO PHY / Serdes modules can be placed on the IO die, while high-frequency digital logic can be placed on the compute die. This effectively reduces the back-end implementation complexity introduced when these two devices were originally placed together.

[0007] 3. Building on the above, it can also accelerate time-to-market for chip products. Analog IP generally matures slowly and is insensitive to process technology. With a well-designed design, performance on a relatively outdated process can be comparable to that of the latest process. Digital logic, on the other hand, offers significant advantages in operating frequency, power consumption, and area. Chiplet technology allows the analog portion of a system-on-chip (SoC) to be deployed on a relatively mature process, while the digital logic portion can utilize the latest process technology. This avoids the lengthy wait for analog IP to mature before standardizing on a new process.

[0008] 4. Chiplet technology can also achieve better performance. As mentioned above, the use of the most advanced process technology in the main computing logic can maximize the energy efficiency of the computing part without significantly compromising the performance of high-speed IO / analog IP. This system has the best overall performance.

[0009] However, the current chiplet-based CPU solutions are as follows:

[0010] 1) As shown in Figure 1, Solution 1 combines the compute die and compute IO. While this solution utilizes chiplet technology, overcoming yield issues, the DDRC in Figure 1 is still configured on the compute die, failing to achieve complete digital and analog separation.

[0011] 2) As shown in Figure 2, Solution 2 uses chiplet expansion. Although this solution reduces the area of ​​a single die, it also lacks complete separation between analog and digital. This prevents the use of different processes for analog and digital, and thus fails to achieve optimal performance and cost.

[0012] 3) As shown in Figure 3, Solution 3 uses an IO Die and multiple Compute Dies. Although this solution overcomes the incomplete digital and analog separation problem of Solutions 1 and 2, the area of ​​the IO Die in this solution is mainly determined by the size of each IO, and the IO is placed around the Die. This will inevitably result in a lot of unused blank space on the IO Die, resulting in a waste of space. In addition, for high-performance computing chips in data centers, many processing tasks need to be offloaded from the host to reduce the burden on the CPU. However, in Solution 3, task offloading is actually achieved through another C Die (such as a DPU), which is more costly. The IO Die in Solution 3 does not have a layout for a coprocessor for computing power offloading. Summary of the Invention

[0013] The purpose of this application is to solve one of the above technical problems at least to a certain extent.

[0014] To achieve the above-mentioned objectives, the present application proposes a microprocessor system, which is based on a chip architecture and includes: a plurality of computing chips with computing functions; a data chip coupled to the plurality of computing chips, the data chip being provided with an external interface unit, a memory read and write unit and a plurality of co-processing units for accelerating data processing; and a plurality of memory units arranged close to the data chip.

[0015] The co-processing unit is located near the memory reading and writing unit.

[0016] The data chip is divided into multiple pieces, and the multiple pieces of data chips are interconnected.

[0017] The plurality of data wafers after being cut are configured to adopt a mesh interconnection or a ring interconnection.

[0018] The plurality of compute wafers are configured to be arranged in a stacked manner on the data wafer.

[0019] The plurality of data wafers are configured to be arranged in a stacked manner relative to each other.

[0020] To achieve the above-mentioned purpose, the present application proposes, on the other hand, an architectural method for a microprocessor system, which is based on a chip architecture. The architectural method includes: arranging multiple computing chips with computing functions; arranging data chips coupled with the multiple computing chips, arranging external interface units, memory read and write units, and multiple co-processing units for data acceleration processing on the data chips; and arranging multiple memory units close to the data chips.

[0021] The architecture method further includes: the co-processing unit is arranged at a position close to the memory read-write unit.

[0022] The architecture method further includes: the data chip is divided into multiple data chips, and the multiple data chips after division are interconnected.

[0023] The plurality of data chips after being cut are interconnected in a grid or ring manner.

[0024] The architecture method further includes: arranging the plurality of computing chips on the data chip in a stacked manner.

[0025] The plurality of data wafers after being cut are arranged in a stacked manner.

[0026] To achieve the above objectives, the present application further provides a processor chip, which includes the aforementioned microprocessor system.

[0027] To achieve the above-mentioned objectives, another aspect of an embodiment of the present application provides an electronic device, which is configured with the aforementioned processor chip.

[0028] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0030] FIG1 is a schematic block diagram of a chiplet-based CPU system in the prior art;

[0031] FIG2 is a schematic block diagram of another chiplet-based CPU system in the prior art;

[0032] FIG3 is a schematic block diagram of another chiplet-based CPU system in the prior art;

[0033] FIG4 is a schematic block diagram of a chiplet-based microprocessor system;

[0034] FIG5 is a schematic block diagram of another chiplet-based microprocessor system;

[0035] FIG6 is a schematic block diagram of another chiplet-based microprocessor system;

[0036] FIG7 is a schematic block diagram of another chiplet-based microprocessor system;

[0037] FIG8 is a schematic diagram of a microprocessor architecture method flow chart; and

[0038] FIG9 is a schematic diagram of an electronic device. DETAILED DESCRIPTION

[0039] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0040] Chiplet, also known as core particle or small chip, is a packaging technology that disassembles a complex chip into a group of small chip unit dies with separate functions, and packages the module chip and the underlying basic chip through interconnection.

[0041] As mentioned above, although current existing technologies have proposed systems based on chiplet packaging, the existing system architecture has problems such as the inability to effectively separate analog and digital data and the inability to completely offload CPU computing power.

[0042] To this end, the present application proposes a microprocessor system, architecture method, chip and electronic device based on core particles to overcome the above-mentioned existing technical problems.

[0043] FIG4 is a schematic block diagram of a microprocessor system. As shown in FIG4 , the microprocessor system is based on a chiplet architecture, and the microprocessor system includes:

[0044] A plurality of computing chips 10 having computing functions; a data chip 20 coupled to the plurality of computing chips 10, wherein the data chip 20 is provided with an external interface unit 30, a memory read / write unit 40, and a plurality of co-processing units 60 for accelerating data processing; and a plurality of memory units 50 arranged near the data chip 20.

[0045] For example, as shown in Figure 4, the CPU system of Figure 4 includes a data chip 20, which can be regarded as a management and data center for multiple computing chips 10. The data chip can be coupled with multiple computing chips 10 through an external interface unit 30. The various units on the data chip can be connected through a bus to realize the transmission of signal data. In the embodiment of the present application, the data chip 20 is arranged with a coprocessing unit 60, which supports programmability and can be used to support data acceleration processing for different applications. For example, network acceleration, storage acceleration, data encryption operations, etc. Since the data chip 20 is arranged with a coprocessing unit 60, the coprocessing unit 60 can assist in processing different computing requests, offload computing power, and reduce data access paths.

[0046] For data encryption, since existing technologies lack dedicated co-processing units for data acceleration on the D-die, they must use the C-core of the C-chip to accelerate data processing. The specific process is: data to be processed is accessed from the memory (DDR) via the bus. After processing, the C-core stores the processed data back to the DDR via the bus. The specific flow is as follows: ddr->ddrc->ddie-bus->sio->cdie-bus->c-core->cdie-bus->sio->ddie-bus->ddrc->ddr.

[0047] For this application, since a co-processing unit is arranged on the D Die of this application, the co-processing unit can assist in data encryption processing. Taking the co-processing unit as an acceleration processor ACC as an example, the data access process of this application is as follows: ddr->ddrc->ddie-bus->ACC->ddie-bus->ddrc->ddr.

[0048] It can be seen from the above process that ACC accesses data from DDR via DDRC via the D die bus, and then after the data processing is completed, the processed data is written to DDR via DDRC via the D die bus. It is obvious that compared with the above-mentioned existing access process, the access path of the embodiment of the present application is greatly shortened.

[0049] As shown in Figure 4, the data chip 20 of the present application is arranged with a memory read-write unit 40, which can read and write data to the memory unit 50. Compared with the existing technology, arranging the memory read-write unit on the data chip effectively realizes the complete separation of analog IP and digital IP.

[0050] In a preferred embodiment, the co-processing unit is located close to the memory read-write unit.

[0051] For example, as shown in Figure 4, the memory read-write units 40 are respectively arranged on the top of the data chip 20. Therefore, the two co-processing units 60 (ACC) in Figure 4 are close to the memory read-write units 40 located on the top of the data chip 20, so that the distance between the co-processing units 60 and the memory read-write units 40 is shortened, and the relative distance is closer, thereby further reducing the data access path and realizing near-memory processing of data.

[0052] In a preferred embodiment, the data wafer is divided into multiple pieces, and the multiple pieces of data wafers are interconnected.

[0053] For example, considering that more and more functions are loaded on the data chip, the area of ​​the data chip will also become larger and larger. In order to improve the product yield, the present application can further divide the data chip into multiple parts, and the external interface unit, memory reading unit and co-processing unit arranged in the data chip are also arranged on the divided data chip. As shown in Figure 5, the D Die in Figure 5 is divided into two. Two ACCs, two SLCs and one DDRC are arranged on the two divided D Dies. Similarly, for multiple coupled C Dies, after the D Die is divided, the C Die is coupled to the divided D Die accordingly.

[0054] It should be noted that the number of D Die splits is not limited to the two mentioned above. The number of DDie splits in this application can also be 3 or more. The specific number of splits can be set according to actual needs, and no further details will be given here.

[0055] In a preferred embodiment, the plurality of data wafers after being cut are configured to adopt a grid interconnection or a ring interconnection.

[0056] For example, a ring interconnect, also known as a ring interconnect, connects multiple D Dies end-to-end after being split, forming a ring structure. This interconnection method facilitates effective interaction between D Dies without the need for central control and relay, reduces latency, and facilitates the expansion of D Die interconnection, thereby improving the overall performance of the CPU system. A mesh interconnection, also known as a mesh interconnection, arranges multiple D Dies into a regular grid, with each D Die connected to adjacent D Dies in the same row and column. This interconnection method can increase the network dimension of multiple D Dies, improve the communication transmission bandwidth between them, and reduce network latency. It also facilitates the addition of D Dies when more D Dies are split, thereby supporting more cores.

[0057] In addition, the above two interconnection methods are only preferred. The embodiments of the present application are not limited to the above two interconnection methods. Those skilled in the art may adopt an interconnection method suitable for expansion as needed, and no excessive restrictions are imposed on this.

[0058] In a preferred embodiment, the plurality of computing chips are configured to be arranged on the data chip in a stacked manner.

[0059] For example, as shown in Figure 5, the multiple C Dies in Figure 5 are distributed in a plane, but as the CPU system loads more functions, the number of C Dies configured will increase, which will inevitably lead to a larger area for the multiple C Dies to be distributed in the plane, which will undoubtedly cause the overall package size of the CPU system to be too large. Therefore, as shown in Figure 6, the present application adopts 3D packaging technology (also known as 3D stacking technology) to stack multiple C Dies on corresponding coupled D Dies. It should be noted that the stacking of multiple C Dies only changes the arrangement relationship between them and the D Die. After stacking, the multiple C Dies are still coupled with the corresponding D Die to realize data communication transmission. In this way, this 3D stacking method can effectively utilize the space in the vertical direction and reduce the plane expansion area. At the same time, it can also reduce the communication path between C Die and D Died, thereby providing a larger communication bandwidth.

[0060] In a preferred embodiment, the plurality of data wafers are configured to be stacked on top of each other.

[0061] Figure 7 is actually a further stacking diagram based on Figure 6. As shown in Figure 7, in order to further reduce the overall area, the present application can also stack multiple D Dies. That is to say, on the basis of stacking multiple C Dies, multiple D Dies can also be further stacked on each other to further optimize the overall packaging size of the CPU system.

[0062] In addition, the present application also takes into account the heat dissipation problem caused by the stacking method. Therefore, the CPU system of the present application can also be configured with appropriate heat dissipation channels and structures according to actual needs to ensure the stable operation of the overall CPU system.

[0063] In summary, the chiplet-based microprocessor system provided by this application has the following advantages:

[0064] 1) It can realize the separation of analog IP and digital IP,

[0065] 2) A co-processing unit is placed on the D die, effectively offloading computing power and improving CPU system performance.

[0066] 3) The co-processing unit is arranged in near memory, which further optimizes the access path and process, and the CPU system runs faster.

[0067] 4) Multiple dies are arranged in a stacked manner, making the CPU system package smaller and the overall structure more compact and reasonable.

[0068] 5) It can achieve optimal performance, power consumption and area (PPA).

[0069] Based on the same technical concept, this application also provides an architecture method. This architecture method applies the architecture of a CPU system, and the CPU system is based on a chiplet architecture. As shown in FIG8 , the architecture method includes:

[0070] Step S810: Arrange a plurality of computing chips with computing functions.

[0071] For example, this application is based on chiplet packaging technology, which implements different functions on different chips (dies).

[0072] Step S820: Arrange a data chip coupled to the multiple computing chips, and arrange an external interface unit, a memory read / write unit, and multiple co-processing units for data acceleration processing on the data chip.

[0073] For example, in order to facilitate the effective management and control of each C Die, the present application configures a D Die (D Chip) coupled with multiple C Dies. Among them, the D Die is arranged with external interface units, such as IO, which is used for the interconnection between the D Die and multiple C Dies, and is arranged with memory read and write units, such as DDR controller (DDRC), which is used to control the reading of data from the DDR memory or the writing of data to the DDR memory. In the present application, multiple co-processing units are arranged on the space part of the D Die except the external interface units and the memory read and write units, which can effectively utilize the D Die space. At the same time, the co-processing units can assist in processing different computing requests, unload computing power, and reduce data access paths.

[0074] In step S830 , a plurality of memory cells are arranged near the data chip.

[0075] For example, multiple memory cells are arranged close to the data chip, specifically close to the memory read-write unit, so that the memory read-write unit can read and write data from and to the memory cells.

[0076] Therefore, the architectural method provided in this application, by giving a single chip computing and data functions based on chiplet packaging technology, and configuring a co-processing unit on the data chip, can effectively utilize the space on the data chip on the one hand, and on the other hand, it can realize computing power offloading and improve the performance of the CPU system of the architecture. On the one hand, the memory reading unit is configured on the data chip to achieve effective and complete separation of analog IP and digital IP.

[0077] In a preferred embodiment, the architecture method further includes: the co-processing unit is arranged at a position close to the memory read-write unit.

[0078] In this application, a coprocessor is arranged near the memory read and write location to further enhance the overall processing capability, realize near-memory processing of data, and further improve the performance of the CPU system.

[0079] In a preferred embodiment, the architecture method further comprises: the data wafer is divided into a plurality of data wafers, and the divided data wafers are interconnected.

[0080] For example, as more complex business functions are configured on the D die, the single die area of ​​the D die will become larger and larger. In order to effectively reduce the single die area and achieve performance expansion of the CPU system, the present application can further split the D die according to the configuration of the D die, and the multiple D die after splitting are interconnected. In this way, the area of ​​each die after splitting is reduced compared to before splitting, thereby avoiding defects caused by excessive area. For example, the original D die is arranged with 4 ACCs, and the D die is interconnected with 8 C dies. If the D die is split into 2, each D die after splitting is arranged with 2 ACCs, and each D die is connected to 4 C dies.

[0081] In this application, by further splitting the D Die, the area of ​​a single D Die can be effectively reduced, and more services can be offloaded to the D die, thereby facilitating the overall performance expansion of the CPU system.

[0082] In a preferred embodiment, the plurality of data chips after being cut are interconnected in a grid or ring manner.

[0083] In a preferred embodiment, the plurality of computing chips are configured to be arranged on the data chip in a stacked manner.

[0084] For example, as mentioned above, this application is based on a chiplet architecture. As more functions are added, the number of C Dies in the entire CPU system also increases. The expansion of multiple C Dies on the same plane will inevitably cause the overall size of the CPU system package to be too large. Therefore, the embodiments of this application adopt a 3D packaging method, specifically stacking multiple C Dies on their corresponding coupled D Dies. For example, multiple C Dies can be vertically coupled to the D Die to form a compact 3D structure.

[0085] In a preferred embodiment, the plurality of data wafers after being cut are arranged in a stacked manner.

[0086] For example, multiple D Dies can be stacked vertically on top of each other.

[0087] In this application, multiple dies are stacked to reduce the package area compared to traditional planar packaging, making the package structure more compact and improving space utilization. At the same time, it can also reduce the interconnection paths of the dies, improve the signal transmission speed and reliability between dies, reduce signal delay and consolidation, and improve the overall performance of the CPU system as a whole, thereby promoting data transmission and processing speed.

[0088] For more details and advantages of the architectural approach, please refer to the introduction of the chip-based microprocessor mentioned above, which will not be elaborated here.

[0089] Correspondingly, the present application also provides a processor chip, which is the microprocessor system based on the core grain architecture described above.

[0090] Correspondingly, the present application also provides an electronic device, which is configured with the processor chip described above.

[0091] As shown in FIG9 , it shows a schematic diagram of the structure of an electronic device 900 suitable for implementing an embodiment of the present application. The electronic devices in the embodiments of the present application may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., as well as fixed terminals such as digital TVs, desktop computers, etc. The electronic device shown in FIG9 is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0092] As shown in Figure 9, the electronic device 900 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage device 908 into a random access memory (RAM) 903. Various programs and data required for the operation of the electronic device 900 are also stored in the RAM 903. The processing device 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0093] Typically, the following devices may be connected to the I / O interface 905: an input device 906 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 907 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 908 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 909. The communication device 909 may allow the electronic device 900 to communicate with other devices wirelessly or by wire to exchange data. Although FIG9 shows the electronic device 900 with various devices, it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or have alternatively.

[0094] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to the technical solutions formed by a specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the above-mentioned disclosed concepts. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

[0095] In addition, although adopting specific order to describe each operation, this should not be interpreted as requiring these operations to be executed in the specific order shown or in sequential order.Under certain environment, multitasking and parallel processing may be advantageous.Similarly, although comprising some specific implementation details in the above discussion, these should not be interpreted as limiting the scope of the application.Some features described in the context of separate embodiment can also be implemented in a single embodiment in combination.On the contrary, the various features described in the context of a single embodiment also can be implemented in multiple embodiments individually or in the mode of any suitable subcombination.

[0096] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims

1. A microprocessor system, characterized in that: The microprocessor system is based on a chiplet architecture, and the microprocessor system comprises: A plurality of computing chips having computing functions; A data chip coupled to the plurality of computing chips, wherein the data chip is provided with an external interface unit, a memory read / write unit, and a plurality of co-processing units for accelerating data processing; A plurality of memory cells are arranged adjacent to the data chip.

2. The CPU system according to claim 1, wherein: The co-processing unit is located close to the memory reading and writing unit.

3. The CPU system according to claim 1, wherein: The data wafer is cut into a plurality of pieces, and the plurality of cut data wafers are interconnected.

4. The CPU system according to claim 3, wherein: The plurality of data wafers after being cut are configured to adopt a mesh interconnection or a ring interconnection.

5. The CPU system according to claim 1, wherein: The plurality of computing wafers are configured to be arranged in a stacked manner on the data wafer.

6. The CPU system according to claim 1, characterized in that: The plurality of data wafers are configured to be arranged in a stacked manner with respect to each other.

7. An architectural method, characterized in that: For a microprocessor system, the microprocessor system is based on a core grain architecture, the architecture method comprises: Arranging a plurality of computing chips having computing functions; Arrange a data chip coupled to the plurality of computing chips, and arrange an external interface unit, a memory read / write unit, and a plurality of co-processing units for accelerating data processing on the data chip; A plurality of memory cells are arranged near the data chip.

8. The architecture method according to claim 7, characterized in that: The architectural method also includes: The co-processing unit is arranged at a position close to the memory reading and writing unit.

9. The architecture method according to claim 7, characterized in that: The architectural method also includes: The data wafer is cut into a plurality of pieces, and the plurality of cut data wafers are interconnected.

10. The architecture method according to claim 9, characterized in that: The plurality of data chips after being cut are interconnected by a grid or a ring.

11. The architecture method according to claim 7, characterized in that: The architectural method also includes: The plurality of computing wafers are arranged on the data wafer in a stacked manner.

12. The architecture method according to claim 9, characterized in that: The plurality of data wafers after being cut are arranged in a stacked manner.

13. A processor chip, characterized in that: The processor chip comprises the microprocessor system based on the core grain architecture as described in claims 1-6.

14. An electronic device, characterized in that: The electronic device is equipped with the processor chip according to claim 13.

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