Floating point continuous accumulation method and adder

Abstract

The invention provides a floating point continuous accumulation method and an adder, and the method comprises the steps: carrying out the addition calculation of the mantissa of a first source operand and the mantissa of a second source operand in a period, obtaining an accumulation result, and obtaining a next second source operand; wherein the source operand is in a floating point format; in the next period, order matching between the accumulation result and the next second source operand is carried out according to the relation between the index of the accumulation result and the index of the next second source operand; in each subsequent period, carrying out addition calculation on the mantissa of the accumulated result after the order and the mantissa of the next second source operand to obtain the accumulated result, and meanwhile, obtaining the next second source operand; and performing order matching between the accumulation result and the next second source operand according to the relationship between the index of the accumulation result and the index of the next second source operand. According to the method, effective data calculation can be performed in each period under the high dominant frequency, so that the operation efficiency is improved, and the power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a floating-point continuous accumulation method and an adder. Background Art

[0002] A floating-point adder is a digital circuit or algorithm module used to implement floating-point addition operations.

[0003] For example, the floating-point adder in a computer's CPU, GPU and other processors can perform floating-point number addition operations and support high-performance computing in various fields such as scientific computing, graphics processing, and artificial intelligence.

[0004] In high-frequency application scenarios, the floating-point adder requires two or more cycles to generate the accumulated calculation results, and it is impossible to perform valid data calculations in every cycle at a high frequency. Summary of the Invention

[0005] In order to solve one of the above technical defects, the present application provides a floating-point continuous accumulation method and an adder.

[0006] In a first aspect, the present application provides a floating-point continuous accumulation method, the method comprising:

[0007] In one cycle, the mantissa of the first source operand and the mantissa of the second source operand are added to obtain an accumulated result, and at the same time, the next second source operand is obtained; wherein the source operands are in floating-point format;

[0008] In the next cycle, the accumulated result and the next second source operand are aligned according to the relationship between the exponent of the accumulated result and the exponent of the next second source operand;

[0009] In each subsequent cycle, the mantissa of the accumulated result after alignment is added to the mantissa of the next second source operand to obtain the accumulated result, and at the same time, the next second source operand is obtained; based on the relationship between the exponent of the accumulated result and the exponent of the next second source operand, the accumulated result and the next second source operand are aligned.

[0010] Optionally, performing an order comparison between the accumulation result and the next second source operand according to a relationship between an exponent of the accumulation result and an exponent of the next second source operand includes:

[0011] Determine whether the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1;

[0012] If the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1, then the accumulated result and the next second source operand are aligned based on the relationship between the exponents of the accumulated result and the next second source operand;

[0013] If the exponent of the accumulated result is different from the exponent of the next second source operand and the difference is not 1, the rounding point position is determined; according to the relationship between the exponent of the accumulated result and the exponent of the next second source operand, the accumulated result and the next second source operand are aligned.

[0014] Optionally, performing an order comparison between the accumulation result and the next second source operand according to a relationship between an exponent of the accumulation result and an exponent of the next second source operand includes:

[0015] determining a restriction code according to a relationship between an exponent of the accumulation result and an exponent of the next second source operand;

[0016] The next second source operand is aligned according to the restriction code.

[0017] Optionally, determining the restriction code according to a relationship between an exponent of the accumulation result and an exponent of the next second source operand includes:

[0018] determining a limit code based on a difference between the exponent of the accumulated result and the exponent of the next second source operand and the number of leading zeros of the accumulated result; or,

[0019] The limit code encoder determines the limit code according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand.

[0020] Optionally, determining a rounding point location includes:

[0021] The rounding point position is determined according to the result of bitwise AND of the sign bit of the exponent difference of the two source operands for obtaining the accumulated result and the mantissa of the accumulated result;

[0022] The mantissa of the accumulated result after the order is adjusted is added to the mantissa of the next second source operand to obtain the accumulated result, including:

[0023] According to the rounding point position, the mantissa of the accumulated result after the order is adjusted and the mantissa of the next second source operand are added to obtain the accumulated result.

[0024] In a second aspect of the present application, an adder is provided, the adder comprising: an input preprocessing module, a fixed-point accumulation unit, and a continuous accumulation step difference preprocessing unit;

[0025] in,

[0026] An input preprocessing module is used to obtain a source operand; wherein the source operand is in a floating point format;

[0027] A fixed-point accumulation unit, configured to perform an addition calculation on the mantissa of a first source operand and the mantissa of a second source operand in one cycle to obtain an accumulation result;

[0028] a continuous accumulation order difference preprocessing unit, configured to compare the order of the accumulation result with the next second source operand according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand in the next cycle and each subsequent cycle;

[0029] The fixed-point accumulation unit is further used to perform addition calculation on the accumulated result after the order and the next second source operand in each subsequent cycle to obtain the accumulated result.

[0030] Optionally, a continuous accumulation order difference pre-processing unit is used to determine whether an exponent of the accumulation result is the same as an exponent of the next second source operand, or whether the exponent differs by 1;

[0031] If the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1, then the accumulated result and the next second source operand are aligned based on the relationship between the exponents of the accumulated result and the next second source operand;

[0032] If the exponent of the accumulated result is different from the exponent of the next second source operand and the difference is not 1, the rounding point position is determined; according to the relationship between the exponent of the accumulated result and the exponent of the next second source operand, the accumulated result and the next second source operand are aligned.

[0033] Optionally, the continuous accumulation order difference preprocessing unit is configured to determine a restriction code according to a relationship between an exponent of an accumulation result and an exponent of a next second source operand; and perform order comparison with the next second source operand according to the restriction code.

[0034] Optionally, the continuous accumulation order difference preprocessing unit is used to determine the restriction code based on the difference between the exponent of the accumulation result and the exponent of the next second source operand and the number of leading zeros of the accumulation result; or, through the restriction code encoder, determine the restriction code based on the relationship between the exponent of the accumulation result and the exponent of the next second source operand.

[0035] Optionally, a continuous accumulation order difference preprocessing unit is used to determine a rounding point position according to a bitwise AND result of a sign bit of an exponent difference of two source operands for obtaining an accumulation result and a mantissa of the accumulation result;

[0036] The fixed-point accumulation unit is further used to perform addition calculation on the mantissa of the accumulated result after rounding and the mantissa of the next second source operand according to the rounding point position to obtain the accumulated result.

[0037] The present application provides a floating-point continuous accumulation method and adder, the method comprising: in one cycle, performing an addition calculation on the mantissa of a first source operand and the mantissa of a second source operand to obtain an accumulation result, and at the same time, obtaining a next second source operand; wherein the source operand is in a floating-point format; in the next cycle, performing an alignment between the accumulation result and the next second source operand according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand; in each subsequent cycle, performing an addition calculation on the mantissa of the accumulation result after alignment and the mantissa of the next second source operand to obtain an accumulation result, and at the same time, obtaining the next second source operand; performing an alignment between the accumulation result and the next second source operand according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand. The method provided by the present application can realize effective data calculation in each cycle at a high main frequency, thereby improving computing efficiency and reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0039] Figure 1 The figure is a flowchart of a floating-point continuous accumulation method.

[0040] Figure 2 A flowchart of a floating-point continuous accumulation method provided in an embodiment of the present application;

[0041] Figure 3 A flowchart of another floating-point continuous accumulation method provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of the structure of a high-performance processor provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of the architecture of a scalar processor provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of a synchronization unit provided in an embodiment of the present application;

[0045] Figure 7 A schematic diagram of the architecture of a vector processor provided in an embodiment of the present application;

[0046] Figure 8 A schematic diagram of the structure of a vector operation unit provided in an embodiment of the present application;

[0047] Figure 9 A schematic diagram of the architecture of another vector processor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0049] During the implementation of this application, the inventors discovered that a floating-point adder (a digital circuit or algorithm module used to perform floating-point addition operations) requires two or more cycles to generate an accumulated result in high-frequency applications, making it impossible to perform valid data calculations in every cycle at high frequency.

[0050] In response to the above problems, an embodiment of the present application provides a floating-point continuous accumulation method and adder, the method comprising: in one cycle, performing an addition calculation on the mantissa of a first source operand and the mantissa of a second source operand to obtain an accumulation result, and at the same time, obtaining the next second source operand; wherein the source operand is in floating-point format; in the next cycle, performing an alignment between the accumulation result and the next second source operand according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand; in each subsequent cycle, performing an addition calculation on the mantissa of the accumulation result after alignment and the mantissa of the next second source operand to obtain an accumulation result, and at the same time, obtaining the next second source operand; performing an alignment between the accumulation result and the next second source operand according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand. The method provided by the present application can realize effective data calculation in each cycle at a high main frequency, thereby improving computing efficiency and reducing power consumption.

[0051] This embodiment provides a floating point continuous accumulation method, which is based on the existing floating point accumulation implementation process. Figure 1 As shown, in the existing floating-point accumulation scheme:

[0052] (1) Get the first source operand (sa[63:0]) and the second source operand (sb[63:0]).

[0053] (2) After decoding the source operands, the exponents of the two source operands (sa_expt and sb_expt) are obtained.

[0054] (3) By determining whether sa_expt>sb_expt is established, the larger exponent and the smaller exponent of the first source operand (sa[63:0]) and the second source operand (sb[63:0]) are obtained, and the difference between the larger exponent and the smaller exponent is used as the exponent difference.

[0055] (4) Shift the mantissa right based on the exponent difference.

[0056] (5) Add the shifted digits.

[0057] (6) Determine whether to continue accumulating.

[0058] (7) If accumulation continues, the mantissa of the accumulation result is shifted to the same order as the next second source operand (this will produce a calculation result that complies with IEEE754). Repeat (5) to add the accumulation result (i.e., the calculation result that complies with IEEE754) to the mantissa of the next second source operand to obtain a new accumulation result.

[0059] (8) If the accumulation is not continued, the mantissa of the accumulation result is normalized and shifted left, rounded, and the calculation result is output.

[0060] Among them, the shift of the mantissa of the accumulated result and the alignment of the next second source operand (at this time, a calculation result that complies with IEEE754 will be generated) require one cycle to complete. Therefore, in the existing solution, there will be a cycle between two adjacent additions, and continuous addition of consecutive cycles cannot be achieved.

[0061] The method provided in this embodiment is located at Figure 1 The dotted box position of the accumulation process shown in the figure can achieve the accumulation result by adding the mantissas, and when continuing the accumulation, the accumulation result is added to the mantissa of the next second source operand in the next cycle to obtain a new accumulation result, and this is repeated until the output result is determined, thereby realizing continuous floating-point accumulation.

[0062] See also Figure 2 This embodiment provides a floating-point continuous accumulation method, the implementation process of which is as follows:

[0063] 201 , within one cycle, perform addition calculation on the mantissa of the first source operand and the mantissa of the second source operand to obtain an accumulation result, and at the same time, obtain the next second source operand.

[0064] The source operand is in floating-point format, for example, FP64 format or FP32 format.

[0065] Before implementing step 201, Figure 1The implementation block shown reads the first source operand (sa[63:0]) and the second source operand (sb[63:0]), dynamically identifies the source operand format, and triggers the corresponding processing channel based on the source operand format. In the processing channel, the source operands are decoded, the exponents of the two source operands (sa_expt and sb_expt) are obtained, and the exponent difference is generated based on the exponential relationship between the two source operands (i.e., whether sa_expt>sb_expt holds). The mantissa is right-shifted. Then, step 201 is executed. Within a cycle, the mantissa of the first source operand is added to the mantissa of the second source operand to obtain the accumulated result. At the same time, the next second source operand is obtained.

[0066] The process of adding the mantissa of the first source operand to the mantissa of the second source operand to obtain the accumulated result is the same as the existing one. When obtaining the next second source operand, the next second source operand can be obtained through a bypass.

[0067] It should be noted that the “cycle” in this embodiment and subsequent embodiments refers to a clock cycle.

[0068] 202 , in the next cycle, performing an order comparison between the accumulation result and the next second source operand according to a relationship between the exponent of the accumulation result and the exponent of the next second source operand.

[0069] The implementation process of step 202 is as follows:

[0070] 202-1, determine whether the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1. If the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1, execute step 202-2. If the exponent of the accumulated result is not the same as the exponent of the next second source operand, and does not differ by 1, execute step 202-3.

[0071] 202-2, performing an alignment between the accumulation result and the next second source operand according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand.

[0072] If the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1, the order can be aligned based on the near path implementation scheme, such as aligning the accumulated result with the next second source operand based on the relationship between the exponent of the accumulated result and the exponent of the next second source operand.

[0073] According to the relationship between the exponent of the accumulation result and the exponent of the next second source operand, the process of performing the order comparison between the accumulation result and the next second source operand is as follows:

[0074] 1. Determine a restriction code based on the relationship between the exponent of the accumulation result and the exponent of the next second source operand.

[0075] The restriction code indicates how many leading zeros need to be removed during the left return, that is, how many bits are left returned. Since there is a level difference between the current accumulated result and the next floating-point number (that is, the next second source operand), the level difference may occur in the following three situations:

[0076] In the first case, the exponent of the accumulated result is greater than the exponent of the next floating-point number (i.e., the next second source operand), and the corrected exponent after subtracting the leading zero from the exponent of the accumulated result is greater than the exponent of the next floating-point number (i.e., the next second source operand).

[0077] In the second case, the exponent of the accumulated result is greater than the exponent of the next floating-point number (i.e., the next second source operand), but the corrected exponent after subtracting the leading zero from the exponent of the accumulated result is less than the exponent of the next floating-point number (i.e., the next second source operand).

[0078] In the third case, the exponent of the accumulated result is smaller than the exponent of the next floating-point number (ie, the next second source operand).

[0079] For the first two types, it is necessary to limit the left return of the accumulated number through a restriction code.

[0080] There are various implementations for determining the limit code. For example, the limit code can be determined based on the difference between the exponent of the accumulated result and the exponent of the next second source operand, as well as the number of leading zeros in the accumulated result. Alternatively, the limit code can be determined based on the relationship between the exponent of the accumulated result and the exponent of the next second source operand, for example, by a limit code encoder. In the limit code encoder, a compressor can be used to compress the exponent difference and other parameters to generate the limit code.

[0081] 2. Align the next second source operand according to the restriction code.

[0082] This process is an existing parallel process and can be implemented using an existing solution.

[0083] If the exponent of the accumulated result is the same as the exponent of the next-second source operand, or differs by 1, then only a left return is performed. That is, a limit code is determined based on the difference between the exponents of the accumulated result and the next-second source operand, as well as the number of leading zeros in the accumulated result. Alternatively, a limit code encoder is used to determine a limit code based on the relationship between the exponent of the accumulated result and the exponent of the next-second source operand. The limit code is then compared with the next-second source operand.

[0084] In addition, when aligning, since there is an exponential difference between the accumulated result and the next second source operand, it is possible that both left shift and right shift are performed in the process of aligning with the next second source operand, which increases the overhead. The method of this embodiment can achieve only left shift and no right shift through the restriction code, thereby reducing the shift overhead.

[0085] 202-3, determine the rounding point position. According to the relationship between the exponent of the accumulation result and the exponent of the next second source operand, perform an order comparison between the accumulation result and the next second source operand.

[0086] If the exponent of the accumulated result is different from the exponent of the next second source operand and the difference is not 1, the order can be aligned based on the far path implementation scheme, such as first determining the rounding point position, and then aligning the accumulated result with the next second source operand based on the relationship between the exponent of the accumulated result and the exponent of the next second source operand.

[0087] The process of determining the rounding point position is as follows: determining the rounding point position according to the bitwise AND result of the sign bit of the exponent difference of the two source operands for obtaining the accumulated result and the mantissa of the accumulated result.

[0088] For example, a truth table corresponding to the sign bit is determined based on the sign bit of the exponent difference of the two source operands used to obtain the accumulated result, and the rounding point position is determined by performing a bitwise AND operation on the corresponding truth table and the mantissa of the accumulated result.

[0089] A truth table corresponding to various sign bit situations can be pre-stored. After obtaining the sign bit of the exponent difference of the two source operands to obtain the accumulation result, the corresponding value can be selected from the pre-stored truth table. The truth table generation scheme is implemented using an existing scheme.

[0090] In addition, the mantissa of the accumulated result (e.g., 5 bits) is bit4, bit3, bit2, bit1, and bit0, respectively, and there are the following three situations:

[0091] If the LSB (Least Significant Bit) of the mantissa is in bit 5, then the G (guard bit) is in bit 4, and the R (round bit) and S (sticky bit) are in bits 3-0 or together. In this case, the CI (carry bit) is in bit 6.

[0092] If the LSB is in bit 4, then the G bit is in bit 3, and the R and S bits are in bits 2-0 or together. In this case, the CI bit is in bit 5.

[0093] If the LSB is in bit 3, then the G bit is in bit 2, the R bit is in bit 1, and the S bit is in bit 0. In this case, the CI bit is in bit 4.

[0094] Perform bitwise AND of the corresponding truth table and the mantissa of the accumulated result in the three cases mentioned above to obtain the rounding point position.

[0095] The rounding point position is used for rounding processing. However, the rounding processing process is not implemented through a separate cycle as in the existing solution. Instead, rounding is performed while adding the mantissa of the current accumulation result and the mantissa of the next second source operand in the next cycle (that is, rounding and addition are performed simultaneously). This ensures that floating-point numbers are accumulated once in each cycle, thereby achieving continuous accumulation.

[0096] The process of aligning the order of the accumulated result and the next second source operand based on the relationship between the exponent of the accumulated result and the exponent of the next second source operand in step 202-3 is the same as the process of aligning the order of the accumulated result and the next second source operand based on the relationship between the exponent of the accumulated result and the exponent of the next second source operand in step 202-2. Please refer to the implementation process of step 102-2 and it will not be repeated here.

[0097] If the exponent of the accumulated result is different from the exponent of the next second source operand and the difference is not 1, then the rounding point position is first determined (this rounding point position is used for rounding during the accumulation in the next cycle). That is, the rounding point position is determined based on the bitwise AND result of the sign bit of the difference between the exponents of the two source operands of the accumulated result and the mantissa of the accumulated result. Then, based on the relationship between the exponent of the accumulated result and the exponent of the next second source operand, the accumulated result and the next second source operand are aligned.

[0098] In each subsequent cycle, 203, the mantissa of the accumulated result after the alignment is added to the mantissa of the next second source operand to obtain the accumulated result. Simultaneously, the next second source operand is obtained. The accumulated result and the next second source operand are aligned based on the relationship between the exponent of the accumulated result and the exponent of the next second source operand.

[0099] Among them, if the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1, then in each subsequent cycle, when the mantissa of the accumulated result after the order is added to the mantissa of the next second source operand, the existing floating-point mantissa addition calculation scheme can be used.

[0100] If the exponent of the accumulated result is different from the exponent of the next second source operand and the difference is not 1, then in each subsequent cycle, when the mantissa of the accumulated result after the exponent is added to the mantissa of the next second source operand, the mantissa of the accumulated result after the exponent is added to the mantissa of the next second source operand will be added according to the rounding point position to obtain the accumulated result.

[0101] If step 201 is implemented in the i-th cycle and step 202 is implemented in the i+1-th cycle, starting from the i+2-th cycle, a floating-point number will be accumulated in each cycle, so that continuous floating-point accumulation can be achieved starting from the i+2-th cycle.

[0102] The floating point continuous accumulation method provided in this embodiment is specifically implemented as follows Figure 3 As shown, in the floating-point continuous accumulation method of this embodiment:

[0103] (1) Get the first source operand (sa[63:0]) and the second source operand (sb[63:0]).

[0104] (2) After decoding the source operands, the exponents of the two source operands (sa_expt and sb_expt) are obtained.

[0105] (3) By determining whether sa_expt>sb_expt is established, the larger exponent and the smaller exponent of the first source operand (sa[63:0]) and the second source operand (sb[63:0]) are obtained, and the difference between the larger exponent and the smaller exponent is used as the exponent difference.

[0106] (4) Shift the mantissa right based on the exponent difference.

[0107] (5) Add the shifted mantissas in step 201 and obtain the next second source operand at the same time.

[0108] (6) Determine whether to continue accumulating.

[0109] (7) If accumulation is to continue, the order of the accumulation result and the next second source operand is compared through step 202. Repeat step (5) and add the shifted mantissa through step 201. At the same time, the next second source operand is obtained. Step (6) determines whether to continue accumulation. If accumulation is to continue in step (7), the order of the accumulation result and the next second source operand is compared through step 202 until accumulation is discontinued.

[0110] (8) If the accumulation is not continued, the mantissa of the accumulation result is normalized and shifted left, rounded, and the calculation result is output.

[0111] The first execution of (7) requires one cycle to complete the process of aligning the accumulated result with the next second source operand through step 202. Subsequently, in each cycle, (5) adding the mantissa and obtaining the next second source operand, (6) confirming to continue accumulation, and (7) aligning the accumulated result with the next second source operand are simultaneously executed until accumulation stops. In other words, one addition is performed in each subsequent cycle, achieving continuous addition in consecutive cycles.

[0112] The floating-point continuous accumulation method that the present embodiment provides can complete the accumulation of floating points in one cycle.Existing floating-point number accumulation scheme can not directly carry out order with next another floating-point number, but left rule produces a result of calculation that meets IEEE754, after this result is outputted, add with next floating-point number again and so on, therefore this calculation often needs 2 cycles to complete under the processor of higher main frequency, therefore new accumulated number also needs to wait for 1 cycle and wait until the calculated number produces and could continue next accumulation calculation.The floating-point continuous accumulation method that the present embodiment provides is after completing two floating-point numbers order accumulation, with the accumulated result directly with next floating-point number order and directly with the floating-point number of new input in next cycle accumulate.

[0113] It should be noted that in order to store intermediate values ​​(such as intermediate accumulation results) in FP64 format during continuous accumulation, they are rounded to FP32 only at the final output to avoid successive truncation errors.

[0114] The floating-point continuous accumulation method provided in this embodiment supports mixed-precision operations in multiple floating-point formats (FP64, FP32) and can achieve continuous floating-point accumulation of source operands in each cycle. It is suitable for scenarios such as artificial intelligence reasoning, scientific computing, and graphics processors, and can improve computing efficiency and reduce power consumption.

[0115] The floating-point continuous accumulation method provided in this embodiment does not require software preprocessing, and the cumulative error in the continuous accumulation operation complies with IEEE754, meeting the requirements of scientific computing scenarios.

[0116] The floating-point continuous accumulation method provided in this embodiment supports continuous accumulation of floating-point addition and complies with the iEEE 754 standard. The floating-point continuous accumulation method provided in this embodiment supports inputting a source operand in each cycle during the accumulation process, and performs accumulation calculation on the newly input source operand and the original accumulation sum.

[0117] The floating-point continuous accumulation method provided in this embodiment suppresses errors during continuous accumulation. The floating-point continuous accumulation method provided in this embodiment retains all intermediate precisions during the continuous accumulation process and complies with the IEEE 754 standard, performing only one rounding operation at the final output.

[0118] This embodiment provides a floating-point continuous accumulation method, wherein, within one cycle, the mantissa of a first source operand is added to the mantissa of a second source operand to obtain an accumulation result, and at the same time, a next second source operand is obtained; wherein the source operands are in floating-point format; within the next cycle, the accumulation result and the next second source operand are aligned based on the relationship between the exponent of the accumulation result and the exponent of the next second source operand; within each subsequent cycle, the mantissa of the accumulated result after alignment is added to the mantissa of the next second source operand to obtain an accumulation result, and at the same time, the next second source operand is obtained; and the accumulation result and the next second source operand are aligned based on the relationship between the exponent of the accumulation result and the exponent of the next second source operand. This method can achieve effective data calculation in each cycle at a high main frequency, thereby improving computing efficiency and reducing power consumption.

[0119] based on Figure 2 and / or Figure 3 With the same inventive concept of the floating-point continuous accumulation method shown in FIG, this embodiment provides an adder, which includes: an input preprocessing module, a fixed-point accumulation unit, and a continuous accumulation step difference preprocessing unit.

[0120] in,

[0121] The input preprocessing module is used to obtain source operands, where the source operands are in floating-point format.

[0122] The fixed-point accumulation unit is used to perform addition calculation on the mantissa of the first source operand and the mantissa of the second source operand in one cycle to obtain an accumulation result.

[0123] The continuous accumulation order difference preprocessing unit is used to compare the order between the accumulation result and the next second source operand according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand in the next cycle and each subsequent cycle.

[0124] The fixed-point accumulation unit is further used to perform addition calculation on the accumulated result after the order and the next second source operand in each subsequent cycle to obtain the accumulated result.

[0125] The continuous accumulation order difference pre-processing unit is used to determine whether the exponent of the accumulation result is the same as the exponent of the next second source operand, or whether the exponent differs by 1.

[0126] If the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1, the accumulated result and the next second source operand are aligned according to the relationship between the exponents of the accumulated result and the next second source operand.

[0127] If the exponent of the accumulated result is different from the exponent of the next second source operand and the difference is not 1, the rounding point position is determined. According to the relationship between the exponent of the accumulated result and the exponent of the next second source operand, the accumulated result and the next second source operand are aligned.

[0128] The continuous accumulation order difference preprocessing unit is used to determine a restriction code according to a relationship between an exponent of an accumulation result and an exponent of a next second source operand, and to compare orders with the next second source operand according to the restriction code.

[0129] The continuous accumulation step difference preprocessing unit is configured to determine a limit code based on a difference between an exponent of the accumulation result and an exponent of a next second source operand, as well as the number of leading zeros of the accumulation result. Alternatively, the limit code is determined by a limit code encoder based on a relationship between an exponent of the accumulation result and an exponent of the next second source operand.

[0130] The continuous accumulation order difference preprocessing unit is used to determine the rounding point position according to the bitwise AND result of the sign bit of the exponent difference of the two source operands for obtaining the accumulation result and the mantissa of the accumulation result.

[0131] The fixed-point accumulation unit is further used to perform addition calculation on the mantissa of the accumulated result after rounding and the mantissa of the next second source operand according to the rounding point position to obtain the accumulated result.

[0132] The adder provided in this embodiment can implement addition calculations for FP64 and FP32 using the same set of fixed-point addition circuits and shift circuits.

[0133] In addition, in a specific implementation, the processor of the device where the adder is located is a high-performance processor, which includes a scalar processor and a vector processor.

[0134] The connection relationship between the scalar processor and the vector processor can be shown as follows Figure 4 shown.

[0135] The scalar and vector processors share data storage. The vector processors can only access the data storage and are executed only by the scalar processors.

[0136] A connection is established between the scalar processor and the vector processor. For example, the scalar processor and the vector processor are connected via a dedicated instruction channel.

[0137] In addition, the high-performance processor may also include two registers, one register corresponding to the scalar processor and the other register corresponding to the vector processor. The vector processor can read and write its corresponding register, and the scalar processor can read and write its corresponding register as well as the vector processor's corresponding register.

[0138] The scalar processor can read and write the registers of the vector processor.

[0139] Scalar processors establish connections to global memory.

[0140] (1) Scalar processor

[0141] See also Figure 5 The scalar processor includes: an instruction fetch unit, a register renaming unit, an operation reservation stack unit, a storage reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0142] In addition, the scalar processor may also include one or more other units, such as one or more other functional modules, one or more instruction caches, one or more data storages, one or more special vector registers, one or more status flag registers, etc.

[0143] 1. Instruction fetch unit

[0144] The instruction fetch unit is used to fetch and dispatch instructions.

[0145] Specifically, the instruction fetch unit generates an instruction fetch request address, outputs the fetch request address to the instruction cache for instruction fetching, receives instructions from the instruction cache, and stores them in the data store. Each cycle, it sequentially reads qualified instructions from the data store, decodes and performs relevant checks on the read instructions, and then dispatches the checked instructions sequentially.

[0146] For example, the instruction fetch unit generates an instruction fetch request address and outputs it to the instruction cache for instruction fetch, and receives instructions from the instruction cache and stores them in the data storage. In each cycle, it sequentially selects one or more instructions from the qualified instructions for decoding and related checks, and dispatches the qualified instructions sequentially, dispatching at most one program control unit instruction and one synchronization unit instruction at a time. In addition, one or more scalar operation unit instructions and one or more memory access unit instructions can also be dispatched each time.

[0147] 2. Register renaming unit

[0148] The register renaming unit is used to receive instructions dispatched by the instruction fetch unit and rename registers.

[0149] Specifically, the register renaming unit receives and stores instructions dispatched by the instruction fetch unit, renames special vector registers, conditionally decodes instructions, and generates pipeline stall signals. It also receives and writes data from one or more of the scalar arithmetic unit, memory access unit, program control unit, synchronization unit, special vector registers, condition registers, and flag registers. It also sends instructions to one or more of the arithmetic hold stack unit, memory hold stack unit, program control unit, and synchronization unit.

[0150] For example, the register renaming unit is used in a scalar processor to receive instructions dispatched by the instruction fetch unit and perform register and special vector register renaming, instruction conditional decoding, and generate pipeline congestion signals. At the same time, it receives data from the execution unit (such as the scalar operation unit, memory access unit, program control unit, synchronization unit) to write back registers, special vector registers, condition registers, and status flag registers and writes them back to the corresponding registers.

[0151] The scalar processor write-back supports out-of-order write-back, has high execution efficiency, and distributes instructions to the operation retention stack unit, the storage retention stack unit, the program control unit, or the synchronization unit.

[0152] The register renaming unit bandwidth may be 6 bits, wherein multiple (eg, 4) input instructions may be valid at the same time.

[0153] There can be multiple condition registers, which are located in the register renaming unit.

[0154] The instructions of the scalar operation unit and memory access unit support the operations of reading and writing condition registers.

[0155] The synchronous unit's instructions support the operation of reading the condition register.

[0156] The jump and function call instructions of the program control unit support the operation of reading the condition register.

[0157] When an instruction enters the condition register, if there is an unexecuted instruction in the condition register, the pipeline is blocked.

[0158] That is, the condition register is not renamed, and when a read-write dependency occurs, a dispatch block is triggered to wait. The read and write rules for the condition register are as follows:

[0159] ●Read the rules:

[0160] (1) All instructions of the scalar arithmetic unit, memory access unit, and synchronization unit support conditional execution and require reading the value of the condition register.

[0161] (2) The scalar arithmetic unit also supports read conditional register instruction operations.

[0162] (3) The jump and function call instructions of the program control unit support read condition register operations.

[0163] ●Write rules:

[0164] (1) The scalar arithmetic unit supports write conditional register instructions.

[0165] (2) Scalar operation unit logic instructions and comparison instructions support the option of writing condition registers.

[0166] When the previously issued instruction to write the condition register has not yet been completed, and an instruction to read or write the same condition register enters, the pipeline is blocked and a conditional execution blocking signal is generated, waiting for the previous condition register to be written.

[0167] In addition, the register renaming unit includes: one or more physical registers and one or more logical registers.

[0168] Wherein, any physical register is one of the following: a scalar physical register, a vector physical register, a condition register, and a flag register.

[0169] Any logical register is one of the following: a scalar logical register, a vector logical register.

[0170] For example, the register renaming unit includes one or more physical registers, such as a plurality of 512-bit wide special vector registers, a plurality of condition registers, and a status flag register.

[0171] Among them, special vector registers are renamed, while condition registers and status flag registers are not renamed.

[0172] There are multiple logical registers, such as multiple read-only logical registers and multiple vector logical registers.

[0173] In addition, the mapping relationship between logical registers and physical registers is maintained by the register mapping table. The mapping relationship between vector logical registers and vector physical registers is maintained by the special vector register mapping table.

[0174] 1) Register Mapping Table

[0175] Initially, the physical registers mapped to the entries corresponding to all logical register indices in the register mapping table are all 0. When an instruction is executed or an interrupt occurs, the logical registers allocated to the relevant physical registers are determined, and the mappings of the entries corresponding to the allocated logical register indices in the register mapping table are updated to the identifiers of the relevant physical registers.

[0176] For example, a register map table with a depth of 32 bits and a width of 6 bits stores the mapping between all logical registers and all physical registers. Initially, the mapping in the register map table is invalid, and all entries for the mapped physical registers are set to zero. When a physical register is assigned to a logical register, the entry corresponding to the logical register index in the register map table is changed to the ID of the physical register.

[0177] It should be noted that the register mapping table is updated only when the instruction is actually executed. If the conditional execution instruction is not executed, the register mapping table will not be updated. In addition, the register mapping table will not be updated when a jump occurs. However, when an interrupt occurs, the interrupt return address must update the register mapping table to ensure that the interrupt can return normally.

[0178] 2) Special vector register mapping table

[0179] Initially, the mapping vector physical registers of all entries corresponding to the vector logical register indexes in the special vector register mapping table are all 0. When an instruction is executed, the vector logical register allocated to the relevant vector physical register is determined, and the mapping of the entry corresponding to the allocated vector logical register index in the special vector register mapping table is updated to the identifier of the relevant vector physical register.

[0180] For example, the special vector register mapping table has a depth of 4 and a width of 3 bits, storing the mapping relationship between all vector logical registers and all vector physical registers. Initially, the special vector register mapping table is invalid, and all entries for the mapped vector physical registers are all zeros. When a vector physical register is assigned to a vector logical register, the entry corresponding to the vector logical register index in the special vector register mapping table is changed to the ID of the vector physical register.

[0181] It should be noted that the special vector register mapping table is updated only when the instruction is actually executed. If the conditional execution instruction is not executed, the special vector register mapping table will not be updated. In addition, the special vector register mapping table will not be updated when a jump occurs.

[0182] 3. Operation reservation stack unit

[0183] The operation reserve stack unit is the emission queue of the scalar operation unit.

[0184] The operation reserve stack unit receives instructions, dispatch and rename information from the register renaming unit and pushes them into the queue. It then pops ready instructions to the scalar operation unit for execution.

[0185] The operation reserve stack unit is also used to decode input instructions and store instruction type information.

[0186] In other words, the Arithmetic Hold Stack unit acts as the issue queue for the scalar arithmetic unit. It receives instructions and associated dispatch and renaming information from the register renaming unit, pushes them into the queue, and then pops ready instructions onto the scalar arithmetic unit for execution. The Arithmetic Hold Stack unit decodes the incoming instructions and stores the instruction type information.

[0187] In specific implementation, the depth of the operation reserve stack unit can be flexibly adjusted, for example, the depth of the operation reserve stack unit is 8. Multiple scalar operation units share one operation reserve stack unit.

[0188] The rules for issuing and receiving instructions for the operation reserve stack unit are as follows:

[0189] (1) The output of the register renaming unit enters the operation preservation stack unit.

[0190] (2) When there is any idle scalar operation unit, it will fetch instructions and operands from the operation reservation stack unit for execution.

[0191] (3) The principle of executing instructions from the operation reservation stack unit is to execute the executable instructions that can be sent from the operation reservation stack unit in a forward-to-back order.

[0192] (4) Whether the transmission can be made is determined by whether the values ​​of all source registers or special vector registers or condition registers and status flag registers are ready.

[0193] (5) If there are multiple instructions that can be sent, the oldest instruction will be sent first according to the instruction order.

[0194] (6) If any scalar operation unit is blocked, it can no longer receive new instructions.

[0195] (7) If the instruction previously sent to any scalar operation unit is a division instruction, a new division instruction can only be sent to it after the division result calculation is completed and the calculation completion En signal is returned.

[0196] 4. Storage Retention Stack Unit

[0197] The storage reservation stack unit is the transmit queue of the memory access unit.

[0198] The storage reservation stack unit is used to receive instructions and register renaming information from the register renaming unit and push them into the queue.

[0199] The storage reservation stack unit is also used to send a read request to the register renaming unit when the instruction address register is ready, and save the read address operand.

[0200] The register renaming unit is also used to calculate the address, decode the address, and save the decoding information after the instruction obtains the address.

[0201] The register renaming unit is also used to detect when the source register of any instruction is ready and the address decoding is completed, and then send it to the memory access unit for execution.

[0202] In specific implementation, the depth of the storage reservation stack unit can be flexibly adjusted, such as the depth of the storage reservation stack unit is 16. Multiple memory access units share one storage reservation stack unit. The storage reservation stack unit is the transmission queue of the memory access unit. The storage reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the storage reservation stack unit is ready, a read request is sent to the register renaming unit and the read address operand is saved in the queue. After the instruction in the storage reservation stack unit obtains the address, the address can be calculated and decoded, and the generated decoding information is saved in the queue. When the source register of an instruction (such as a write instruction) in the storage reservation stack unit is ready and the address decoding is completed, it can be transmitted to the memory access unit for execution. Before transmission, it must undergo a series of checks, such as address type check, address comparison check, and address forward check.

[0203] The rules for sending and receiving instructions to the storage reserve stack unit are as follows:

[0204] (1) The output of the register renaming unit enters the storage reservation stack unit.

[0205] (2) When the source operand for calculating the address is ready, the memory access address is calculated and saved in the storage reservation stack unit.

[0206] (3) Instructions with unrelated addresses: They can be sent out of order. The out-of-order rules are: read instructions after read instructions, write instructions after read instructions, and read instructions after write instructions. They can all be sent out of order. Write instructions after write instructions need to maintain order (they cannot be sent to different memory access units at the same time). Even if the addresses are unrelated, write instructions after write instructions still need to maintain order.

[0207] (4) Address-related instructions: read instructions followed by write instructions, write instructions followed by read instructions, write instructions followed by write instructions, and read instructions followed by read instructions all need to be performed in order.

[0208] (5) When the addresses are unrelated but all instructions that have not been sent successfully (i.e., instructions on the way that have not been sent to the destination, including those at the memory access unit level and the memory access unit output level) are located in the same storage space, they can be sent out of order to the same memory access unit, but they cannot be sent to two or more memory access units.

[0209] (6) Only one memory access instruction located in the same storage space but with unrelated addresses can be sent at the same time, and two or more memory access units cannot be sent at the same time.

[0210] (7) Address correlation judgment principle: Whether the addresses are related is irrelevant if they are located in different storage spaces. If they are located in the same storage space, whether the addresses are related is determined based on the data granularity.

[0211] 5. Scalar arithmetic unit

[0212] In a specific implementation, there may be one or more scalar operation units.

[0213] For example, the scalar processor includes two scalar arithmetic units, namely scalar arithmetic unit 0 and scalar arithmetic unit 1.

[0214] The scalar operation unit is used to receive instructions and data sent by the operation reservation stack unit, perform operations on the data based on the instructions, and write the operation results back to the register renaming unit.

[0215] The scalar arithmetic unit is the computing unit of the scalar processor, which can perform various types of fixed-point and floating-point operations, such as addition, subtraction, multiplication, division, logical operations, comparison operations, shifts, etc. It receives instructions and data sent by the operation reserve stack unit, performs operations, and writes the results back to the register file unit of the register renaming unit or the special vector register file unit.

[0216] Several instruction examples are provided below as examples. In specific implementations, they are not limited to the following instructions, nor are they limited to including all instructions.

[0217] Instructions with execution level one include: fixed-point addition and subtraction, logical instructions, shift instructions, fixed-point and floating-point comparison instructions, read and write Flag instructions, fixed-point maximum and minimum instructions, ABS instructions, bit reversal instructions, selection instructions, special vector register distribution instructions, read special vector register instructions, Byte reversal instructions, Merge instructions, immediate value assignment instructions, FirstOne instructions, CRC instructions, floating-point classification instructions, floating-point partial domain extraction, and Rounding instructions.

[0218] Instructions with execution level three include: fixed-point multiplication instructions, fixed-floating-point conversion instructions, bit filtering instructions, Count instructions, and floating-point addition and subtraction instructions.

[0219] Instructions that support Bypass include: selection instructions, fixed-point addition and subtraction instructions, shift instructions, immediate value assignment instructions, ABS instructions, logical instructions, comparison instructions, and maximum and minimum instructions.

[0220] The execution cycle of the division instruction is uncertain and is related to the data of the divisor and the dividend. When the instruction is executed, a DivEn instruction will be generated to indicate that the instruction is executed and the result is output to the register stack. No new division instructions can be input during the execution of the division instruction, but other scalar calculation unit instructions can be input. After the division is executed, the output result is reused with the output port of the first-stage pipeline. When the output port of the first-stage pipeline is not used by other scalar calculation unit instructions, the division outputs its result and outputs the DivEn identifier at the same time. The DivEn identifier is output to the operation retention stack unit, indicating that the Div instruction can continue to be output to the current scalar calculation unit.

[0221] 6. Memory access unit

[0222] In a specific implementation, there may be one or more memory access units.

[0223] For example, a scalar processor includes two memory access units, namely memory access unit 0 and memory access unit 1.

[0224] The memory access unit is used to receive instructions, data and register information sent by the storage reservation stack unit, and read and write the data based on the instructions and register information.

[0225] The memory access unit is a functional module that executes memory access-related instructions for scalar processors. The memory access unit receives instructions and data, as well as register-related information, from the storage retention stack unit. It executes instructions accordingly and interacts with other units to read and write data. Read instructions and atomic write instructions require writing data back to the register renaming unit. These instructions include register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector read and write instructions, including 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing cycles.

[0226] In addition, the memory access unit is responsible for providing the relevant instruction quantity information required by FENCE. The memory access unit interacts with the storage reservation stack unit to complete the data storage configuration.

[0227] 7. Program control unit

[0228] In a specific implementation, there is only one program control unit.

[0229] The program control unit is configured to receive instructions and data from the register renaming unit, process the data based on the instructions, and output a processing result.

[0230] The program control unit (PCU) executes instructions related to the scalar processor's program execution sequence. The PCU receives instructions and data from the register renaming unit (RRU), processes the data accordingly, and outputs the results to other modules in the scalar processor. Different instructions are processed in different time periods.

[0231] The program control unit is responsible for controlling the direction of program execution (such as stop, interrupt, jump, function call), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetch operations of the instruction cache, as well as FENCE operations; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information.

[0232] 8. Synchronization unit

[0233] In a specific implementation, there is only one synchronization unit.

[0234] Synchronization unit, used to synchronize the scalar processor and the vector processor.

[0235] like Figure 6 As shown, a communication connection is established between the synchronization unit and the pipeline control unit, the register renaming unit, the program control unit, and the vector processor.

[0236] The instructions of the synchronization unit come from the register renaming unit, and the reading and writing of the data of the synchronization unit interact with the register renaming unit.

[0237] The synchronization unit is used to receive the pause signal sent by the pipeline control unit and send the execution level pause signal generated when communicating with the vector processor to the pipeline control unit so as to generate the execution pause signal of the scalar processor.

[0238] The synchronization unit is used to generate instructions and transmit them to the program control unit.

[0239] That is to say, the synchronization unit is a unit that synchronizes the scalar processor and the vector processor. It receives instructions and data sent by the register renaming unit, reads data from the vector processor and writes it back to the register stack, reads data from the register stack unit or the special vector register stack unit and sends it to the functional module of the vector processor. It is responsible for the startup and status query of the vector processor, such as querying the reading and writing of the read and write FIFO (FirstInput FirstOutput) in the vector program control unit of the vector processor, the configuration of the register file stack, the reading or writing of the scalar register, the register file stack status query, the reading FIFO depth, the reading of the startup vector processor instruction counter, etc., and providing the program control unit with the synchronization unit instruction information.

[0240] The synchronization unit interacts with the pipeline control unit, register renaming unit, and program control unit within the scalar processor, as well as with the external vector processor, scalar processor, and vector processor transfer queue module. Synchronization unit instructions originate from the register renaming unit, and data reading and writing must interact with the register renaming unit. The synchronization unit receives a stall signal from the pipeline control unit and, when communicating with the vector processor, generates its own execute-level stall signal, which is sent to the pipeline control unit to generate the ExeStall signal for the entire scalar processor. The synchronization unit generates the instruction to be executed in the next cycle and transmits it to the program control unit for use by the program control unit's counter instruction. Interactions with the vector processor include, but are not limited to, configuring the register file with special vector registers or registers, reading and writing scalar registers, and querying the write status of the register file. Interactions with the scalar processor and vector processor transfer queue module include, but are not limited to, starting the vector processor, querying vector processor status, reading and writing data in the vector processor's instruction fetch unit FIFO, reading the FIFO depth, and reading the start vector processor instruction counter.

[0241] Therefore, in a specific implementation, the synchronization unit may have the following functions (it should be noted that the following functions are only examples, and other functions may be provided. This embodiment and subsequent embodiments do not limit the specific functions of the synchronization unit):

[0242] The start vector processor function is used to start the vector processor, including immediate start and register start, such as the pipeline waits until the start is successful, or writes the result of the start success or failure back to the destination register.

[0243] Query the vector processor execution status function, support option B.

[0244] Read and write FIFO function, the FIFO is located in the instruction fetch unit of the vector processor, such as the FIFO bit width 32 bits, the read and write FIFO such as the read and write FIFO waits until success, or the read and write FIFO success or failure result is written back to the register.

[0245] Write register file stack functions, including special vector register writes or register writes.

[0246] Read and write scalar register functions, including immediate index or register index read and write.

[0247] Query the register file stack write back status function, such as waiting until all writes to the register file stack are completed, or returning the result of whether the write to the register file stack is completed to the register.

[0248] When the related operations are not completed, the synchronization unit will generate its own blocking signal, blocking and waiting, and the signal will be sent to the pipeline control unit to generate a pipeline blocking signal.

[0249] A FIFO (such as a 32-bit deep FIFO) can also be added between the scalar processor and the vector processor to store the request to start the vector processor, and move the read and write FIFO previously located in the vector processor to the scalar processor and vector processor transmission queue module. The scalar processor and vector processor transmission queue module unit implements the startup of the vector processor, queries the execution status of the vector processor, reads and writes FIFO functions, reads FIFO depth functions, and reads the startup vector processor instruction counter function. The condition for the successful startup of the vector processor is that the startup vector processor FIFO is not full, and the query of the vector processor execution status is passed. The condition for the vector processor status to be stopped is that the vector processor execution is completed and the startup vector processor FIFO is empty.

[0250] 9. Assembly line control unit

[0251] The pipeline control unit is used to generate a pipeline pause signal and / or generate a start and stop signal for the scalar processor.

[0252] The pipeline control unit is the pipeline control unit of the scalar processor, which is connected to each unit inside the scalar processor and is responsible for generating pipeline blocking signals, such as blocking in normal working mode and blocking in debug mode.

[0253] The pipeline control unit also communicates with the communication and synchronization unit to generate signals for starting and stopping the scalar processor.

[0254] Furthermore, in practical applications, scalar processors can also perform conditional execution decoding. For example, when performing conditional execution decoding, a scalar processor determines the execution condition of the instruction's preset bits. If the condition is met, a valid instruction is output; otherwise, a null instruction is output. A null instruction refers to an empty or invalid instruction.

[0255] If there is a read or write operation on the condition register, the pipeline is blocked and the read operation can be performed after the write operation is completed. There is no bypass in the read or write operation of the condition register.

[0256] Taking two condition registers, namely condition register 0 and condition register 1, and the preset bits being [29:28] as an example, when the scalar processor performs conditional execution decoding, the scalar processor judges the execution condition of the input instruction based on the [29:28] bits of the instruction set encoding. If the condition is met, a valid instruction is output, otherwise an empty instruction is output.

[0257] Among them, [29:28] bits are 00, which means that the condition register 0 is 1 and the instruction is executed; [29:28] bits are 01, which means that the condition register 1 is 1 and the instruction is executed; [29:28] bits are 10, which means that the condition register 0 is executed; [29:28] bits are 11, which means unconditional execution. If the condition is not met, the instruction is invalid and an empty instruction is output.

[0258] If the condition register is read or written, the pipeline is blocked and the read operation is performed after the condition register is written. There is no bypass when reading or writing the condition register.

[0259] (2) Vector Processor

[0260] See also Figure 7 ,The vector processor includes : a vector program control unit, multiple ,functional units, a register file stack and a scalar register.

[0261] In addition, the vector processor also includes: a private vector register of a vector interleaving unit and a private vector register of a vector access unit.

[0262] 1. Vector program control unit

[0263] Vector program control unit, used for instruction fetching and instruction issuance.

[0264] That is, the vector program control unit is used to fetch instructions, determine whether to execute them, and send the instructions to the functional units based on the determination result.

[0265] The vector program control unit is also used to control instruction jumps.

[0266] The vector program control unit has scalar computing capabilities.

[0267] The vector program control unit interacts with the scalar registers.

[0268] In specific implementation, the vector program control unit is an instruction fetch and instruction issuance unit. It takes instructions from the cache according to the PC value, and after determining whether to execute them, it issues the instructions to each functional unit according to the wait value (configured by the wait instruction). At the same time, it controls the jump of instructions and has some scalar computing capabilities.

[0269] In addition, the vector program control unit is further configured to receive a start command from other operation processors to start the vector processor and return an indication signal to the other operation processors indicating whether the vector processor has finished operation.

[0270] Taking the scalar processor as an example, the vector program control unit receives the start command issued by the synchronization unit of the scalar processor, starts the vector processor execution, and also returns an indication signal indicating whether the synchronization unit vector processor execution is completed.

[0271] 2. Functional Unit

[0272] Functional unit, used to perform functional processing according to instructions.

[0273] For example, the functional unit receives an instruction from the vector program control unit, processes data accordingly according to the instruction, and outputs the processing result according to the address specified in the instruction.

[0274] The functional units include: one or more vector operation units, one or more vector interleaving units, and one or more vector access units.

[0275] 1) Vector operation unit

[0276] Any vector arithmetic unit, used to perform vector operations according to instructions.

[0277] like Figure 8 As shown, any vector operation unit includes: a floating-point multiplication-addition operator unit, a floating-point multiplication-accumulation operator unit, a floating-point arithmetic operator unit, a tensor multiplication subunit and an intermediate result register.

[0278] The floating-point multiplication and addition unit and the floating-point arithmetic unit share a single issue slot, so a maximum of eight vector unit instructions can be issued per cycle.

[0279] The floating-point multiply-accumulate operator and the tensor multiplication subunit share one emit slot.

[0280] The floating-point multiply-add operator unit is a functional unit that executes floating-point multiply-add operator unit related instructions. For example, floating-point multiply-add operator unit related instructions include integer and floating-point vector multiplication and accumulation, multiplication, addition, tensor calculation, etc.

[0281] 1 vector operation unit has independent intermediate result registers.

[0282] One floating-point multiplication-addition operator unit, one floating-point multiplication-accumulation operator unit, one tensor multiplication subunit, and one floating-point arithmetic operator unit share intermediate result registers.

[0283] (1) Floating-point multiplication-addition operator unit and floating-point multiplication-accumulation operator unit, which can perform integer and floating-point vector multiplication, multiplication-accumulation and other operations. Supported types include but are not limited to int32, fp32, and fp64.

[0284] (2) The floating-point arithmetic subunit can perform integer and floating-point vector arithmetic operations, such as comparison, addition, subtraction, bitwise operations, etc. Supported types include but are not limited to int8, uint8, int16, uint16, int32, uint32, bool, fp16, bf16, fp32, tf32, and fp64.

[0285] (3) The tensor multiplication subunit can perform tensor multiplication, multiply-accumulate and other operations. Supported types include but are not limited to int8, bf16, fp16, and tf32.

[0286] 2) Vector interleaving unit

[0287] Any vector interleaving unit is used to perform data interleaving and logic processing according to instructions.

[0288] The vector interleaver unit is the control and data processing unit within the vector processor. It is responsible for interleaving data and supports logical and some fixed-point and floating-point calculations. It also supports a wide range of customized instructions, including table lookup, lateral calculations, sparse matrix calculations, precision conversion, and FIFO (First Input First Output). It also executes instructions such as data broadcasting, extraction, and internal interleaving.

[0289] Each vector interleaving unit has a set of private vector registers, so the private vector registers of the vector interleaving units correspond one to one with the vector interleaving units.

[0290] 3) Vector access unit

[0291] Any vector access unit, used to perform multi-mode memory access, address calculation and scalar calculation according to the instruction.

[0292] The vector access unit is the memory access unit within the vector processor, which is mainly responsible for reading / writing instructions and various scalar calculations.

[0293] The read instruction / write instruction supports multiple memory access modes, such as row mode, column mode / discrete mode / extended mode / accumulated mode.

[0294] It also supports multiple parameter configurations, with a maximum read / write instruction data width of 1024 bits. It can also perform address calculation, load / store and other instructions.

[0295] All vector access units share a set of private vector registers, so the private vector registers of a vector access unit are shared by multiple vector access units.

[0296] 3. Register file stack

[0297] The register file receives read and write requests and returns data. It rearranges the data before returning it. It interacts with the functional units for read and write operations. The vector program control unit's configuration registers are configured using data in the register file.

[0298] The register file is a general-purpose vector register stack and is the main storage unit within the vector processor. It is responsible for receiving read and write requests and returning data. In some functions, it can rearrange the data before returning it to the request module.

[0299] The register file stack performs read and write interactions with the functional units in the vector processor (such as the floating-point multiplication-addition operator unit, the floating-point arithmetic operator unit, the floating-point multiplication-accumulation operator unit, and the tensor multiplication subunit), and supports the use of data in the register file stack to configure the instruction fetch unit configuration register.

[0300] The register file stack is also used to write data to other processors and receive status information from other processors to check whether the data has been written.

[0301] Taking a scalar processor as an example, the synchronization unit of the scalar processor can write data into the register file stack, and the register file stack can also receive status information from the synchronization unit of the scalar processor to inquire whether the data has been written.

[0302] The depth of the register file is configurable.

[0303] Figure 9 A schematic diagram of a vector processor is shown, in which the functional units include four vector operation units, four vector interleaving units, and four vector access units.

[0304] The vector processor provided in this embodiment supports a VLIW (Very Long Instruction Word) instruction set. Each VLIW may be composed of one or more instructions, and each instruction corresponds to a functional unit.

[0305] In addition, a read FIFO unit and a write FIFO unit are provided between the vector processor and other operation processors.

[0306] The vector program control unit and other operation processors both perform a read operation on the read FIFO unit and a write operation on the write FIFO unit.

[0307] Other arithmetic processors perform read operations or write operations on the vector registers.

[0308] Taking a scalar processor as an example, a read FIFO and a write FIFO unit for transmitting data are provided between the scalar processor and the vector processor. The scalar processor and the vector program control unit can perform read operations or write operations on the read and write FIFO.

[0309] At the same time, the synchronization unit of the scalar processor can read or write the scalar registers of the vector processor.

[0310] The device provided in this embodiment can realize effective data calculation in each cycle at a high main frequency, thereby improving computing efficiency and reducing power consumption.

[0311] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiment of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal translation scripting language JavaScript, etc.

[0312] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0313] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0314] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0315] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0316] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0317] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A floating point continuous accumulation method, characterized in that: The method comprises: In one cycle, the mantissa of the first source operand and the mantissa of the second source operand are added to obtain an accumulated result, and at the same time, the next second source operand is obtained; wherein the source operand is in floating point format; In the next cycle, the accumulated result and the next second source operand are aligned according to the relationship between the exponent of the accumulated result and the exponent of the next second source operand; In each subsequent cycle, the mantissa of the accumulated result after alignment is added to the mantissa of the next second source operand to obtain the accumulated result, and at the same time, the next second source operand is obtained; based on the relationship between the exponent of the accumulated result and the exponent of the next second source operand, the accumulated result and the next second source operand are aligned.

2. The method according to claim 1, characterized in that The step of performing an order comparison between the accumulation result and the next second source operand according to a relationship between the exponent of the accumulation result and the exponent of the next second source operand includes: Determine whether the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1; If the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1, then the accumulated result and the next second source operand are aligned based on the relationship between the exponents of the accumulated result and the next second source operand; If the exponent of the accumulated result is different from the exponent of the next second source operand and the difference is not 1, the rounding point position is determined; according to the relationship between the exponent of the accumulated result and the exponent of the next second source operand, the accumulated result and the next second source operand are aligned.

3. The method according to claim 1 or 2, characterized in that The step of performing an order comparison between the accumulation result and the next second source operand according to a relationship between the exponent of the accumulation result and the exponent of the next second source operand includes: determining a restriction code according to a relationship between an exponent of the accumulation result and an exponent of the next second source operand; Alignment is performed with the next second source operand according to the restriction code.

4. The method according to claim 3, characterized in that The step of determining the restriction code according to a relationship between an exponent of the accumulation result and an exponent of the next second source operand includes: determining a limit code based on a difference between the exponent of the accumulated result and the exponent of the next second source operand and the number of leading zeros of the accumulated result; or, The limit code encoder determines the limit code according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand.

5. The method according to claim 2, characterized in that Determining the rounding point position includes: Determine a rounding point position according to a bitwise AND result of a sign bit of a difference in exponents of two source operands from which the accumulated result is obtained and a mantissa of the accumulated result; The adding calculation of the mantissa of the accumulated result after the order is adjusted and the mantissa of the next second source operand to obtain the accumulated result includes: According to the rounding point position, the mantissa of the accumulated result after the order is adjusted and the mantissa of the next second source operand are added to obtain the accumulated result.

6. An adder, characterized in that: The adder includes: an input preprocessing module, a fixed-point accumulation unit, and a continuous accumulation step difference preprocessing unit; in, The input preprocessing module is used to obtain a source operand; wherein the source operand is in a floating point format; The fixed-point accumulation unit is used to perform an addition calculation on the mantissa of the first source operand and the mantissa of the second source operand in one cycle to obtain an accumulation result; a continuous accumulation order difference preprocessing unit, configured to compare the order of the accumulation result with the next second source operand according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand in the next cycle and each subsequent cycle; The fixed-point accumulation unit is further configured to perform an addition calculation on the accumulated result after the order and the next second source operand in each subsequent cycle to obtain an accumulated result.

7. The adder according to claim 6, wherein: The continuous accumulation order difference preprocessing unit is used to determine whether the exponent of the accumulation result is the same as the exponent of the next second source operand, or whether the exponent differs by 1; If the exponent of the accumulated result is the same as the exponent of the next second source operand, or differs by 1, then the accumulated result and the next second source operand are aligned based on the relationship between the exponents of the accumulated result and the next second source operand; If the exponent of the accumulated result is different from the exponent of the next second source operand and the difference is not 1, the rounding point position is determined; according to the relationship between the exponent of the accumulated result and the exponent of the next second source operand, the accumulated result and the next second source operand are aligned.

8. The adder according to claim 6 or 7, characterized in that The continuous accumulation order difference preprocessing unit is used to determine a restriction code according to the relationship between the exponent of the accumulation result and the exponent of the next second source operand; and perform order comparison with the next second source operand according to the restriction code.

9. The adder according to claim 8, wherein: The continuous accumulation order difference preprocessing unit is used to determine the restriction code according to the difference between the exponent of the accumulation result and the exponent of the next second source operand and the number of leading zeros of the accumulation result; Alternatively, the restriction code is determined by a restriction code encoder according to a relationship between an exponent of the accumulation result and an exponent of the next second source operand.

10. The adder according to claim 7, wherein: The continuous accumulation order difference preprocessing unit is used to determine a rounding point position according to a bitwise AND result of a sign bit of an exponent difference of two source operands for obtaining the accumulation result and a mantissa of the accumulation result; The fixed-point accumulation unit is further configured to perform an addition calculation on the mantissa of the accumulated result after rounding and the mantissa of the next second source operand according to the position of the rounding point to obtain an accumulated result.

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