A switching circuit for cell balancing in a battery management system

Abstract

A switching circuit for cell balancing in a battery management system, BMS. The switching circuit comprises: a first battery connection terminal, for connecting to a first battery terminal; a second battery connection terminal, for connecting to a second battery terminal; and a cell balancing field effect transistor, FET. The cell balancing FET comprises: a gate terminal; a drain terminal connected to the first battery connection terminal; a source terminal connected to the second battery connection terminal; and a body terminal. The switching circuit also comprises a FET control circuit that is configured to connect the gate terminal and the body terminal of the cell balancing FET to the battery connection terminal that has the lowest voltage.

Description

[0001] A SWITCHING CIRCUIT FOR CELL BALANCING IN A BATTERY MANAGEMENT

[0002] SYSTEM

[0003] Field

[0004] The present disclosure relates to a switching circuit for cell balancing in a battery management system (BMS)

[0005] Summary

[0006] According to a first aspect of the present disclosure there is provided a switching circuit for cell balancing in a battery management system, BMS, the switching circuit comprising : a first battery connection terminal, for connecting to a first battery terminal; a second battery connection terminal, for connecting to a second battery terminal; a cell balancing field effect transistor, FET, comprising : a gate terminal; a drain terminal connected to the first battery connection terminal; a source terminal connected to the second battery connection terminal; and a body terminal; a FET control circuit that is configured to connect the gate terminal and the body terminal of the cell balancing FET to the battery connection terminal that has the lowest voltage.

[0007] Advantageously, such a switching circuit can benefit from occupying a relatively low area on an integrated circuit, while still achieving leakage currents that are equivalent to a back-to-back switch implementation. In one or more embodiments, the cell balancing FET is the only FET that is connected between the first battery connection terminal and the second battery connection terminal.

[0008] In one or more embodiments, the FET control circuit comprises: a lowest-of-supply node; and a gate pull-down switch that is connected between the lowest-of-supply node and the gate terminal of the cell balancing FET.

[0009] In one or more embodiments, the body terminal of the cell balancing FET is connected to the lowest-of-supply node.

[0010] In one or more embodiments, the FET control circuit comprises: a first battery connection switch that is connected between the first battery connection terminal and the lowest-of-supply node; a second battery connection switch that is connected between the second battery connection terminal and the lowest-of-supply node; and an LOS node control circuit that is configured to: close the first battery connection switch and open the second battery connection switch when the voltage level at the first battery connection terminal is lower than the voltage level at the second battery connection terminal; and open the first battery connection switch and close the second battery connection switch when the voltage level at the first battery connection terminal is higher than the voltage level at the second battery connection terminal.

[0011] In one or more embodiments, the LOS node control circuit comprises: an amplifier that is configured to: compare the voltage level at the first battery connection terminal with the voltage level at the second battery connection terminal; provide a first amplifier output signal to a control terminal of the first battery connection switch in order to: i) close the first battery connection switch when the voltage level at the first battery connection terminal is lower than the voltage level at the second battery connection terminal; and ii) open the first battery connection switch when the voltage level at the first battery connection terminal is higher than the voltage level at the second battery connection terminal; and provide a second amplifier output signal to a control terminal of the second battery connection switch in order to: i) open the second battery connection switch when the voltage level at the first battery connection terminal is lower than the voltage level at the second battery connection terminal; and ii) close the second battery connection switch when the voltage level at the first battery connection terminal is higher than the voltage level at the second battery connection terminal.

[0012] In one or more embodiments, the amplifier is a hysteresis amplifier.

[0013] In one or more embodiments, the FET control circuit further comprises a gate pull-up switch that is connected between a supply voltage terminal and the gate terminal of the cell balancing FET.

[0014] There is also disclosed a battery management system, BMS, comprising: any switching circuit disclosed herein; a battery cell having a first battery terminal and a second battery terminal; a first balancing resistor that is connected in series between the first battery connection terminal and the first battery terminal; and a second balancing resistor that is connected in series between the second battery connection terminal and the second battery terminal.

[0015] While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that other embodiments, beyond the particular embodiments described, are possible as well. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are covered as well.

[0016] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future Claim sets. The figures and Detailed Description that follow also exemplify various example embodiments. Various example embodiments may be more completely understood in consideration of the following Detailed Description in connection with the accompanying Drawings.

[0017] Brief Description of the Drawings

[0018] One or more embodiments will now be described by way of example only with reference to the accompanying drawings in which:

[0019] Figure 1 shows an example of a cell balancing switch;

[0020] Figure 2 shows a back-to-back cell balancing switch;

[0021] Figure 3 shows an example embodiment of a switching circuit for cell balancing in a BMS according to the present disclosure;

[0022] Figure 4 shows a Direct Power Injection "DPI" simulation bench; and Figure 5 shows simulation results.

[0023] Detailed Description

[0024] In a battery management system (BMS), it is possible to perform passive cell balancing with an IC (integrated circuit) integrated switch. This switch can have a very low on-resistance (which can be referred to as Rdson when a FET is used as the switch; i.e., the resistance between the drain and the source when the FET is switched on), such as 0.25 Ohms. Advantageously, such a low on- resistance can result in minimal heat dissipation in the IC during when the switch is closed and cell balancing is activated. The leakage through this switch has a significant impact on the accuracy of cell measurement, which is a crucial aspect of the BMS. Moreover, this switch should have minimal leakage even if the battery cell is replaced by a busbar. When the battery cell is replaced by a busbar, it can result in a negative voltage across the switch when current is drawn from the battery pack that includes the battery cell. If a single MOS was used as a switch, an undesirable leakage current will flow through its body diode if a busbar is used such that a negative voltage exists across the switch. Such a busbar can simply be a metal wire that is used in place of a battery cell. When current is drawn from the battery pack, the busbar can create up to -3V across the switch due to its resistance.

[0025] Figure 1 shows an example of a cell balancing switch 102, which in Figure 1 is a MOSFET (metal oxide semiconductor field effect transistor). In an EMI (electromagnetic interference) polluted environment, transient voltages can be imposed on the battery cell's DC level and injected upon the switch 102. Also, a leakage current (Leak) can occur when the cell balancing switch 102 is connected to a busbar. The negative leakage current (Ipeak) passes through the body diode of the MOSFET 102. Using a single MOS switch with a single body diode (Figi) would lead to a DC shift if: the EMI levels go into the negative; and / or the switch 102 is connected to a busbar. As shown on the right-hand side of Figure 1, this results in a DC voltage shift / offset 103, which in turn causes clipping for the negative part of the alternating voltage waveform that is shown in Figure 1. This would highly impact the achievable accuracy of the cell voltage measurement accuracy, which is dire for the BMS performance and may cause safety issues.

[0026] Figure 2 shows a back-to-back cell balancing switch 204, which limits the negative leakage current and prevents the DC voltage shift that is shown in Figure 1.

[0027] However, the area required on the integrated circuit to implement the back- to-back cell balancing switch 204 of Figure 2 is 4 times greater than the cell balancing switch of Figure 1. Furthermore, in some applications there can be 18 cell balancing switches on a single integrated circuit, in which case the total area of those switches increases substantially.

[0028] Figure 3 shows an example embodiment of a switching circuit 305 for cell balancing in a BMS according to the present disclosure. The switching circuit 305 includes a first battery connection terminal (CBH - cell balancing high) 306 and a second battery connection terminal (CBL 0 cell balancing low) 307. The first battery connection terminal 306 is for connecting to a first battery terminal, in this example a positive terminal of a battery cell 308. The second battery connection terminal 307 is for connecting to a second battery terminal, in this example a negative terminal of the battery cell 308.

[0029] The switching circuit 305 includes a cell balancing field effect transistor, FET, 309 that is connected between the first battery connection terminal 306 and the second battery connection terminal 307. More particularly, a conduction channel of the cell balancing FET 309 is connected in series between the first battery connection terminal 306 and the second battery connection terminal 307. In this example, as shown in Figure 3, the cell balancing FET 309 is the only FET that is connected between the first battery connection terminal 306 and the second battery connection terminal 307. That is, a back-to-back arrangement, such as the one illustrated in Figure 2, is not required.

[0030] The cell balancing FET 309 has a gate terminal, a drain terminal, a source terminal and a body terminal. The drain terminal is connected to the first battery connection terminal 306. The source terminal is connected to the second battery connection terminal. In Figure 3 an NMOS cell balancing FET 309 is shown. However, it will be appreciated that in other examples a PMOS cell balancing FET can be used instead, and that the necessary changes to the circuit can be made to accommodate the different type of FET.

[0031] The switching circuit 305 also includes a FET control circuit 310. As will be discussed in detail below, the FET control circuit 310 connects the gate terminal and the body terminal of the cell balancing FET 309 to the battery connection terminal 306, 307 that has the lowest voltage. This lowest voltage will be referred to as the lowest of supply (LOS). In this way, since the body terminal of the cell balancing FET 309 is tied to the LOS, the body diode is set to block any incoming leakage currents. Therefore, advantageously, a highly accurate BMS can be achieved.

[0032] The FET control circuit 310 includes a lowest-of-supply node (LOS) 311, which, as will be discussed below, is set at a voltage level that corresponds to the lower one of the voltages at the first battery connection terminal 306 and the second battery connection terminal 307. The FET control circuit 310 also includes a gate pull-down switch (MPD_swi) 312 that is connected between the lowest-of-supply node (LOS) 311 and the gate terminal of the cell balancing FET 309. More particularly, the conduction channel of the gate pull-down switch (MpD swi) 312 is connected in series between the gate terminal of the cell balancing FET 309 and the lowest-of-supply node (LOS) 311. In this way, the gate pull-down switch (MPD_swi) 312 can selectively connect the gate terminal of the cell balancing FET 309 to the lowest-of-supply node (LOS) 311.

[0033] The FET control circuit 310 also includes a gate pull-up switch (MPU_swi) 314 that is connected between a supply voltage terminal 313 and the gate terminal of the cell balancing FET 309. More particularly, the conduction channel of the gate pull-up switch (MPU_swi) 314 is connected in series between the supply voltage terminal 313 and the gate terminal of the cell balancing FET 309. In this way, the gate pull-up switch (MPU_swi) 314 can selectively connect the gate terminal of the cell balancing FET 309 to a supply voltage. As is known in the art, the gate pull-down switch (MPD_swi) 312 and the gate pull-up switch (MPU_swi) 314 are controlled by complementary control signals such that they are not both closed or open at the same time. In this example, the voltage level at the supply voltage terminal 313 is set at 5V above the voltage at the second battery connection terminal 307 (CBL + 5V).

[0034] The body terminal of the cell balancing FET 309 is connected directly to the lowest-of-supply node (LOS) 311 in this example.

[0035] The FET control circuit 310 also includes a first battery connection switch (Ml) 315, a second battery connection switch (M2) 316 and an LOS node control circuit 317 for controlling these switches. The first battery connection switch (Ml) 315 is connected between the first battery connection terminal (CBH) 306 and the lowest-of-supply node (LOS) 311. The second battery connection switch (M2) 316 is connected between the second battery connection terminal (CBL) 307 and the lowest-of-supply node (LOS) 311. The LOS node control circuit 317 is operable to:

[0036] • close the first battery connection switch (Ml) 315 and open the second battery connection switch (M2) 316 when the voltage level at the first battery connection terminal (CBH) 306 is lower than the voltage level at the second battery connection terminal (CBL) 307; and • open the first battery connection switch (Ml) 315 and close the second battery connection switch (M2) 316 when the voltage level at the first battery connection terminal (CBH) 306 is higher than the voltage level at the second battery connection terminal (CBL) 307.

[0037] In the example of Figure 3, the LOS node control circuit 317 is provided as an amplifier. The amplifier compares the voltage level at the first battery connection terminal (CBH) 306 with the voltage level at the second battery connection terminal (CBL) 307. The amplifier can then provide a first amplifier output signal (Vom) and a second amplifier output signal (Vop) to respective control terminals of the first and second battery connection switches (Ml, M2) 315. 316.

[0038] The first amplifier output signal (Vom) is provided to the control terminal of the first battery connection switch (Ml) 315 in order to: i) close the first battery connection switch (Ml) 315 when the voltage level at the first battery connection terminal (CBH) 306 is lower than the voltage level at the second battery connection terminal (CBL) 307; and ii) open the first battery connection switch (Ml) 315 when the voltage level at the first battery connection terminal (CBH) 306 is higher than the voltage level at the second battery connection terminal (CBL) 307.

[0039] The second amplifier output signal (Vop) is provided to the control terminal of the second battery connection switch (M2) 316 in order to: i) open the second battery connection switch (M2) 316 when the voltage level at the first battery connection terminal (CBH) 306 is lower than the voltage level at the second battery connection terminal (CBL) 307; and ii) close the second battery connection switch (M2) 316 when the voltage level at the first battery connection terminal (CBH) 306 is higher than the voltage level at the second battery connection terminal (CBL) 307.

[0040] Beneficially, in this example the amplifier is a hysteresis amplifier such that it implements hysteresis when changing the polarity of the first and second amplifier output signals (Vop, Vom). An important aspect of the circuit of Figure 3 is that a single MOSFET 309 can be used as a cell balancing switch (MSWi). The gate pull-up switch (MPU_swi) 314 and the gate pull-down switch (MPD_swi) 312 are used to turn ON and OFF the MOSFET 309. When the voltage at the first battery connection terminal 306 is greater than the voltage at the second battery connection terminal 307 (i.e., CBH >CBL), which reflects the case of a battery cell or positive busbar (current injected into the battery pack), the hysteresis amplifier 317 (which can also be referred to as a hysteresis comparator) turns the second battery connection switch (M2) 316 ON and turns the first battery connection switch (Ml) 315 OFF. This allows the gate of the cell balancing FET 309 to be pulled down by the gate pull-down switch (MPD_swi) 312 to the lowest of supply (LOS). By doing so, since the body of the cell balancing FET 309 is tied to LOS, the body diode is set to block the incoming leakage from the 306. Conversely, if the voltage at the first battery connection terminal 306 is less than the voltage at the second battery connection terminal 307 (i.e., CBH<CBL), which can happen in the case of a negative busbar voltage (current drawn from the battery pack), then the second battery connection switch (M2) 316 is OFF and the first battery connection switch (Ml) 315 is ON. This allows the gate of the cell balancing FET 309 to be pulled down by the gate pull-down switch (MPD_swi) 312 to LOS, which in this case is the first battery connection terminal 306. By doing so, since the body of the cell balancing FET 309 is tied to LOS, the body diode is set to block the incoming leakage from the second battery connection terminal 307.

[0041] In Figure 3, a single MOSFET is used as a cell balancing switch, whose body is connected either to the source or drain depending on the polarity of a busbar. Thus, this single MOSFET switch has a blocking diode that limits the leakage in all cases. More importantly, this drive automatically follows the polarity changes across the switch to turn the MOSFET OFF correctly and limit the leakage by connecting the body either to the source or drain of the MOSFET depending on the polarity of whatever the switch is shorting. Finally, this drive is also capable of setting its own ground in order to keep functioning correctly.

[0042] The circuits of Figure 3 and Figure 2 were tested in terms of induced DC shift in a harsh DPI environment. Figure 4 shows the setup that was used to simulate DPI, where the switching circuit 405 was either the circuit of Figure 3 or the circuit of Figure 2.

[0043] It was found that the circuit of Figure 3 results in a very comparable DC shift to the back-to-back switch of Figure 2. However, the circuit of Figure 3 requires significantly less area on the IC.

[0044] In order to perform the comparison, the following setup was implemented:

[0045] • DPI is applied to both the designs with a 30 dBm level coupled onto the IC through PCB (printed circuit board) traces which were modelled appropriately.

[0046] • 30 dBm is injected differentially to generate high amplitude levels across the switch. High enough to have negative oscillations in order to test the circuit of Figure 3 and compare it.

[0047] • 40 points per decade was considered in the range of [150kHz; 1GHz] to cover as many frequencies as possible and resonances.

[0048] • 2000 periods were simulated for each frequency to be sure that the permanent regime has been reached.

[0049] • The voltage of the battery cell (represented by a voltage source in Figure 4) was given the lowest value that a cell can take, which is around 2V so that the oscillations across the switch can go negative (below 0V).

[0050] • The DC value of the oscillations across the switch is calculated and averaged over the last 50 periods of the simulation. Then the delta between this quantity and the cell voltage (2V) is calculated and compared.

[0051] Figure 5 shows the results of the tests. A first plot (shown as a dot-dashed line) 560 is the DC value of the oscillations generated across the switch for the circuit of Figure 3 minus the cell voltage (2V). A second plot (shown as a dashed line) 561 is the DC shift value generated by the oscillations across the switch for the circuit of Figure 2 minus the cell voltage (2V). As can be seen, the DC shifts of both circuits are very comparable, which means that the same results can be achieved with just one the one MOSFET of Figure 3 instead of multiplying the area by 4 by using a back-to-back circuit such as the one of Figure 2. Furthermore, @1.125 MHZ both circuits fail due to the very high injection levels. In most of the rest of the frequency range, the DC shifts match. In fact, starting from 100 MHz, the circuit of Figure 3 does not fail whereas the DC shift for the circuit of Figure 2 reaches very high values.

[0052] Returning to Figure 3, a first balancing resistor 322 is connected in series between the first battery connection terminal (CBH) 306 and the first battery terminal of the battery cell 308. Also, a second balancing resistor 323 is connected in series between the second battery connection terminal (CBL) 307 and the second battery terminal of the battery cell 308. Therefore, examples disclosed herein relate to a BMS that includes:

[0053] • any of the switching circuits disclosed herein;

[0054] • a battery cell 308 having a first battery terminal and a second battery terminal;

[0055] • a first balancing resistor 322 that is connected in series between the first battery connection terminal (CBH) 306 and the first battery terminal; and

[0056] • a second balancing resistor 323 that is connected in series between the second battery connection terminal (CBL) 307 and the second battery terminal.

[0057] Advantages associated with the switching circuits disclosed herein can include one or more of:

[0058] • A reduction of area on the integrated circuit, which can be a reduction by as much as 1mm2.

[0059] • The leakage of the switching circuits disclosed herein can be equivalent to a back-to-back switch implementation.

[0060] • A drive that can successfully turn off the cell balancing MOS in the case of fast busbar polarity change by connecting its gate: to the source if a positive voltage is across the switch; and to the drain if a negative voltage is across the switch.

[0061] • A drive that can successfully connect the body either to the source or the drain depending on the fast changing polarity across the switch in order to the oppose the leakage current with a blocking body-to-source or body-to-drain diode. • Controlling the body in a fast polarity change across the switch through a hysteresis comparator.

[0062] • Enabling passive cell balancing with one MOS while having the possibility to manage a busbar in case the consumer chooses to put some busbars in the pack (randomly).

[0063] • Dynamically tying the body and gate of the single MOS balancing switch to the lowest potential out of the source and drain depending on the polarity of electromagnetic interference (EMI) oscillations across the switch.

[0064] • Improved electromagnetic compatibility (EMC) with very little IC area cost.

[0065] • Comparable DC shifts as the back to back solution.

[0066] • Improved accuracy measurements in highly EMI polluted environments with very little IC area cost.

[0067] • A drive configuration capable of setting the gate and body of the single MOS switch to the lowest transient voltage (drain or source) in order to keep the switch OFF and prevent it from causing any DC shift in the entirety of the DPI frequency range [150 kHz; 1GHZ] even if the drive configuration includes a bandwidth-limited hysteresis amplifier.

[0068] Advantageously, one or more of the embodiments disclosed herein enables passive cell balancing with one MOS switch with the capability to impede both positive and negative leakage current in case the consumer chooses to replace a battery cell in the pack with a busbar.

[0069] Any of the switching circuits disclosed herein can be used in the battery cell controllers (BCC) and battery management systems (BMS), especially in an EMI polluted environment as can be the case with electric cars.

[0070] The instructions and / or flowchart steps in the above figures can be executed in any order, unless a specific order is explicitly stated. Also, those skilled in the art will recognize that while one example set of instructions / method has been discussed, the material in this specification can be combined in a variety of ways to yield other examples as well, and are to be understood within a context provided by this detailed description. In some example embodiments the set of instructions / method steps described above are implemented as functional and software instructions embodied as a set of executable instructions which are effected on a computer or machine which is programmed with and controlled by said executable instructions. Such instructions are loaded for execution on a processor (such as one or more CPUs). The term processor includes microprocessors, microcontrollers, processor modules or subsystems (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor can refer to a single component or to plural components.

[0071] In other examples, the set of instructions / methods illustrated herein and data and instructions associated therewith are stored in respective storage devices, which are implemented as one or more non-transient machine or computer- readable or computer-usable storage media or mediums. Such computer- readable or computer usable storage medium or media is (are) considered to be part of an article (or article of manufacture). An article or article of manufacture can refer to any manufactured single component or multiple components. The non-transient machine or computer usable media or mediums as defined herein excludes signals, but such media or mediums may be capable of receiving and processing information from signals and / or other transient mediums.

[0072] Example embodiments of the material discussed in this specification can be implemented in whole or in part through network, computer, or data based devices and / or services. These may include cloud, internet, intranet, mobile, desktop, processor, look-up table, microcontroller, consumer equipment, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0073] In one example, one or more instructions or steps discussed herein are automated. The terms automated or automatically (and like variations thereof) mean controlled operation of an apparatus, system, and / or process using computers and / or mechanical / electrical devices without the necessity of human intervention, observation, effort and / or decision. It will be appreciated that any components said to be coupled may be coupled or connected either directly or indirectly. In the case of indirect coupling, additional components may be located between the two components that are said to be coupled.

[0074] In this specification, example embodiments have been presented in terms of a selected set of details. However, a person of ordinary skill in the art would understand that many other example embodiments may be practiced which include a different selected set of these details. It is intended that the following claims cover all possible example embodiments.

Claims

CLAIMS1. A switching circuit for cell balancing in a battery management system, BMS, the switching circuit comprising: a first battery connection terminal, for connecting to a first battery terminal; a second battery connection terminal, for connecting to a second battery terminal; a cell balancing field effect transistor, FET, comprising: a gate terminal; a drain terminal connected to the first battery connection terminal; a source terminal connected to the second battery connection terminal; and a body terminal; a FET control circuit that is configured to connect the gate terminal and the body terminal of the cell balancing FET to the battery connection terminal that has the lowest voltage.

2. The switching circuit of claim 1, wherein the cell balancing FET is the only FET that is connected between the first battery connection terminal and the second battery connection terminal.

3. The switching circuit of claim 1 or claim 2, wherein: the FET control circuit comprises: a lowest-of-supply node; and a gate pull-down switch that is connected between the lowest-of- supply node and the gate terminal of the cell balancing FET; and the body terminal of the cell balancing FET is connected to the lowest- of-supply node.

4. The switching circuit of claim 3, wherein: the FET control circuit comprises: a first battery connection switch that is connected between the first battery connection terminal and the lowest-of-supply node; a second battery connection switch that is connected between the second battery connection terminal and the lowest-of-supply node; and an LOS node control circuit that is configured to: close the first battery connection switch and open the second battery connection switch when the voltage level at the first battery connection terminal is lower than the voltage level at the second battery connection terminal; and open the first battery connection switch and close the second battery connection switch when the voltage level at the first battery connection terminal is higher than the voltage level at the second battery connection terminal.

5. The switching circuit of claim 4, wherein the LOS node control circuit comprises: an amplifier that is configured to: compare the voltage level at the first battery connection terminal with the voltage level at the second battery connection terminal; provide a first amplifier output signal to a control terminal of the first battery connection switch in order to: i) close the first battery connection switch when the voltage level at the first battery connection terminal is lower than the voltage level at the second battery connection terminal; and ii) open the first battery connection switch when the voltage level at the first battery connection terminal is higher than the voltage level at the second battery connection terminal; and provide a second amplifier output signal to a control terminal of the second battery connection switch in order to: i) open the second battery connection switch when the voltage level at the first battery connection terminal is lower than the voltage level at the second battery connection terminal; and ii) close the second battery connection switch when the voltage level at the first battery connection terminal is higher than the voltage level at the second battery connection terminal.

6. The switching circuit of claim 5, wherein the amplifier is a hysteresis amplifier.

7. The switching circuit of any preceding claim, wherein the FET control circuit further comprises a gate pull-up switch that is connected between a supply voltage terminal and the gate terminal of the cell balancing FET.

8. A battery management system, BMS, comprising: the switching circuit of any preceding claim; a battery cell having a first battery terminal and a second battery terminal; a first balancing resistor that is connected in series between the first battery connection terminal and the first battery terminal; and a second balancing resistor that is connected in series between the second battery connection terminal and the second battery terminal.

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