Contour-based framework for monitoring and evaluating process quality and variation

Abstract

A method of monitoring and evaluating a wafer fabrication process variation using a characteristic of extracted two-dimensional measurement data of a fabricated feature on a wafer is disclosed. Two-dimensional measurement data may be determined without using a physical measurement or a mathematical model and does not rely on any prior assumption on how a process variation should behave. A wafer map may be generated to identify a spatial distribution of an impact of fabrication process variation on a fabricated feature. The extracted two-dimensional measurement of fabricated features may be combined and engineered to obtain more insight of the fabrication process and lead to the possibility of classification based on contour quality, modeling of process windows, and other wafer fabrication modeling applications.

Description

CONTOUR-BASED FRAMEWORK FOR MONITORING AND EVALUATING PROCESS QUALITY AND VARIATIONCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of US application 63 / 612,799 which was filed on 20 December 2023 and which is incorporated herein in its entirety by reference.FIELD

[0002] The embodiments provided herein disclose a method of monitoring and evaluating wafer fabrication process variation using a characteristic of a two-dimensional contour of a fabricated pattern on a wafer.BACKGROUND

[0003] A lithographic apparatus is a machine that applies a desired pattern onto a target portion of a substrate. The lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). An IC chip in a smart phone can be as small as a person’s thumbnail and may include over 2 billion transistors. Making an IC is a complex and time-consuming process, with circuit components in different layers and including hundreds of individual steps. Errors in even one step may potentially result in problems with the final IC and may cause device failure. Therefore, in manufacturing processes of ICs, unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and are free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes, such as a scanning electron microscope (SEM) can be employed. As the physical sizes of IC components continue to shrink, accuracy and yield in IC inspection become increasingly important. High process yield and high wafer throughput can be impacted by the presence of defects, especially if physical testing is required for reviewing the defects. Therefore, monitoring and identifying lithographic conditions that may induce formation of defects during fabrication of ICs is desired.SUMMARY

[0004] The embodiments provided herein disclose a method of monitoring and evaluating a wafer fabrication process variation using a characteristic of extracted two-dimensional measurement data of a fabricated feature on a wafer.

[0005] Some embodiments of the present disclosure provide a method for evaluating a wafer fabrication process condition. In some embodiments, the method comprises obtaining a first image of a sample, extracting a contour from the first image, wherein the contour comprises discrete data points, calculating a characteristic based on the contour, evaluating a fabrication process variation based on the characteristic.

[0006] In some embodiments, a non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for evaluating a wafer fabrication process condition is provided. In some embodiments, the operations comprise obtaining a first image of a sample, extracting a contour from the first image, wherein the contour comprises discrete data points, calculating a characteristic based on the contour, evaluating a fabrication process variation based on the characteristic.

[0007] In some embodiments, a system using a computational model to monitor a wafer fabrication process condition is provided. In some embodiments, the system comprises one or more processors configured to execute instructions to cause the system to perform operations comprising obtaining a first image of a sample, extracting a contour from the first image, wherein the contour comprises discrete data points, calculating a characteristic based on the contour, evaluating a fabrication process variation based on the characteristic.

[0008] Other advantages of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present disclosure.BRIEF DESCRIPTION OF FIGURES

[0009] The above and other aspects of the present disclosure will become more apparent from the description of exemplary embodiments, taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a schematic diagram illustrating an example lithographic projection assembly to fabricate an IC, consistent with embodiments of the present disclosure.

[0011] FIG. 2 is a schematic diagram illustrating an example electron beam inspection (EBI) system, consistent with embodiments of the present disclosure.

[0012] FIG. 3 is a schematic diagram of an example multi-beam tool, consistent with embodiments of the present disclosure.

[0013] FIG. 4 is an example block diagram for generating input data for a conventional method.

[0014] FIG. 5 is an example wafer map generated according to a conventional method.

[0015] FIG. 6A is an example illustration of IC structures imaged in a die on a wafer.

[0016] FIG. 6B is an illustration of example wafer maps generated based on averaged CD measurements of a contact hole.

[0017] FIG. 7 is an example block diagram for generating input data, consistent with embodiments of the present disclosure.

[0018] FIG. 8 is an illustration of extracting two-dimensional information from a fabricated IC structure, consistent with embodiments of the present disclosure.

[0019] FIG. 9A is an illustration of an example reference -based approach comparison between design data and two-dimensional measurement data, consistent with embodiments of the present disclosure.

[0020] FIG. 9B is an illustration of an example non-reference-based approach for two-dimensional measurement data, consistent with embodiments of the present disclosure.

[0021] FIG. 10 is an example workflow for building a wafer map to evaluate a fabrication process variation or quality corresponding to two-dimensional measurement data according to a referenced- based approach, consistent with embodiments of the present disclosure.

[0022] FIG. 11 is an example workflow for building a wafer map to evaluate a process variation or quality corresponding to two-dimensional measurement data according to a non-referenced-based approach a, consistent with embodiments of the present disclosure.

[0023] FIGs. 12A-P are example illustrations of generated wafer maps representing spatial distribution of an averaged characteristic of an extracted contour across a wafer, consistent with embodiments of the present disclosure.

[0024] FIG. 13 is an example flow diagram illustrating a method of extracting two-dimensional measurement data from an IC structure to monitor a lithographic fabrication process variation, consistent with embodiments of the present disclosure.DETAILED DESCRIPTION

[0025] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the invention. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the invention as recited in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, the disclosure is not so limited. Other types of charged particle beams may be similarly applied. Furthermore, other imaging systems may be used, such as optical imaging, photo detection, x-ray detection, etc.

[0026] The enhanced computing power of electronic devices, while reducing the physical size of the devices, can be accomplished by significantly increasing the packing density of circuit components such as transistors, capacitors, diodes, etc. on an IC chip. For example, an IC chip of a smart phone, which is the size of a thumbnail, may include over 2 billion transistors, the size of each transistor being less than l / 1000th of a human hair. Thus, it is not surprising that semiconductor IC manufacturing is a complex and time-consuming process, with hundreds of individual steps. Errors in even one step have the potential to dramatically affect the functioning of the final product. Even one “killer defect” can cause device failure. The goal of the manufacturing process is to improve the overall yield of the process. For example, for a 50-step process to get to a 75% yield, each individual step must have a yield greater than 99.4%, and if the individual step yield is 95%, the overall process yield drops to 7%.

[0027] While high process yield is desirable in an IC chip manufacturing facility, maintaining a high wafer throughput, defined as the number of wafers processed per hour, is also essential. High process yields and high wafer throughput can be impacted by the presence of defects, especially if operator intervention is required for reviewing the defects. Moreover, the number of transistors fabricated onto an IC chip is forecasted to grow from billions up to one trillion by 2030. Thus, high throughput detection and identification of micro and nano-sized defects by inspection tools (such as a charged particle beam inspection tool) is essential for maintaining high yields and low cost. Inspection of a wafer using an electron beam inspection tool may generate images of the wafer to measure IC structure dimensions. The measured dimensions may be compared to a reference structure absent any defects to determine the presence of defects in the imaged structure. However, inspection of ICs for defect detection is often a time-consuming process. It may be desirable to prevent defects from occurring during the fabrication stages instead of further refining IC inspection methods. Therefore, it is desired to monitor and evaluate lithographic fabrication conditions that may induce defects in a fabricated IC structure.

[0028] ICs may be manufactured using lithography, which is a fabrication process involving creating complex circuit patterns drawn on a mask deposited onto a substrate. Lithography may be performed by a lithographic apparatus, which is a machine that applies a source of radiation (e.g., light or X-ray) onto a target portion of the substrate to form a desired pattern. The target portion of the substrate may be covered with a pattern device (e.g., mask) that may be either eliminated or developed after exposure to the radiation source. This process of transferring the desired pattern to the substrate is called a patterning process. The patterning process may include a patterning step to transfer a pattern from a pattern device (e.g., a mask) to the substrate. There can also be one or more related pattern processing steps, such as mask development by a development apparatus, baking of the substrate using a bake tool, etching the pattern onto the substrate using an etch apparatus, or other chemical and physical processing steps involved in fabricating a pattern onto the substrate. Variations in experimental parameters (e.g., stochastic variations, errors, or noise due to an inspection tool or pattern processing tool) can potentially limit lithography implementation for high volume manufacturing (HVM), or process yield, of ICs and introduce defects into IC structures.

[0029] In the manufacture of ICs using a lithographic apparatus, typically many lithographic patterning steps are performed, thereby forming functional features in successive layers on the substrate. A critical aspect of performance of the lithographic apparatus is therefore the ability to place the applied pattern correctly and accurately in relation to features laid down in previous layers. For this purpose, the substrate is provided with one or more sets of alignment marks. Each mark is a structure whose position can be measured later using, for example, an electron beam inspection tool. Defects may occur in which an applied pattern structure or pattern layer is incorrectly placed in relation to a reference mark, or when the fabrication conditions are suboptimal. A reference mark or layout define the desired structure, structure dimensions, and the distance between IC structures (such as gates, capacitors, etc.) or interconnect lines. This may ensure that the IC devices or lines do not interact with one another in anundesirable way. The structure limitations provided by the reference layouts are typically referred to as critical dimensions. A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the critical dimension determines the overall size and packing density of the designed IC. A goal in IC fabrication is to faithfully reproduce the original IC design on the substrate. If an error occurs during fabrication where the created IC design pattern does not match the reference design, this may result in a defect in the IC structure and render the IC inoperable.

[0030] As mentioned above, high throughput of IC fabrication with low amounts of structural defects is desired. Additionally, the number of transistors fabricated onto a wafer is projected to reach one trillion by 2030. As the fabrication process for such transistors becomes more complex and includes a larger number of steps, this may increase fabrication process variation and introduce more defects. Additionally, scaling up production of semiconductors may introduce stochastic variation in the lithographic fabrication process. Stochasticity and process variation may introduce structural defects in a manufactured wafer such as dopant concentration fluctuation, pattern line edge roughness, edge placement error, and variation between structures intended to be identical, which may ultimately render the wafer inoperable. Therefore, the ability to accurately manufacture IC structures according to a desired design and fabrication conditions in lithography is desired. Furthermore, an accurate framework to monitor and evaluate both systematic and random variations at each step of the fabrication process to better understand the fabrication process, evaluate process quality, and enable process optimization to increase yield is desired. Current methods use parameterized mathematical and statistical models to fit and predict process variation and electrical measurements of a manufactured wafer to infer when a particular metric deviates from a specification value during the fabrication process (e.g., at a particular step during the fabrication process) or if the process overall induces structural defects into the manufactured wafer. However, the models relied on in conventional methods make assumptions on the sources and form of variations, but the variations are not directly measured. The assumptions made in conventional methods may be inaccurate and may draw a false hypothesis and false conclusion. Performing electrical measurements (e.g., resistance, frequency response time, time delay, etc.) may provide an accurate process equality evaluation, but to do so may require measuring thousands to millions of features on a fabricated wafer. Thus, this aspect of conventional methods is costly both in time and resources. Current methods also rely on critical dimension (CD) measurements of fabricated features to evaluate process quality. However, CD provides too little information about process variation and is susceptible to metrology error because CD is only a 1 -directional measurement. Therefore, CD measurements may result in incomplete or biased modeling of process variations in semiconductor manufacturing. Thus, using current methods relying on inappropriate models and measurements may result in an incomplete or biased evaluation of both systematic and random variations at each step of the fabrication process, inaccurate predictions of the fabrication process quality, and decreased wafer yields during high volume manufacturing (HVM).

[0031] Embodiments of the present disclosure provide a method to monitor and evaluate a wafer fabrication process variation using two-dimensional measurement data of a fabricated feature on a wafer. Some embodiments of the present disclosure may provide a method of extracting a contour from an image of a fabricated wafer and determining a characteristic of the contour. The characteristic may be used to characterize, analyze, and monitor the process variation. In some embodiments, the two- dimensional measurement data may be determined without using a physical measurement or a mathematical model and not rely on any prior assumption on how a process variation should behave. In some embodiments, an intrinsic shape characteristic of the two-dimensional measurement data may be extracted and used to evaluate a process quality or process variation. A wafer map may be generated to identify a spatial distribution of contours with specific feature characteristics. In some embodiments, the intrinsic shape characteristic of the two-dimensional measurement data may be compared to design data to evaluate process variation. Moreover, some embodiments of the present disclosure may increase throughput of IC manufacturing and confidence in predicting lithographic fabrication variations associated with a fabrication process or processing step to manufacture defect-free ICs.

[0032] Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described. As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a database can include A or B, then, unless specifically stated otherwise or infeasible, the database can include A, or B, or A and B. As a second example, if it is stated that a database can include A, B, or C, then, unless specifically stated otherwise or infeasible, the database can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0033] Reference is now made to FIG. 1, which is a schematic diagram illustrating an exemplary lithographic projection apparatus 100. Lithographic projection apparatus 100 may include an emission source 101, which may be a charged-particle emission source, deep-ultraviolet excimer laser source or other type of source including an extreme ultraviolet (EUV) source and emits a beam 108. Illumination optics which may include illumination optics components 102 and 103 that shape radiation from the radiation source 101; a patterning device 104; and transmission optics 105 that project an image of the patterning device pattern onto a substrate 106. An adjustable filter or aperture 107 at the pupil plane of the projection optics may restrict the range of beam angles that impinge on substrate 106, where the largest possible angle defines the numerical aperture of the projection optics NA=sin(0max) or region on substrate 106 where beam 108 impacts is called a target portion 109, in which the beam impacts the top layer or mask (not shown).

[0034] Illumination optics components 102 and 103 may direct and shape beam 108 via patterning device 104 onto substrate 106 and may include any optical component that may alter the wavefront of beam 108. A resist layer on substrate 106 may be exposed and a radiation intensity distribution atsubstrate 106 (i.e., an aerial image) may be transferred to the resist layer. Optical properties of the lithographic projection apparatus (e.g., properties of the source, the patterning device, and the projection optics) dictate this process. The resist layer may be removed and the applied pattern from beam 108 may then be applied to the substrate as discussed above.

[0035] Although reference may be made in the present disclosure to ICs, it is appreciated that the present disclosure may be applicable to other possible applications or designs. For example, the present disclosure may be applied to integrated optical systems, magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, and other nanoscale structures. It is further appreciated that the terms “reticle”, “wafer”, or “die” may be used interchangeably with the terms “mask”, “substrate” or “sample”, and “target portion”, respectively.

[0036] FIG. 2 illustrates an example electron beam inspection (EBI) system 200 consistent with embodiments of the present disclosure. EBI system 200 may be used for imaging. As shown in FIG. 2, EBI system 200 includes a main chamber 201, a load / lock chamber 202, a beam tool 204, and an equipment front end module (EFEM) 206. Beam tool 204 is located within main chamber 201. EFEM 206 includes a first loading port 206a and a second loading port 206b. EFEM 206 may include additional loading port(s). First loading port 206a and second loading port 206b receive wafer front opening unified pods (FOUPs) that contain wafers (e.g., semiconductor wafers or wafers made of other material(s)) or samples to be inspected (wafers and samples may be used interchangeably). A “lot” is a plurality of wafers that may be loaded for wafer processing as a batch.

[0037] One or more robotic arms (not shown) in EFEM 206 may transport the wafers to load / lock chamber 202. Load / lock chamber 202 is connected to a load / lock vacuum pump system (not shown) which removes gas molecules in load / lock chamber 202 to reach a first pressure below the atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) may transport the wafer from load / lock chamber 202 to main chamber 201. Main chamber 201 is connected to a main chamber vacuum pump system (not shown) which removes gas molecules in main chamber 201 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer is subject to inspection by beam tool 204. Beam tool 204 may be a single-beam system or a multi-beam system.

[0038] A controller 209 is electronically connected to beam tool 204. Controller 209 may be a computer configured to execute various controls of EBI system 200. While controller 209 is shown in FIG. 2 as being outside of the structure that includes main chamber 201, load / lock chamber 202, and EFEM 206, it is appreciated that controller 209 may be a part of the structure.

[0039] In some embodiments, controller 209 may include one or more processors (not shown). A processor may be a generic or specific electronic device capable of manipulating or processing information. For example, the processor may include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic(PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field- Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), a neural processing unit (NPU), and any type of circuit capable of data processing. The processor may also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.

[0040] In some embodiments, controller 209 may further include one or more memories (not shown). A memory may be a generic or specific electronic device capable of storing codes and data accessible by the processor (e.g., via a bus). For example, the memory may include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or any type of storage device. The codes and data may include an operating system (OS) and one or more application programs (or “apps”) for specific tasks. The memory may also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.

[0041] FIG. 3 illustrates a schematic diagram of an example multi-beam tool 204 (also referred to herein as apparatus 204) and an image processing system 390 that may be configured for use in EBI system 200 (FIG. 2), consistent with embodiments of the present disclosure.

[0042] Beam tool 204 comprises a charged-particle source 302, a gun aperture 304, a condenser lens 306, a primary charged-particle beam 310 emitted from charged-particle source 302, a source conversion unit 312, a plurality of beamlets 314, 316, and 318 of primary charged-particle beam 310, a primary projection optical system 320, a motorized wafer stage 380, a wafer holder 382, multiple secondary charged-particle beams 336, 338, and 340, a secondary optical system 342, and a charged- particle detection device 344. Primary projection optical system 320 can comprise a beam separator 322, a deflection scanning unit 326, and an objective lens 328. Charged-particle detection device 344 can comprise detection sub-regions 346, 348, and 350.

[0043] Charged-particle source 302, gun aperture 304, condenser lens 306, source conversion unit 312, beam separator 322, deflection scanning unit 326, and objective lens 328 can be aligned with a primary optical axis 360 of apparatus 204. Secondary optical system 342 and charged-particle detection device 344 can be aligned with a secondary optical axis 352 of apparatus 204.

[0044] Charged-particle source 302 can emit one or more charged particles, such as electrons, protons, ions, muons, or any other particle carrying electric charges. In some embodiments, charged-particle source 302 may be an electron source. For example, charged-particle source 302 may include a cathode, an extractor, or an anode, wherein primary electrons can be emitted from the cathode and extracted or accelerated to form primary charged-particle beam 310 (in this case, a primary electron beam) with a crossover (virtual or real) 308. For ease of explanation without causing ambiguity, electrons are used as examples in some of the descriptions herein. However, it should be noted that any charged particle may be used in any embodiment of this disclosure, not limited to electrons. Primary charged-particlebeam 310 can be visualized as being emitted from crossover 308. Gun aperture 304 can block off peripheral charged particles of primary charged-particle beam 310 to reduce Coulomb effect. The Coulomb effect may cause an increase in size of probe spots.

[0045] Source conversion unit 312 can comprise an array of image-forming elements and an array of beam-limit apertures. The array of image-forming elements can comprise an array of micro-deflectors or micro-lenses. The array of image-forming elements can form a plurality of parallel images (virtual or real) of crossover 308 with a plurality of beamlets 314, 316, and 318 of primary charged-particle beam 310. The array of beam-limit apertures can limit the plurality of beamlets 314, 316, and 318. While three beamlets 314, 316, and 318 are shown in FIG. 3, embodiments of the present disclosure are not so limited. For example, in some embodiments, the apparatus 204 may be configured to generate a first number of beamlets. In some embodiments, the first number of beamlets may be in a range from 1 to 1000. In some embodiments, the first number of beamlets may be in a range from 200-500. In an exemplary embodiment, the apparatus 204 may generate 400 beamlets.

[0046] Condenser lens 306 can focus primary charged-particle beam 310. The electric currents of beamlets 314, 316, and 318 downstream of source conversion unit 312 can be varied by adjusting the focusing power of condenser lens 306 or by changing the radial sizes of the corresponding beam-limit apertures within the array of beam-limit apertures. Objective lens 328 can focus beamlets 314, 316, and 318 onto a wafer 330 for imaging, and can form a plurality of probe spots 370, 372, and 374 on a surface of wafer 330.

[0047] Beam separator 322 can be a beam separator of Wien filter type generating an electrostatic dipole field and a magnetic dipole field. In some embodiments, if they are applied, the force exerted by the electrostatic dipole field on a charged particle (e.g., an electron) of beamlets 314, 316, and 318 can be substantially equal in magnitude and opposite in a direction to the force exerted on the charged particle by magnetic dipole field. Beamlets 314, 316, and 318 can, therefore, pass straight through beam separator 322 with zero deflection angle. However, the total dispersion of beamlets 314, 316, and 318 generated by beam separator 322 can also be non-zero. Beam separator 322 can separate secondary charged-particle beams 336, 338, and 340 from beamlets 314, 316, and 318 and direct secondary charged-particle beams 336, 338, and 340 towards secondary optical system 342.

[0048] Deflection scanning unit 326 can deflect beamlets 314, 316, and 318 to scan probe spots 370, 372, and 374 over a surface area of wafer 330. In response to the incidence of beamlets 314, 316, and 318 at probe spots 370, 372, and 374, secondary charged-particle beams 336, 338, and 340 may be emitted from wafer 330. Secondary charged-particle beams 336, 338, and 340 may comprise charged particles (e.g., electrons) with a distribution of energies. For example, secondary charged-particle beams 336, 338, and 340 may be secondary electron beams including secondary electrons (energies < 50 eV) and backscattered electrons (energies between 50 eV and landing energies of beamlets 314, 316, and 318). Secondary optical system 342 can focus secondary charged-particle beams 336, 338, and 340 onto detection sub-regions 346, 348, and 350 of charged-particle detection device 344. Detection sub-regions346, 348, and 350 may be configured to detect corresponding secondary charged-particle beams 336, 338, and 340 and generate corresponding signals (e.g., voltage, current, or the like) used to reconstruct an SCPM image of structures on or underneath the surface area of wafer 330.

[0049] The generated signals may represent intensities of secondary charged-particle beams 336, 338, and 340 and may be provided to image processing system 390 that is in communication with charged- particle detection device 344, primary projection optical system 320, and motorized wafer stage 380. The movement speed of motorized wafer stage 380 may be synchronized and coordinated with the beam deflections controlled by deflection scanning unit 326, such that the movement of the scan probe spots (e.g., scan probe spots 370, 372, and 374) may orderly cover regions of interests on the wafer 330. The parameters of such synchronization and coordination may be adjusted to adapt to different materials of wafer 330. For example, different materials of wafer 330 may have different resistance-capacitance characteristics that may cause different signal sensitivities to the movement of the scan probe spots.

[0050] The intensity of secondary charged-particle beams 336, 338, and 340 may vary according to the external or internal structure of wafer 330, and thus may indicate whether wafer 330 includes defects. Moreover, as discussed above, beamlets 314, 316, and 318 may be projected onto different locations of the top surface of wafer 330, or different sides of local structures of wafer 330, to generate secondary charged-particle beams 336, 338, and 340 that may have different intensities. Therefore, by mapping the intensity of secondary charged-particle beams 336, 338, and 340 with the areas of wafer 330, image processing system 390 may reconstruct an image that reflects the characteristics of internal or external structures of wafer 330.

[0051] In some embodiments, image processing system 390 (which may be part of controller 209) may include an image acquirer 392, a storage 394, and a controller 396. Image acquirer 392 may comprise one or more processors. For example, image acquirer 392 may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, or the like, or a combination thereof. Image acquirer 392 may be communicatively coupled to charged-particle detection device 344 of beam tool 204 through a medium such as an electric conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, or a combination thereof. In some embodiments, image acquirer 392 may receive a signal from charged-particle detection device 344 and may construct an image. Image acquirer 392 may thus acquire SCPM images of wafer 330. Image acquirer 392 may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, or the like. Image acquirer 392 may be configured to perform adjustments of brightness and contrast of acquired images. In some embodiments, storage 394 may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), other types of computer-readable memory, or the like. Storage 394 may be coupled with image acquirer 392 and may be used for saving scanned raw image data as original images, and post-processed images. Image acquirer 392 and storage 394 may be connected to controller 396. In some embodiments, image acquirer 392, storage 394, and controller 396 may be integrated together as one control unit.

[0052] In some embodiments, image acquirer 392 may acquire one or more SCPM images of a wafer based on an imaging signal received from charged-particle detection device 344. An imaging signal may correspond to a scanning operation for conducting charged particle imaging. An acquired image may be a single image comprising a plurality of imaging areas. The single image may be stored in storage 394. The single image may be an original image that may be divided into a plurality of regions. Each of the regions may comprise one imaging area containing a feature of wafer 330. The acquired images may comprise multiple images of a single imaging area of wafer 330 sampled multiple times over a time sequence. The multiple images may be stored in storage 394. In some embodiments, image processing system 390 may be configured to perform image processing steps with the multiple images of the same location of wafer 330.

[0053] In some embodiments, image processing system 390 may include measurement circuits (e.g., analog-to-digital converters) to obtain a distribution of the detected secondary charged particles (e.g., secondary electrons). The charged-particle distribution data collected during a detection time window, in combination with corresponding scan path data of beamlets 314, 316, and 318 incident on the wafer surface, can be used to reconstruct images of the wafer structures under inspection. The reconstructed images can be used to reveal various features of the internal or external structures of wafer 330, and thereby can be used to reveal any defects that may exist in the wafer.

[0054] In some embodiments, the charged particles may be electrons. When electrons of primary charged-particle beam 310 are projected onto a surface of wafer 330 (e.g., probe spots 370, 372, and 374), the electrons of primary charged-particle beam 310 may penetrate the surface of wafer 330 for a certain depth, interacting with particles of wafer 330. Some electrons of primary charged-particle beam 310 may elastically interact with (e.g., in the form of elastic scattering or collision) the materials of wafer 330 and may be reflected or recoiled out of the surface of wafer 330. An elastic interaction conserves the total kinetic energies of the bodies (e.g., electrons of primary charged-particle beam 310) of the interaction, in which the kinetic energy of the interacting bodies does not convert to other forms of energy (e.g., heat, electromagnetic energy, or the like). Such reflected electrons generated from elastic interaction may be referred to as backscattered electrons (BSEs). Some electrons of primary charged-particle beam 310 may inelastically interact with (e.g., in the form of inelastic scattering or collision) the materials of wafer 330. An inelastic interaction does not conserve the total kinetic energies of the bodies of the interaction, in which some or all of the kinetic energy of the interacting bodies convert to other forms of energy. For example, through the inelastic interaction, the kinetic energy of some electrons of primary charged-particle beam 310 may cause electron excitation and transition of atoms of the materials. Such inelastic interaction may also generate electrons exiting the surface of wafer 330, which may be referred to as secondary electrons (SEs). Yield or emission rates of BSEs and SEs depend on, e.g., the material under inspection and the landing energy of the electrons of primary charged-particle beam 310 landing on the surface of the material, among others. The energy of the electrons of primary charged-particle beam 310 may be imparted in part by its acceleration voltage (e.g.,the acceleration voltage between the anode and cathode of charged-particle source 302 in FIG. 3). The quantity of BSEs and SEs may be more or fewer (or even the same) than the injected electrons of primary charged-particle beam 310.

[0055] The images generated by SCPM may be used for defect inspection. For example, a generated image capturing a test device region of a wafer may be compared with a reference image capturing the same test device region. The reference image may be predetermined (e.g., by simulation) and include no known defect. If a difference between the generated image and the reference image exceeds a tolerance level, a potential defect may be identified. For another example, the SCPM may scan multiple regions of the wafer, each region including a test device region designed as the same, and generate multiple images capturing those test device regions as manufactured. The multiple images may be compared with each other. If a difference between the multiple images exceeds a tolerance level, a potential defect may be identified.

[0056] Although reference may be made in the present disclosure to ICs, it is appreciated that the present disclosure may be applicable to other possible applications or designs. For example, the present disclosure may be applied to integrated optical systems, magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, and other nanoscale structures. It is further appreciated that the terms “die”, “structure”, and “IC structure” are used interchangeably in this disclosure.

[0057] Reference is now made to FIG. 4, which is an example block diagram for generating input data for a conventional method. Input data may be generated using two steps as illustrated in FIG. 4. A lithographic projection apparatus 401 may be used to fabricate an IC structure onto a wafer using focus and dose conditions for a radiation source) onto a surface of a wafer. A focus condition is an indication of the focal point of the beam onto the surface of the sample, and a dose condition is an indication of the energy of the radiation beam per area of the sample (e.g., mJ / cm2). A processor 403 with a memory may be communicatively connected to lithographic projection apparatus 401 to store the focus and dose conditions of the radiation beam used to fabricate the IC structure at a particular wafer processing step or process. A metrology tool 402 may be used to measure critical dimensions of the structures formed in the IC according to the lithographic fabrication conditions. Each critical dimension measured for the IC structures may correspond to a focus and dose condition during the lithographic fabrication process.

[0058] Reference is now made to FIG. 5, which is an example wafer map generated according to a conventional method. FIG. 5 corresponds to a wafer 501, which contains a die 502. Each die 502 is represented as a square on wafer 501 that is outlined in black. FIG. 5 is illustrated as a gradient image, where darker color indicates a larger CD value and lighter color represents a lower CD value. Three wafer regions are illustrated in FIG. 5, where the dotted line 503 represents a first wafer region boundary between a first wafer region and a second wafer region, and the dotted line 504 represents a second wafer region boundary between the second wafer region and a third wafer region. The second wafer region (e.g., the region between dotted line 503 and dotted line 504) exhibits the darkest color and thus indicates a wafer region with the largest CD distribution. FIG. 5 thus illustrates a CD signature,or CD pattern, distributed across a wafer that may be representative of the lithographic fabrication process variation or quality. Specifically, the second wafer region located between dotted lines 503 and 504 may be a CD signature that provides insight into a variation or quality of a fabrication process or processing step used to manufacture IC structures on wafer 501.

[0059] As discussed above, CD may provide insufficient information about process variation and may be susceptible to metrology error because CD is only a 1 -directional measurement. Reference is now made to FIG. 6A, which illustrates example IC structures imaged in a die on a wafer. FIG. 6A illustrates contact holes as the IC structures, which may contain some variation in shape due to process variation in lithography. According to conventional methods, CD measurements may be taken for a contact hole. A first CD measurement 602 may be taken across contact hole 601, a second CD measurement 603 may be taken across contact hole 601, and a third CD measurement 604 may be taken across contact hole 601. First CD measurement 602, second CD measurement 603, and third CD measurement 604 may be collected from the other contact holes present in the image. Each collected CD measurement (e.g., each first CD measurement 602) may be averaged to obtain an average CD measurement for a die on the wafer, and a wafer map may be generated to indicate a spatial distribution of CD for a contact hole across the wafer. Reference is now made to FIG. 6B, which illustrate example wafer maps generated based on averaged CD measurements of a contact hole. Water map 605 may illustrate averaged values of first CD measurement 602, wafer map 606 may illustrate averaged values of second CD measurement 603, and wafer map 607 may illustrate averaged values of third CD measurement 604 for all IC structures (e.g., contact holes) imaged. Wafer maps 605-607 are illustrated as gradient images, and gradient 608 illustrates a darker color that represents a larger average CD value and lighter color represents a lower average CD value. FIG. 6B illustrates that wafer maps 605-607 each exhibit a similar CD signature, or distribution of average CD values, of an IC structure (e.g., contact hole) across a wafer. This could be interpreted to mean that a lithographic fabrication process may have a similar effect for CD of an IC structure no matter the structural orientation. However, the example contact holes illustrated in FIG. 6A all exhibit variation in shape and length. Thus, the wafer maps generated according to a conventional method may not completely or accurately model a lithographic process variation because CD measurements may contain too little information to effectively evaluate fabrication process variation or quality.

[0060] Reference is now made to FIG. 7, which is an example block diagram for generating input data, consistent with embodiments of the present disclosure. Input data may be generated using two steps as illustrated in FIG. 7. A lithographic projection apparatus 701 (such as lithographic projection apparatus 100 in FIG. 1) may be used to fabricate an IC structure onto a wafer using focus and dose conditions for a radiation source (such as radiation source 101 in FIG. 1) onto a surface of a wafer. A focus condition is an indication of the focal point of the beam (such as beam 108 in FIG. 1) onto the surface of the sample, and a dose condition is an indication of the energy of the radiation beam (such as beam 108 in FIG. 1) per area of the sample (e.g., mJ / cm2). A controller 703 with a memory may becommunicatively connected to lithographic projection apparatus 701 to store the focus and dose conditions of the radiation beam used to fabricate the IC structure at a particular wafer processing step or process. An inspection tool 702 (e.g., an optical microscope or a charged particle beam microscope) may be used to collect an image of the structures formed in the IC according to the lithographic fabrication conditions. Controller 703 (e.g., controller 209 in FIG. 2) may evaluate the imaged structures and extract two-dimensional measurement data, which is described further below.

[0061] Reference is now made to FIG. 8, which is an illustration of extracting two-dimensional contours from a fabricated IC structure, consistent with embodiments of the present disclosure. FIG. 8 illustrates collected images of fabricated IC structures. For example, image 801 contains images of contact holes. Image 801 may be supplied to a controller (e.g., controller 209 in FIG. 2 or controller 703 in FIG. 7) and the controller may extract two-dimensional measurement data from the IC structures. Extracted image 802 illustrates extracted two-dimensional measurement data of the contact holes. In some embodiments, the two-dimensional measurements manifest themselves as contours, which are extracted as discrete datapoints outlining a shape of the IC structure.

[0062] In some embodiments, a characteristic of the two-dimensional measurement data may be calculated and may be used to characterize the two-dimensional measurement data. In some embodiments, the characteristic may be a geometric characteristic, an image moment, or a transformative characteristic of the two-dimensional measurement data. In some embodiments, the two- dimensional measurement data includes a contour. In some embodiments, the characteristic of the two- dimensional measurement data is a geometric characteristic. In some embodiments, the geometric characteristic of the contour may comprise a centroid, an area, an aspect ratio, a bounding box, a boundary descriptor, a bending energy, a compactness, a convexity, a curvature, an elongation, a major axis angle, a major axis length, a minor axis angle, a perimeter, a roundness, a shape variation, an eccentricity, a sphericity, or a solidity value. In some embodiments, the characteristic of the two- dimensional measurement data is a transformative characteristic. In some embodiments, the transformative characteristic may comprise a Fourier transform, a Hough transform, or a Zernike transform. A characteristic of the two-dimensional measurement data (e.g., a contour) may be calculated based on known formulas or algorithms used to extract such information. As non-limiting examples, a compactness characteristic, an eccentricity characteristic, a roundness characteristic, a sphericity characteristic, a convexity characteristic, and a solidity characteristic may be calculated via the following equations:(perimeter)2Compactness = are a (Eqn. 1) axis lengthshoj-fEccentricity = axis lengthio g (Eqn. 2)4n >areaRoundness = (convex perimeter)2(Eqn. 3)„ convex perimeterConvexity = - perimeter (Eqn. 5) areaSolidity = convex area (Eqn. 6)

[0063] In some embodiments, a characteristic of the two-dimensional measurement data (e.g., a contour) may be calculated based on a reference-based approach. In some embodiments, a referenced- based approach may rely on design data of a target IC structure and compare the design data to the two- dimensional measurement data of the fabricated IC structure. Reference is now made to FIG. 9A, which is an illustration of an example reference-based approach comparison between design data and two- dimensional measurement data, consistent with embodiments of the present disclosure. FIG. 9A illustrates extracted two-dimensional measurement data of contact holes, where the extracted information is a contour 901 of a contact hole. Contour 901 may be compared to design data 902 of the contact hole. In some embodiments, design data 902 may be a GDS, golden image, design template, or other data file representing a target IC structure. A characteristic of contour 901 (e.g., convexity, solidity, eccentricity, or other characteristics described above) may be calculated and compared to that of design data 902. As a non-limiting example, design data 902 may have a convexity characteristic value of 1.0. A convexity characteristic of contour 901 may be compared to the convexity value of design data 902, and a difference 903 between the two values may be used to evaluate the lithographic fabrication process variation or quality. For example, a lower difference of a convexity characteristic value between design data 902 and contour 901 may indicate the lithographic fabrication process variation is desirably low and the quality is desirably high. A same or similar approach may be used for the other characteristics described above. It is appreciated that any form of design data may be used for any IC structure, and embodiments of the present disclosure should not be limited to design data for contact holes and are generalizable to other irregular pattern types.

[0064] In some embodiments, a characteristic of the two-dimensional measurement data (e.g., contour) may be calculated based on a non-reference-based approach. In some embodiments, a non-referenced- based approach may rely on averaging a calculated characteristic of a same target IC structure. Reference is now made to FIG. 9B, which is an illustration of an example non-reference-based approach for two-dimensional measurement data, consistent with embodiments of the present disclosure. FIG. 9B illustrates an image 904 within a die on a wafer containing a region of interest 905. Region of interest 905 may contain fabricated IC structures 906 according to a lithographic fabrication process orprocessing step. In some embodiments, IC structures 906 may be contact holes 906 and region of interest 905 includes contact hole 906a, contact hole 906b, contact hole 906c, contact hole 906d, and contact hole 906e (contact holes 906a-e). Two-dimensional measurement data may be extracted for contact holes 906a-e. In some embodiments, the two-dimensional measurement data includes a contour and may be extracted as described above. Contours 907a-e correspond to contact holes 906a-e. A characteristic for each of contours 907 a-e may be calculated as described above (e.g., solidity, perimeter, area, etc.). It is appreciated that any number of characteristics may be calculated for each of contours 907a-e at the same time. In some embodiments, any number of the characteristics as described above may be calculated from contours 907a-e. The calculated characteristic may be a value or a vector and an average calculated characteristic 908 may be determined by averaging each of the same characteristics calculated from contours 907a-e. As a non-limiting example, all calculated solidity characteristics calculated from contours 907 a-e may be averaged, and all calculated eccentricity characteristics calculated from contours 907 a-e may be averaged separately. An averaged characteristic value may be calculated for other regions of interest on the same die or on the wafer (e.g., regions of interest on a different die). The statistical difference between an averaged characteristic value across a wafer may indicate the lithographic fabrication process variation may have an impact on the characteristic of the IC structure.

[0065] Reference is now made to FIG. 10, which is an example workflow of a referenced-based approach for building a wafer map to evaluate a fabrication process variation or quality corresponding to two-dimensional measurement data, consistent with embodiments of the present disclosure. A wafer 1001 may be fabricated according to a lithographic fabrication process or processing step with a first die 1002 containing one or more IC structures. Wafer 1001 may be imaged via a charged particle apparatus (e.g., EBI system 200 of FIG. 2 or multi-beam tool 204 of FIG. 3). An image 1003 may be collected from first die 1002. Image 1003 may contain IC structure 1004. It is appreciated that IC structure 1004 represents contact holes in this example, but embodiments of this disclosure are not so limited. Any IC structure may be used. A controller (e.g., controller 209 in FIG. 2 or controller 703 in FIG. 7 may evaluate image 1003 to extract two-dimensional measurement data from an IC structure (e.g., structure 1004 in image 1003).

[0066] In some embodiments, the two-dimensional measurement data of structure 1004 is contour A. Contour A may be supplied to a computational model, and the computational model may calculate one or more characteristics from contour A. In some embodiments, a computational model may calculate characteristic Acl contour A, which may be a compactness characteristic. The computational model may calculate characteristic Acl as described via Equation 1 above. It is appreciated that other characteristics may be calculated other than the characteristics used in this non-limiting example. It is further appreciated that any number of characteristics may be calculated from a contour (e.g., contour A). The computational model may then compare the calculated characteristic to the same characteristic calculated from design data of the IC structure (e.g., contact hole). In some embodiments, thecomputational model may calculate a difference Diff Acl between the calculated characteristics of a contour and a calculated characteristic of design data. In some embodiments, Diff Acl may be a difference between a calculated compactness characteristic of design data and a calculated compactness characteristic, Acl, of contour A. FIG. 10 illustrates the computational model may calculate a perimeter 1005 of contour A and a perimeter 1006 of design data of IC structure 1004. The computational model may also calculate an area of contour A and an area of the design data (not shown). As described above, IC structure 1004 may be considered a contact hole, and the design data may be understood to be a circle. The compactness characteristic for the design data and the compactness characteristic for contour A may be calculated according to Equation 1 above, and a difference between the two compactness characteristics may be calculated. The computational model may then calculate an average of characteristic difference values of the same characteristic. For example, difference Diff Acl may be averaged with a second difference value of a compactness characteristic (obtained by following a same or similar approach as described above) to obtain average compactness characteristic difference Avg Diff cl for image 1003 of die 1002. An image from a second die on wafer 1001 may be collected, and the above steps may be repeated to obtain an average compactness difference of the second die. The averaged characteristic differences may be supplied to the computational model to build a map of wafer 1001 illustrating a spatial distribution of the averaged characteristic differences from design data of a target IC structure across wafer 1001. A wafer map may be generated per an averaged characteristic difference, and a first die on the wafer map may contain a different value of the averaged characteristic difference compared to a second die. Thus, wafer map 1007 may be generated using averaged difference values of a first characteristic (e.g., a compactness characteristic) from a first die and a second die on wafer 1001. The generated wafer map may illustrate a different signature of an averaged characteristic difference according to a lithographic fabrication processing condition or processing step. For example, wafer map 1007 may illustrate regions 1008 throughout the wafer where a higher average value of compactness characteristic differences from design data are present. The signature, or pattern, of regions 1008 may provide an evaluation of the lithographic fabrication process variation or quality. In some embodiments, a second wafer map may be generated using averaged difference values of a second characteristic (e.g., a solidity characteristic) from a first die and a second die on wafer 1001. The generated second wafer map may illustrate a different signature of an averaged solidity characteristic difference according to a lithographic fabrication processing condition or processing step, and the signature may provide an evaluation of the lithographic fabrication process variation or quality on a solidity characteristic. Thus, embodiments of the present disclosure may extract more information to evaluate a lithographic fabrication process variation or quality according to a specific characteristic of a fabricated feature (e.g., compactness or solidity of an IC structure) compared to a conventional method.

[0067] Reference is now made to FIG. 11, which is an example workflow for building a wafer map to evaluate a process variation or quality corresponding to two-dimensional measurement data according to a non-referenced-based approach a, consistent with embodiments of the present disclosure. A wafer1101 may be fabricated according to a lithographic fabrication process or processing step with a first die 1102 containing one or more IC structures. Wafer 1101 may be imaged via a charged particle apparatus (e.g., EBI system 200 of FIG. 2 or multi-beam tool 204 of FIG. 3). An image 1103 may be collected from first die 1102 and image 1103 may contain IC structure 1104. It is appreciated that IC structure 1104 represents a contact hole in this example, but embodiments of this disclosure are not limited. Any IC structure may be used. A controller (e.g., controller 209 in FIG. 2 or controller 703 in FIG. 7 may evaluate image 1103 to extract two-dimensional measurement data from an IC structure (e.g., structure 1104). In some embodiments, the two-dimensional measurement data of structure 1104 is contour B. Contour B may be supplied to a computational model, and the computational model may calculate one or more characteristics from contour B. In some embodiments, a computational model may calculate characteristic Bel from contour B. In some embodiments, characteristic Bel may be a compactness characteristic and the computational model may calculate characteristic Bel via Equation 1 described above. It is appreciated that other characteristics may be calculated other than the characteristics used in this non-limiting example. It is further appreciated that any number of characteristics may be calculated from a contour (e.g., contour B). The computational model may then average the characteristic values of the same characteristic. For example, characteristic Bel and a compactness characteristic of a second IC structure (not shown) on die 1102 may be averaged to obtain average compactness characteristic Avg cl for die 1102. An image from a second die (not shown) on wafer 1101 may be collected, and the above steps may be repeated to obtain an average compactness characteristic of the second die. The averaged compactness characteristics may be supplied to the computational model to build a map of wafer 1101 illustrating a spatial variation of the averaged characteristic across wafer 1101. It is appreciated that any number of characteristics may be averaged and supplied to the computational model to build any number of wafer maps. A wafer map may be generated per an averaged characteristic, and a first die on the wafer map may contain a different value of the averaged characteristic compared to a second die. Wafer map 1105 may be generated using averaged values of a first characteristic (e.g., a compactness characteristic) from a first die and a second die on wafer 1101. The generated wafer map may illustrate a different signature of an averaged characteristic according to a lithographic fabrication processing condition or processing step. For example, wafer map 1105 may illustrate regions 1106 throughout the wafer where a higher average value of a first characteristic (e.g., a compactness characteristic) is present. In some embodiments, a second wafer map may be generated using averaged difference values of a second characteristic (e.g., a solidity characteristic) from a first die and a second die. The generated second wafer map may illustrate a different signature of an averaged solidity characteristic difference according to a lithographic fabrication processing condition or processing step, and the signature may provide an evaluation of the lithographic fabrication process variation or quality on a solidity characteristic Thus, embodiments of the present disclosure may extract more information to evaluate a lithographicfabrication process variation or quality according to a specific characteristic of a fabricated feature (e.g., elongation or area of an IC structure) compared to a conventional method.

[0068] Reference is now made to FIGs. 12A-P, which are example illustrations of generated wafer maps representing spatial distribution of an averaged characteristic of an extracted contour across a wafer, consistent with embodiments of the present disclosure. A same workflow as described for FIG. 11 above may be performed to generate the wafer maps illustrated in FIGs. 12A-P. FIG. 12A illustrates a spatial distribution of an averaged area characteristic of an extracted contour across a wafer. A gradient 1201 indicates a lighter color representing a larger average characteristic value. FIG. 12B illustrates a spatial distribution of an averaged bending energy characteristic of an IC structure across a wafer. FIG. 12C illustrates a spatial distribution of an averaged compactness characteristic of an IC structure across a wafer. FIG. 12D illustrates a spatial distribution of an averaged convexity characteristic of an IC structure across a wafer. FIG. 12E illustrates a spatial distribution of an averaged curvature (maximum) characteristic of an IC structure across a wafer. FIG. 12F illustrates a spatial distribution of an averaged curvature (medium) characteristic of an IC structure across a wafer. A gradient 1202 indicates a darker color represents a larger average characteristic value (e.g., curvature (medium) characteristic). FIG. 12G illustrates a spatial distribution of an averaged curvature (minimum) characteristic of an IC structure across a wafer. FIG. 12H illustrates a spatial distribution of an averaged elongation characteristic of an IC structure across a wafer. FIG. 121 illustrates a spatial distribution of an averaged major axis angle characteristic of an IC structure across a wafer. FIG. 12J illustrates a spatial distribution of an averaged major axis length characteristic of an IC structure across a wafer. FIG. 12K illustrates a spatial distribution of an averaged minor axis characteristic of an IC structure across a wafer. FIG. 12L illustrates a spatial distribution of an averaged perimeter characteristic of an IC structure across a wafer. FIG. 12M illustrates a spatial distribution of an averaged roundness characteristic of an IC structure across a wafer. FIG. 12N illustrates a spatial distribution of an averaged shape variation characteristic of an IC structure across a wafer. FIG. 120 illustrates a spatial variation of an averaged solidity characteristic of an IC structure across a wafer. FIG. 12P illustrates a spatial variation of an averaged Fourier transform characteristic of an IC structure across a wafer. FIGs. 12A-P illustrate how embodiments of the present disclosure may provide different signatures for a characteristic of an IC structure that may provide additional insight compared to a conventional method to evaluate how a lithographic fabrication process variation or quality may impact fabrication of an IC structure.

[0069] Reference is now made to FIG. 13, which is an example flow diagram illustrating a method 1300 of extracting two-dimensional measurement data from an IC structure to monitor a lithographic fabrication process variation, consistent with embodiments of the present disclosure. The steps of method 1300 may be performed by a computing device that includes, e.g., controller 209 of FIG. 2 or controller 703 of FIG. 7 or image processing system 390 of FIG. 3. It is appreciated that the illustrated method 1300 may be altered to modify the order of steps and to include the additional steps.

[0070] In step 1301, input data is acquired and supplied to a computational model. The input data may include an image of an IC structure. The image may be a region of interest within a die on a wafer.

[0071] In step 1302, two-dimensional measurement data is extracted from the input data. The two- dimensional measurement data may be a contour. In some embodiments, the two-dimensional measurement data may be extracted from any number of IC structures within the input data (e.g., a SEM image). In some embodiments, the two-dimensional measurements are extracted as discrete datapoints outlining a shape of the IC structure.

[0072] In step 1303, one or more characteristics of the two-dimensional measurement data is calculated. In some embodiments, the one or more characteristics may be a geometric characteristic, an image moment, or a transformative characteristic of the two-dimensional measurement data. The geometric characteristics may be described above. In some embodiments, the transformative characteristic may comprise a Fourier transform, a Hough transform, or a Zernike transform. In some embodiments, the calculated characteristic may be a value or a vector. In some embodiments, the one or more characteristics may be calculated in a referenced-based approach or a non-referenced-based approach.

[0073] In step 1304, a lithographic fabrication process variation is evaluated using the calculated one or more characteristics. In some embodiments, an average characteristic is calculated and used to evaluate the lithographic fabrication process variation. In some embodiments, the average characteristic is calculated from characteristics calculated from two-dimensional measurement data. In some embodiments, the average characteristic is used to generate a wafer map. The wafer map may contain an average characteristic value for each die on the wafer. In some embodiments, the wafer map may contain an average characteristic value for two or more die on the wafer. The wafer map may indicate how a lithographic process variation causes a characteristic to deviate across a wafer (e.g., from die-to- die). In some embodiments, a difference between a calculated characteristic and design data is used to evaluate the lithographic fabrication process variation. The difference may be a value or a vector. In some embodiments, the difference may indicate how a lithographic process variation causes a characteristic to deviate from the design data. In some embodiments, the difference value may be averaged from characteristics calculated from two-dimensional measurement data and the corresponding design data. In some embodiments, the average difference value is used to generate a wafer map.

[0074] A benefit provided by embodiments of the present disclosure may be a method to monitor an impact of a lithographic process variation more accurately regarding IC structure fabrication. In some embodiments, more information regarding lithographic process variation may be made available compared to conventional methods. Embodiments of the present disclosure may distinguish various characteristics of an IC structure that may be impacted by a fabrication process variation or may provide insight on how to monitor a fabrication process variation. Embodiments of the present disclosure provide a reference-based approach to quantify process variation or quality in a data and pattern independent manner. This may make it possible to compare different lithographic fabrication processesand pattern types. The present disclosure also provides a non-referenced-based approach to quantify process variation or quality without design data. Some embodiments of the present disclosure may provide a method to establish a more discriminant and representative combination of features compared to a one-directional measurement (e.g., CD). Moreover, some embodiments of the present disclosure may provide a more accurate method to monitor process variation or quality without using models to make prior assumptions to fabricated IC structures and may forgo time-intensive physical measurements to evaluate a fabrication process variation on IC structure formation. Some embodiments of the present disclosure may provide a method to maintain defect inspection accuracy and yield of defect-free devices throughout HVM.

[0075] A non-transitory computer readable medium may be provided that may store instructions for a processor of a lithographic projection apparatus (e.g., lithographic projection apparatus 100 of FIG. 1), a processor of an inspection tool (e.g., EBI system 200 of FIG. 2 or multi-beam inspection tool 204 of FIG. 3) to collect images of a sample, method 1300 of FIG. 13, and other executable functions relating to collecting two-dimensional measurement data of an IC structure other fabricated features on a wafer, extracting a characteristic from the two-dimensional measurement data, or generating a wafer map. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc Read Only Memory (CD-ROM), any other optical data storage medium, any physical medium with patterns of holes, a Random Access Memory (RAM), a Programmable Read Only Memory (PROM), and Erasable Programmable Read Only Memory (EPROM), a FLASH-EPROM or any other flash memory, Non- Volatile Random Access Memory (NVRAM), a cache, a register, any other memory chip or cartridge, and networked versions of the same.

[0076] The embodiments may further be described using the following clauses:1. A method for evaluating a wafer fabrication process condition, comprising: obtaining a first image of a sample; extracting a contour from the first image, wherein the contour comprises discrete data points; calculating characteristics based on the contour; and evaluating a fabrication process variation based on the characteristic.2. The method of clause 1 , wherein the characteristic is value or a vector.3. The method of clause 1 or 2, wherein the characteristic is a geometric characteristic.4. The method of clause 3, wherein the characteristic is a shape descriptor.5. The method of clause 4, wherein the shape descriptor comprises a global descriptor or a local descriptor.6. The method of any one of clauses 3 to 5, wherein the characteristic comprises a centroid, an area, an aspect ratio, a bounding box, a boundary descriptor, a bending energy, a compactness, a convexity, a curvature, an elongation, a major axis angle, a major axis length, a minor axis angle, a perimeter, a roundness, a shape variation, an eccentricity, a sphericity, or a solidity.7. The method of clause 1 or 2, wherein the characteristic is a transformative characteristic.8. The method of clause 7, wherein the characteristic comprises a Fourier transform, a Hough transform, or a Zernike transform.9. The method of clause 1 or 2, wherein the characteristic is an image moment.10. The method of any one of clauses 1 to 9, wherein evaluating a fabrication process variation based on the characteristic further comprises: collecting a second image of the sample; calculating a first average characteristic value from two or more contours extracted from the first image; calculating a second average characteristic value from two or more contours extracted from the second image, wherein the second average characteristic is calculated from different contours from the first average characteristic; and using the first average characteristic value and the second average characteristic value to generate a wafer map.11. The method of clause 10, wherein the wafer map indicates a spatial distribution of an average characteristic value across a wafer.12. The method of clause 10 or 11, wherein the first image and the second image are collected from a same die on a wafer.13. The method of clause 10 or 11, wherein the first image and the second image are collected from a different die on a wafer.14. The method of any one of clauses 1 to 9, wherein evaluating a fabrication process variation based on the characteristic further comprises: collecting a second image of the sample; calculating a first difference between the calculated characteristic from the first image and a calculated characteristic of a reference; calculating a second difference between a second calculated characteristic from the first image and a second calculated characteristic of the reference; calculating a first average difference from the first difference and the second difference; calculating a third difference between a calculated characteristic from the second image and a calculated characteristic of the reference; calculating a fourth difference between a second calculated characteristic from the second image and a second calculated characteristic of the reference; calculating a second average difference from the third difference and the fourth difference; and using the first average difference and the second average difference to generate a wafer map.15. The method of clause 14, wherein the reference is design data of the first image and the second image.16. The method of clause 15, wherein the design data comprises a graphical design system (GDS) file, a target pattern design, or a golden image.17. The method of clause 14, wherein the reference is a previously collected image of the sample.18. The method of any one of clauses 14 to 17, wherein the wafer map indicates a spatial distribution of an average difference value of a calculated characteristic from a characteristic of the reference across a wafer.19. The method of any one of clauses 14 to 18, wherein the first image and the second image are collected from a same die on a wafer.20. The method of any one of clauses 14 to 19, wherein the first image and the second image are collected from a different die on a wafer.21. The method of any one of clauses 1 to 20, wherein the first image of the sample is a SEM image.22. The method of any one of clauses 10 to 20, wherein the second image of the sample is a SEM image.23. A method for evaluating a wafer fabrication process condition, comprising: using an inspection tool to obtain a first image of a sample; collecting two-dimensional measurement data of a feature in the first image; calculating a characteristic of the feature from the two-dimensional measurement data; and evaluating a process variation based on the characteristic.24. The method of clause 23, wherein the two-dimensional measurement data comprises a value or a vector.25. The method of clause 23 or 24, wherein the two-dimensional measurement data comprises a contour.26. The method of clause 25, wherein the contour comprises discrete data points.27. The method of any one of clauses 23 to 26, wherein the characteristic is a geometric characteristic.28. The method of clause 27, wherein the characteristic is a shape descriptor.29. The method of clause 28, wherein the shape descriptor comprises a global descriptor or a local descriptor.30. The method of any one of clauses 27 to 29, wherein the characteristic comprises a centroid, an area, an aspect ratio, a bounding box, a boundary descriptor, a bending energy, a compactness, a convexity, a curvature, an elongation, a major axis angle, a major axis length, a minor axis angle, a perimeter, a roundness, a shape variation, an eccentricity, a sphericity, or a solidity.31. The method of any one of clauses 23 to 26, wherein the characteristic is a transformative characteristic.32. The method of clause 31, wherein the characteristic comprises a Fourier transform, a Hough transform, or a Zernike transform.33. The method of any one of clauses 23 to 26, wherein the characteristic is an image moment.34. The method of any one of clauses 23 to 33, wherein evaluating a fabrication process variation based on the characteristic further comprises: collecting a second image of the sample;calculating a first average characteristic value from two-dimensional measurement data extracted from the first image; calculating a second average characteristic value from two-dimensional measurement data extracted from the second image, wherein the second average characteristic is calculated from different two- dimensional measurement data from the first average characteristic; and using the first average characteristic value and the second average characteristic value to generate a wafer map.35. The method of clause 34, wherein the wafer map indicates a spatial distribution of an average characteristic value across a wafer.36. The method of clause 34 or 35, wherein the first image and the second image are collected from a same die on a wafer.37. The method of clause 34 or 35, wherein the first image and the second image are collected from a different die on a wafer.38. The method of any one of clauses 23 to 33, wherein evaluating a fabrication process variation based on the characteristic further comprises: colleting a second image of the sample; calculating a first difference between the calculated characteristic from the first image and a calculated characteristic of a reference; calculating a second difference between a second calculated characteristic from the first image and a second calculated characteristic of the reference; calculating a first average difference from the first difference and the second difference; calculating a third difference between a calculated characteristic from the second image and a calculated characteristic of the reference; calculating a fourth difference between a second calculated characteristic from the second image and a second calculated characteristic of the reference; calculating a second average difference from the third difference and the fourth difference; and using the first average difference and the second average difference to generate a wafer map.39. The method of clause 38, wherein the reference is design data of the first image and the second image.40. The method of clause 39, wherein the design data comprises a graphical design system (GDS) file, a target pattern design, or a golden image.41. The method of clause 38, wherein the reference is a previously collected image of the sample.42. The method of any one of clauses 38 to 41, wherein the wafer map indicates a spatial distribution of an average difference value of a calculated characteristic from a characteristic of the reference across a wafer.43. The method of any one of clauses 38 to 41, wherein the first image and the second image are collected from a same die on a wafer.44. The method of any one of clauses 38 to 41, wherein the first image and the second image are collected from a different die on a wafer.45. The method of any one of clauses 23 to 44, wherein the inspection tool is an optical microscope.46. The method of any one of clauses 23 to 44, wherein the inspection tool is a charged particle beam apparatus.47. The method of any one of clauses 23 to 44 or 46, wherein the first image of the sample is a SEM image.48. The method of any one of clauses 34 to 44, wherein the second image of the sample is a SEM image.49. A non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for evaluating a wafer fabrication process condition, the operations comprising: obtaining a first image of a sample; extracting a contour from the first image, wherein the contour comprises discrete data points; calculating a characteristic based on the contour; and evaluating a fabrication process variation based on the characteristic.50. The non-transitory computer readable medium of clause 49, wherein the characteristic is value or a vector.51. The non-transitory computer readable medium of clause 49 or 50, wherein the characteristic is a geometric characteristic.52. The non-transitory computer readable medium of clause 51 , wherein the characteristic is a shape descriptor.53. The non-transitory computer readable medium of clause 52, wherein the shape descriptor comprises a global descriptor or a local descriptor.54. The non-transitory computer readable medium of any one of clauses 51 to 53, wherein the characteristic comprises a centroid, an area, an aspect ratio, a bounding box, a boundary descriptor, a bending energy, a compactness, a convexity, a curvature, an elongation, a major axis angle, a major axis length, a minor axis angle, a perimeter, a roundness, a shape variation, an eccentricity, a sphericity, or a solidity.55. The non-transitory computer readable medium of clause 49 or 50, wherein the characteristic is a transformative characteristic.56. The non-transitory computer readable medium of clause 55, wherein the characteristic comprises a Fourier transform, a Hough transform, or a Zernike transform.57. The non-transitory computer readable medium of clause 49 or 50, wherein the characteristic is an image moment.58. The non-transitory computer readable medium of any one of clauses 49 to 57, wherein evaluating a fabrication process variation based on the characteristic further comprises:collecting a second image of the sample; calculating a first average characteristic value from two or more contours extracted from the first image; calculating a second average characteristic value from two or more contours extracted from the second image, wherein the second average characteristic is calculated from different contours from the first average characteristic; and using the first average characteristic value and the second average characteristic value to generate a wafer map.59. The non-transitory computer readable medium of clause 58, wherein the wafer map indicates a spatial distribution of an average characteristic value across a wafer.60. The non-transitory computer readable medium of clause 58 or 59, wherein the first image and the second image are collected from a same die on a wafer.61. The non-transitory computer readable medium of clause 58 or 59, wherein the first image and the second image are collected from a different die on a wafer.62. The non-transitory computer readable medium of any one of clauses 49 to 57, wherein evaluating a fabrication process variation based on the characteristic further comprises: colleting a second image of the sample; calculating a first difference between the calculated characteristic from the first image and a calculated characteristic of a reference; calculating a second difference between a second calculated characteristic from the first image and a second calculated characteristic of the reference; calculating a first average difference from the first difference and the second difference; calculating a third difference between a calculated characteristic from the second image and a calculated characteristic of the reference; calculating a fourth difference between a second calculated characteristic from the second image and a second calculated characteristic of the reference; calculating a second average difference from the third difference and the fourth difference; and using the first average difference and the second average difference to generate a wafer map.63. The non-transitory computer readable medium of clause 62, wherein the reference is design data of the first image and the second image.64. The non-transitory computer readable medium of clause 63, wherein the design data comprises a graphical design system (GDS) file, a target pattern design, or a golden image.65. The non-transitory computer readable medium of clause 62, wherein the reference is a previously collected image of the sample.66. The non-transitory computer readable medium of any one of clauses 62 to 65, wherein the wafer map indicates a spatial distribution of an average difference value of a calculated characteristic from a characteristic of the reference across a wafer.67. The non-transitory computer readable medium of any one of clauses 62 to 66, wherein the first image and the second image are collected from a same die on a wafer.68. The non-transitory computer readable medium of any one of clauses 62 to 66, wherein the first image and the second image are collected from a different die on a wafer.69. The non-transitory computer readable medium of any one of clauses 49 to 68, wherein the first image of the sample is a SEM image.70. The non-transitory computer readable medium of any one of clauses 58 to 68, wherein the second image of the sample is a SEM image.71. A non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for monitoring a wafer fabrication process condition, the operations comprising: using an inspection tool to obtain a first image of a sample; collecting two-dimensional measurement data of a feature in the first image; calculating a characteristic of the feature from the two-dimensional measurement data; and monitoring a process variation based on the characteristic.72. The non-transitory computer readable medium of clause 71, wherein the two-dimensional measurement data comprises a value or a vector.73. The non-transitory computer readable medium of clause 71 or 72, wherein the two-dimensional measurement data comprises a contour.74. The non-transitory computer readable medium of clause 73, wherein the contour comprises discrete data points.75. The non-transitory computer readable medium of any one of clauses 71 to 74, wherein the characteristic is a geometric characteristic.76. The non-transitory computer readable medium of clause 75, wherein the characteristic is a shape descriptor.77. The non-transitory computer readable medium of clause 76, wherein the shape descriptor comprises a global descriptor or a local descriptor.78. The non-transitory computer readable medium of any one of clauses 75 to 77, wherein the characteristic comprises a centroid, an area, an aspect ratio, a bounding box, a boundary descriptor, a bending energy, a compactness, a convexity, a curvature, an elongation, a major axis angle, a major axis length, a minor axis angle, a perimeter, a roundness, a shape variation, an eccentricity, a sphericity, or a solidity.79. The non-transitory computer readable medium of any one of clauses 71 to 74, wherein the characteristic is a transformative characteristic.80. The non-transitory computer readable medium of clause 79, wherein the characteristic comprises a Fourier transform, a Hough transform, or a Zernike transform.81. The non-transitory computer readable medium of any one of clauses 71 to 74, wherein the characteristic is an image moment.82. The non-transitory computer readable medium of any one of clauses 71 to 81 , wherein monitoring a fabrication process variation based on the characteristic further comprises: collecting a second image of the sample; calculating a first average characteristic value from two-dimensional measurement data extracted from the first image; calculating a second average characteristic value from two-dimensional measurement data extracted from the second image, wherein the second average characteristic is calculated from different two- dimensional measurement data from the first average characteristic; and using the first average characteristic value and the second average characteristic value to generate a wafer map.83. The non-transitory computer readable medium of clause 82, wherein the wafer map indicates a spatial distribution of an average characteristic value across a wafer.84. The non-transitory computer readable medium of clause 82 or 83, wherein the first image and the second image are collected from a same die on a wafer.85. The non-transitory computer readable medium of clause 82 or 83, wherein the first image and the second image are collected from a different die on a wafer.86. The non-transitory computer readable medium of any one of clauses 71 to 81, wherein operations for monitoring a fabrication process variation based on the characteristic further comprise: colleting a second image of the sample; calculating a first difference between the calculated characteristic from the first image and a calculated characteristic of a reference; calculating a second difference between a second calculated characteristic from the first image and a second calculated characteristic of the reference; calculating a first average difference from the first difference and the second difference; calculating a third difference between a calculated characteristic from the second image and a calculated characteristic of the reference; calculating a fourth difference between a second calculated characteristic from the second image and a second calculated characteristic of the reference; calculating a second average difference from the third difference and the fourth difference; and using the first average difference and the second average difference to generate a wafer map.87. The non-transitory computer readable medium of clause 86, wherein the reference is design data of the first image and the second image.88. The non-transitory computer readable medium of clause 87, wherein the design data comprises a graphical design system (GDS) file, a target pattern design, or a golden image.89. The non-transitory computer readable medium of clause 86, wherein the reference is a previously collected image of the sample.90. The non-transitory computer readable medium of any one of clause 86 to 89, wherein the wafer map indicates a spatial distribution of an average difference value of a calculated characteristic from a characteristic of the reference across a wafer.91. The non-transitory computer readable medium of any one of clauses 86 to 89, wherein the first image and the second image are collected from a same die on a wafer.92. The non-transitory computer readable medium of any one of clauses 86 to 89, wherein the first image and the second image are collected from a different die on a wafer.93. The non-transitory computer readable medium of any one of clauses 71 to 92, wherein the inspection tool is an optical microscope.94. The non-transitory computer readable medium of any one of clauses 71 to 92, wherein the inspection tool is a charged particle beam apparatus.95. The non-transitory computer readable medium of any one of clauses 71 to 92 or 94, wherein the first image of the sample is a SEM image.96. The non-transitory computer readable medium of any one of clauses 82 to 92, wherein the second image of the sample is a SEM image.97. A system using a computational model to monitor a wafer fabrication process condition, the system comprising: one or more processors configured to execute instructions to cause the system to perform operations comprising: obtaining a first image of a sample; extracting a contour from the first image, wherein the contour comprises discrete data points; calculating a characteristic based on the contour; and monitoring a fabrication process variation based on the characteristic.98. The system of clause 97, wherein the characteristic is value or a vector.99. The system of clause 97 or 98, wherein the characteristic is a geometric characteristic.100. The system of clause 99, wherein the characteristic is a shape descriptor.101. The system of clause 100, wherein the shape descriptor comprises a global descriptor or a local descriptor.102. The system of any one of clauses 99 to 101, wherein the characteristic comprises a centroid, an area, an aspect ratio, a bounding box, a boundary descriptor, a bending energy, a compactness, a convexity, a curvature, an elongation, a major axis angle, a major axis length, a minor axis angle, a perimeter, a roundness, a shape variation, an eccentricity, a sphericity, or a solidity.103. The system of clause 97 or 98, wherein the characteristic is a transformative characteristic.104. The system of clause 103, wherein the characteristic comprises a Fourier transform, a Hough transform, or a Zernike transform.105. The system of clause 97 or 98, wherein the characteristic is an image moment.106. The system of any one of clauses 97 to 105, wherein operations for monitoring a fabrication process variation based on the characteristic further comprise: collecting a second image of the sample; calculating a first average characteristic value from two or more contours extracted from the first image; calculating a second average characteristic value from two or more contours extracted from the second image, wherein the second average characteristic is calculated from different contours from the first average characteristic; and using the first average characteristic value and the second average characteristic value to generate a wafer map.107. The system of clause 106, wherein the wafer map indicates a spatial distribution of an average characteristic value across a wafer.108. The system of clause 106 or 107, wherein the first image and the second image are collected from a same die on a wafer.109. The system of clause 106 or 107, wherein the first image and the second image are collected from a different die on a wafer.110. The system of any one of clauses 97 to 105, wherein operations for monitoring a fabrication process variation based on the characteristic further comprise: colleting a second image of the sample; calculating a first difference between the calculated characteristic from the first image and a calculated characteristic of a reference; calculating a second difference between a second calculated characteristic from the first image and a second calculated characteristic of the reference; calculating a first average difference from the first difference and the second difference; calculating a third difference between a calculated characteristic from the second image and a calculated characteristic of the reference; calculating a fourth difference between a second calculated characteristic from the second image and a second calculated characteristic of the reference; calculating a second average difference from the third difference and the fourth difference; and using the first average difference and the second average difference to generate a wafer map.111. The system of clause 110, wherein the reference is design data of the first image and the second image.112. The system of clause 111, wherein the design data comprises a graphical design system (GDS) file, a target pattern design, or a golden image.113. The system of clause 110, wherein the reference is a previously collected image of the sample.114. The system of any one of clauses 110 to 113, wherein the wafer map indicates a spatial distribution of an average difference value of a calculated characteristic from a characteristic of the reference across a wafer.115. The system of any one of clauses 110 to 114, wherein the first image and the second image are collected from a same die on a wafer.116. The system of any one of clauses 110 to 114, wherein the first image and the second image are collected from a different die on a wafer.117. The system of any one of clauses 97 to 116, wherein the first image of the sample is a SEM image.118. The system of any one of clauses 106 to 116, wherein the second image of the sample is a SEM image.119. A system using a computational model to monitor a wafer fabrication process condition, the system comprising: one or more processors configured to execute instructions to cause the system to perform operations comprising: using an inspection tool to obtain a first image of a sample; collecting two-dimensional measurement data of a feature in the first image; calculating a characteristic of the feature from the two-dimensional measurement data; and monitoring a process variation based on the characteristic.120. The system of clause 119, wherein the two-dimensional measurement data comprises a value or a vector.121. The system of clause 119 or 120, wherein the two-dimensional measurement data comprises a contour.122. The system of clause 121, wherein the contour comprises discrete data points.123. The system of any one of clause 119 to 122, wherein the characteristic is a geometric characteristic.124. The system of clause 123, wherein the characteristic is a shape descriptor.125. The system of clause 124, wherein the shape descriptor comprises a global descriptor or a local descriptor.126. The system of any one of clauses 123 to 125, wherein the characteristic comprises a centroid, an area, an aspect ratio, a bounding box, a boundary descriptor, a bending energy, a compactness, a convexity, a curvature, an elongation, a major axis angle, a major axis length, a minor axis angle, a perimeter, a roundness, a shape variation, an eccentricity, a sphericity, or a solidity.127. The system of any one of clauses 119 to 123, wherein the characteristic is a transformative characteristic.128. The system of clause 127, wherein the characteristic comprises a Fourier transform, a Hough transform, or a Zernike transform.129. The system of any one of clauses 119 to 123, wherein the characteristic is an image moment.130. The system of any one of clauses 119 to 129, wherein operations for monitoring a fabrication process variation based on the characteristic further comprise: collecting a second image of the sample; calculating a first average characteristic value from two-dimensional measurement data extracted from the first image; calculating a second average characteristic value from two-dimensional measurement data extracted from the second image, wherein the second average characteristic is calculated from different two- dimensional measurement data from the first average characteristic; and using the first average characteristic value and the second average characteristic value to generate a wafer map.131. The system of clause 130, wherein the wafer map indicates a spatial distribution of an average characteristic value across a wafer.132. The system of clause 130 or 131, wherein the first image and the second image are collected from a same die on a wafer.133. The system of clause 130 or 131, wherein the first image and the second image are collected from a different die on a wafer.134. The system of any one of clauses 119 to 129, wherein operations for monitoring a fabrication process variation based on the characteristic further comprise: colleting a second image of the sample; calculating a first difference between the calculated characteristic from the first image and a calculated characteristic of a reference; calculating a second difference between a second calculated characteristic from the first image and a second calculated characteristic of the reference; calculating a first average difference from the first difference and the second difference; calculating a third difference between a calculated characteristic from the second image and a calculated characteristic of the reference; calculating a fourth difference between a second calculated characteristic from the second image and a second calculated characteristic of the reference; calculating a second average difference from the third difference and the fourth difference; and using the first average difference and the second average difference to generate a wafer map.135. The system of clause 134, wherein the reference is design data of the first image and the second image.136. The system of clause 135, wherein the design data comprises a graphical design system (GDS) file, a target pattern design, or a golden image.137. The system of clause 134, wherein the reference is a previously collected image of the sample.138. The system of any one of clauses 134 to 137, wherein the wafer map indicates a spatial distribution of an average difference value of a calculated characteristic from a characteristic of the reference across a wafer.139. The system of any one of clauses 134 to 137, wherein the first image and the second image are collected from a same die on a wafer.140. The system of any one of clauses 134 to 137, wherein the first image and the second image are collected from a different die on a wafer.141. The system of any one of clauses 119 to 140, wherein the inspection tool is an optical microscope.142. The system of any one of clauses 119 to 140, wherein the inspection tool is a charged particle beam apparatus.143. The system of any one of clauses 119 to 140 or 142, wherein the first image of the sample is a SEM image.144. The system of any one of clauses 129 to 140, wherein the second image of the sample is a SEM image.

[0077] It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The present disclosure has been described in connection with various embodiments, other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

CLAIMS1. A method for evaluating a wafer fabrication process condition, comprising: obtaining a first image of a sample; extracting a contour from the first image, wherein the contour comprises discrete data points; calculating a characteristic based on the contour; and evaluating a fabrication process variation based on the characteristic.

2. The method of claim 1 , wherein the characteristic is value or a vector.

3. The method of claim 1, wherein the characteristic is a geometric characteristic.

4. The method of claim 3, wherein the characteristic is a shape descriptor.

5. The method of claim 4, wherein the shape descriptor comprises a global descriptor or a local descriptor.

6. The method of claim 3, wherein the characteristic comprises a centroid, an area, an aspect ratio, a bounding box, a boundary descriptor, a bending energy, a compactness, a convexity, a curvature, an elongation, a major axis angle, a major axis length, a minor axis angle, a perimeter, a roundness, a shape variation, an eccentricity, a sphericity, or a solidity.

7. The method of claim 1, wherein the characteristic is a transformative characteristic.

8. The method of claim 7, wherein the characteristic comprises a Fourier transform, aHough transform, or a Zernike transform.

9. The method of claim 1, wherein the characteristic is an image moment.

10. The method of claim 1, wherein evaluating a fabrication process variation based on the characteristic further comprises: collecting a second image of the sample; calculating a first average characteristic value from two or more contours extracted from the first image; calculating a second average characteristic value from two or more contours extracted from the second image, wherein the second average characteristic is calculated from different contours from the first average characteristic; andusing the first average characteristic value and the second average characteristic value to generate a wafer map.

11. The method of claim 10, wherein the wafer map indicates a spatial distribution of an average characteristic value across a wafer.

12. The method of claim 10, wherein the first image and the second image are collected from a same die on a wafer.

13. The method of claim 10, wherein the first image and the second image are collected from a different die on a wafer.

14. A non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for evaluating a wafer fabrication process condition, the operations comprising: obtaining a first image of a sample; extracting a contour from the first image, wherein the contour comprises discrete data points; calculating a characteristic based on the contour; and evaluating a fabrication process variation based on the characteristic.

15. A system using a computational model to monitor a wafer fabrication process condition, the system comprising: one or more processors configured to execute instructions to cause the system to perform operations comprising: obtaining a first image of a sample; extracting a contour from the first image, wherein the contour comprises discrete data points; calculating a characteristic based on the contour; and monitoring a fabrication process variation based on the characteristic.

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