Diagnosis circuit for an I / O cell and for detecting faults in the I / O cell

Abstract

The invention relates to a diagnosis circuit for an I / O cell (10) and for detecting faults in the I / O cell (10), comprising: an input interface (110) having an OEN input port (112), an MUX config port (114) and a cell in-port (116); an output interface (120) having an OEN output port (122), an out-port (124) and a fault port (126); a function interface (140) having at least two function inputs (142); an MUX memory block (150) having a memory block input (152) and a diagnosis function; an OEN memory block (170) having a memory block input (152) and a diagnosis function for an OEN status based on the OEN signal; at least two diagnosis blocks (180), each for checking the function signal of one of the function modules (50) depending on at least one additional signal of the signals from the input interface (110).

Description

[0001] University of Kassel

[0002] Diagnostic circuit for an I / O cell and for detecting errors in the I / O cell

[0003] The present invention relates to a diagnostic circuit for an I / O cell and for detecting errors in the I / O cell, as well as to a circuit arrangement comprising a multiplexer and such a diagnostic circuit. Furthermore, the invention relates to an electronic chip, in particular for safety-relevant applications, and to a method for diagnosing and detecting errors in an electronic chip with at least two functional components, a multiplexer, and an I / O cell.

[0004] On electronic chips and other safety-relevant microcontrollers or systems-on-a-chip (SoC), the connection from the chip to the surrounding system, PCB, or package is made via I / O cells. These cells include an input, an output, a configuration input, and a bond pad. The bond pad serves as an area for wiring the chip or I / O cell to the peripherals surrounding the chip. These I / O cells require a lot of space, so it is not possible to provide a separate I / O cell for all the functional components in the chip. Since the I / O cells are very large compared to the rest of the logic on the digital chip and require a particularly large amount of chip space, attempts are made to use this space as efficiently as possible and to save costs. Therefore, compared to the internal functionality of the digital chip, only a few I / O cells are used, which can be occupied multiple times with internal logic.Multiplexers are used to perform so-called multiplexing, i.e., to control different internal functional units or function blocks with only a few I / O cells. An I / O cell is thus connected to several function blocks via the multiplexer. Which assignment occurs when can be configured during program execution. The number of functions or function blocks is not limited to two or four, but encompasses several function blocks—theoretically, any number. US Pat. No. 7,366,967 B2 proposes a diagnostic circuit for testing an I / O cell.

[0005] Especially for safety-relevant chips, it is therefore important to diagnose the functionality of the I / O cell and the corresponding pins. This is done, for example, using software-based methods. This saves chip space and involves less hardware and development effort. However, depending on the frequency of execution of the diagnostic code, software-based methods require a fixed proportion of the computing power of the chip or microcontroller. Thus, the response time until an error is detected depends on the execution frequency. The shorter the response time, the higher the load on the chip or microcontroller and the less computing power remains for the actual application. Performance therefore decreases.

[0006] Another diagnostic method involves functionally defining I / O cells at the hardware configuration level. This prevents runtime misconfiguration due to software errors. This requires predefined pins or I / O cells to be defined prior to chip production, and in particular, their capability as input pins or output pins to be fixed. However, this significantly reduces flexibility and increases the required I / O pins or I / O cells, both at the chip and package levels. The result is higher production costs compared to a chip with multiplexable I / O cells.

[0007] A typical digital I / O cell processes multiple input signals and configuration signals, as well as output signals for reading the cell. Configuration signals can be used to configure the cell for its function as an input circuit or as an output circuit. Driver strengths or other functions can also be specified. If the I / O cell is to operate as an output driver, for example, an Oen configuration signal is applied to the so-called output enable port or Oen port. When this signal is deactivated (Oen signal), the cell assumes a high-impedance state and reads the level present at the bond pad. This level is then output at an output of the I / O cell and is available to the chip's internal logic, meaning it can be buffered to be processed later, for example, by a microprocessor.

[0008] The object of the present invention is therefore to detect errors and defects in the I / O cell and its logic on the microchip in multiplex-capable I / O cells and to output a corresponding error signal without burdening the chip or microprocessor with a diagnostic routine. It is desirable that the detection be performed with a very high response speed.

[0009] The present object is achieved by a diagnostic circuit having the features of claim 1, by a circuit arrangement having the features of claim 11, by an electronic chip having the features of claim 13 and by a method having the features of claim 14.

[0010] In a first aspect, the present invention relates to a diagnostic circuit for an I / O cell and for detecting errors in the I / O cell, wherein the diagnostic circuit comprises an input interface, an output interface, a functional interface, a secure memory block for a MUX signal (so-called MUX memory block), a secure memory block for an Oen signal (so-called Oen memory block), and at least two diagnostic blocks. The input interface has an Oen input port for receiving an Oen signal, a MUX config port for receiving a MUX config signal for configuration for a multiplexer, and a cell-in port for connection to a cell output of the I / O cell to receive a cell output signal of the I / O cell.

[0011] The output interface of the diagnostic circuit has an Oen output port for outputting the Oen signal, an Out port for outputting a signal, and an Error port for outputting an error signal when an error is detected by the diagnostic circuit. A control signal, such as the MUX config signal, can be output at the Out port. Alternatively, the Out port can also be connected to a cell input of the I / O cell to supply an (input) signal to the I / O cell.

[0012] The function interface has at least two function inputs, each for connecting to a function block and for receiving a function signal, which is then forwarded to a multiplexer (as an input signal). The design of the function interface therefore depends on the number of function blocks to be connected to the I / O cell to be diagnosed.

[0013] The two safe memory blocks (MUX memory block, OEN memory block) preferably have two independent outputs for the same function signal: one output for connecting to the function circuit (multiplexer, I / O cell) and one output for connecting to the diagnostic blocks. There is also a memory block error output for outputting an error signal when an error is detected in the memory block.

[0014] The secure MUX memory block has a memory block input to which the MUX config signal is forwarded from the input interface of the diagnostic circuit. The MUX memory block performs a diagnostic function for the MUX configuration. The MUX config signal can be stored and processed in the MUX memory block.

[0015] The secure Oen memory block has a memory block input for receiving the Oen signal present at the input interface. The Oen memory block has a diagnostic function for an Oen status based on the Oen signal at the memory block input.

[0016] Each of the at least two diagnostic blocks is configured to check the function signal of one of the function blocks, wherein the check depends on at least one further signal of the input interface.

[0017] This provides a diagnostic circuit that depends on the number of function blocks to be connected to the I / O cell via a multiplexer. The number of diagnostic blocks included in the diagnostic circuit also depends on the number of function blocks to be connected. A diagnostic block is provided for each function block.

[0018] In a further aspect, the invention relates to a circuit arrangement comprising a multiplexer with a MUX output for a MUX signal and a diagnostic circuit, as described above. Such a circuit arrangement can replace the multiplexer typically present in the electronic chip. It is thereby expanded by a diagnostic circuit, as just described.

[0019] In a further aspect, the invention relates to an electronic chip, such as is provided, for example, for safety-relevant applications. Such a chip comprises at least two functional components for generating a functional signal, an I / O cell with a bonding pad for connecting a connecting wire to a substrate or a package. The chip further comprises a multiplexer for interconnecting the functional components with the I / O cell and for forwarding functional signals from the functional components to the I / O cell, and a diagnostic circuit as described above.

[0020] A further aspect relates to a corresponding method. Preferred embodiments of the invention are described in the dependent claims. It is understood that the features mentioned above and those to be explained below can be used not only in the respective combinations specified, but also in other combinations or on their own, without departing from the scope of the present invention. In particular, the method and the computer program product can be implemented according to the embodiments described for the device in the dependent claims.

[0021] According to the invention, the diagnostic circuit for the I / O cell allows the storage and buffering of a configuration signal for the multiplexer (MUX config signal). This signal is stored and further processed, resulting in a diagnostic run. For example, it can be determined whether the MUX memory block in which the diagnostic run is performed is itself error-free. Thus, a self-diagnosis is performed, not only of individual elements but also of the entire diagnostic circuit, including wiring and connecting lines.

[0022] According to the invention, the present diagnostic circuit provides an Oen memory block in which an Oen signal is used to control the function of the I / O cell, in particular to switch the I / O cell between output and input driver functions. Here, too, the Oen signal, which reflects the Oen status for the I / O cell, is temporarily stored in the Oen memory block and further processed. This results in a diagnosis of the signal as well as the Oen memory block itself, i.e., a self-diagnosis.

[0023] Since a separate diagnostic block is provided for each chip functional component to be monitored, the corresponding function signal, which can be connected to the I / O cell via the multiplexer, can be diagnosed. For diagnostics and error detection, not only the signal itself is processed. Rather, the diagnosis is performed depending on another signal from the input interface. Preferably, several signals from the input interface are processed; particularly preferably, all signals present at the input interface are included in the function signal check. This ensures that the internal circuitry of the diagnostic circuit itself, as well as the diagnostic block, can be diagnosed and errors detected.

[0024] In a preferred embodiment, the diagnostic block for checking a function signal has a diagnostic Oen input, which is connected to the Oen input port for the Oen signal of the input interface. In this way, the Oen signal present at the Oen input port can be forwarded to the diagnostic port. The diagnostic block also has a diagnostic MUX input for the MUX config signal, which is connected to the MUX config port of the input interface. A diagnostic Cell-in input for a cell output signal of the I / O cell is connected to the Cell-in port of the input interface, so that an output signal of the I / O cell is transmitted to the diagnostic block. The diagnostic block also has a diagnostic function input for the function signal of one of the function blocks connected to the diagnostic circuit.A connection exists between the diagnostic function input and one of the function inputs of the function interface. A connection is established to one of the function inputs for each diagnostic block.

[0025] In a preferred embodiment, the diagnostic block is designed to diagnose the function signal of one of the function modules depending on the output signal of the I / O cell. This is always possible when the I / O cell is connected as an output driver, i.e., an open signal is present at the corresponding input of the I / O cell. In this case, the I / O cell assumes a low-impedance state, so that the bond pad is driven by the output driver of the I / O cell to the desired level corresponding to the function signal. The level of the function signal present at the bond pad is simultaneously read back and forwarded to the diagnostic circuit. This provides permanent diagnosis of the function signal, regardless of the level and state changes of the function signal.In a preferred embodiment of the diagnostic circuit, the diagnostic block is configured to perform the diagnosis based on a comparison of the function signal of one of the function blocks, in particular the function block connected to the diagnostic block, and the output signal of the I / O cell. This checks whether the function signal and the output signal of the I / O cell are identical. In the event of a discrepancy, an error is output.

[0026] A preferred embodiment of the diagnostic circuit has a secure memory block comprising two memory chips. The signal present at the memory block input is stored redundantly, namely in each of the two memory chips. The memory block is designed to perform a self-diagnosis by checking the memory chips and the internal circuitry of the memory block for errors. If an error occurs, an error signal is output at a corresponding memory block error output and further processed in the diagnostic circuit.

[0027] Particularly preferably, the memory component of the memory block is a flip-flop component. In such a component, the two outputs, i.e., the output and the negated output, are compared. If they are equal, an error in the memory component or flip-flop component is detected. An error signal is output. Furthermore, the output of one memory component and the output of the other (redundant) memory component (diag memory component) are compared. If the output signals are unequal, an error signal is generated.

[0028] In a preferred embodiment of the diagnostic circuit, the MUX memory block comprises a memory block output that is connected to the multiplexer and influences the configuration of the multiplexer. The MUX config signal, which is further processed in the MUX memory block, determines the configuration of the multiplexer, i.e., it specifies which of the function blocks is connected to the I / O cell. A preferred embodiment of the diagnostic circuit has an input interface that has a reset port for a reset signal. The reset signal is used to initiate a reset of a memory block in the memory block. In particular, if the memory block is a flip-flop, the reset signal can be used to reset the flip-flop at a reset input provided there.

[0029] In a preferred embodiment, the diagnostic circuit is configured to generate an error signal upon the occurrence of an error in one of the memory blocks or one of the diagnostic blocks and to output this signal to its error port of the output interface. The error signal, which can be further processed in the chip, can be used to interrupt or modify the further execution of processes in the chip.

[0030] In a preferred embodiment, the diagnostic circuit is designed to perform self-diagnosis. In the event of an error, an error signal is preferably output at the error port if the self-diagnosis reveals an error in the diagnostic circuit. This includes not only errors in the individual memory blocks or diagnostic blocks, but also errors in the wiring of the diagnostic circuit itself. A self-diagnosis is therefore performed. Furthermore, incorrect multiplexer configurations or incorrect configurations of the programmed output state of the I / O cell or the control logic can also be directly detected, stored, and reported using the diagnostic circuit. With suitable interconnection with the I / O cell, the self-diagnosis also includes the I / O cell, the multiplexer, and / or the wiring of the elements.

[0031] In a preferred embodiment, the circuit arrangement comprises an I / O cell and at least two function blocks. The I / O cell preferably comprises a bond pad, a circuit block, a cell-on input for an Oen signal, a cell input for a MUX signal, and a cell output for a cell output signal. Depending on the wiring of the I / O cell with the Oen signal, the function signals forwarded by the multiplexer, which are present in the form of the MUX signal, are routed to the cell input and transmitted via the bond pad to the connected peripherals. In this case, the function signal output at the bond pad is fed back to the diagnostic blocks at the cell output. In the diagnostic blocks, the signal output at the bond pad is compared for equality with the function signal itself, which is supplied directly from the function block. If these two signals differ from one another, an error signal is output from the diagnostic block.

[0032] In a preferred embodiment of the method according to the invention, it is preferably implemented in the form of a hardware description language, for example, VHDL. The procedure described in the method using the VHDL description language is preferably technology-independent and manufacturer-independent. It thus enables hardware diagnostics for any modern and common cell library or technology.

[0033] The present invention implements the fundamental idea of ​​expanding the control of I / O cells with hardware diagnostic logic, so that simple errors such as single event upsets (SEU), defects in the multiplexer configuration, or defects in the programmed output state of the cell or the control logic are automatically detected, stored, and reported. According to the invention, the input state of the respective function inputs of the function interface, which correspond to the outputs of the function blocks, is therefore continuously compared via the diagnostic blocks of the diagnostic circuit with the state read back from the I / O cell, which is present at the cell output.

[0034] The output signal of the I / O cell present at the cell output corresponds to the initial state output at the bond pad. This allows a comparison to be made up to the bond pad to determine whether the state programmed by software or hardware and reflected in the function signals at the function interface matches the value output at the bond pad, or whether this value has been corrupted by the multiplexer circuit or a defect. This involves diagnosing not only the multiplexer, the I / O cell, and the diagnostic circuit, but also the connecting lines between the elements and within the diagnostic circuit.

[0035] Overall, the multiplexer configuration signal, i.e., the configured multiplexer state, as well as the output enable state (Oen state) are evaluated in the diagnostic blocks. This prevents a false positive diagnosis if the I / O cell or the I / O cell's output driver is deactivated, for example, to use the I / O cell as an input line. In this case, a signal is transmitted to the chip's function blocks via the bond pad.

[0036] If the multiplexer is switched to another function, the signal from the input functions that are not selected is ignored. This is said to be the case when the logic of the diagnostic circuit or circuit arrangement masks the signals.

[0037] The two signals, the MUX config signal and the open signal, are each stored redundantly in their own memory block, allowing separate memory chips or two separate signals to be used for diagnostics and control of the I / O cell. This further increases diagnostic capability.

[0038] If a simple error (single event upset) or a defect occurs in one of the memory modules or one of the flip-flops of the memory blocks, the logic as a whole, or one of the connecting lines leading to the I / O cell, the individual signals no longer match, and an error signal is generated. Such a signal can be fed back to the diagnostic circuit via a memory block error output. The individual error signals from the memory blocks and the diagnostic blocks are combined and output at the error port of the output interface of the diagnostic circuit. This diagnostic circuit has the advantage of being capable of self-diagnosis, allowing it to detect even permanent defects in its own circuit, so-called latent faults. It is possible to add signals for deliberate error injection, so-called failure injection, in order to intentionally trigger an error.In this way, the entire logic path and connections of the diagnostic circuit as well as the entire circuit arrangement can be tested for defects during operation.

[0039] The invention is described and explained in more detail below using selected embodiments in conjunction with the accompanying drawings. They show:

[0040] Figure 1 shows a schematic diagram of a circuit arrangement with diagnostic circuit, I / O cell, multiplexer and two function blocks;

[0041] Figure 2 shows a diagnostic circuit with integrated multiplexer;

[0042] Figure 3 shows a memory block in detailed view;

[0043] Figure 4 shows a diagnostic block in detail; and

[0044] Figure 5 shows a basic sequence of the method according to the invention.

[0045] Figure 1 shows an arrangement with a diagnostic circuit 100 according to the invention, an I / O cell 10, a multiplexer 20 and two function blocks 50, the outputs of which are connected to a function interface 140 of the diagnostic circuit 100.

[0046] The diagnostic circuit 100 further comprises an input interface 110, an output interface 120, two memory blocks 130 and two diagnostic blocks 180 as well as a logic element 102.

[0047] The I / O cell 10 has a circuit component 11 and a bond pad 12, which has an area for a bond wire or connecting wire to the periphery of the chip to which the I / O cell belongs. The state of the I / O cell 10 can be controlled via a Cell-Open input 14, which influences the circuit component 11 and allows the I / O cell 10 to function as both an input row and an output row. The circuit component 11 is connected via a Cell input 16 to a MUX output 22 of the multiplexer 20. The signal output via the bond pad 12 is fed back to the input interface 110 of the diagnostic circuit via a Cell output 18. The output signal of the I / O cell is present at a Cell-In port 116 of the input interface 110.

[0048] The input interface 110 further includes an open input port 112, a MUX config port 114, to which a configuration signal for the multiplexer 20 is fed and ultimately routed to a MUX config input 24 of the multiplexer. Optionally, the input interface 110 can include a reset port 118, to which a reset signal is fed, which is fed to memory blocks 130 and can reset the memory components contained therein.

[0049] One of the memory blocks 130 is designed as a MUX memory block 150 and processes the MUX config signal for configuring the multiplexer 20. The other memory module 130 is designed as an Oen memory block 170 and serves to process the Oen signal applied to the Oen input port 112 of the input interface 110, which is fed to the Cell Oen input 14 of the I / O cell 10 and controls the state of the I / O cell 10.

[0050] The output interface 120 of the diagnostic circuit 100 comprises, firstly, the Oen output port 122, at which the output enable signal, which is fed into the diagnostic circuit 100 at the Oen input port 112 and forwarded to the Cell Oen input 14 of the I / O cell, is applied. In addition, the output interface 120 comprises an error port 126, at which an error signal is output when the diagnostic circuit 100 detects an error. Another port of the output interface 120 is the Out port 124, which, in the example shown here, outputs the configuration signal for the multiplexer 20 and forwards it to the MUX config input 24 of the multiplexer 20. The Out port 124 is thus a MUX Out port. The configuration signal was fed into the diagnostic circuit 10 in the MUX config port 114 of the input interface and diagnosed in the MUX memory block 150.

[0051] Of course, the diagnostic circuit can also connect and control more than two function blocks 50 to an I / O cell 10. The function interface 140 then has several function inputs 142 and several diagnostic blocks 180. The multiplexer 20 also has several MUX inputs 26.

[0052] Regardless of whether the I / O cell 10 is configured as an input or output row, the signal is read back at bond pad 12. For example, the signal output at bond pad 12 of the I / O cell 10, regardless of the state of the Cell Open input 14, is fed back to the diagnostic circuit 100 via the Cell output 18 and then compared in the diagnostic blocks 180 with the individual function signals of the function blocks 50. This also simultaneously checks and diagnoses the entire wiring from the I / O cell 10 to the diagnostic circuit 100 and the wiring between the multiplexer 20 and the I / O cell 10.

[0053] Since the diagnostic circuit 100 is configured in hardware, neither the chip's computing power is required for the diagnosis, nor are the communication interfaces used by these I / O cells to send and receive signals affected. The diagnostic circuit according to the invention eliminates the need for complex software implementation, as is frequently used in the prior art, and the associated expensive certification. Furthermore, various functionalities can be combined on the input pins or output pins of the I / O cell, creating versatile application possibilities for small, functionally safe system-on-a-chip solutions. Each pin, i.e., each I / O cell 10, can be used as an input, an output, or any digital interface, with neither the number of functionalities nor the maximum possible switching frequency being limited.

[0054] Figure 2 shows an alternative embodiment of the diagnostic circuit 100 according to the invention, which is illustrated here in the form of a circuit arrangement 30. The circuit arrangement 30 comprises the diagnostic circuit 100 and an integrated multiplexer 20. Figure 2 also shows the I / O cell 10 together with the circuit arrangement 30.

[0055] In addition to the multiplexer 20, the diagnostic circuit 100 includes the MUX memory block 150, into which the configuration signal for the multiplexer present at the MUX config port 114 is fed. This signal is output at a memory block output 154 and fed to the MUX config input 24 of the multiplexer 20. At a memory block diagnostic output 158, a redundant output signal from the MUX memory block 150 is fed to the individual diagnostic blocks 180 at their diagnostic MUX input 184 and diagnosed in the diagnostic block 180.

[0056] The error signals present at a diagnostic block error output 190 are combined in the logic element 102 of the diagnostic circuit 100 and transmitted to the error port 126, where they are available for the internal circuitry of the chip or for other modules.

[0057] The MUX memory block 150 also has a memory block error output 156, which is also fed to the logic element 102.

[0058] Just like the MUX memory block 150, the Oen memory block 170 also has a memory block error output 156, which is also fed to the logic element 102.

[0059] The input signals of the corresponding ports of the input interface 110 and the diagnostic circuit 100 are present at the memory block inputs 152 of the MUX memory block 150 and the OEN memory block 170, respectively. This is the configuration signal for the multiplexer 20 and the output enable signal for the I / O cell 10, respectively.

[0060] The individual memory blocks 130 and the diagnostic blocks 180 are shown in more detail in drawings 3 and 4, respectively.

[0061] Figure 3 shows a memory block 130 with two redundant memory components, memory component 160 and redundant memory component 162, both of which are implemented as flip-flop components 164. Three comparators 166 are also provided, in which the individual output signals of the memory components or flip-flops 164 are compared with each other. The output signals of the comparators 166, which correspond to an error signal, are combined in a logic element 168 and output at a memory block error output 156.

[0062] The memory block 130 has a memory block input 152 and a memory block reset input 153. The memory block input 152 is connected to the D inputs of the two redundant flip-flops 164, while the memory block reset input 153 is connected to the R reset inputs of the flip-flops 164.

[0063] In memory block 130, the output of each memory chip is compared with the inverted output of the memory chip. If both signals are equal, an error signal is generated and sent to the memory block error output 156. This checks the function of the memory chips or flip-flop chips 164.

[0064] The third comparator checks whether the positive outputs of the two flip-flop modules 164 are equal. If this is not the case, an error signal 156 is output.

[0065] The output of memory module 160 is output at a memory block output 154 and, in the case of MUX memory block 150, is routed to the MUX config input 24 of multiplexer 20 to configure multiplexer 20, i.e., to select one of the input ports. In the case of Oen memory block 170, the Oen signal or output enable signal is output at memory block output 154.

[0066] The signal present at the output of the redundant memory module 162 is output at a memory block diagnostic output 158 ​​and fed to the diagnostic blocks 180.

[0067] An example of a diagnostic block 180 is shown in Figure 4. The output signal of the Oen memory block 170, which is present at the memory block diagnostic output 158, is fed to a diagnostic Oen input 182. The MUX configuration signal present at the memory block diagnostic output 158 ​​of the MUX memory block 150 is fed to a diagnostic MUX input 184. The signal present from the I / O cell 10 at its cell output 18 is applied to a diagnostic cell-in input 186. This signal is compared with the function signal of one of the function blocks 50, which is present at a diagnostic function input 188. The output signal of the I / O cell 10 and the function signal of the corresponding function block 50 must be the same; otherwise, an error is generated. The individual signals are fed into the comparator 192 of the diagnostic block 180 and output to a diagnostic block error output 190.These output signals are later passed to the logic element 102 and combined there and finally reach the error port 126 of the diagnostic circuit 100.

[0068] Figure 5 shows the basic sequence of the method according to the invention for diagnosis and error detection in an electronic chip with at least two functional modules 50, a multiplexer 20, an I / O cell 10 and a diagnostic circuit 100 with error port 126.

[0069] In a step S10, function signals from at least two function blocks 50 are received. The reception of a MUX config signal for configuring the multiplexer 20 is performed in step S12. Step S14 concerns the reception of an Oen signal for controlling the function of the I / O cell 10. A step S16 for receiving a cell output signal from the I / O cell 10 follows.

[0070] Buffering of the MUX config signal in a memory chip 160 and in a redundant memory chip 162 of a MUX memory block 150 of the diagnostic circuit 100 is performed in step S18. In step S20, the output signals of the two memory chips 160, 162 are compared for equality, and any discrepancy is detected.

[0071] In a step S22, a Diag-MUX output signal of the redundant Diag memory chip 162 is output to a diagnostic block 180 of the diagnostic circuit 100. The step also includes outputting an Oen output signal of the memory chip 160 to the multiplexer 20 and outputting an Oen error signal to the error port 126 of the diagnostic circuit 100.

[0072] A step S24 of comparing the function signal of a function block 50 with an output signal of the I / O cell 10 for a deviation in a diagnostic block 180 follows. A step S26 concerns the generation of a diagnostic block error signal depending on the deviation of the Diag-MUX output signal of the MUX memory block 150 and the Diag-Oen output signal of the Oen memory block 170.

[0073] A step S28 of processing the function signals of the function blocks 50 in the multiplexer as a function of the MUX config signal is also one of the method steps, as is a step S30 which comprises supplying a multiplexer output signal to a cell input 16 of the I / O cell.

[0074] A step S32 relates to supplying the Oen output signal to the CellOen input 14 of the I / O cell. In a step S34, the diagnostic block error signals of the diagnostic blocks 180, the MUX error signal, and the Oen error signal are combined, preferably in a logic element 102. By combining them, an error signal is generated in a step S36, which is output at the error port 126 of the diagnostic circuit 100. The method can optionally include further preferred steps or execute individual steps in multiple steps. The order of the method steps specified here is not binding. Rather, individual steps can be performed in a different order.

[0075] The method can be implemented in a computer program product, for example, in the form of program code applied on an FPGA or chip. For example, the method can be implemented in VHDL, a type of description language.

[0076] Within the scope of the invention, it was recognized that the inventive diagnostic circuit, memory or registers for storing the configuration of this initial state of the chip or I / O cell, should be designed redundantly. This allows the configuration to be continuously monitored for errors. For example, all memories are designed as redundant memory cells or flip-flops, and their outputs are continuously monitored for differences, as shown, for example, in Figure 3. The redundancy has the further advantage that separate signals can be used for configuring the I / O cell 10 and for diagnostics (signals at the memory block diagnostic output 158). This enables very reliable error detection.

[0077] The diagnostic circuit according to the invention also allows, for example, a comparison to determine whether the state output by the I / O cell on the bond pad matches the internal state programmed for the output. This comparison is performed depending on the configuration of the multiplexer and the component that selects which function determines the output state of the I / O cell 10. Should a defect occur in one of the memory modules or flip-flops, the logic, the function modules, the diagnostic blocks, or in one of the connecting lines leading to the I / O cell 10, the signals would no longer match, and an error signal would be generated. The diagnostic circuit preferably also detects when the circuit module 11, i.e., one of the transistors of the I / O cell 10, is defective. In this case, too, there would be a discrepancy between the output signal of the I / O cell and the function signal of the corresponding function module 50.

[0078] In addition to self-diagnosis, the diagnostic circuit also allows for diagnostics of the multiplexer, the I / O cell, and the connections between the individual function blocks and the I / O cell to which the function blocks are linked via the multiplexer. This applies both to signals present at the bond pad, which are thus considered input signals for the chip, and to signals output at the bond pad and forwarded by the chip to the peripherals.

[0079] Diagnosis using the diagnostic circuit is performed continuously and therefore in real time. An error that occurs is output to the error port and can, for example, be stored in a dedicated module. Depending on the configuration, an interrupt can be reported to the microprocessor or chip. This allows the software to respond to the error almost immediately. The necessary measures can be taken. The reaction time from the occurrence of the error to the generation of an interrupt is deterministic and amounts to a maximum of only a few system clock cycles. It therefore depends solely on the system clock frequency.

[0080] The invention has been comprehensively described and explained with reference to the drawings and the description. The description and explanation are to be understood as exemplary and not restrictive. The invention is not limited to the disclosed embodiments. Other embodiments or variations will become apparent to those skilled in the art upon use of the present invention and upon careful analysis of the drawings, the disclosure, and the following claims.

[0081] In the claims, the words "comprising" and "having" do not exclude the presence of further elements or steps. The undefined article "a" or "an" does not exclude the presence of a plurality. A single element or unit can perform the functions of several of the units recited in the claims. An element, unit, arrangement, and system can be partially or completely implemented in hardware and / or software. The mere mention of some measures in several different dependent claims should not be understood to mean that a combination of these measures cannot also be used advantageously. A computer program can be stored / distributed on a non-volatile data carrier, for example on an optical memory or on a solid-state drive (SSD).A computer program may be distributed together with hardware and / or as part of hardware, for example, via the Internet or via wired or wireless communication systems. Reference signs in the patent claims are not to be construed as limiting.

Claims

Patent claims 1. A diagnostic circuit for an I / O cell (10) and for detecting errors in the I / O cell (10), comprising an input interface (110) with an Oen input port (112) for receiving an Oen signal, a MUX config port (114) for receiving a MUX config signal for a multiplexer (20), and a cell-in port (116) for connection to a cell output (18) of the I / O cell (10) for a cell output signal of the I / O cell (10); an output interface (120) with an Oen output port (122) for outputting the Oen signal, an out port (124) for outputting a signal, and an error port (126) for outputting an error signal; a function interface (140) with at least two function inputs (142) for connection to a function module (50) each and for receiving a function signal each for a multiplexer (20);a MUX memory block (150) with a memory block input (152) and with a diagnostic function for a MUX configuration and for storing and processing the MUX config signal; an Oen memory block (170) with a memory block input (152) and with a diagnostic function for an Oen status based on the Oen signal; at least two diagnostic blocks (180), each for checking the function signal of one of the function blocks (50) as a function of at least one further signal of the input interface (110); 2. Diagnostic circuit according to claim 1, characterized in that the diagnostic block (180) has a diagnostic Oen input (182) with connection to the Oen input port (112) for the Oen signal, a diagnostic MUX input (184) for the MUX config signal with connection to the MUX config port (24), a diagnostic Cell-In input (186) for the cell output signal of the I / O cell (10) with connection to the Cell-In port (116) and a diagnostic function input (188) for the function signal with connection to one of the function inputs (142).

3. Diagnostic circuit according to claim 1 or 2, characterized in that the diagnostic block (180) is designed to carry out a diagnosis of the function signal of one of the function modules (50) as a function of the output signal of the I / O cell (10).

4. Diagnostic circuit according to the preceding claim, characterized in that the diagnostic block (180) is designed to carry out the diagnosis based on the comparison of the function signal of one of the function blocks (50) and the output signal of the I / O cell (10).

5. Diagnostic circuit according to one of the preceding claims, characterized in that the memory block (130) comprises two memory modules (160) in order to redundantly store the signals applied to the memory block input (152), and the memory block (130) is designed to carry out a self-diagnosis.

6. Diagnostic circuit according to the preceding claim, characterized in that the memory module (160) of the memory block (130) is a flip-flop module (164).

7. Diagnostic circuit according to one of the preceding claims, characterized in that the MUX memory block (150) has a memory block output (154) which is connected to the out port (124) of the output interface (120).

8. Diagnostic circuit according to one of the preceding claims, characterized in that the input interface (110) has a reset port (118) for a reset signal, wherein the reset signal is provided for resetting the memory module (160) of the memory block (130).

9. Diagnostic circuit according to one of the preceding claims, characterized in that the diagnostic circuit (100) is designed to output an error signal at the error port (126) when an error occurs in one of the memory blocks (130) or one of the diagnostic blocks (180).

10. Diagnostic circuit according to one of the preceding claims, characterized in that the diagnostic circuit (100) is designed to carry out a self-diagnosis and, in the event of an error, to output an error signal at the error port (126).

11. Circuit arrangement comprising a multiplexer (20) with a MUX output (22) for a MUX signal and a diagnostic circuit (100) according to one of the preceding claims, wherein the memory block output (154) of the MUX memory block (150) is connected to the multiplexer (20) and the MUX output (22) is connected to the out port (124) which is connected to a cell input (16) of the I / O cell (10).

12. Circuit arrangement according to the preceding claim, further comprising an I / O cell (10) and at least two functional modules (50), wherein the I / O cell (10) preferably has a bond pad (12), a circuit module (11), a cell open input (14) for an open signal, a cell input (16) for a mux signal and a cell output (18) for a cell output signal.

13. Electronic chip, in particular for safety-relevant applications, comprising at least two functional modules (50) for generating a signal, an I / O cell (10) with a bonding pad (12) for connecting a Connecting wire with a chip holder, a multiplexer (20) for connecting the functional modules (50) with the I / O cell (10) and a diagnostic circuit (100) according to one of the preceding claims 1 to 10.

14. A method for diagnosis and error detection in an electronic chip with at least two functional modules (50), a multiplexer (20) and an I / O cell (10) as well as a diagnostic circuit (100) with an error port (126), comprising the following steps: Receiving function signals from at least two function blocks (50); Receiving a MUX config signal to configure the multiplexer (20); Receiving an Oen signal to control the function of the I / O cell (10); Receiving a cell output signal of the I / O cell (10); Buffering the MUX config signal in a memory module (160) and in a redundant diag memory module (162) of a MUX memory block (150) of the diagnostic circuit (100); Comparing the output signal of the two memory modules (160, 162) for equality and detecting a deviation; Outputting the Diag-MUX output signal of the Diag memory chip (162) to a diagnostic block (180) of the diagnostic circuit (100), outputting the MUX output signal of the memory chip (160) to the multiplexer (20) and outputting a MUX error signal to an error port (126) of the diagnostic circuit (100); Buffering the Oen signal in a memory module (160) and in a redundant Diag memory module (162) of an Oen memory block (170) of the diagnostic circuit (100); Comparing the output signal of the two memory modules (160) for equality and detecting a deviation; Outputting the Diag-Oen output signal of the Diag memory chip (162) to a diagnostic block (180) of the diagnostic circuit (100), outputting the Oen output signal of the memory chip (160) to the multiplexer (20) and outputting an Oen error signal to the error port (126) of the diagnostic circuit (100); Comparing the function signal of a function block (50) with an output signal of the I / O cell (10) for deviation in a diagnostic block (180) and generating a diagnostic block error signal depending on the deviation, the Diag-MUX output signal of the MUX memory block and the Diag-Oen output signal of the Oen memory block (170); Processing the function signals of the function blocks (50) in the multiplexer (20) as a function of the MUX config signal and supplying a multiplexer output signal to a cell input (16) of the I / O cell (10); Supplying the Oen output signal to the Cell Oen input (14) of the I / O cell (10); Generating an error signal at the error port (126) of the diagnostic circuit (100) by supplying the diagnostic block error signal of the diagnostic blocks (180), the MUX error signal and the Oen error signal.

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