Automatic test method and system for digital chip PWM module

Abstract

The invention discloses an automatic test method for a digital chip PWM module, and the method comprises the steps: enabling a plurality of PWM capture channels to be connected with a plurality of PWM output channels, and enabling the fault input channels of the PWM output channels to be connected with a general purpose input / output (GPIO); creating an output signal data frame, wherein the data frame records a channel number, a channel state, a period value, a pulse width value, an output channel frequency division value, an effective level and a fault level; a PWM channel is started for capturing, and the pulse width and the period of an output channel are captured; the method comprises the steps of setting a period value, a pulse width value and an output frequency division value of a PWM output channel, outputting a PWM signal with a set duty ratio, initializing a data frame, and recording a channel number, the period value, the pulse width value, the frequency division value, an effective level and a fault level of the current PWM output channel; when the PWM capture channel detects that the state of the PWM output channel is RUN, whether the capture pulse width and period are consistent with the output pulse width and period of the output channel is compared, and when the capture pulse width and period are consistent with the output pulse width and period of the output channel and the number of normal capture times reaches a set threshold value, the PWM output period and duty ratio test is completed.

Description

Technical Field

[0001] The present invention belongs to the field of automated testing, and in particular relates to an automated testing method and system for a digital chip PWM module. Background Art

[0002] PWM (Pulse Width Modulation) modules, at the core of power electronics technology, are widely used in numerous fields, including industry, new energy, transportation, and consumer electronics. During digital chip verification, the PWM output waveform is affected by numerous PWM parameters. Considering only frequency, duty cycle, and frequency division, the resulting waveforms can reach hundreds of millions. Furthermore, in applications such as automotive domain controllers, dozens or even hundreds of PWM channels are required. Traditional PWM verification methods, such as manually adjusting PWM output parameters to alter the output waveform and observing with an oscilloscope or logic analyzer, are inefficient and lack sufficient verification coverage.

[0003] Furthermore, with the widespread adoption of PWM modules in new energy vehicle motor and power supply control, PWM modules have introduced numerous new features, including synchronization, fault detection, and output shielding. This has made PWM module verification increasingly complex. For example, in PWM motor control, it may be necessary to adjust both the period and duty cycle of the PWM output simultaneously. However, due to the sequential nature of the configuration registers, simultaneous adjustment of both the period and duty cycle is difficult during software modifications. By using the synchronization function, registers trigger synchronization after the register modification is complete, allowing the PWM period and duty cycle to be modified simultaneously. Furthermore, in power management systems, the PWM fault detection function can quickly set the PWM output to a fault level in the event of an overvoltage or overcurrent emergency, thereby ensuring power supply stability and safety. The output shielding function can quickly set the PWM output to an inactive level, thereby shutting down the MOS transistors.

[0004] Currently, most digital chip tests rely on manual verification by observing the PWM output waveform using an oscilloscope or logic analyzer. Regarding PWM output frequency and duty cycle verification alone, common PWM module parameters affecting the PWM output frequency and duty cycle include the counter maximum value (range 0 to 65535), the frequency divider value (range 0 to 255), and the duty cycle (0% to 100%). Duty cycle verification is performed at a 1% granularity, resulting in over 1.6 billion waveforms requiring verification. Furthermore, a chip can have dozens or even hundreds of PWM channels. Observing the PWM waveform's frequency and duty cycle using an oscilloscope consumes considerable time and effort, making manual verification a significantly inefficient approach.

[0005] In addition, there are also existing technologies that propose automated testing solutions for PWM modules. These solutions require the use of host computer software to read the logic analyzer results from the serial port and compare them with the period and duty cycle of the PWM transmitted waveform. This testing solution can only test a single PWM channel at intervals, and cannot guarantee that each period and duty cycle of the PWM output is correct. In addition, it requires reliance on external devices such as logic analyzers, oscilloscopes, and computers. Finally, many PWM characteristics, including PWM capture, synchronization, fault detection, and output control, are difficult to automate. Summary of the Invention

[0006] To solve the problem of difficulty in automated PWM testing of digital chips, the present invention proposes a solution for verifying PWM output using the PWM capture function. This solution can effectively solve the problem of difficulty in verification caused by the diversity of PWM module output waveforms during digital chip verification, and realize automated testing of the PWM module of the digital chip.

[0007] According to one aspect of the present invention, there is provided a method for automatically testing a PWM module of a digital chip, comprising: Connect multiple PWM capture channels to multiple PWM output channels, and connect the fault input channels of the PWM output channels to general GPIOs; Create an output signal data frame, which records the channel number, channel status, period value, pulse width value, output channel frequency division value, valid level, and fault level. The initial state of the channel is CLOSE. Start the PWM channel to capture the pulse width and period of the output channel; Set the period value, pulse width value, and output frequency division value of the PWM output channel, output the PWM signal with the set duty cycle, initialize the data frame, and record the channel number, period value, pulse width value, frequency division value, effective level, and fault level of the current PWM output channel; When the PWM capture channel detects that the PWM output channel state is RUN, it compares the captured pulse width and period with the output pulse width and period of the output channel to see if they are consistent. When the two are consistent and the number of normal captures reaches the set threshold, the PWM output period and duty cycle test is completed.

[0008] As a further technical solution, after completing the PWM output period and duty cycle test, it also includes: Modify the period value of the PWM output channel and enable the synchronization function. At this time, the channel period value is recorded separately and the PWM output channel status is not updated. Before triggering synchronization, the PWM output state is modified to SYNC, the capture channel stops capturing, and the period value of the data frame is updated to the modified period value. After triggering synchronization, the PWM output frequency is changed and the output state is set to RUN. The PWM capture channel continuously captures the pulse width and period and compares them with the output pulse width and period. When the two are consistent and the number of normal captures reaches the set threshold, the PWM frequency conversion and synchronization function test is completed.

[0009] As a further technical solution, after completing the PWM frequency conversion and synchronization function test, it also includes: Modify the pulse width value of the PWM output channel and trigger the synchronization function. At this time, the pulse width value is recorded separately and the PWM output channel status is not updated. Before triggering synchronization, modify the PWM output state to SYNC, stop the PWM capture channel comparison, update the PWM output channel pulse width to the recorded pulse width value, set the software trigger synchronization function, the PWM output pulse width changes according to the updated pulse width value, update the PWM output state to RUN, and the PWM capture channel continuously compares the captured pulse width and period with the output pulse width and period of the output channel to see if they are consistent. When the two are consistent and the number of normal captures reaches the set threshold, the PWM duty cycle change and synchronization function test is completed.

[0010] As a further technical solution, after completing the PWM duty cycle and synchronization function test, it also includes: Change the PWM output channel status to MASK; If the PWM capture channel cannot capture an edge, the PWM generates an overflow interrupt, reads the channel status in the overflow interrupt, and compares the valid level in the PWM output data frame with the PWM capture channel status. If they match, the capture will continue until the number of normal captures reaches the set threshold, completing the PWM output shielding function test.

[0011] As a further technical solution, after completing the PWM output shielding function test, it also includes: Update the status of all PWM output channels to CLOSE; Modify the GPIO pin status connected to the fault input channel to trigger PWM fault detection. At this time, all PWM output channels output fault levels, and the status of all PWM output channels is updated to FAULT. The PWM capture channel will continue to compare the results. At this time, the PWM generates an overflow interrupt, reads the channel status in the overflow interrupt, and compares the fault level in the PWM output data frame with the PWM capture channel status. If they are consistent, it will continue to capture until the number of normal captures reaches the set threshold, completing the PWM fault detection function test.

[0012] As a further technical solution, when performing any functional test, if the comparison results of the PWM capture channels are inconsistent, it indicates that the test is abnormal and the PWM capture channel is turned off.

[0013] As a further technical solution, when starting the PWM channel for capture, it also includes: starting the channel matching interrupt and overflow interrupt, and starting the serial port printing task.

[0014] As a further technical solution, the output channel of the test is reconfigured into a capture channel, and the capture channel is configured as an output channel, and each functional test is re-performed in sequence.

[0015] According to one aspect of the present invention, an automated testing system for a digital chip PWM module is provided, comprising a memory and a processor. The processor is connected to a printing device via a serial port and to a PWM module via a general GPIO port, wherein each PWM output channel in the PWM module corresponds to a PWM capture channel. The memory stores program instructions executed by the processor, and the processor calls the program instructions to execute the automated testing method for the digital chip PWM module.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention supports simultaneous testing of multiple PWM output channels, improving test efficiency.

[0017] 2. The present invention can simultaneously test PWM capture, synchronization function, fault detection, and modification of PWM output, channel interruption, overflow interruption and other PWM characteristics when testing PWM output.

[0018] 4. Compared with other automated testing solutions that can only verify the output of a single PWM cycle of the PWM module, this patent can test the output of multiple consecutive PWM cycles to verify the stability of the PWM output.

[0019] 5. The automated test of the present invention does not require external equipment such as logic analyzers and signal generators, and can complete the test by only checking the PWM channels against each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction will be given below to the drawings used in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 This is a schematic diagram of the automated testing process for various functions of the PWM output channel.

[0022] Figure 2 It is the PWM output information data frame, including channel number, channel status, period value, pulse width value, frequency division value, effective level and fault level.

[0023] Figure 3 Schematic diagram of the PWM capture channel initialization process.

[0024] Figure 4 This is a diagram of the channel interrupt callback function of the PWM capture channel.

[0025] Figure 5 This is a diagram of the overflow interrupt callback function of the PWM capture channel.

[0026] Figure 6 This is a diagram of the serial port printing task for the PWM capture channel.

[0027] Figure 7 This is a schematic diagram of the hardware related to the automated testing of the digital chip PWM module. DETAILED DESCRIPTION

[0028] Manual testing of digital chip PWM modules requires adjusting PWM output parameters, resulting in complex and changeable waveforms. Manual comparison of logic analyzer results consumes a lot of manpower costs. The present invention provides an automatic testing method that can solve the problem of manual testing of digital chip PWM modules.

[0029] The technical solution adopted by the present invention mainly includes: 1. Connect multiple PWM capture channels to multiple PWM output channels, and connect the fault input channels of the PWM output channels to general GPIO; 2. The software creates an output signal data frame, which records the channel number, channel status, period value, pulse width value, output channel frequency division value, valid level, and fault level. The initial state of the channel is CLOSE. 3. Start the PWM channel to capture the pulse width and period of the output channel, enable the channel match interrupt and overflow interrupt, and start the serial port printing task. At this time, the output channel status is CLOSE, and the PWM output and PWM capture results are not compared; 4. Set the period, pulse width, and output frequency division value of the PWM output channel, output a PWM signal with the set duty cycle, enable the overflow interrupt, and record the number of transmission cycles in the overflow interrupt. Output pulse width = pulse width value × output channel frequency division value, output value = period pulse width × output channel frequency division value. Initialize the data frame, record the channel number, period value, pulse width value, frequency division value, active level, and fault level of the current PWM output channel, and set the channel status to RUN. 5. The channel interrupt callback function of the PWM capture channel detects that the PWM output channel state is RUN and begins comparing the captured pulse width and period with the output pulse width and period of the output channel. The captured pulse width = captured pulse width value × capture channel frequency division value, and the captured period = captured period value × capture channel frequency division value. If the captured pulse width and period match the output, the pulse width and period capture of the next cycle continues. When the number of normal captures reaches the set threshold, the semaphore is released. If they do not match, the channel capture state is changed to abnormal and the semaphore is released. 6. After waiting for the signal, the serial port printing task determines the status of the PWM capture channel. If the status is normal, the serial port prints the PWM test as normal. If the status is abnormal, the serial port prints the PWM test as abnormal and closes the PWM channel capture.

[0030] 7. After the PWM output channel outputs a set number of cycles, the synchronization function is enabled on the PWM output channel to modify the cycle value. The PWM output frequency does not change due to the synchronization function. At this time, the channel cycle value is recorded separately and the PWM output channel status is not updated. At this time, the PWM capture channel continues to capture.

[0031] 8. Before software-triggered synchronization, change the PWM output state to SYNC. At this point, the PWM capture channel stops comparing results. Update the PWM output channel period to the period value recorded in step 7. Set the software-triggered synchronization function. The PWM output frequency changes according to the updated period value. Update the PWM output state to RUN. The PWM capture channel continues comparing results. If the captured pulse width and period match the output, capture continues for the next cycle. If not, capture stops, the serial port displays a PWM test exception, and PWM channel capture is disabled.

[0032] 9. In step 8, change the PWM output state to SYNC before triggering, and then set the output state to RUN after the PWM output changes. The reason is that after the PWM trigger is synchronized, there may be waveform distortion in the first cycle of the PWM cycle change. The waveform distortion of this cycle meets the design expectations, but it will cause PWM capture abnormalities, thereby stopping the automated test. This problem can be solved through state transition, which is also one of the design points of this solution. The state switching in the following text is also for this purpose and will not be repeated.

[0033] 10. When the PWM output channel outputs a set number of cycles, the pulse width value is modified. The PWM output pulse width does not change due to the synchronization function. At this time, the pulse width value is recorded separately and the PWM output channel status is not updated. At this time, the PWM capture channel continues to compare the results.

[0034] 11. Before software-triggered synchronization, change the PWM output state to SYNC. At this point, the PWM capture channel stops comparing and updates the PWM output channel pulse width to the value recorded in step 10. The software-triggered synchronization function is set, and the PWM output pulse width changes according to the updated value. Update the PWM output state to RUN, and the PWM channel will continue comparing results. If the captured pulse width and period match the output, capture continues for the next cycle. If not, the serial port displays a PWM test error message, and PWM channel capture is disabled.

[0035] 12. After the PWM output channel outputs a set number of cycles, test the PWM output shielding function. By shielding the output, the PWM output channel can control the PWM channel to output an invalid level. Before setting the software output, change the PWM output state to CLOSE. After setting the shielded output, the output channel outputs an invalid level. Change the PWM output channel state to MASK. Since the PWM capture channel cannot capture the edge, the PWM generates an overflow interrupt. The channel state is read in the overflow interrupt and the valid level in the PWM output data frame is compared with the PWM capture channel state. If they match, capture will continue. If they do not match, the serial port will print a PWM test exception and disable PWM channel capture.

[0036] 13. The PWM output channel has a fault detection function. Once the fault input channel pin detects a fault signal, all PWM channels will output a fault level. After the PWM output channel outputs a certain number of cycles, the status of all PWM output channels will be updated to CLOSE, and the PWM capture channel will stop comparing. Modifying the status of the GPIO pin connected to the fault input channel has triggered PWM fault detection. At this time, all PWM output channels output a fault level, and the status of all PWM output channels is updated to FAULT. The PWM capture channel will continue to compare the results. Since the edge cannot be captured, the PWM will generate an overflow interrupt. The channel status is read in the overflow interrupt, and the fault level in the PWM output data frame and the PWM capture channel status are compared. If they are consistent, capture will continue. If they are inconsistent, the serial port will print a PWM test exception and turn off PWM channel capture.

[0037] 14. If all the above test results are passed, when the PWM output channel outputs the set number of cycles, the PWM channel output is stopped, the PWM output channel state is changed to STOP, the PWM capture channel stops capturing, and the serial port printing test passes.

[0038] 15. Reconfigure the output channel tested in steps 1-14 as a capture channel, set the capture channel as an output channel, and retest according to steps 1-14 to complete the automated test of all PWM channels.

[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention are arbitrarily combined with each other to form a new technical solution. This combination is not restricted by the sequence of steps and / or structural composition mode, but must be based on the ability of ordinary technicians in this field to implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that this combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0040] Figure 1 This article describes the automated testing process for PWM digital chips. The first function tested is the PWM output period and duty cycle. The channel match value, maximum value, and frequency division value of the PWM channel are set. The PWM channel output mode is set. After the PWM counter is enabled, the PWM outputs the set period and duty cycle according to the set values.

[0041] After the PWM channel output is set, the PWM channel counter generates an overflow interrupt when it reaches its maximum value. Each overflow interrupt indicates the completion of a PWM output cycle. The static variables in the PWM output channel are accumulated to obtain the actual PWM output cycle. When the accumulated value reaches the set value, the test automatically switches to the next function to continue. If the PWM function is normal, the PWM frequency conversion and synchronization test, duty cycle change and synchronization test, output shielding test, and fault detection test will be completed in sequence.

[0042] Figure 2 An information data frame describing the PWM output channel. This frame records the channel number, channel status, period value, pulse width value, frequency division value, effective level, and fault level of the PWM output channel. This frame data is shared with the PWM capture channel, which uses this data frame to determine whether the actual output of the current PWM output channel is correct.

[0043] Figure 3This section describes the initialization process for PWM channel capture. Setting the PWM capture mode enables the channel to capture both the period and pulse width of the PWM output channel. The overflow value and frequency divider are set for the PWM capture channel. This configuration determines the frequency of PWM overflow interrupts. Next, the PWM channel interrupt and overflow interrupt are enabled. The channel interrupt determines the period and pulse width of the PWM output square wave, and the overflow interrupt determines the PWM output level. The serial port print task prints the channel test status in real time. Any test anomalies can also be printed through the serial port for easy observation. Finally, the PWM capture channel is enabled to begin capture.

[0044] Figure 4 This describes the channel interrupt callback function for the PWM capture channel. The PWM capture channel enters this function after capturing the output edge of the PWM output channel. If the PWM output channel status is RUN, the PWM channel capture value is read from the register. This capture value is multiplied by the frequency division value of the PWM capture channel to calculate the period and pulse width of the PWM channel input signal. The period and pulse width of the output channel calculated from the PWM output information data frame are then compared.

[0045] If the PWM input / output cycle and the pulse width calculation result are consistent, further determination is made as to whether the set threshold is reached. The threshold is set to adjust the serial port printing frequency. Generally, the PWM output frequency is high, and during automated testing, it is not desirable to print the test status in every cycle. If the threshold is not reached, the PWM signal of the next cycle will be captured. If the channel capture status is set to normal and a semaphore is sent to the serial port print task, the serial port will print that the channel capture is normal. If the PWM input / output cycle and the pulse width calculation result are inconsistent, the capture channel status is directly set to abnormal and a semaphore is sent. The test abnormality is printed in the serial port print task, and then the PWM capture channel is closed.

[0046] Figure 5 Describes the overflow interrupt callback function of the capture channel. When testing the PWM mask output or fault detection function, the PWM output channel outputs a level instead of a square wave. At this time, the PWM capture channel cannot capture the PWM output edge. When the counter value exceeds the overflow value, the program will enter the overflow interrupt. In the overflow interrupt, the PWM capture channel input level will be read. If the channel status bit of the PWM output data frame is MASK, the input level is compared with the effective level of the PWM output. If they match, it indicates that the PWM frequency-locked output function is normal. If the channel status bit is FAULT, the input level is compared with the fault level of the PWM output. If they match, it indicates that the PWM fault detection function is normal. Similar to testing the PWM period and pulse width, this test solution will test the output level of multiple PWM periods. If the test is abnormal, the serial port prints the test abnormality and shuts down the PWM capture channel.

[0047] Figure 6 Describes a serial port printing task. At the beginning of the printing task, the PWM output status is checked. If the output status is STOP, it indicates that all test items for the channel have been tested. At this point, the serial port printing test is complete and the PWM capture channel is closed. If the test is normal, the system waits for a signal sent by a channel interrupt or overflow interrupt. Once the signal is received, the PWM capture status is checked. If normal, the capture is normal, and the print function prints the abnormality. If abnormal, the test is abnormal, the PWM capture channel is closed, and the test for the channel is terminated.

[0048] Figure 7 This article describes the hardware required for automated testing of integrated chip PWM modules. The PWM output channels must be connected to the PWM capture channels. Furthermore, to test the PWM fault detection function, the PWM fault input channels must be connected to a general-purpose GPIO. Software can be used to change the GPIO output level to trigger the PWM fault detection function, causing all PWM output channels to output a fault level. Note that because this invention supports simultaneous multi-channel testing, triggering the PWM fault detection function requires switching the PWM output state of all channels to FAULT. The serial port is used to print test status information, including test normal, test abnormal, and test completed.

[0049] The present invention is also applicable to production line verification of integrated chip PWM modules. During production line verification, since the PWM output channel and the PWM capture channel cannot be connected through hardware, the loopback function of the integrated chip can be used to feed back the PWM output signal to the PWM capture channel, thereby completing the automated testing of the PWM module on the production line.

[0050] In summary, the key points of the present invention are: 1. The present invention uses the PWM capture function to verify PWM output, synchronization, fault detection, output shielding, interruption and other functions, which basically covers the core functions of the PWM module; 2. The present invention can simultaneously verify the output and capture functions of multiple channels, thereby improving the efficiency of verification; 3. The present invention can verify PWM outputs over multiple consecutive cycles, including scenarios where the PWM output is a square wave or high or low level. Compared to traditional verification methods that rely on sampling to verify PWM outputs, the present invention can verify the stability of PWM outputs. 4. The present invention can complete the test without external equipment, avoiding the time cost and software overhead of debugging external equipment, and is particularly suitable for the verification of digital chips on the production line.

[0051] The terms "including" and "having" and any variations thereof in the description and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions, for example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. An automated testing method for a digital chip PWM module, characterized in that: include: Connect multiple PWM capture channels to multiple PWM output channels, and connect the fault input channels of the PWM output channels to general GPIOs; Create an output signal data frame, which records the channel number, channel status, period value, pulse width value, output channel frequency division value, valid level, and fault level. The initial state of the channel is CLOSE. Start the PWM channel to capture the pulse width and period of the output channel; Set the period value, pulse width value, and output frequency division value of the PWM output channel, output the PWM signal with the set duty cycle, initialize the data frame, and record the channel number, period value, pulse width value, frequency division value, effective level, and fault level of the current PWM output channel; When the PWM capture channel detects that the PWM output channel state is RUN, it compares the captured pulse width and period with the output pulse width and period of the output channel to see if they are consistent. When the two are consistent and the number of normal captures reaches the set threshold, the PWM output period and duty cycle test is completed.

2. The automated testing method for a digital chip PWM module according to claim 1, characterized in that: After completing the PWM output period and duty cycle test, it also includes: Modify the period value of the PWM output channel and enable the synchronization function. At this time, the channel period value is recorded separately and the PWM output channel status is not updated. Before triggering synchronization, the PWM output state is modified to SYNC, the capture channel stops capturing, and the period value of the data frame is updated to the modified period value. After triggering synchronization, the PWM output frequency is changed and the output state is set to RUN. The PWM capture channel continuously captures the pulse width and period and compares them with the output pulse width and period. When the two are consistent and the number of normal captures reaches the set threshold, the PWM frequency conversion and synchronization function test is completed.

3. The automated testing method for a digital chip PWM module according to claim 2, characterized in that: After completing the PWM frequency conversion and synchronization function test, it also includes: Modify the pulse width value of the PWM output channel and trigger the synchronization function. At this time, the pulse width value is recorded separately and the PWM output channel status is not updated. Before triggering synchronization, modify the PWM output state to SYNC, stop the PWM capture channel comparison, update the PWM output channel pulse width to the recorded pulse width value, set the software trigger synchronization function, the PWM output pulse width changes according to the updated pulse width value, update the PWM output state to RUN, and the PWM capture channel continuously compares the captured pulse width and period with the output pulse width and period of the output channel to see if they are consistent. When the two are consistent and the number of normal captures reaches the set threshold, the PWM duty cycle change and synchronization function test is completed.

4. The automated testing method for a digital chip PWM module according to claim 3, characterized in that: After completing the PWM duty cycle and synchronization function test, it also includes: Change the PWM output channel status to MASK; If the PWM capture channel cannot capture an edge, the PWM generates an overflow interrupt, reads the channel status in the overflow interrupt, and compares the valid level in the PWM output data frame with the PWM capture channel status. If they match, the capture will continue until the number of normal captures reaches the set threshold, completing the PWM output shielding function test.

5. The automated testing method for a digital chip PWM module according to claim 4, characterized in that: After completing the PWM output shielding function test, it also includes: Update the status of all PWM output channels to CLOSE; Modify the GPIO pin status connected to the fault input channel to trigger PWM fault detection. At this time, all PWM output channels output fault levels, and the status of all PWM output channels is updated to FAULT. The PWM capture channel will continue to compare the results. At this time, the PWM generates an overflow interrupt, reads the channel status in the overflow interrupt, and compares the fault level in the PWM output data frame with the PWM capture channel status. If they are consistent, it will continue to capture until the number of normal captures reaches the set threshold, completing the PWM fault detection function test.

6. The automated testing method for a digital chip PWM module according to any one of claims 1 to 5, characterized in that: When performing any functional test, if the comparison results of the PWM capture channels are inconsistent, it indicates that the test is abnormal and the PWM capture channel is turned off.

7. The automated testing method for a digital chip PWM module according to any one of claims 1 to 5, characterized in that: When starting the PWM channel for capture, it also includes: enabling the channel match interrupt and overflow interrupt, and enabling the serial port printing task.

8. The automated testing method for a digital chip PWM module according to any one of claims 1 to 5, characterized in that: Reconfigure the output channel of the test into a capture channel, and then configure the capture channel into an output channel, and then re-perform each functional test in sequence.

9. The automated test system for digital chip PWM modules is characterized by: The method comprises a memory and a processor, wherein the processor is connected to a printing device via a serial port and to a PWM module via a general GPIO port, wherein each PWM output channel in the PWM module corresponds to a PWM capture channel; the memory stores program instructions executed by the processor, and the processor calls the program instructions to execute the automated testing method for the digital chip PWM module according to any one of claims 1 to 5.

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