Magnetic sensor device

Abstract

A magnetic sensor device (1) comprises a magnetic detection element (2), an energization circuit (3) that periodically excites the magnetic detection element (2), and a magnetic detection circuit (4) to which a detection signal (S1) generated in the magnetic detection element (2) in association with periodic excitation is input. The magnetic detection circuit (4) is provided with: a plurality of sample-and-hold circuits (41) that are electrically connected in parallel to the magnetic detection element (2), hold detection signals (S1) at different timings of excitation by the energization circuit (3), and output the detection signals as analog hold signals (S2); and an AD conversion circuit (42) that converts the hold signals (S2) into digital signals.

Description

magnetic sensor device

[0001] The present invention relates to a magnetic sensor device.

[0002] A magnetic sensor device using a magnetic detection element generally includes a current-carrying circuit that excites the magnetic detection element, and a magnetic detection circuit that receives a detection signal generated in the magnetic detection element upon excitation. The magnetic detection circuit is configured to periodically perform sampling at a predetermined timing synchronized with the timing of current flow to the magnetic detection element, and detect the strength of the external magnetic field to be measured.

[0003] The application of magnetic sensor devices in various fields is being considered. For example, Patent Document 1 proposes a small sensor package to be mounted on electronic devices. This sensor package comprises two electronic component chips that can operate independently as magnetic sensors and are spaced apart on a substrate. Each of the two electronic component chips includes a sensor element and an integrated circuit to which a signal from the sensor element is input. The two electronic component chips are electrically insulated from each other and connected to separate power sources. Furthermore, terminals for each electronic component chip are arranged together on adjacent sides of the substrate to prevent conductors such as wires connected to each electronic component chip from contacting each other.

[0004] Patent No. 7192688

[0005] In recent years, there has been a demand for faster magnetic detection by magnetic sensor devices. Meanwhile, the sensor package disclosed in Patent Document 1 aims to improve operational reliability by using one of two electronic component chips as a spare and operating it in the event of a failure, but does not address the need for higher speeds. While it is conceivable to shorten the sampling interval by operating both electronic component chips, attempting to further increase the speed by, for example, further increasing the number of electronic component chips leads to the following problems. Not only do components corresponding to the number of electronic component chips become necessary, but the arrangement of terminals and conductors is restricted from the standpoint of electrical insulation, which can lead to an increase in the size of the device. Furthermore, it becomes difficult to arrange the sensor elements of each electronic component chip closely together, which may increase the likelihood of errors depending on the position of the sensor elements.

[0006] The present invention has been made in view of the above-mentioned problems, and aims to provide a magnetic sensor device that is capable of increasing the sampling speed.

[0007] In order to solve the above problem, a magnetic sensor device according to one aspect of the present disclosure is a magnetic sensor device comprising: a magnetic detection element; a current-carrying circuit that periodically excites the magnetic detection element; and a magnetic detection circuit to which a detection signal generated in the magnetic detection element due to the periodic excitation is input, wherein the magnetic detection circuit comprises: a plurality of sample-and-hold circuits that are electrically connected in parallel to the magnetic detection element and hold the detection signal at different excitation timings by the current-carrying circuit and output it as an analog hold signal; and an AD conversion circuit that performs analog-to-digital conversion processing to convert the hold signal into a digital signal.

[0008] In the magnetic sensor device configured as described above, the magnetic detection element is periodically excited by the energization circuit, and the detection signal generated in the magnetic detection element is periodically input to the magnetic detection circuit. The multiple sample-and-hold circuits of the magnetic detection circuit can hold detection signals at different excitation timings, enabling faster sampling by adjusting the excitation period. The hold signals from the multiple sample-and-hold circuits are output to an AD conversion circuit as needed, where they are converted to digital signals and output as digital signals. The timing of the analog-to-digital conversion process can be set arbitrarily; for example, the processing time can be shortened by processing multiple hold signals together. This further shortens the excitation period, facilitating faster sampling.

[0009] As described above, according to the above aspect, it is possible to provide a magnetic sensor device that can increase the sampling speed.

[0010] 1 is a block diagram showing a basic configuration of a magnetic sensor device according to embodiment 1. FIG. 2 is a circuit diagram showing a configuration example of the magnetic sensor device according to embodiment 1. FIG. 3 is a timing chart showing a basic operation of the magnetic sensor device according to embodiment 1. FIG. 4 is a timing chart showing the operation of the magnetic sensor device according to embodiment 1. FIG. 5 is a circuit diagram showing a configuration example of a magnetic sensor device according to embodiment 2. FIG. 6 is a timing chart showing the operation of the magnetic sensor device according to embodiment 2. FIG. 7 is a timing chart showing the operation of the magnetic sensor device according to embodiment 2. FIG. 8 is a circuit diagram showing a configuration example of a magnetic sensor device according to embodiment 3. FIG. 9 is a timing chart showing the operation of the magnetic sensor device according to embodiment 3. FIG. 10 is a timing chart showing the operation of the magnetic sensor device according to embodiment 3.

[0011] Each embodiment will be specifically described below with reference to the drawings.

[0012] It should be noted that the embodiments described below are all comprehensive or specific examples, and the numerical values, shapes, components, arrangement positions and connection forms of the components shown in the embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims that represent the highest concept will be described as optional components.

[0013] Furthermore, although the magnetic sensor device of the present disclosure will be described based on the embodiments, the magnetic sensor device according to the present disclosure is not limited to the following embodiments. The following embodiments, modifications obtained by applying various modifications to the following embodiments that would occur to those skilled in the art without departing from the spirit of the present disclosure, and various devices incorporating the magnetic sensor device according to the present disclosure are also included in the present disclosure.

[0014] 1 is a block diagram showing a basic configuration of a magnetic sensor device 1 according to embodiment 1. FIG. 2 is a circuit diagram showing an example of a specific configuration of the magnetic sensor device 1.

[0015] 1 , the magnetic sensor device 1 includes a magnetic detection element 2, a current-carrying circuit 3, and a magnetic detection circuit 4. The magnetic sensor device 1 may further include a control circuit 5 and a signal processing circuit 6.

[0016] The energizing circuit 3 periodically excites the magnetic detection element 2. The magnetic detection element 2 is excited by the energization from the energizing circuit 3 and generates a detection signal S1. The magnetic detection element 2 includes, for example, a magnetosensitive body 21 and a detection coil 22.

[0017] A detection signal S1 generated in the magnetic detection element 2 due to periodic excitation is input to the magnetic detection circuit 4. The magnetic detection circuit 4 includes a plurality of sample-hold circuits 41 and an AD (Analog-Digital) conversion circuit .

[0018] The plurality of sample-and-hold circuits 41 are electrically connected in parallel to the magnetic detection element 2. Each sample-and-hold circuit 41 holds the detection signal S1 at a different excitation timing by the energization circuit 3 and outputs it as an analog hold signal S2. The AD conversion circuit 42 performs analog-to-digital conversion processing (hereinafter also referred to as "AD conversion processing") to convert the analog hold signal S2 into a digital signal S3.

[0019] The number (m) of sample-and-hold circuits 41 electrically connected in parallel to the magnetic detection element 2 can be any number equal to or greater than 2. In addition, a plurality of AD conversion circuits 42 are provided corresponding to the plurality of sample-and-hold circuits 41, respectively. That is, in this example, the number (n) of AD conversion circuits 42 is the same as the number of sample-and-hold circuits 41 (m=n).

[0020] 2, four AD conversion circuits 42a to 42d are provided corresponding to the four sample-and-hold circuits 41a to 41d, respectively. In this case, the magnetic detection circuit 4 can perform AD conversion processing on the hold signals S2 held in the four sample-and-hold circuits 41a to 41d by the corresponding AD conversion circuits 42a to 42d, and output the digital signals S3.

[0021] In this way, the magnetic detection circuit 4 includes multiple sample-and-hold circuits 41 for one magnetic detection element 2, so that the detection signal S1 output from the magnetic detection element 2 can be sampled in sequence and processed at any timing using the corresponding AD conversion circuit 42. Therefore, by adjusting the excitation timing of the energization circuit 3 to repeatedly excite the magnetic detection element 2 at shorter cycles and processing the detection signal S1 in parallel using the multiple sample-and-hold circuits 41, sampling can be performed at high speed.

[0022] The AD conversion processes by the AD conversion circuits 42 may be performed at the same time or at different times. Alternatively, the AD conversion circuits 42 may be divided into multiple groups, and each group may perform the AD conversion process at the same time. In this case, for example, the AD conversion circuits 42 may be divided into two or more groups, and the periods during which the AD conversion processes are performed may be combined for each group, thereby reducing the time required for the AD conversion processes.

[0023] Specifically, the AD conversion circuits 42 corresponding to a first group constituting a part of the plurality of sample-and-hold circuits 41 can perform AD conversion processing at the same timing. Also, the AD conversion circuits 42 corresponding to a second group constituting another part of the plurality of sample-and-hold circuits 41 can perform AD conversion processing at the same timing.

[0024] In this case, the AD conversion process in the first group and the AD conversion process in the second group are performed at different times, so that the AD conversion processes are not concentrated in a specific period but are distributed among the groups, thereby making it possible to suppress the influence of noise associated with the AD conversion processes on magnetic detection.

[0025] The control circuit 5 can output various control command signals at predetermined timing to the energization circuit 3, each circuit of the magnetic detection circuit 4, the signal processing circuit 6, etc. The signal processing circuit 6 can perform signal generation processing to generate magnetic detection information based on the digital signal S3 from the AD conversion circuit 42.

[0026] Specifically, the signal processing circuit 6 can acquire multiple digital signals S3 based on multiple hold signals S2 at the same timing. Furthermore, the signal processing circuit 6 can perform signal generation processing based on the acquired digital signals S3 at a timing different from that of the AD conversion processing. For example, the signal processing circuit 6 can generate multiple pieces of magnetic detection information based on each of the multiple digital signals S3. In this way, when performing the signal generation processing, it is desirable to set the timing of signal acquisition, processing, and post-processing signal output in consideration of the timing of the AD conversion processing, which suppresses the effects of noise associated with the AD conversion processing and enables highly accurate magnetic detection.

[0027] The signal generation process and the output of the processed signals in the first and second groups may be performed at different times after the respective AD conversion processes, or may be performed at the same time. If performed at different times, the magnetic detection information is output at shorter intervals. If performed at the same time, it is easier to set a different timing from the AD conversion process, thereby shortening the overall processing time. In either case, multiple pieces of magnetic detection information can be generated in a short period of time, enabling magnetic detection with good responsiveness. Alternatively, multiple digital signals S3 acquired at the same time can be used to output, for example, averaged magnetic detection information. In this case, variation due to sampling timing, etc., can be suppressed, enabling more accurate magnetic detection.

[0028] [Configuration of Each Part of Magnetic Sensor Device 1] Next, each part constituting the magnetic sensor device 1 of this embodiment will be specifically described. In Fig. 2, the magnetic sensor device 1 includes a magnetic detection element 2 and an integrated circuit 10 in which various circuits connected to the magnetic detection element 2 are integrated. The integrated circuit 10 includes a current supply circuit 3, a magnetic detection circuit 4 including a plurality of analog blocks 40, a control circuit 5, a signal processing circuit 6, and an output circuit 61.

[0029] The magnetic detection element 2 is configured as, for example, a magneto-impedance (MI) element (hereinafter also referred to as "MI element 2") including a magneto-sensitive body 21 and a detection coil 22. When an excitation current is supplied to the magneto-sensitive body 21, the MI element 2 outputs an induced voltage in the detection coil 22 as a detection signal S1.

[0030] Here, the magnetic detection circuit 4 includes four analog blocks 40a to 40d. Each analog block 40a to 40d includes one sample-and-hold circuit 41a to 41d, as well as amplifier circuits 43a to 43d, AD conversion circuits 42a to 42d, and latch circuits 44a to 44d corresponding to the sample-and-hold circuits 41a to 41d. For simplicity, in FIG. 2, only the analog block 40a is shown with subscripts, such as the corresponding sample-and-hold circuit 41a, amplifier circuit 43a, AD conversion circuit 42a, and latch circuit 44a. Although the interior of the AD conversion circuit 42a is not shown for the analog blocks 40b to 40d, they have a similar configuration.

[0031] The four analog blocks 40a to 40d are electrically connected in parallel to the MI element 2 via a pair of signal lines 71 and 72, and the output detection signal S1 is held as a hold signal S2 by one of the four sample-and-hold circuits 41a to 41d.

[0032] A precharge circuit 7 is disposed between the magnetic detection element 2 and the magnetic detection circuit 4. The precharge circuit 7 is electrically connected to each of a pair of signal lines 71, 72, and can precharge each of the signal lines 71, 72 to a predetermined reference voltage.

[0033] The control circuit 5 outputs an energization command signal MI_SW to the energization circuit 3, and outputs a sampling command signal SH_SW to the corresponding sample-and-hold circuits 41 a to 41 d to hold the detection signal S1 at a predetermined timing. Also, the control circuit 5 outputs an amplification command signal PRE_SW, an AD reset command signal AD_RST, an AD conversion command signal AD_EN, and a latch command signal AD_LAT to the corresponding amplifier circuits 43 a to 43 d, AD conversion circuits 42 a to 42 d, and latch circuits 44 a to 44 d, respectively.

[0034] The control circuit 5 can also generate and output a precharge command signal PREC_SW for driving the precharge circuit 7, a signal processing command signal SIG_EN for driving the signal processing circuit 6, and the like.

[0035] A level shift block 50 including a plurality of level shift circuits 51 is disposed on the output side of the control circuit 5. These control command signals output from the control circuit 5 are appropriately input to the level shift circuit 51, shifted to a predetermined signal level, and then output to each circuit. Note that, as with the sampling command signal SH_SWa shown in FIG. 2, the subscripts a to d added after these control command signals indicate that the signals correspond to each circuit in the analog blocks 40a to 40d. For simplicity, some of the control command signals are indicated by grouping the subscripts, such as the AD reset command signal AD_RSTab (AD reset command signals AD_RSTa, AD_RSTb). The same applies hereinafter to figures other than FIG. 2.

[0036] Specifically, the MI element 2 includes an element substrate 20, and a magnetosensitive body 21 and a detection coil 22 arranged on the element substrate 20. The magnetosensitive body 21 is made of, for example, amorphous wire, and the detection coil 22 is wound around the magnetosensitive body 21 with an insulating layer interposed between them. The element substrate 20 is provided with a pair of wire pads 23 electrically connected to both ends of the magnetosensitive body 21, respectively, and a pair of coil pads 24 electrically connected to both ends of the detection coil 22, respectively.

[0037] A pair of wire pads 23 of the MI element 2 are electrically connected to a pair of terminal portions 311, 312 of the energization circuit 3. A pair of coil pads 24 of the MI element 2 are electrically connected to a pair of signal lines 71, 72 leading to the four sample-and-hold circuits 41a to 41d of the magnetic detection circuit 4. A pulse current is supplied to the MI element 2 from the energization circuit 3 via the wire pads 23, and a detection signal S1 is output to the magnetic detection circuit 4 via the coil pads 24.

[0038] The magnetic detection element 2 may be any element capable of detecting magnetism, and may be, in addition to the MI element 2, a Hall element, an MR element (magnetoresistive element), a GMR element (giant magnetoresistive element), a TMR element (tunnel junction magnetoresistive element), or the like.

[0039] The energization circuit 3 periodically supplies an excitation current to the MI element 2. The excitation current may be, for example, a pulse current. Here, as an example, the energization circuit 3 is configured as a pulse energization circuit that can apply a pulse current to the magnetic sensitive element 21. The excitation current may be any periodic current, and may be, for example, a high-frequency current.

[0040] The energization circuit 3 includes a pair of switches 31, 32 driven by an energization command signal MI_SW from the control circuit 5, and a variable resistor 33. One of the pair of switches 31 is configured with a pMOS transistor and is inserted between one terminal portion 311 leading to one end of the magnetosensitive body 21 and the power supply terminal AVDD. The other of the pair of switches 32 is configured with an nMOS transistor and is inserted via the variable resistor 33 between the other terminal portion 312 leading to the other end of the magnetosensitive body 21 and the ground terminal GND.

[0041] The energization circuit 3 is driven by inputting a level-shifted signal of the energization command signal MI_SW to the switch 32 and inputting an inverted signal of the level-shifted signal to the switch 31. That is, the pair of switches 31 and 32 are simultaneously turned on or off in response to the energization command signal MI_SW from the control circuit 5, thereby starting or cutting off the supply of pulse current to the magnetic sensitive element 21.

[0042] When a pulse current flows through the magnetosensitive element 21, a change in magnetization of the amorphous wire generates an induced voltage in the detection coil 22. More specifically, the amorphous wire changes its circumferential permeability in response to the strength of the external magnetic field acting on it, causing a change in impedance. This change in magnetization generates an induced voltage across both ends of the detection coil 22, which is output as a detection signal S1.

[0043] The detection signal S1 is input to the magnetic detection circuit 4 via branch signal lines 711a to 711d and 721a to 721d branching from a pair of signal lines 71 and 72, and is held as a hold signal S2 in the corresponding sample-and-hold circuits 41a to 41d in response to a sampling command signal SH_SW from the control circuit 5. The four sample-and-hold circuits 41a to 41d have the same configuration.

[0044] The sample-and-hold circuit 41 a shown as an example has a pair of switches 411 and 412 and a pair of capacitors 413 and 414 arranged between a pair of input terminals 415 and 416 and a pair of output terminals 417 and 418 .

[0045] In the sample-and-hold circuit 41a, one switch 411 of the pair opens and closes between one input terminal 415 of the pair and an output terminal 417. One end of a capacitor 413 is connected between the switch 411 and the output terminal 417, and the other end is grounded. The other switch 412 of the pair opens and closes between the other input terminal 416 of the pair and an output terminal 418. One end of a capacitor 414 is connected between the switch 412 and the output terminal 418, and the other end is grounded.

[0046] A signal obtained by level-shifting the sampling command signal SH_SW (SH_SWa) from the control circuit 5 and its inverted signal are input to the control terminals of the pair of switches 411, 412. As will be described later, the sampling command signal SH_SW is a pulse signal that rises before the energization command signal MI_SW is output and falls when the detection signal S1 reaches its peak value. As a result, while the sampling command signal SH_SW is being output, the detection signal S1 from the pair of signal lines 71, 72 is input to the sample-and-hold circuit 41a, and the peak value of the detection signal S1 is held by the pair of capacitors 413, 414.

[0047] The sample and hold circuits 41b to 41d also have a similar configuration in which a pair of switches 411, 412 are used to open and close between a pair of input terminal sections 415, 416 and a pair of output terminal sections 417, 418 to acquire a hold signal S2, and therefore illustrations and explanations thereof will be omitted.

[0048] The hold signal S2 is amplified at a predetermined amplification factor in amplifier circuits 43a to 43d, which are arranged downstream of the sample-and-hold circuits 41a to 41d. This amplified signal S21 is input to the AD conversion circuits 42a to 42d via output lines 73a to 73d. Note that the amplifier circuits 43a to 43d may be omitted. In this embodiment, the latch circuits 44a to 44d are built into the AD conversion circuits 42a to 42d, and latch the AD-converted digital signal S3 via digital signal lines 74a to 74d. The digital signal S3 is output at a predetermined timing from digital output lines 75a to 75d to the signal processing circuit 6.

[0049] The precharge circuit 7 has, for example, a configuration in which a pair of precharge switches 701, 702 are electrically connected in series between a pair of signal lines 71, 72. A reference voltage generation circuit 70 is connected to a series connection point that serves as the input terminals of the precharge switches 701, 702, and output terminals of the precharge switches 701, 702 are connected to the signal lines 71, 72, respectively. A signal obtained by level-shifting a precharge command signal PREC_SW from the control circuit 5 and an inverted signal of the signal are input to the control terminals of the precharge switches 701, 702.

[0050] The precharge circuit 7 is driven, for example, prior to input of the detection signal S1 based on the energization command signal MI_SW, so that the pair of signal lines 71 and 72 are precharged to a predetermined reference voltage, suppressing errors due to fluctuations in the potential of each signal line 71 and 72, thereby enabling stable magnetic detection.

[0051] [Operation of Magnetic Sensor Device 1] The operation of the magnetic sensor device 1 having the above-described configuration will be described below with reference to Figures 3 to 5. Figures 4 and 5 are timing charts showing the operation of each part of the magnetic sensor device 1. Figure 3 shows a timing chart of a sampling operation using an analog block 40a including a sample-and-hold circuit 41a as a basic operation.

[0052] 3 and 4, the control circuit 5 outputs the sampling command signal SH_SW (SH_SWa to SH_SWd) as a pulse signal that rises before the energization command signal MI_SW is output and falls when the detection signal S1 reaches its peak value. As a result, the corresponding sample-and-hold circuits 41a to 41d acquire hold signals S2 that are the peak values ​​of the detection signals S1, and the amplified signals S21 are AD converted for each group.

[0053] Prior to this, the control circuit 5 outputs a precharge command signal PREC_SW to drive the precharge circuit 7. Furthermore, it is desirable that the AD conversion circuits 42a to 42d and the amplifier circuits 43a to 43d corresponding to the sampling command signal SH_SW are reset to their initial states prior to their respective operations.

[0054] 3, the control circuit 5 outputs a sampling command signal SH_SWa and a precharge command signal PREC_SW to the sample-and-hold circuit 41a, and also outputs an amplification command signal PRE_SWa to the amplifier circuit 43a.

[0055] Thereafter, at time T2, the control circuit 5 outputs the energization command signal MI_SW, and the energization circuit 3 starts exciting the MI element 2. Note that Fig. 3 shows the sampling operation using the analog block 40a extracted from Figs. 4 and 5. The period from time T1 to time T21 indicated by the arrow in the figure (from one rising edge of the sampling command signal SH_SWa to the next rising edge) corresponds to the sampling frequency (20T).

[0056] Immediately before time T1, the detection signal S1 is not being output, and the sample-and-hold circuit 41a is in a state of holding the hold signal S2 from the previous detection. When the precharge command signal PREC_SW and the sampling command signal SH_SWa rise at time T1, the potential difference between the pair of branch signal lines 711a and 721a gradually decreases and reaches the same reference potential by time T2. As a result, the potential of the output line 73a of the corresponding amplifier circuit 43a also decreases.

[0057] In this way, while the precharge command signal PREC_SW is being output, the precharge switches 701 and 702 are in an ON state, and the reference voltage from the reference voltage generation circuit 70 is supplied to the pair of signal lines 71 and 72. Because the pair of signal lines 71 and 72 to which the detection signal S1 is output is in a floating state, the potential may not stabilize after the previous detection is completed. Even in this case, the pair of signal lines 71 and 72 are precharged to a predetermined reference voltage prior to the current detection, thereby resetting, for example, the potential difference occurring between the pair of signal lines 71 and 72.

[0058] Furthermore, the amplifier circuit 43a to which the hold signal S2 is input is reset, for example, to its initial state in response to the input of the amplification command signal PRE_SWa. Through these processes, the potential of the output line 73a corresponding to the amplified signal S21 is quickly reduced, allowing the current detection to be performed in a stable state.

[0059] At time T2, when excitation of the MI element 2 is initiated by the energization command signal MI_SW, the potential difference (detection signal S1) between the pair of signal lines 71, 72 gradually increases. Then, as the potential difference between the pair of branch signal lines 711a, 721a increases, the potential of the output line 73a of the amplifier circuit 43 also increases. The sampling command signal SH_SWa is set in consideration of the delay time until the detection signal S1 reaches its peak value, and falls, for example, at time T3. Accordingly, the sample-and-hold circuit 41a holds the peak value of the detection signal S1 as a hold signal S2, and the amplified signal S21 is output from the output line 73a.

[0060] Thereafter, at time T5, when the energization command signal MI_SW falls, the potential difference signal between the pair of signal lines 71 and 72 inverts from the positive side to the negative side and then returns to a state where there is almost no potential difference by, for example, around time T6. Therefore, for example, in the period from time T6 to time T8, the AD reset command signal AD_RSTa is output, and the AD conversion circuit 42a is reset to the initial state.

[0061] Next, at time T9, the AD conversion command signal AD_ENa rises, causing the AD conversion circuit 42a to read the amplified signal S21 of the hold signal S2 from the output line 73a, and start the AD conversion process. The AD conversion circuit 42a has, for example, an N-bit resolution, compares the input analog voltage signal with a reference voltage, converts it into an N-bit digital signal S3, and stores it.

[0062] The AD conversion circuit 42a ends the AD conversion process when the digital signal S3 is established. For example, at time T15, the AD conversion process ends and the AD conversion command signal AD_ENa falls, and the control circuit 5 outputs the latch command signal AD_LATa from time T15 to time T16. This causes the latch circuit 44a to latch the digital signal S3 stored in the AD conversion circuit 42a.

[0063] Thereafter, for example, at time T26, when the control circuit 5 outputs a signal processing command signal SIG_EN, the signal processing circuit 6 reads the digital signal S3 latched in the latch circuit 44a. Then, the signal processing circuit 6 performs predetermined arithmetic processing as a signal generation process to generate magnetic detection information and outputs it to the output circuit 61. The arithmetic processing includes, for example, calculations to suppress individual variations and calculations to detect the position of an object.

[0064] The output circuit 61 can output the result of the signal generation process to the outside as magnetic detection data D (or its inverted data / D) (time T27).

[0065] Here, it is desirable that the timing at which the signal processing command signal SIG_EN and the magnetic detection data D are output is a period during which AD conversion processing is not performed. For example, if the AD conversion processing period is set to end at time T25, the signal processing command signal SIG_EN and the magnetic detection data D are output later than that and during the period (time T26 to time T28) before the start of the next AD conversion processing period (time T29).

[0066] During this period, the AD reset command signal AD_RSTa before the next AD conversion process is also output. In other words, it is desirable that the previous signal generation process and data output are performed during the output period (time T6 to time T8) of the current AD reset command signal AD_RSTa. This suppresses the influence of noise generated during the AD conversion process, allowing for accurate signal generation process.

[0067] In this way, magnetic detection data D based on the Mth digital signal S3 (N-bit (M) in the figure) obtained by the current AD conversion process is output before the next AD conversion process. Similarly, before the current AD conversion process, the (M-1)th digital signal S3 (N-bit (M-1) in the figure) obtained by the previous AD conversion process is read in at the timing when the AD reset command signal AD_RSTa is output, and magnetic detection data D based on it is output.

[0068] [Group-specific operation by analog blocks 40a to 40d] As shown in Figures 4 and 5, sampling using sample-and-hold circuits 41b to 41d and AD conversion processing by AD conversion circuits 42b to 42d in analog blocks 40b to 40d can also be performed in the same manner.

[0069] At this time, the processes by the analog blocks 40a to 40d are performed in parallel, so it is possible to speed up sampling by adjusting the excitation timing of the MI element 2. In this case, the analog blocks 40a to 40d can be divided into multiple groups, and the corresponding AD conversion process can be performed for each group.

[0070] 5, the AD conversion process is performed by dividing the analog blocks 40a to 40d into two groups. That is, of the four sample-and-hold circuits 41a to 41d, two sample-and-hold circuits 41a and 41b are grouped as a first group, and the AD conversion processes by the corresponding AD conversion circuits 42a and 42b are performed at the same timing. The other two sample-and-hold circuits 41c and 41d are grouped as a second group, and the AD conversion processes by the corresponding AD conversion circuits 42c and 42d are performed at the same timing.

[0071] The AD conversion processes in the same group are performed at the same timing after the corresponding multiple hold signals S2 are acquired. The AD conversion process in the first group is performed at a different timing from the AD conversion process in the second group. Note that the number of groups and the method of division are merely examples and can be set arbitrarily depending on the number of analog blocks and the timing of the AD conversion process and other processes.

[0072] 4 and 5, the sampling (from time T1 to time T6) using the sample-and-hold circuit 41a of the first group and the operation of each circuit including the corresponding AD conversion circuit 42a are the same as those in the example shown in Fig. 3. Subsequently, the sample-and-hold circuit 41b of the first group performs sampling in the same manner as the sample-and-hold circuit 41a, based on the control command signal output from the control circuit 5, during the period from time T6 to time T11.

[0073] Specifically, at time T6, the control circuit 5 outputs a sampling command signal SH_SWb and a precharge command signal PREC_SW prior to exciting the MI element 2. The control circuit 5 also outputs an amplification command signal PRE_SWb to the amplifier circuit 43b.

[0074] Thereafter, when the energization command signal MI_SW is output during the period from time T7 to time 10, the MI element 2 is excited and the detection signal S1 is output. Next, at time T8, when the sampling command signal SH_SWb falls, the sample-and-hold circuit 41b holds the peak value of the detection signal S1 as a hold signal S2 based on the potential difference signal between the branch signal lines 711b and 721b. The hold signal S2 is further amplified by the amplifier circuit 43b and output to its output line 73b as an amplified signal S21.

[0075] Furthermore, during the period from time T6 to time T8, prior to the AD conversion processing by the AD conversion circuits 42a, 42b, AD reset command signals AD_RSTa, AD_RSTb are output from the control circuit 5. Subsequently, at time T9, the AD conversion command signals AD_ENa, AD_ENb rise, causing the AD conversion circuits 42a, 42b to read the amplified signal S21 of the hold signal S2 from the output lines 73a, 73b, respectively, and start the AD conversion processing.

[0076] Then, when the AD conversion process is completed at time T15, the AD conversion command signals AD_ENa and AD_ENb fall, and the latch command signals AD_LATa and AD_LATb are output from time T15 to time T16. This causes the latch circuit 44a to latch the Mth digital signal S3 (N-bit (M) in the figure) stored in the AD conversion circuit 42a. Also, the latch circuit 44b latches the (M+1)th digital signal S3 (N-bit (M+1) in the figure) stored in the AD conversion circuit 42b.

[0077] Subsequently, sampling by the sample-and-hold circuits 41c and 41d of the second group and operation of each circuit including the corresponding AD conversion circuits 42c and 42d are performed in the same manner as in the first group.

[0078] That is, at time T11, the control circuit 5 outputs a sampling command signal SH_SWc and a precharge command signal PREC_SW prior to exciting the MI element 2. In addition, the control circuit 5 outputs an amplification command signal PRE_SWc to the amplifier circuit 43c.

[0079] Thereafter, when the energization command signal MI_SW is output during the period from time T12 to time T15, the MI element 2 is excited and the detection signal S1 is output. Next, at time T13, when the sampling command signal SH_SWc falls, the sample-and-hold circuit 41c holds the peak value of the detection signal S1 as a hold signal S2 based on the potential difference signal between the branch signal lines 711c and 721c. The hold signal S2 is further amplified by the amplifier circuit 43c and output to its output line 73c as an amplified signal S21.

[0080] Furthermore, at time T16, the control circuit 5 outputs a sampling command signal SH_SWd and a precharge command signal PREC_SW prior to exciting the MI element 2. Furthermore, the control circuit 5 outputs an amplification command signal PRE_SWd to the amplifier circuit 43d.

[0081] Thereafter, when the energization command signal MI_SW is output during the period from time T17 to time T20, the MI element 2 is excited and the detection signal S1 is output. Next, at time T18, when the sampling command signal SH_SWd falls, the sample-and-hold circuit 41d holds the peak value of the detection signal S1 as a hold signal S2 based on the potential difference signal between the branch signal lines 711d and 721d. The hold signal S2 is further amplified by the amplifier circuit 43d and output to its output line 73d as an amplified signal S21.

[0082] Meanwhile, in the period from time T16 to time T18, prior to the AD conversion processing by the AD conversion circuits 42c, 42d, AD reset command signals AD_RSTc, AD_RSTd are output from the control circuit 5. Subsequently, at time T19, the AD conversion command signals AD_ENc, AD_ENd rise, causing the AD conversion circuits 42c, 42d to read the amplified signal S21 of the hold signal S2 from the output lines 73c, 73d, respectively, and start the AD conversion processing.

[0083] Then, when the AD conversion process is completed at time T25, the AD conversion command signals AD_ENc and AD_ENd fall, and the latch command signals AD_LATc and AD_LATd are output from time T25 to time T26. As a result, the latch circuit 44c latches the (M+2)th digital signal S3 (N-bit(M+2) in the figure) stored in the AD conversion circuit 42c. Also, the latch circuit 44d latches the (M+3)th digital signal S3 (N-bit(M+3) in the figure) stored in the AD conversion circuit 42d.

[0084] Thereafter, at time T26, when the control circuit 5 outputs a signal processing command signal SIG_EN, digital signals S3 are output from the digital output lines 75a to 75d to the signal processing circuit 6. The signal processing circuit 6 reads the four digital signals S3 latched in the latch circuits 44a to 44d, and performs predetermined signal generation processing on each of them. The results of this signal generation processing are output as four pieces of magnetic detection data D (or / D) from the output circuit 61 at the following time T27.

[0085] During this period, at time T21, the sampling command signal SH_SWa for the next sampling by the sample-and-hold circuit 41a is output. In this manner, sampling by the sample-and-hold circuits 41a to 41d can be repeatedly performed during the period from time T1 to time T21. In this case, the sampling frequency is, for example, 5T, which corresponds to the period from time T1 to time T6, and is reduced to one-fourth of the basic operation (sampling frequency: 20T) shown in FIG. 3.

[0086] According to this embodiment, the magnetic sensor device 1 can perform sampling and the subsequent AD conversion process at high speed because it includes four electrically parallel sample-hold circuits 41a to 41d and four corresponding AD conversion circuits 42a to 42d for one MI element 2. Furthermore, the four sample-hold circuits 41a to 41d are divided into first and second groups, and the corresponding AD conversion processes are performed at the same time, thereby reducing the time required for the AD conversion process and enabling even faster speeds.

[0087] In this case, the reading of the digital signal S3 by the signal processing circuit 6, the signal generation process, and the subsequent output of the magnetic detection data D can be performed at any timing different from the AD conversion process. This shortens the period during which noise output due to the AD conversion process is a concern, thereby suppressing its influence on other signals. Furthermore, because the AD conversion process is performed at different times for the first and second groups, the AD conversion process periods within one sampling period are dispersed, reducing variability in the influence of noise and improving detection accuracy.

[0088] In this way, the magnetic sensor device 1 includes a magnetic detection circuit 4 including a plurality of sample-and-hold circuits 41 and the same number of AD conversion circuits 42, thereby enabling high-speed parallel processing of the detection signal S1 from the MI element 2. In this case, it is possible to output a plurality of pieces of magnetic detection data D based on a plurality of digital signals S3 in a short time, and by adjusting the timing of each process, it is possible to perform magnetic detection with good responsiveness and high accuracy.

[0089] (Embodiment 2) Fig. 6 is a diagram showing an example of the circuit configuration of a magnetic sensor device 1 according to embodiment 2, and Figs. 7 and 8 are timing charts showing the operation of each part of the magnetic sensor device 1. In this embodiment, the basic configuration and basic operation of the magnetic sensor device 1 are the same as those of embodiment 1, but the configurations and operations of the analog blocks 40a to 40d are partially different. The differences will be described below.

[0090] In this embodiment, the magnetic sensor device 1 includes sub-sample and hold circuits 45a to 45d in the analog blocks 40a to 40d of the magnetic detection circuit 4. The sub-sample and hold circuits 45a to 45d are arranged between the amplifier circuits 43a to 43d and the AD conversion circuits 42a to 42d in the corresponding analog blocks 40a to 40d, respectively. The other configurations of the magnetic detection circuit 4 and other circuit configurations are the same as those in the first embodiment, and therefore description thereof will be omitted.

[0091] In addition, in the first embodiment, the four sample-and-hold circuits 41a to 41d are divided into two groups and the corresponding AD conversion processes are performed at different timings, but in this embodiment, they are not divided into groups, that is, for all sample-and-hold circuits 41a to 41d in the analog blocks 40a to 40d, the corresponding AD conversion circuits 42a to 42d perform the AD conversion processes at the same timing.

[0092] 6, the sub-sample and hold circuits 45a to 45d are connected to output lines 73a to 73d of the amplifier circuits 43a to 43d, respectively. The sub-sample and hold circuits 45a to 45d have the same configuration as the sample and hold circuits 41a to 41d, and are driven by sub-sampling command signals SHS_SWa to SHS_SWd from the control circuit 5. When the sub-sampling command signals SHS_SWa to SHS_SWd are output, a signal level-shifted by the level shift circuit 51 and its inverted signal are input to the corresponding sub-sample and hold circuits 45a to 45d.

[0093] The sub-sample-and-hold circuits 45a to 45d hold the amplified signals S21 of the hold signals S2 output to the output lines 73a to 73d at the falling edges of the sub-sampling command signals SHS_SWa to SHS_SWd, respectively. The amplified signals S21 thus held are output to the AD conversion circuits 42a to 42d and are subjected to AD conversion processing.

[0094] In FIG. 7, the operation (the period from time T1 to time T18) until the amplified signal S21 of the hold signal S2 is output to the output lines 73a to 73d by sampling using the sample-and-hold circuits 41a to 41d is the same as the example shown in the first embodiment (FIG. 4), and therefore a description thereof will be omitted.

[0095] 8, the sub-sampling command signals SHS_SWa to SHS_SWd rise, driving the sub-sample-and-hold circuits 45a to 45d at the same timing. Then, at time T19, the sub-sampling command signals SHS_SWa to SHS_SWd fall, and the AD conversion command signals AD_ENa to AD_ENd rise. Furthermore, during the period from time T15 to time T17 prior to the AD conversion process, the AD reset command signals AD_RSTa to AD_RSTd are output at the same timing.

[0096] As a result, the sub-sample-and-hold circuits 45a to 45d hold the amplified signals S21 of the hold signals S2 output to the output lines 73a to 73d, respectively. The amplified signals S21 thus held are output to the AD conversion circuits 42a to 42d, and the AD conversion process starts at time T19.

[0097] Then, when the AD conversion process is completed at time T25, the AD conversion command signals AD_ENa to AD_ENd fall, and the latch command signals AD_LATa to AD_LATd are output from time T25 to time T26, causing the latch circuits 44a to 44d to latch the M-th to M+3-th digital signals S3 stored in the corresponding AD conversion circuits 42c, respectively.

[0098] After that, at time T26, when the signal processing command signal SIG_EN is output from the control circuit 5, the signal processing circuit 6 reads the four digital signals S3 and performs predetermined signal generation processing for each of them. Then, at time T27, the output circuit 61 outputs four pieces of magnetic detection data D (or / D).

[0099] In this way, the four AD conversion circuits 42a to 42d can perform AD conversion processes at the same time in the magnetic sensor device 1. At that time, each analog block 40a to 40d can use the sub-sample-and-hold circuits 45a to 45d to hold the amplified signal S21 of the hold signal S2 from the sample-and-hold circuits 41a to 41d at the same time and output it to the AD conversion circuits 42a to 42d. After the conversion process, the signal processing circuit 6 can quickly perform signal generation processing to output magnetic detection information based on the four digital signals S3.

[0100] According to this embodiment, the magnetic sensor device 1 includes the same number of AD conversion circuits 42 as the four sample-and-hold circuits 41a to 41d, and AD conversion processing is performed for all of them at the same timing, further shortening the time required for AD conversion processing. Therefore, in addition to speeding up sampling, it becomes easier to adjust the timing of other processing, further reducing the impact on other signals and timing variations. This enables responsive and highly accurate magnetic detection.

[0101] 9 is a diagram showing an example of the circuit configuration of a magnetic sensor device 1 according to embodiment 3, and FIGS. 10 and 11 are timing charts showing the operation of each part of the magnetic sensor device 1. In this embodiment, the basic configuration of the magnetic sensor device 1 is the same as that of embodiment 2, with a partial difference in the configuration of the magnetic detection circuit 4. The basic operation of this sample is also the same as that of embodiment 1, and the differences will be explained below.

[0102] The magnetic detection circuit 4 does not need to have the same number of AD conversion circuits 42 for the multiple sample and hold circuits 41, and may have a configuration in which one AD conversion circuit 42 is provided in common for two or more sample and hold circuits 41. In this embodiment, two AD conversion circuits 42e and 42f are provided, corresponding to two of the four sample and hold circuits 41a to 41d. Also, switches 46e and 46f are provided for the two AD conversion circuits 42e and 42f, respectively, so that connection with the corresponding sample and hold circuits 41a to 41d can be switched.

[0103] 9, the magnetic detection circuit 4 includes four analog blocks 40a to 40d corresponding to four sample and hold circuits 41a to 41d. Each of the analog blocks 40a to 40d includes an amplifier circuit 43a to 43d and a sub-sample and hold circuit 45a to 45d corresponding to the sample and hold circuit 41a to 41d, respectively.

[0104] The magnetic detection circuit 4 also has two AD conversion circuits 42e and 42f, each corresponding to two of the four sample and hold circuits 41a to 41d. Of the two AD conversion circuits 42e and 42f, the AD conversion circuit 42e is connected to two sub sample and hold circuits 45a and 45c via a switch 46e. The AD conversion circuit 42f is also connected to two sub sample and hold circuits 45b and 45d via a switch 46f.

[0105] The selector 46e has, for example, a changeover switch 461 and selectively connects the AD conversion circuit 42e to one of the two sub-sample and hold circuits 45a and 45c. The selector 46f has, for example, a changeover switch 462 and can selectively connect the AD conversion circuit 42f to one of the two sub-sample and hold circuits 45b and 45d.

[0106] The control circuit 5 outputs switching command signals AD_SWa to AD_SWd to drive the changeover switch 461 of the switch 46e or the changeover switch 462 of the switch 46f. Specifically, the control circuit 5 outputs the switching command signal AD_SWa or the switching command signal AD_SWc to drive the changeover switch 461 of the switch 46e, connecting the AD conversion circuit 42e to a selected one of the two sub-sample and hold circuits 45a, 45c. The control circuit 5 also outputs the switching command signal AD_SWb or the switching command signal AD_SWd to drive the changeover switch 462 of the switch 46f, connecting the AD conversion circuit 42f to a selected one of the two sub-sample and hold circuits 45b, 45d. In this way, the connections between the AD conversion circuits 42e, 42f and the analog blocks 40a to 40d that perform AD conversion processing can be switched.

[0107] In this embodiment, as in the first embodiment, the four sample-and-hold circuits 41a to 41d are divided into two groups, and AD conversion processing is performed for each group. Specifically, the two AD conversion circuits 42e and 42f are first connected to the corresponding analog blocks 40a and 40b for the two sample-and-hold circuits 41a and 41b that make up the first group, respectively, and perform AD conversion processing. Next, the other two sample-and-hold circuits 41c and 41d that make up the second group are connected to the corresponding analog blocks 40c and 40d, respectively, and perform AD conversion processing.

[0108] In this way, when the four sample-and-hold circuits 41a to 41d are divided into pairs each and AD conversion processing is performed at different timings, only two AD conversion circuits 42e, 42f are required, and the number of AD conversion circuits 42 can be reduced. The configuration of the AD conversion circuits 42e, 42f is the same as in the first embodiment, and the latch circuits 44e, 44f latch the AD-converted digital signal S3 via digital signal lines 74e, 74f. The digital signal S3 is output from digital output lines 75e, 75f to the signal processing circuit 6 at a predetermined timing. The rest of the circuit configuration of the magnetic sensor device 1 is the same as in the second embodiment, and therefore description thereof will be omitted.

[0109] 10 and 11, the operation (the period from time T1 to time T18) until the amplified signal S21 of the hold signal S2 is output to the output lines 73a to 73d by sampling using the sample-and-hold circuits 41a to 41d is the same as the example shown in the first embodiment (FIG. 4), and therefore a description thereof will be omitted.

[0110] In this embodiment, for example, from time T6 to time T8, the control circuit 5 outputs AD reset command signals AD_RSTe and AD_RSTf prior to the AD conversion processing by the AD conversion circuits 42e and 42f. Subsequently, at time T8, the sub-sampling command signals SHS_SWa and SHS_SWb rise, causing the sub-sample-and-hold circuits 45a and 45b to be driven at the same timing. Then, at time T9, the sub-sampling command signals SHS_SWa and SHS_SWb fall, and the switching command signals AD_SWa and AD_SWb are output. Also at time T9, the AD conversion command signals AD_ENe and AD_ENf rise. As a result, the AD conversion circuits 42e and 42f are connected to the sub sample-and-hold circuits 45a and 45b, respectively, and the amplified signal S21 of the held hold signal S2 is read in, starting the AD conversion process.

[0111] Then, for example, when the AD conversion process is completed at time T15, the AD conversion command signals AD_ENe and AD_ENf fall, and the latch command signals AD_LAte and AD_LATf are output from time T15 to time T16, causing the latch circuits 44e and 44f to latch the M-th to (M+1)-th digital signals S3 of the AD conversion circuits 42e and 42f corresponding to the first group of sample-and-hold circuits 41a and 41b.

[0112] Subsequently, similar to the sample-and-hold circuits 41a and 41b of the first group, AD conversion processing is performed by the AD conversion circuits 42e and 42f corresponding to the sample-and-hold circuits 41c and 41d of the second group.

[0113] First, during the period from time T16 to time T18, the control circuit 5 again outputs AD reset command signals AD_RSTe and AD_RSTf. In this embodiment, the signal processing command signal SIG_EN is output during this period. For example, when the signal processing command signal SIG_EN is output at time T16, the two latched digital signals S3 are output from the digital output lines 75e and 75f to the signal processing circuit 6. The signal processing circuit 6 performs a predetermined signal generation process on each of the read digital signals S3, and at time T17, the output circuit 61 outputs two pieces of magnetic detection data D (or / D).

[0114] Subsequently, at time T18, the sub-sampling command signals SHS_SWc and SHS_SWd rise, driving the sub-sample and hold circuits 45c and 45d at the same timing. Then, at time T19, the sub-sampling command signals SHS_SWc and SHS_SWd fall, and the switching command signals AD_SWc and AD_SWd are output. Also at time T19, the AD conversion command signals AD_ENe and AD_ENf rise. As a result, the AD conversion circuits 42e and 42f are connected to the sub-sample and hold circuits 45c and 45d, respectively, and the amplified signal S21 of the held hold signal S2 is read in, starting the AD conversion process.

[0115] Then, for example, when the AD conversion process is completed at time T25, the AD conversion command signals AD_ENe and AD_ENf fall, and the latch command signals AD_LAte and AD_LATf are output from time T25 to time T26, causing the latch circuits 44e and 44f to latch the (M+2)-th to (M+3)-th digital signals S3 of the AD conversion circuits 42e and 42f corresponding to the second group of sample-and-hold circuits 41c and 41d.

[0116] Thereafter, at time T26, when the control circuit 5 outputs a signal processing command signal SIG_EN, the signal processing circuit 6 reads the two latched digital signals S3 and performs a predetermined signal generation process on each of them. Then, at time T27, the output circuit 61 outputs two pieces of magnetic detection data D (or / D). In this way, each time an AD conversion process is performed, the digital signals S3 may be read into the signal processing circuit 6 and signal processing may be performed during the period until the next AD conversion process is performed. Alternatively, the digital signals S3 may only be read, and the signal processing and output of the results may be performed during any period when the AD conversion process is not performed.

[0117] According to this embodiment, the magnetic sensor device 1 includes two AD conversion circuits 42e-42f corresponding to the four sample-and-hold circuits 41a-41d, and performs AD conversion processing by dividing the circuits into first and second groups, thereby enabling high-speed sampling and subsequent AD conversion processing. In this case, by using the two AD conversion circuits 42e-42f in common for the first and second groups and switching the connection with the corresponding sample-and-hold circuits 41a-41d, the configuration required for AD conversion processing can be made more compact, allowing for efficient and accurate detection. This enables responsive and highly accurate magnetic detection.

[0118] In the third embodiment, two AD conversion circuits 42e to 42f are provided for four sample and hold circuits 41a to 41d and driven simultaneously, but the two AD conversion circuits 42e to 42f may be driven separately. Also, in a configuration including more sample and hold circuits 41, one AD conversion circuit 42 may correspond to three or more sample and hold circuits 41, or three or more AD conversion circuits 42 may be provided corresponding to two sample and hold circuits 41.

[0119] In the above-described embodiments, the four hold signals S2 acquired by the four sample-and-hold circuits 41a to 41d are subjected to AD conversion processing by the corresponding AD conversion circuits 42a to 42d, 42e to 42f, and then simultaneously read into the signal processing circuit 6, but this is not limiting. For example, the digital signals S3 divided into two groups and subjected to AD conversion processing may be separately read into the signal processing circuit 6 to perform signal generation processing.

[0120] The present invention is not limited to the above-described embodiments, and can be applied to various embodiments within the scope of the present invention.

Claims

1. A magnetic sensor device comprising: a magnetic detection element; a current supply circuit which periodically excites the magnetic detection element; and a magnetic detection circuit to which a detection signal generated in the magnetic detection element due to the periodic excitation is input, wherein the magnetic detection circuit comprises: a plurality of sample-and-hold circuits which are electrically connected in parallel to the magnetic detection element and which hold the detection signals at different excitation timings by the current supply circuit and output them as analog hold signals; and an AD conversion circuit which performs analog-to-digital conversion processing to convert the hold signals into digital signals.

2. The magnetic sensor device according to claim 1, further comprising a plurality of the AD conversion circuits respectively corresponding to the plurality of the sample-and-hold circuits.

3. A magnetic sensor device as described in claim 2, wherein for a first group constituting a portion of the plurality of sample-and-hold circuits, the corresponding AD conversion circuits perform the analog-to-digital conversion process at the same timing, and for a second group constituting another portion of the plurality of sample-and-hold circuits, the corresponding AD conversion circuits perform the analog-to-digital conversion process at the same timing, and the AD conversion circuit corresponding to the first group and the AD conversion circuit corresponding to the second group perform the analog-to-digital conversion process at different timings.

4. The magnetic sensor device according to claim 2, wherein the AD conversion circuits corresponding to all of the plurality of sample-and-hold circuits perform the analog-to-digital conversion process at the same timing.

5. The magnetic sensor device according to claim 1, further comprising a switch for switching connections between two or more of said sample-and-hold circuits and one of said AD conversion circuits.

6. The magnetic sensor device according to claim 5, further comprising a plurality of the AD conversion circuits connectable to two or more of the sample-and-hold circuits, the plurality of the AD conversion circuits performing the analog-to-digital conversion process at the same timing.

7. A magnetic sensor device as claimed in any one of claims 1 to 6, further comprising a signal processing circuit that performs signal generation processing to generate magnetic detection information based on the digital signal from the AD conversion circuit, and the signal processing circuit acquires a plurality of the digital signals based on a plurality of the hold signals at the same timing.

8. A magnetic sensor device as claimed in any one of claims 1 to 6, further comprising a signal processing circuit that performs signal generation processing to generate magnetic detection information based on the digital signal from the AD conversion circuit, wherein the signal processing circuit performs the signal generation processing at a timing different from that of the analog-to-digital conversion processing.

9. The magnetic sensor device according to any one of claims 1 to 6, further comprising a precharge circuit that precharges a reference voltage to a signal line between the magnetic detection element and the sample-and-hold circuit.

10. A magnetic sensor device as described in any one of claims 1 to 6, wherein the magnetic detection element comprises a magnetic sensitive body and a detection coil, and an induced voltage generated in the detection coil when an excitation current is supplied to the magnetic sensitive body is output as the detection signal, and the current supply circuit periodically supplies the excitation current to the magnetic detection element.

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