Resizing device and method based on data reuse

Abstract

Provided are a resizing device and method based on data reuse. The device comprises: a memory for storing at least one process for resizing based on data reuse; and a processor for performing the operation according to the process. The processor resizes axb pieces of input data to a'xb' pieces of output data (here, a and b are natural numbers), wherein the preset number of pieces of the input data required for outputting each piece of the output data may be selected from among the axb pieces of input data on the basis of a reuse mode preset for each piece of the output data.

Description

Data reuse-based resizing device and method The present disclosure relates to a data reuse-based resizing device and method. NPU (Neural Processing Unit) is a hardware designed for artificial intelligence tasks. NPU (Neural Processing Unit), which is modeled after the human brain, can perform tasks faster and more efficiently than CPU (Central Processing Unit) and GPU (Graphics Processing Unit), so it is used for calculations used in deep learning or AI algorithms. The AI ​​inference process involves various resizing operations, and a general-purpose device that supports all of these is required within the NPU. The purpose of the embodiments disclosed in the present disclosure is to provide a data reuse-based resizing device and method. The problems to be solved by the present disclosure are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below. According to the present disclosure for achieving the above-described technical problem, a data reuse-based resizing device includes a memory storing at least one process for performing data reuse-based resizing and a processor performing an operation according to the process, wherein the processor resizes input data of axb into output data of a'xb' (wherein a and b are natural numbers), and selects a preset number of input data required to output each output data from among the input data of axb based on a preset reuse mode for each output data. Additionally, the reuse mode may include a first mode in which all of the preset number of input data are reused, a second mode in which only some of the preset number of input data are reused, and a third mode in which none of the preset number of input data are reused. Additionally, the processor can classify the output data of a'xb' into a plurality of output groups based on the input data of axb, and classify the input data of axb into a plurality of input groups based on the preset number. In addition, the plurality of output groups include first to fourth output groups, the plurality of input groups include first to fourth input groups, and output data included in each of the first to fourth output groups can be produced based on input data included in each of the first to fourth input groups. In addition, the processor reuses input data corresponding to a specific row or column among input groups utilized to produce adjacent output data of the specific output data set to the second mode, and the specific output data and the adjacent output data may be included in different output groups. In addition, in the case of an operation that requires a smaller number of input data than the preset number to produce the output data, the processor can determine data that should be read-skipped among the preset number of input data for each output data based on a preset table. Additionally, the processor can calculate the value of the output data from the value corresponding to each of the input data using three multipliers. Additionally, the area of ​​the three multipliers can be calculated based on the mathematical formula below. [Mathematical formula] (L, M: constants, n: bits of input data, k: bits of weight) In addition, a data reuse-based resizing method according to another aspect of the present disclosure for achieving the above-described technical problem includes a step of obtaining input data of axb (wherein a and b are natural numbers) and a step of resizing the input data of axb into output data of a'xb', wherein the resizing step can select a preset number of input data required to output each output data from among the input data of axb based on a preset reuse mode for each output data. In addition, a computer program stored in a computer-readable recording medium for executing a method for implementing the present disclosure may be further provided. In addition, a computer-readable recording medium recording a computer program for executing a method for implementing the present disclosure may be further provided. According to the aforementioned problem solving means of the present disclosure, the efficiency of the area and performance of the device can be improved by supporting various resizing operations required for the AI ​​inference process through a single module within the NPU. The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below. FIG. 1 is a diagram for explaining a data reuse-based resizing device according to an embodiment of the present disclosure. FIG. 2 is a flowchart of a data reuse-based resizing method according to an embodiment of the present disclosure. FIG. 3 is a drawing for explaining an output group according to an embodiment of the present disclosure. FIG. 4 is a drawing for explaining an input group according to an embodiment of the present disclosure. FIGS. 5A to 5D are diagrams for explaining the use of input data for each output data according to an embodiment of the present disclosure. FIG. 6 is a hardware diagram for an input data reuse process according to an embodiment of the present disclosure. FIG. 7 and FIG. 8 are diagrams for explaining a valid-in table according to an embodiment of the present disclosure. FIG. 9 is a hardware diagram of a valid-in table application structure according to an embodiment of the present disclosure. FIG. 10 is a diagram for explaining bilinear interpolation according to an embodiment of the present disclosure. FIG. 11 is a drawing for explaining the area difference according to the number of multipliers according to an embodiment of the present disclosure. FIG. 12 is a drawing for explaining the overall structure of a resizing device according to an embodiment of the present disclosure. Throughout this disclosure, the same reference numerals denote the same components. This disclosure does not describe all elements of the embodiments, and general contents in the technical field to which this disclosure belongs or overlapping contents between embodiments are omitted. The terms 'part, module, element, block' used in the specification can be implemented by software or hardware, and according to the embodiments, a plurality of 'parts, modules, elements, blocks' can be implemented as a single component, or a single 'part, module, element, block' can include a plurality of components. Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is directly connected, but also the case where it is indirectly connected, and the indirect connection includes the connection via a wireless communication network. Additionally, when a part is said to "include" a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise specifically stated. Throughout the specification, when it is said that an element is "on" another element, this includes not only cases where the element is in contact with the other element, but also cases where there is another element between the two elements. The terms first, second, etc. are used to distinguish one component from another, and the components are not limited by the aforementioned terms. Singular expressions include plural expressions unless the context clearly indicates otherwise. The identification codes in each step are used for convenience of explanation and do not describe the order of each step. Each step may be performed in a different order than specified unless the context clearly indicates a specific order. The operating principle and embodiments of the present disclosure are described below with reference to the attached drawings. In this specification, the term 'device' includes all kinds of devices that can perform computational processing and provide results to a user. For example, a device according to the present disclosure may include all of a computer, a server device, and a portable terminal, or may be in the form of any one of them. Here, the computer may include, for example, a notebook, desktop, laptop, tablet PC, slate PC, etc. equipped with a web browser. The above server device is a server that processes information by communicating with an external device, and may include an application server, a computing server, a database server, a file server, a game server, a mail server, a proxy server, and a web server. The above portable terminal may include, for example, all kinds of handheld-based wireless communication devices such as a PCS (Personal Communication System), GSM (Global System for Mobile communications), PDC (Personal Digital Cellular), PHS (Personal Handyphone System), PDA (Personal Digital Assistant), IMT (International Mobile Telecommunication)-2000, CDMA (Code Division Multiple Access)-2000, W-CDMA (W-Code Division Multiple Access), WiBro (Wireless Broadband Internet) terminal, a smart phone, and a wearable device such as a watch, a ring, a bracelet, an anklet, a necklace, glasses, contact lenses, or a head-mounted-device (HMD). The function related to artificial intelligence according to the present disclosure is operated through a processor and a memory. The processor may be composed of one or more processors. At this time, one or more processors may be a general-purpose processor such as a CPU, an AP, a DSP (Digital Signal Processor), a graphics-only processor such as a GPU, a VPU (Vision Processing Unit), or an artificial intelligence-only processor such as an NPU. One or more processors control to process input data according to a predefined operation rule or artificial intelligence model stored in a memory. Alternatively, when one or more processors are artificial intelligence-only processors, the artificial intelligence-only processor may be designed with a hardware structure specialized for processing a specific artificial intelligence model. The predefined operation rules or artificial intelligence models are characterized by being created through learning. Here, being created through learning means that the basic artificial intelligence model is learned by using a plurality of learning data by a learning algorithm, thereby creating a predefined operation rule or artificial intelligence model set to perform a desired characteristic (or purpose). Such learning may be performed in the device itself on which the artificial intelligence according to the present disclosure is performed, or may be performed through a separate server and / or system. Examples of the learning algorithm include supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but are not limited to the examples described above. The artificial intelligence model may be composed of a plurality of neural network layers. Each of the plurality of neural network layers has a plurality of weight values, and performs a neural network operation through an operation between the operation result of the previous layer and the plurality of weights. The plurality of weights of the plurality of neural network layers may be optimized by the learning result of the artificial intelligence model. For example, the plurality of weights may be updated so that a loss value or a cost value obtained from the artificial intelligence model is reduced or minimized during the learning process. The artificial neural network may include a deep neural network (DNN), and examples thereof include, but are not limited to, a convolutional neural network (CNN), a deep neural network (DNN), a recurrent neural network (RNN), a restricted boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), or a deep Q-network. The processor can create a neural network, train or learn a neural network, perform a computation based on received input data, and generate an information signal based on the result of the computation, or retrain the neural network. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. FIG. 1 is a drawing for explaining a data reuse-based resizing device (hereinafter, “resizing device”) (10) according to an embodiment of the present disclosure. Before the explanation, it should be noted that various resizing operations are involved in the AI ​​inference process, and when multiple modules are used for each operation, there is an advantage of low implementation difficulty, but a disadvantage of low area efficiency. In this disclosure, a single general-purpose module that can support all various operations is utilized for area efficiency of the device. The resizing device (10) of the present disclosure can perform various resizing operations used in AI inference algorithms by introducing a resize-specific data reuse technique, a read-skip technique utilizing a validate-in table, and a generalization and modification of a fixed-point system NPU-specific resizing algorithm for achieving low area. Here, the resizing operation can include bilinear interpolation, nearest-neighbor interpolation, constant padding, zero padding, crop, flip, rotation, and various other custom resizing algorithms. Referring to FIG. 1, the resizing device (10) may include a communication unit (11), a memory (12), and a processor (13). In some embodiments, the resizing device (10) and the processor (13) may include fewer or more components than the components illustrated in FIG. 1. The communication unit (11) may include one or more components that enable communication with various devices equipped with communication modules, and may include, for example, at least one of a broadcast receiving module, a wired communication module, a wireless communication module, a short-range communication module, and a location information module. The short-range communication module may include a module for recognizing the approach of an external device (e.g., a UWB (Ultra-Wideband) communication module). The communication network may use various types of communication networks, for example, wireless communication methods such as WLAN (Wireless LAN), Wi-Fi, Wibro, WiMAX, and HSDPA (High Speed ​​Downlink Packet Access), or wired communication methods such as Ethernet, xDSL (ADSL, VDSL), HFC (Hybrid Fiber Coax), FTTC (Fiber to The Curb), and FTTH (Fiber To The Home) may be used. Meanwhile, the communication network is not limited to the communication methods presented above, and may include all other forms of communication methods that are widely known or will be developed in the future in addition to the above-described communication methods. The wired communication module may include various wired communication modules such as a Local Area Network (LAN) module, a Wide Area Network (WAN) module, or a Value Added Network (VAN) module, as well as various cable communication modules such as a Universal Serial Bus (USB), a High Definition Multimedia Interface (HDMI), a Digital Visual Interface (DVI), RS-232 (recommended standard232), power line communication, or plain old telephone service (POTS). The wireless communication module may include a wireless communication module that supports various wireless communication methods such as GSM (global System for Mobile Communication), CDMA (Code Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), UMTS (universal mobile telecommunications system), TDMA (Time Division Multiple Access), LTE (Long Term Evolution), 4G, 5G, and 6G, in addition to a WiFi module and a Wireless broadband module. The short-range communication module is for short-range communication and can support short-range communication using at least one of Bluetooth™, RFID (Radio Frequency Identification), Infrared Data Association (IrDA), UWB (Ultra Wideband), ZigBee, NFC (Near Field Communication), Wi-Fi (Wireless-Fidelity), Wi-Fi Direct, and Wireless USB (Wireless Universal Serial Bus) technologies. The memory (12) may store at least one process for performing data reuse-based resizing. The memory (12) can store data supporting various functions of the resizing device (10) and a program for the operation of the processor (13), can store input / output data (e.g., music files, still images, moving images, etc.), and can store a plurality of application programs (or applications) run on the resizing device (10), data for the operation of the resizing device (10), and commands. At least some of these application programs can be downloaded from an external server via wireless communication. The memory (12) may include at least one type of storage medium among a flash memory type, a hard disk type, an SSD (Solid State Disk type), an SDD (Silicon Disk Drive) type, a multimedia card micro type, a card type memory (for example, an SD or XD memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, and an optical disk. In addition, the memory (12) may be a database that is separate from the resizing device (10) but is connected by wire or wirelessly. The processor (13) can perform operations according to the process stored in the memory (11). The processor (13) can perform the above-described operations using the memory that stores data for an algorithm for controlling the operations of components in the resizing device (10) or a program that reproduces the algorithm, and the data stored in the memory. At this time, the memory (12) and the processor (13) can be implemented as separate chips. Alternatively, the memory (12) and the processor (13) can be implemented as a single chip. The processor (13) is a Neural Processing Unit (NPU) and may include a resizing module (131), which is a single general-purpose module. In some embodiments, the processor (13) may include fewer or more components than the components illustrated in FIG. 1. In addition, the processor (13) can control one or more of the components discussed above in combination to implement various embodiments according to the present disclosure described in FIGS. 2 to 12 below on the resizing device (10). Hereinafter, with reference to FIGS. 2 to 12, a method for resizing data based on data reuse by a resizing device (10) will be specifically described. FIG. 2 is a flowchart of a data reuse-based resizing method according to an embodiment of the present disclosure. FIG. 3 is a drawing for explaining an output group according to an embodiment of the present disclosure. FIG. 4 is a drawing for explaining an input group according to an embodiment of the present disclosure. FIGS. 5A to 5D are diagrams for explaining the use of input data for each output data according to an embodiment of the present disclosure. FIG. 6 is a hardware diagram for an input data reuse process according to an embodiment of the present disclosure. FIG. 7 and FIG. 8 are diagrams for explaining a valid-in table according to an embodiment of the present disclosure. FIG. 9 is a hardware diagram of a valid-in table application structure according to an embodiment of the present disclosure. FIG. 10 is a diagram for explaining bilinear interpolation according to an embodiment of the present disclosure. FIG. 11 is a drawing for explaining the area difference according to the number of multipliers according to an embodiment of the present disclosure. FIG. 12 is a drawing for explaining the overall structure of a resizing device according to an embodiment of the present disclosure. Referring to Fig. 2, the processor (13) can obtain input data of axb from an external server or external device through the communication unit (11) (S210). Here, a and b are the same or different natural numbers. The input data may be in the form of an image, but is not limited thereto. The purpose of resizing input data is to increase the accuracy of analysis results without losing any data. The resizing module (131) of the processor (13) can resize the input data of axb to output data of a'xb' (S220). Here, the number of output data may be a multiple of the number of input data. In order to resize the input data of axb to the output data of a'xb', the resizing module (131) of the processor (13) can select a preset number of input data required to output each output data from among the input data of axb based on a preset reuse mode for each output data. Here, the reuse mode may include a first mode in which all of a preset number of input data are reused, a second mode in which only some of the preset number of input data are reused, and a third mode in which none of the preset number of input data are reused. That is, the resizing module (131) of the processor (13) reads the input data required for each output data in accordance with three modes: when the input data used to obtain one output data completely overlaps with the input data of the previous output data, when some of the input data overlaps, and when none of the input data overlaps, the previous input data is reused. Hereinafter, a method for reading input data for each output data (a data reuse technique specialized for resizing) will be specifically described with reference to FIGS. 3 to 5d. In the following, an example will be described in which the input data has a size of 3x3 and the output data has a size of 6x6 (i.e., the size of the input data is resized to double). However, the sizes of the input data and the output data are not limited to 3x3 and 6x6, respectively, and various sizes can be applied, and can also be applied to non-square cases. The resizing module (131) of the processor (13) can classify 6x6 output data into multiple output groups based on 3x3 input data. Specifically, the output data can be classified into multiple output groups according to the number of input data. Referring to Figure 3, since there are 9 input data, 36 output data can be classified into 4 output groups of 9 each. The resizing module (131) of the processor (13) can classify 3x3 input data into multiple input groups based on the preset number. Specifically, input data can be classified into multiple input groups according to a preset number, and in this case, some of the input data included in each of the multiple input groups may overlap with some of the input data included in another input group. Referring to Fig. 4, nine input data can be classified into four input groups of four each. At this time, I[0][1] can be included in the first input group and the second input group, I[1][0] can be included in the first input group and the third input group, I[1][2] can be included in the second input group and the fourth input group, and I[2][1] can be included in the second input group and the fourth input group. In addition, I[1][1] can be included in the first input group, the second input group, the third input group, and the fourth input group. When the grouping of input data and output data is completed in this way, for the nine output data included in each output group, the four input data included in the same input group are read. That is, the nine output data included in the first output group can be used for the calculation of the four input data included in the first input group. In addition, the input data included in the multiple input groups described above can be reused for the calculation. The order of operations for the 36 output data is from left to right for each row, so the first order for each row can be O[0][0], O[1][0], O[2][0], O[3][0], O[4][0], O[5][0], and the last order can be O[0][5], O[1][5], O[2][5], O[3][5], O[4][5], O[5][5]. Referring to Fig. 5a, since the output data O[0][0] included in the first output group is the first order of the row, O[0][0] can be set to the third mode in which no input data is reused. Accordingly, the operation of O[0][0] can read I[0][0], I[0][1], I[1][0], I[1][1] included in the first input group. Referring to Fig. 5b, the output data O[0][1] included in the first output group is the second order of the row and is included in the same group as the previous output data O[0][0], so the first mode in which all input data are reused can be set. Accordingly, the operation of O[0][1] can read I[0][0], I[0][1], I[1][0], I[1][1] included in the first input group. Referring to Fig. 5c, the output data O[0][2] included in the first output group is the third order of the row and is included in the same group as the previous output data O[0][1], so the first mode in which all input data are reused can be set. Accordingly, the operation of O[0][2] can read I[0][0], I[0][1], I[1][0], and I[1][1] included in the first input group. Referring to FIG. 5d, the output data O[0][3] included in the second output group is the fourth order of the row, and since there is a change in the output group (i.e., from the first output group to the second output group), a second mode in which some of the input data is reused can be set. Accordingly, the operation of O[0][3] can read I[0][1], I[0][2], I[1][1], I[1][2] included in the second input group. Here, I[0][1], I[1][1] are reused. In this way, when the output group changes, the first output data of each output group (O[0][3], O[3][0], O

[0003] [3]) may be set to a second mode in which some input data is reused. The resizing module (131) of the processor (13) may reuse input data corresponding to a specific row or column among input groups utilized to produce adjacent output data of specific output data (O[0][3], O[3][0], O

[0003] [3]) set to the second mode. At this time, the specific output data and the adjacent output data may be included in different output groups. For example, O[0][3] can reuse input data I[0][1] and I[1][1] corresponding to a specific column among the first input group utilized in the adjacent O[0][2]. In addition, O[3][0] can reuse input data I[1][0] and I[1][1] corresponding to a specific row among the first input group utilized in the adjacent O[2][0]. In addition, O[3][3] can reuse input data I[1][1] and I[2][1] corresponding to a specific column among the third input group utilized in the adjacent O[3][2]. Alternatively, O[3][3] can reuse input data I[1][1] and I[1][2] corresponding to a specific row among the second input group utilized in the adjacent O[2][3]. Referring to Figure 6, it can be seen that the values ​​of four input data are output according to the set reuse mode. In this way, in order to perform various resizing operations in a single module, the present disclosure includes a circuit that weights-sums four input data based on the operation with the highest complexity (e.g., bilinear interpolation). However, in this case, while bilinear interpolation requires four adjacent input data for one output data, other operations (e.g., nearest-neighbor interpolation, zero, and constant padding, etc.) require less input data, so even if four input data are read, the weight multiplied by unnecessary input data becomes 0, so that the actual output data is not affected. Therefore, in the present disclosure, the resizing module (131) is implemented based on bilinear interpolation, but as illustrated in FIG. 7, a valid-in table is introduced to select which data to read from four adjacent input data, thereby eliminating unnecessary delay in various resizing operations. That is, in the case of an operation that requires a smaller number of input data than the preset number to produce output data, the resizing module (131) of the processor (13) can determine which data among the preset number of input data should be read-skipped for each output data based on the preset valid-in table. Referring to Figure 7, invalid input data is skipped while being read, and valid input data can be read. Referring to Figure 8, (0,0) in ③ is 1*1=1, (0,1) is 1*0=0, (1,0) is 0*1=0, and (1,1) is 0*0=0. Therefore, only I[0][0] is valid, and the rest, I[0][1], I[1][0], and I[1][1], are invalid. Also, if all four input data are invalid, as in ①, the constant may be judged as valid. In this way, the resizing module (131) of the processor (13) can reduce unnecessary delay in the resizing operation by determining whether to skip reading four input data for each of the 6x6 output data (total of 36). Referring to Figure 9, it is possible to determine whether to output the value of each input data or 0 depending on the valid_in value. Meanwhile, in this disclosure, we propose a modification of a generalized algorithm for generalization and low-area implementation of the algorithm in order to implement hardware that can universally support various resizing algorithms used in AI inference operations. In the following, we will explain using bilinear interpolation, which is a standard resizing operation, as an example. P in the graph shown in Fig. 10 can be obtained using the following mathematical expressions 1 to 3. At this time, Let wx1 be Let wx2 be Let wy1 be If is wy2, the mathematical expressions 1 to 3 above can be expressed as mathematical expressions 4 to 6 below. And finally, P(x, y) can be obtained according to the mathematical formula 7 below. When the input data is n bits and the weight is k bits, if the circuit is configured as in the mathematical expression 7 above, it is composed of four k-bit x k-bit x n-bit multipliers, and the area A of the four multipliers can be calculated according to the mathematical expression 8 below. (L, M: constants, n: bits of input data, k: bits of weight) At this time, wx2 is equal to 1- wx1, and wy2 is equal to 1- wy1. Accordingly, mathematical expression 7 can be expressed as mathematical expressions 9 and 10 below. By transforming mathematical expression 7 into mathematical expression 10, the number of multipliers is reduced to three, and the area B of the three multipliers can be calculated according to mathematical expression 11 below. (L, M: constants, n: bits of input data, k: bits of weight) Referring to Fig. 11, the area A of four multipliers and the area B of three multipliers can be confirmed according to the bit sizes of the input data and weights. As can be seen from the comparison table in Fig. 11, the size of the area B is smaller than that of the area A in all cases. In other words, low-area implementation is possible by transforming mathematical expression 7 into mathematical expression 10. In addition, by masking unnecessary data to 0 through the values ​​of the valid-in table in the above mathematical expression 7 or mathematical expression 10, or by adjusting the weight to 0 or an appropriate value, it can be applied not only to bilinear interpolation but also to other resizing algorithms. As illustrated in FIG. 12, the resizing module (131) of the processor (13) reads input data according to the reuse mode (121), and at this time, in order to reduce unnecessary operations, unnecessary data is read-skip (122) using a valid-in table, and the read values ​​are calculated using three multipliers (123), thereby calculating the value of the output data from the value corresponding to each input data. Although FIG. 2 describes the steps as being executed sequentially, this is only an example to explain the technical idea of ​​the present embodiment, and those with ordinary knowledge in the technical field to which the present embodiment belongs can modify and apply various modifications and variations by changing the order described in FIG. 2 and executing them or executing them in parallel without departing from the essential characteristics of the present embodiment, and therefore FIG. 2 is not limited to a chronological order. Meanwhile, in the above description, the steps described in FIG. 2 may be further divided into additional steps or combined into fewer steps, depending on the implementation example of the present disclosure. In addition, some steps may be omitted as needed, and the order between the steps may be changed. Meanwhile, the disclosed embodiments may be implemented in the form of a recording medium storing instructions executable by a computer. The instructions may be stored in the form of program codes, and when executed by a processor, may generate program modules to perform the operations of the disclosed embodiments. The recording medium may be implemented as a computer-readable recording medium. Computer-readable storage media include all types of storage media that store instructions that can be deciphered by a computer. Examples include ROM (Read Only Memory), RAM (Random Access Memory), magnetic tape, magnetic disk, flash memory, and optical data storage devices. As described above, the disclosed embodiments have been described with reference to the attached drawings. Those skilled in the art to which the present disclosure pertains will understand that the present disclosure can be implemented in forms other than the disclosed embodiments without changing the technical idea or essential features of the present disclosure. The disclosed embodiments are exemplary and should not be construed as limiting.

Claims

1. Memory storing at least one process for performing resizing based on data reuse; and A processor for performing operations according to the above process; The above processor, A data reuse-based resizing device that resizes input data of axb to output data of a'xb' (wherein a and b are natural numbers), and selects a preset number of input data required to output each output data from among the input data of axb based on a preset reuse mode for each output data.

2. In paragraph 1, A data reuse-based resizing device, wherein the reuse mode includes a first mode in which all of the preset number of input data are reused, a second mode in which only some of the preset number of input data are reused, and a third mode in which none of the preset number of input data are reused.

3. In paragraph 2, The above processor, Based on the input data of the above axb, the output data of the above a'xb' is classified into multiple output groups, A data reuse-based resizing device that classifies the input data of axb into multiple input groups based on the above-mentioned preset number.

4. In paragraph 3, The above multiple output groups include first to fourth output groups, The above multiple input groups include first to fourth input groups, A data reuse-based resizing device, wherein output data included in each of the first to fourth output groups is calculated based on input data included in each of the first to fourth input groups.

5. In paragraph 4, The above processor, For specific output data set to the above second mode, input data corresponding to a specific row or column among the input groups utilized to produce adjacent output data of the specific output data is reused, A data reuse-based resizing device, wherein the specific output data and the adjacent output data are included in different output groups.

6. In paragraph 1, The above processor, A data reuse-based resizing device that determines which data among the preset number of input data should be read-skipped for each output data based on a preset table, in the case of an operation that requires a smaller number of input data than the preset number to produce the output data.

7. In paragraph 1, The above processor, A data reuse-based resizing device that calculates the value of the output data from the value corresponding to each of the input data using three multipliers.

8. In paragraph 7, The area of ​​the above three multipliers is calculated based on the mathematical formula below, and is a data reuse-based resizing device. [Mathematical formula] (L, M: constants, n: bits of input data, k: bits of weight) 9. In a method performed by a device, A step of obtaining input data of axb (where a and b are natural numbers); and A step of resizing the input data of the above axb into the output data of a'xb'; The above resizing steps are: A data reuse-based resizing method for selecting a preset number of input data required to output each output data from among the input data of axb based on a preset reuse mode for each output data.

10. A computer-readable recording medium that is combined with a computer as hardware and stores a computer program that executes the method of claim 9.

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