Method and apparatus for decoding data

Abstract

The present disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate than a 4G communication system such as LTE. The present disclosure can be applied to intelligent services (for example, smart homes, smart buildings, smart cities, smart cars or connected cars, health care, digital education, retail businesses, security- and safety-related services, and the like) on the basis of 5G communication technology and IoT-related technology. A method performed by a receiver, according to an embodiment of the present disclosure, may comprise the steps of: acquiring an original input sequence on the basis of a received signal; acquiring P candidate input sequences on the basis of the original input sequence, P being 2 or more, and each of the P candidate input sequences being obtained by changing at least one of elements included in the original input sequence to a predefined value; acquiring a single input sequence on the basis of the P candidate input sequences; and acquiring a decoding result corresponding to the received signal on the basis of an output obtained as the single input sequence is input into a single decoder.

Description

Data decryption method and device

[0001] The present disclosure relates generally to communication or broadcasting systems, and more particularly to a method and apparatus for decrypting data in a communication or broadcasting system using channel codes.

[0002] Looking back at the development process through the successive generations of wireless communication, technologies have been developed primarily for human-targeted services such as voice, multimedia, and data. 5G (5 th Connected devices, which have been increasing explosively since the commercialization of 6G (6th generation) communication systems, are expected to be connected to communication networks. Examples of networked objects include vehicles, robots, drones, home appliances, displays, smart sensors installed in various infrastructures, construction machinery, and factory equipment. Mobile devices are also expected to evolve into various form factors, such as augmented reality glasses, virtual reality headsets, and holographic devices. th In the era of 5G (6th generation), efforts are being made to develop an improved 6G communication system to connect hundreds of billions of devices and objects and provide diverse services. For this reason, 6G communication systems are being called "Beyond 5G."

[0003] The 6G communication system, expected to be realized around 2030, will have a maximum transmission speed of terabytes per second (i.e., 1,000 gigabits per second) and a wireless latency of 100 microseconds (μsec). In other words, compared to 5G, the transmission speed in a 6G communication system will be 50 times faster, while the wireless latency will be reduced to one-tenth.

[0004] To achieve these high data rates and ultra-low latency, 6G communication systems are being considered for implementation in the terahertz band (e.g., from 95 gigahertz (GHz) to 3 terahertz (THz)). Compared to the millimeter wave (mmWave) band introduced in 5G, the terahertz band is expected to experience more severe path loss and atmospheric absorption, making it more crucial to ensure signal reach, or coverage, in this band. Key technologies to ensure coverage include radio frequency (RF) components, antennas, new waveforms that offer better coverage than orthogonal frequency division multiplexing (OFDM), beamforming, and multiple antenna transmission technologies such as massive multiple-input and multiple-output (MIMO), full-dimensional MIMO (FD-MIMO), array antennas, and large-scale antennas. In addition, new technologies such as metamaterial-based lenses and antennas, high-dimensional spatial multiplexing using orbital angular momentum (OAM), and reconfigurable intelligent surfaces (RIS) are being discussed to improve the coverage of terahertz band signals.

[0005] In addition, in order to improve frequency efficiency and system network, 6G communication systems are developing full duplex technology that utilizes the same frequency resources for uplink and downlink at the same time; network technology that integrates satellites and high-altitude platform stations (HAPS); network structure innovation technology that supports mobile base stations and enables optimization and automation of network operation; dynamic spectrum sharing technology through collision avoidance based on spectrum usage prediction; AI-based communication technology that utilizes artificial intelligence (AI) from the design stage and internalizes end-to-end AI support functions to realize system optimization; and next-generation distributed computing technology that realizes services with complexity that exceeds the limits of terminal computing capabilities by utilizing ultra-high-performance communication and computing resources (mobile edge computing (MEC), cloud, etc.). In addition, efforts are being made to further strengthen connectivity between devices, further optimize networks, promote softwareization of network entities, and increase the openness of wireless communications through the design of new protocols to be used in 6G communication systems, the implementation of hardware-based security environments, the development of mechanisms for the safe use of data, and the development of technologies for maintaining privacy.

[0006] Research and development of these 6G communication systems are expected to enable a new level of hyper-connected experience through the hyper-connectivity of 6G communication systems, which encompass not only connections between things but also connections between people and things. Specifically, 6G communication systems are expected to enable services such as truly immersive extended reality (XR), high-fidelity mobile holograms, and digital replicas. Furthermore, services such as remote surgery, industrial automation, and emergency response, which are provided through 6G communication systems through enhanced security and reliability, will be applied in diverse fields such as industry, medicine, automobiles, and home appliances.

[0007] Various embodiments of the present disclosure may provide a method and apparatus for decrypting data in a communication or broadcasting system using a channel code.

[0008] The technical problems to be achieved in various embodiments of the present disclosure are not limited to those mentioned above, and other technical problems not mentioned can be considered by a person having ordinary skill in the art from various embodiments of the present disclosure described below.

[0009] According to one embodiment, a method performed by a device may be provided.

[0010] According to one embodiment, the method may include obtaining an original input sequence based on the received signal.

[0011] According to one embodiment, the method may include obtaining P candidate input sequences based on the original input sequence.

[0012] In one embodiment, P may be greater than or equal to 2.

[0013] According to one embodiment, each of the P candidate input sequences may have at least one element included in the original input sequence changed to a predefined value.

[0014] According to one embodiment, the method may include obtaining a single input sequence based on the P candidate input sequences.

[0015] According to one embodiment, the method may include obtaining a decoding result corresponding to the received signal based on an output as the single input sequence is input to the single decoder.

[0016] According to one embodiment, the single decoder may be for decoding low-density parity-check (LDPC) codes.

[0017] According to one embodiment, the lifting size associated with the LDPC code may be set to one of a plurality of predefined lifting sizes.

[0018] According to one embodiment, P can be determined based on a maximum lifting size among the plurality of predefined lifting sizes and the set lifting size.

[0019] According to one embodiment, the set lifting size may correspond to the size of each of the P candidate input sequences.

[0020] In one embodiment, when the maximum lifting size is 384: when the set lifting size is 12 or less, P may be 32; when the set lifting size is greater than 12 and less than or equal to 24, P may be 16; when the set lifting size is greater than 24 and less than or equal to 48, P may be 8; when the set lifting size is greater than 48 and less than or equal to 96, P may be 4; and when the set lifting size is greater than 96 and less than or equal to 192, P may be 2.

[0021] In one embodiment, when the maximum lifting size is 192: when the set lifting size is 12 or less, P may be 16; when the set lifting size is greater than 12 and less than or equal to 24, P may be 8; when the set lifting size is greater than 24 and less than or equal to 48, P may be 4; and when the set lifting size is greater than 48 and less than or equal to 96, P may be 2.

[0022] In one embodiment, P is is determined to satisfy, is the maximum lifting size, may be the lifting size set above.

[0023] According to one embodiment, the at least one element that has been changed may be p elements selected in descending order of absolute value from among the elements included in the original input sequence.

[0024] According to one embodiment, the P candidate input sequences are different sequences obtained by changing each of the p elements to the maximum positive or minimum negative number expressible by the single decoder, can be satisfied.

[0025] In one embodiment, the output may be a single output comprising decoding results of the P candidate input sequences.

[0026] According to one embodiment, the decoding result corresponding to the received signal may correspond to the decoding result of one candidate input sequence identified based on a suitability check of the decoding results of the P candidate input sequences included in the single output.

[0027] According to one embodiment, when the single decoder is set to distributely allocate elements included in an input sequence, when the single input sequence is input to the single decoder, elements included in any candidate input sequence among the P candidate input sequences included in the single input sequence may be discontinuously allocated to one or more of a memory or a processing element (PE) corresponding to the single decoder within an area corresponding to a maximum lifting size.

[0028] According to one embodiment, when the single decoder is set to sequentially allocate elements included in an input sequence, when the single input sequence is input to the single decoder, elements included in any candidate input sequence among the P candidate input sequences included in the single input sequence may be sequentially allocated to one or more of the memories or PEs corresponding to the single decoder within an area corresponding to a set lifting size.

[0029] According to one embodiment, the single input sequence may be obtained by: concatenating the P candidate input sequences, or by sequentially selecting elements from each of the P candidate input sequences and sequentially arranging the selected elements, or by interleaving the P candidate input sequences.

[0030] According to one embodiment, a device may be provided.

[0031] According to one embodiment, the device may include a transceiver and a processor connected to the transceiver.

[0032] According to one embodiment, the processor may be configured to obtain an original input sequence based on the received signal.

[0033] According to one embodiment, the processor may be configured to obtain P candidate input sequences based on the original input sequence.

[0034] In one embodiment, P may be greater than or equal to 2.

[0035] According to one embodiment, each of the P candidate input sequences may have at least one element included in the original input sequence changed to a predefined value.

[0036] According to one embodiment, the processor may be configured to obtain a single input sequence based on the P candidate input sequences.

[0037] According to one embodiment, the processor may be configured to obtain a decoding result corresponding to the received signal based on an output as the single input sequence is input to the single decoder.

[0038] According to one embodiment, the single decoder may be for decoding low-density parity-check (LDPC) codes.

[0039] According to one embodiment, the lifting size associated with the LDPC code may be set to one of a plurality of predefined lifting sizes.

[0040] According to one embodiment, P can be determined based on a maximum lifting size among the plurality of predefined lifting sizes and the set lifting size.

[0041] According to one embodiment, the set lifting size may correspond to the size of each of the P candidate input sequences.

[0042] In one embodiment, when the maximum lifting size is 384: when the set lifting size is 12 or less, P may be 32; when the set lifting size is greater than 12 and less than or equal to 24, P may be 16; when the set lifting size is greater than 24 and less than or equal to 48, P may be 8; when the set lifting size is greater than 48 and less than or equal to 96, P may be 4; and when the set lifting size is greater than 96 and less than or equal to 192, P may be 2.

[0043] In one embodiment, when the maximum lifting size is 192: when the set lifting size is 12 or less, P may be 16; when the set lifting size is greater than 12 and less than or equal to 24, P may be 8; when the set lifting size is greater than 24 and less than or equal to 48, P may be 4; and when the set lifting size is greater than 48 and less than or equal to 96, P may be 2.

[0044] In one embodiment, P is is determined to satisfy, is the maximum lifting size, may be the lifting size set above.

[0045] According to one embodiment, the at least one element that has been changed may be p elements selected in descending order of absolute value from among the elements included in the original input sequence.

[0046] According to one embodiment, the P candidate input sequences are different sequences obtained by changing each of the p elements to the maximum positive or minimum negative number expressible by the single decoder, can be satisfied.

[0047] In one embodiment, the output may be a single output comprising decoding results of the P candidate input sequences.

[0048] According to one embodiment, the decoding result corresponding to the received signal may correspond to the decoding result of one candidate input sequence identified based on a suitability check of the decoding results of the P candidate input sequences included in the single output.

[0049] According to one embodiment, when the single decoder is set to distributely allocate elements included in an input sequence, when the single input sequence is input to the single decoder, elements included in any candidate input sequence among the P candidate input sequences included in the single input sequence may be discontinuously allocated to one or more of a memory or a processing element (PE) corresponding to the single decoder within an area corresponding to a maximum lifting size.

[0050] According to one embodiment, when the single decoder is set to sequentially allocate elements included in an input sequence, when the single input sequence is input to the single decoder, elements included in any candidate input sequence among the P candidate input sequences included in the single input sequence may be sequentially allocated to one or more of the memories or PEs corresponding to the single decoder within an area corresponding to a set lifting size.

[0051] According to one embodiment, the single input sequence may be obtained by: concatenating the P candidate input sequences, or by sequentially selecting elements from each of the P candidate input sequences and sequentially arranging the selected elements, or by interleaving the P candidate input sequences.

[0052] The various embodiments of the present disclosure described above are only some of the preferred embodiments of the present disclosure, and various embodiments reflecting the technical features of the various embodiments of the present disclosure can be derived and understood by a person having ordinary skill in the art based on the detailed description to be described below.

[0053] According to various embodiments of the present disclosure, the efficiency of a decoder for an LDPC code can be effectively improved.

[0054] The effects that can be obtained from the present disclosure are not limited to the effects mentioned above, and other effects that are not mentioned can be clearly understood by a person having ordinary skill in the art to which the present disclosure belongs from the description below.

[0055] FIG. 1 illustrates a wireless communication system to which various embodiments of the present disclosure can be applied.

[0056] FIG. 2 illustrates an example of a configuration of a device for performing communication in a wireless communication system to which various embodiments of the present disclosure are applicable.

[0057] FIG. 3 illustrates an example of a parity check matrix of an LDPC code to which various embodiments of the present disclosure are applicable.

[0058] FIG. 4 illustrates an example of a binary graph corresponding to a parity check matrix to which various embodiments of the present disclosure are applicable.

[0059] FIG. 5 is a block diagram of a transmitting device according to various embodiments of the present disclosure.

[0060] FIG. 6 is a block diagram of a receiving device according to various embodiments of the present disclosure.

[0061] FIG. 7 illustrates an example of an ensemble decoding procedure to which various embodiments of the present disclosure can be applied.

[0062] FIG. 8 is a block diagram illustrating an example of the operation sequence of ensemble decoding to which various embodiments of the present disclosure are applicable.

[0063] FIG. 9 illustrates an example of a process for constructing a QC-LDPC code to which various embodiments of the present disclosure are applicable.

[0064] FIG. 10 illustrates an example of the configuration of a decoder for a reconfigurable LDPC code to which various embodiments of the present disclosure are applicable.

[0065] FIG. 11 illustrates an example of an operation of a decoder of a reconfigurable LDPC code to which various embodiments of the present disclosure are applicable, for decoding an LDPC code having a lifting size smaller than a maximum lifting size.

[0066] FIG. 12 illustrates an example of an invalid component when a decoder of a reconfigurable LDPC code to which various embodiments of the present disclosure are applicable decodes an LDPC code having a lifting size smaller than the maximum lifting size.

[0067] FIG. 13 illustrates an example of a decoder of a reconfigurable LDPC code decoding an input for at least two LDPC codes having a lifting size smaller than a maximum lifting size according to an ensemble decoding method according to various embodiments of the present disclosure.

[0068] FIG. 14 illustrates an example of the decoder operation of a reconfigurable LDPC code implemented based on an Extended Barrel Shifter (EBS) to which various embodiments of the present disclosure are applicable.

[0069] FIG. 15 illustrates an example of applying an ensemble decoding method according to various embodiments of the present disclosure based on the decoder operation of a reconfigurable LDPC code implemented based on EBS.

[0070] FIG. 16 illustrates an example of the decoder operation of a reconfigurable LDPC code implemented based on a QC-LDPC Shifter Network (QSN) to which various embodiments of the present disclosure are applicable.

[0071] FIG. 17 illustrates an example of applying an ensemble decoding method according to various embodiments of the present disclosure based on the decoder operation of a reconfigurable LDPC code implemented based on QSN.

[0072] FIG. 18 is a conceptual diagram generally illustrating operations according to various embodiments of the present disclosure.

[0073] FIG. 19 is a flowchart illustrating an example of the operation of a device according to various embodiments of the present disclosure.

[0074] Hereinafter, embodiments of the present disclosure will be described in detail with the attached drawings.

[0075] In describing the embodiments, descriptions of technical details that are well known in the technical field to which the present disclosure pertains and are not directly related to the present disclosure will be omitted. This is to ensure that the gist of the present disclosure is conveyed more clearly without obscuring it by omitting unnecessary explanations.

[0076] For the same reason, some components in the attached drawings are highlighted, omitted, or schematically depicted. Furthermore, the dimensions of each component do not entirely reflect its actual size. Identical or corresponding components in each drawing are assigned the same reference numbers.

[0077] The advantages and features of the present disclosure, and methods for achieving them, will become clearer with reference to the embodiments described below in detail together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided only to complete the disclosure of the present disclosure and to fully inform those skilled in the art of the scope of the present disclosure, and the present disclosure is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

[0078] At this time, it will be understood that each block of the processing flow diagrams and combinations of the flow diagrams can be performed by computer program instructions. These computer program instructions can be installed in a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing equipment, so that the instructions executed by the computer or the processor of the other programmable data processing equipment create a means for performing the functions described in the flow diagram block(s). These computer program instructions can also be stored in a computer-available or computer-readable memory that can be directed to a computer or other programmable data processing equipment to implement the functions in a specific manner, so that the instructions stored in the computer-available or computer-readable memory can also produce a manufactured item that includes an instruction means for performing the functions described in the flow diagram block(s). Since the computer program instructions may be installed on a computer or other programmable data processing device, a series of operational steps may be performed on the computer or other programmable data processing device to create a computer-executable process, and the instructions that cause the computer or other programmable data processing device to perform the steps for performing the functions described in the flowchart block(s) may also provide steps for performing the functions described in the flowchart block(s).

[0079] Additionally, each block may represent a module, segment, or portion of code that contains one or more executable instructions for performing a specific logical function(s). It should also be noted that in some alternative implementation examples, the functions described in the blocks may occur out of order. For example, two blocks depicted in succession may actually be executed substantially concurrently, or the blocks may sometimes be executed in reverse order, depending on their respective functions.

[0080] Here, the term '~ unit' used in this embodiment means a software or hardware component such as an FPGA or ASIC, and the '~ unit' performs certain roles. However, the '~ unit' is not limited to software or hardware. The '~ unit' may be configured to be on an addressable storage medium and may be configured to regenerate one or more processors. Thus, as an example, the '~ unit' includes components such as software components, object-oriented software components, class components, and task components, processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and '~ units' may be combined into a smaller number of components and '~ units' or further separated into additional components and '~ units'. In addition, the components and '~ units' may be implemented to regenerate one or more CPUs within a device or a secure multimedia card.

[0081] Hereinafter, various embodiments will be described in detail with reference to the attached drawings. At this time, it should be noted that the same components in the attached drawings are represented by the same reference numerals as much as possible. In addition, it should be noted that the drawings of the present disclosure attached below are provided to help understand the present disclosure, and the present disclosure is not limited to the forms or arrangements illustrated in the drawings of the present disclosure. In addition, detailed descriptions of well-known functions and configurations that may obscure the gist of the present disclosure will be omitted. It should be noted that in the following description, only the parts necessary for understanding the operation according to various embodiments of the present disclosure will be described, and the description of other parts will be omitted so as not to distract from the gist of the present disclosure.

[0082] Various embodiments of the present disclosure relate to a method and apparatus for effectively decoding data in a communication and broadcasting system using a low-density parity-check code (LDPC code) that gradually updates a posterior probability or a metric equivalent thereto for codeword bits through an iterative decoding operation.

[0083] Various embodiments of the present disclosure relate to the configuration of an ensemble decoding architecture for LDPC codes in communication and broadcasting systems.

[0084] Typically, when transmitting and receiving data between a transmitter and a receiver in a communication and broadcasting system, the performance of the link can be significantly degraded by various forms of noise, fading, and inter-symbol interference (ISI) present in the communication channel. Therefore, in order to implement high-speed digital communication or broadcasting systems that require high data throughput and reliability, such as next-generation mobile communications, digital broadcasting, and portable Internet, it is required to develop technologies to overcome noise, fading, and inter-symbol interference.

[0085] In order to overcome errors that may occur in the communication channel, error detection codes and error correcting codes (ECC) are utilized at the receiver. The error correction codes used in communication between the transmitter and receiver are generally called channel coding or forward error correction (FEC). The transmitter encodes the information vector to be transmitted, generates a codeword vector, and transmits it, and the receiver decodes the received signal after performing a series of processing to estimate the information vector.

[0086] A variety of channel coding techniques are used in communications and broadcasting systems. Examples include convolutional codes, turbo codes, low-density parity-check coding (LDPC) codes, and polar codes. Turbo and LDPC codes are channel coding techniques that perform iterative decoding. They excel particularly when the length of the information vector is long, and are therefore used in various communications and broadcasting systems.

[0087] LDPC codes are also known as channel coding techniques that achieve performance approaching channel capacity with decoding algorithms of realistic complexity. In particular, the decoding method, called belief-propagation (BP), is suitable for parallelizing each detailed operation, which is advantageous for achieving high throughput. Due to these advantages, LDPC codes are used in various communication and broadcasting systems, such as IEEE 802.11n / ad Wi-Fi, DVB-T2 / C2 / S2, and ATSC 3.0. In particular, they are being adopted and used in the 3GPP New Radio (NR) system, a 5G mobile communication system.

[0088] Various embodiments of the present disclosure can improve the decoding performance of low-density parity-check codes (LDPC codes) in communication or broadcasting systems. In theory, channel codes have low error-correction performance when the code dimension (the number of information bits to be encoded, which is the encoder input length) and the code length (the number of codeword bits obtained by encoding, which is the encoder output length) are short. For example, even at the same code rate (the ratio of the code dimension to the code length), the error correction performance when the code dimension and length are short is lower than that when the code dimension and length are long. In addition, LDPC codes are characterized in that their performance deteriorates more significantly when the code dimension and length are short. The present disclosure provides a method and apparatus for efficiently performing decoding based on a decoder structure and architecture, thereby improving error-correction performance without additional hardware cost, complexity, and delay increases.

[0089] While the embodiments of the present disclosure are described below using a 5G system as an example, the embodiments of the present disclosure can also be applied to other communication systems with similar technical backgrounds or channel types. For example, this may include LTE or LTE-A mobile communication, as well as mobile communication technologies developed after 5G. Accordingly, the embodiments of the present disclosure can be applied to other communication systems with some modifications, as determined by those skilled in the art, without significantly departing from the scope of the present disclosure.

[0090] Additionally, when describing the present disclosure, detailed descriptions of related functions or configurations will be omitted if they are deemed to unnecessarily obscure the gist of the present disclosure. Furthermore, the terms described below are defined based on the functions of the present disclosure and may vary depending on the intent or custom of the user or operator. Therefore, their definitions should be based on the contents of this specification.

[0091] FIG. 1 illustrates a wireless communication system to which various embodiments of the present disclosure can be applied.

[0092] FIG. 1 illustrates a transmitter (110) and a receiver (120) as part of devices or nodes that utilize a wireless channel in a wireless communication system. FIG. 1 illustrates one transmitter (110) and one receiver (120), but may include multiple transmitters or multiple receivers. In addition, for convenience of explanation, in the present disclosure, the transmitter (110) and the receiver (120) are described as separate entities, but the functions of the transmitter (110) and the receiver (120) may be interchanged. For example, in the case of an uplink in a cellular communication system, the transmitter (110) may be a terminal, and the receiver (120) may be a base station. In the case of a downlink, the transmitter (110) may be a base station, and the receiver (120) may be a terminal.

[0093] In various embodiments, the transmitter (110) may generate a codeword by encoding information bits based on a turbo code, and the receiver (120) may decode a signal of the received codeword based on the turbo code. For example, the receiver (120) may decode a signal of the received codeword using a turbo decoding method, and may check with a concatenated CRC (cyclic redundancy check) code to determine whether the decoding result is normal. The transmitter (110) and the receiver (120) perform encoding and decoding using a structure of a turbo code known to each other (trellis, linear feedback shift register, etc.). For example, the structure of the turbo code is 3GPP (3 rd It may include trellis, linear feedback shift register, etc. defined in the LTE (long-term evolution) standard.

[0094] In various embodiments, the transmitter (110) may generate a codeword by encoding information bits based on an LDPC code, and the receiver (120) may decode a signal of the received codeword based on the LDPC code. For example, the receiver (120) may use the LDPC decoding method according to the present disclosure and may perform a syndrome check to determine whether the decoding result is normal. The transmitter (110) and the receiver (120) perform LDPC encoding and decoding using a parity check matrix known to each other. For example, the parity check matrix may include a parity check matrix defined in the 3GPP NR standard.

[0095] FIG. 2 illustrates an example of a configuration of a device for performing communication in a wireless communication system according to various embodiments of the present disclosure.

[0096] The configuration illustrated in Fig. 2 can be understood as a configuration of a transmitter (110) or a receiver (120). Terms such as '... unit', '... unit', etc. used hereinafter mean a unit that processes at least one function or operation, and this can be implemented by hardware, software, or a combination of hardware and software.

[0097] Referring to FIG. 2, the device may include a communication unit (210), a storage unit (220), and a control unit (230).

[0098] The communication unit (210) can perform functions for transmitting and receiving signals through a wireless channel. For example, the communication unit (210) can perform a conversion function between a baseband signal and a bit stream according to the physical layer specifications of the system. For example, when transmitting data, the communication unit (210) can generate complex symbols by encoding and modulating a transmission bit stream. In addition, when receiving data, the communication unit (210) can restore a reception bit stream by demodulating and decoding a baseband signal. In addition, the communication unit (210) can up-convert a baseband signal into an RF (radio frequency) band signal and transmit it through an antenna, and down-convert an RF band signal received through the antenna into a baseband signal.

[0099] To this end, the communication unit (210) may include a transmitting filter, a receiving filter, an amplifier, a mixer, an oscillator, a digital to analog convertor (DAC), an analog to digital convertor (ADC), etc. In addition, the communication unit (210) may include a plurality of transmitting and receiving paths. Furthermore, the communication unit (210) may include at least one antenna array composed of a plurality of antenna elements. In terms of hardware, the communication unit (210) may be composed of a digital unit and an analog unit, and the analog unit may be composed of a plurality of sub-units according to operating power, operating frequency, etc. In addition, the communication unit (210) may include a decoding unit to perform decoding according to various embodiments of the present disclosure.

[0100] The communication unit (210) transmits and receives signals as described above. Accordingly, the communication unit (210) may be referred to as a "transmitter," a "receiver," or a "transceiver." Furthermore, in the following description, transmission and reception performed via a wireless channel are used to mean that processing as described above is performed by the communication unit (210). Furthermore, if the device of FIG. 2 is a base station, the communication unit (210) may further include a backhaul communication unit for communication with other network entities connected via a backhaul network.

[0101] The storage unit (220) can store data such as basic programs, application programs, and setting information for the operation of the receiver (120). The storage unit (220) can be composed of volatile memory, non-volatile memory, or a combination of volatile memory and non-volatile memory. In addition, the storage unit (220) can provide stored data upon request from the control unit (230).

[0102] The control unit (230) can control the overall operations of the device. For example, the control unit (230) can transmit and receive signals through the communication unit (220). In addition, the control unit (230) can record or read data in the storage unit (230). To this end, the control unit (230) may include at least one processor or microprocessor, or may be a part of a processor. According to various embodiments, the control unit (230) can control the device to perform operations according to various embodiments described below.

[0103] This disclosure describes various embodiments using terminology used in certain communication standards (e.g., 3GPP). However, these are merely illustrative examples. The various embodiments of this disclosure can be easily modified and applied to other communication and broadcasting systems.

[0104] The detailed description of the present disclosure may use commonly used mathematical symbols to clearly express the meaning. These mathematical symbols will be clearly understandable to those skilled in the art to which the present disclosure pertains. For example, the following commonly known mathematical symbols may be used in the detailed description of the present disclosure.

[0105] ● Calligraphic characters (e.g., ) is used to refer to a set.

[0106] ● Unless otherwise stated throughout this disclosure, it is assumed that the index of the first element of a set, sequence, or vector starts from 0 (zero-based numbering).

[0107] ● A set of indexed elements About, is a set of indices of elements . For example, About am.

[0108] ● Two sets and About, is a set A set for It represents the relative complement of .

[0109] ● Group and any number About, Is to all elements of A set consisting of values ​​that have been added It represents.

[0110] ● Symbol are used to refer to the set of natural numbers, the set of integers, and the set of real numbers, respectively.

[0111] ● represents a binary field.

[0112] ● Non-negative integer About, Silver from 0 A series of Represents a set of integers of a dog. That is, am.

[0113] ● Boldface lowercase (e.g., ) is used to refer to vectors, and boldface capital letters (e.g., ) is used to indicate a matrix. In the case of vectors, unless otherwise stated, it indicates a column vector.

[0114] ● Vector and matrix About and represents each transpose.

[0115] ● Matrix and two non-negative integers About, is a matrix of th row, Represents the element of the th column.

[0116] ● Matrix and the set of two non-negative integers About, is a matrix Gather in Rows and sets specified by elements of Represents a submatrix consisting of columns specified by elements of .

[0117] Turbo codes and low-density parity-check codes (LDPC codes) are error-correction codes that show performance close to the channel capacity. Because of their excellent performance and characteristics suitable for implementation, turbo codes and LDPC codes are used in various communication and broadcasting systems. For example, turbo codes are used in the 4th generation (4) of 3GPP. th In the Long-Term Evolution (LTE) mobile communication system standard of 3GPP, LDPC codes are used for the 5th generation (5G) thGeneration, 5G) New Radio (NR) mobile communication system standards have been adopted and are being used.

[0118] Hereinafter, embodiments of the present disclosure are described based on a communication or broadcasting system using LDPC codes. However, these are merely examples to avoid redundant descriptions of different channel coding techniques and to simplify the explanation. The various embodiments of the present disclosure described herein can be easily modified and applied to communication and broadcasting systems using other channel coding techniques, including turbo codes.

[0119] The characteristics of LDPC codes as channel coding are described. LDPC codes are linear codes, and each LDPC code is typically defined by a parity-check matrix. The number of input bits to be encoded using LDPC codes is , and the number of output bits of the encoded result is expressed as is expressed as . In terms of coding theory, the number of input bits for encoding is called the code dimension, and is the number of output bits of the encoding. is called the code length. One of the important characteristics of the channel code is the code rate. It is defined as the sign length minus the sign dimension. The number of parity bits is called the number of redundant bits.

[0120] Sign dimension and the sign length LDPC codes with a parity-check matrix is defined by the parity check matrix All valid codeword vectors generated by LDPC codes defined as satisfies the relationship of the following mathematical expression 1.

[0121] [Mathematical Formula 1]

[0122]

[0123] In mathematical expression 1 Silver length is the zero vector of . According to mathematical expression 1, the parity check matrix A codeword vector generated by encoding with an LDPC code defined by is a parity check matrix is the nullspace for . of The row vector corresponding to the th row is It is written as, of th row, The element of the th column It is expressed as . The encoding and decoding of LDPC codes are performed using the above parity check matrix It is based on .

[0124] Parity check matrix The operation of LDPC codes defined by is described in detail using drawings. Decoding of LDPC codes is performed using a parity check matrix. It can be understood as a so-called belief-propagation (BP) process, which repeatedly exchanges messages on a bipartite graph corresponding to .

[0125] Fig. 3 shows an example of a parity check matrix of an LDPC code to which various embodiments of the present disclosure are applicable. Specifically, Fig. 3 shows that the number of rows is And the number of columns is Parity check matrix of binary LDPC code , which represents an example.

[0126] The number of 1s in a parity check matrix is ​​called density, and this density determines the computational complexity of encoding and decoding. The density of a typical parity check matrix of an LDPC code is the total size of the parity check matrix. The contrast is very low, and this characteristic is what makes this class of codes called low-density parity check codes. However, the parity check matrix in Fig. 3 is very small. class As an example of an LDPC code having a relatively high density, it should be noted that a conventionally designed LDPC code has a larger number of bits than the example in Fig. 3. class , and the density of the parity check matrix can be much lower.

[0127] FIG. 4 illustrates an example of a binary graph corresponding to a parity check matrix to which various embodiments of the present disclosure are applicable. Specifically, FIG. 4 illustrates the parity check matrix of FIG. 3. A bipartite graph formed when considering a binary adjacency matrix It represents.

[0128] bipartite graph is a set of variable nodes , a set of check nodes , and a set of edges connecting the elements of the two sets. It consists of. By the usual expression of graph theory. Is th variable node and th inspection node indicates that they are connected. Conversely, Is th variable node and th inspection node indicates that the parity check matrix is ​​not connected. About, th row, Element of the th column If the value is 1 and, If the value is 0 am.

[0129] Variable nodes are encoded word output vectors corresponds to each bit of , th variable node have the same index th code word bit corresponds to the parity check matrix. Each row and codeword vector It represents a linear equation represented by the inner product on the binary field of . Specifically, th inspection node Is represents the corresponding linear equation. This linear equation is On the bipartite graph given by The result of performing a modulo-2 sum (or bitwise XOR) of the bit values ​​corresponding to all variable nodes connected to the th test node is 0. The belief-propagation (BP) decoding of LDPC codes can be understood as an iterative message exchange process utilizing the relationship between variable nodes and test nodes on this graph.

[0130] LDPC codes are used in various communication and broadcasting systems, and are designed and used to satisfy requirements given according to the characteristics of the system.

[0131] For example, one of the required characteristics of channel codes for communication systems is code length flexibility. In a communication system, the number of information bits to be transmitted may vary with each transmission depending on the message to be transmitted. For example, when transmitting multimedia information such as video, the number of information bits may be large. Conversely, when transmitting text messages, the number of information bits may be small. Furthermore, in a communication system, the amount of communication resources, such as time and frequency, available for the transmission of specific information may vary with each transmission for various reasons. For example, the total amount of available communication resources may vary, or the amount of communication resources allocated to transmitting a given piece of information from the total available communication resources may vary. Since the number of bits to be transmitted varies with each transmission, the channel code used in a communication system must be designed to flexibly handle encoding and decoding in situations where the number of input bits and output bits of the code change variably.

[0132] Another desirable characteristic of channel codes for communication systems is rate flexibility. In communication systems, especially mobile communication systems, the channel quality between the transmitter and receiver constantly changes. For example, if the receiver physically moves, the distance between the transmitter and receiver may change, resulting in channel conditions such as path loss and multipath fading. When the channel quality is good, the transmitter can increase the code rate (i.e., reduce the number of parity bits) to achieve error-free encoding / decoding by efficiently utilizing communication resources. Conversely, when the channel quality is poor, the transmitter can decrease the code rate (i.e., increase the number of parity bits) to increase the probability of overcoming the poor channel quality. Therefore, channel codes used in communication systems must be designed to flexibly change the code rate according to the situation.

[0133] LDPC codes for practical communication and broadcasting systems are designed to have the above-mentioned required characteristics (flexible code length adjustment, flexible code rate adjustment). For example, LDPC codes that satisfy the above-mentioned required characteristics are designed and used in 3GPP NR mobile communication systems.

[0134] FIG. 5 is a block diagram of a transmitter according to various embodiments of the present disclosure. More specifically, FIG. 5 illustrates an example of a process of performing channel encoding and a series of operations performed by a transmitter according to various embodiments of the present disclosure.

[0135] Referring to FIG. 5, the transmitting device (500) (transmitter) may include a segmentation unit (510), an outer encoding unit (520), a zero addition unit (530), an LDPC encoding unit (540), a code rate adjustment unit (550), an interleaving unit (560), a combining unit (570), and a modulation unit (580) to transmit an input bit sequence by LDPC encoding and modulating it. Examples of modulation methods include BPSK (binary phase shift keying), -BPSK, QPSK (quadrature phase shift keying), 16-QAM (quadrature amplitude modulation), 64-QAM, 256-QAM, 1024QAM, etc., and any other modulation technique is possible. The components illustrated in FIG. 5 are components that perform encoding and modulation on the input bit sequence, and this is only an example, and in some cases, some of the components illustrated in FIG. 5 may be omitted or changed, and other components may be added.

[0136] The transmitter (500) determines code parameters to be used for the LDPC code based on given scheduling parameters, such as the number of input bits, the number of final output bits, and the code rate, which is the relationship between them, for encoding and modulation. The code parameters may include a parity check matrix of the LDPC code to be used and information thereon, information for segmentation, information for code rate adjustment (shortening, puncturing, repetition, etc.), information for bit interleaving, information for modulation, etc.

[0137] The information bits that the transmitting device (500) wants to transmit can be referred to as a transport block (TB). Accordingly, the number of bits in a transport block can be referred to as a transport block size (TBS). The transport block may be a result obtained by encoding with an external concatenation code, such as a cyclic redundancy check (CRC) code.

[0138] In a typical communication system, the number of bits to be transmitted, i.e., TBS (or the sum of the number of parity bits generated by the TBS and the externally concatenated code), varies depending on the situation. TBS is the parity check matrix determined above. If the number of input bits that can be encoded is greater than the maximum number of input bits, the transport block can be divided into two or more code blocks (CB), i.e., segmented (510). Each segmented code block is input to one LDPC encoder. If the number of input bits is less than or equal to a preset value, segmentation is not performed. The number of code blocks determined or calculated through the above process is It is called index About The second block of code , where indicates the length of the corresponding code block.

[0139] Each segmented code block can be encoded (520) with a concatenated outer code. The outer code includes CRC encoding, etc., and the present disclosure is not limited to a specific coding technique. Whether to perform outer encoding and the type of outer code can be determined differently depending on whether segmentation was performed in advance. Outer encoding can be used to assist in the decoding operation of an LDPC code performed by a receiver to improve performance. Outer encoding can be used to verify and examine the validity of the decoding result of an LDPC code performed by the receiver.

[0140] th code block The outer codeword obtained by encoding the vector It is written as, represents its length ( ). If external encoding is not performed For consistency, the description of this disclosure includes the case where external encoding is not performed. The result substituted into is called an external codeword. The bit sequence generated in this way is input to the LDPC encoder.

[0141] The outer codewords for each code block are independently LDPC encoded. Therefore, understanding how a code block is processed allows for understanding the overall processing of the transmitter. Therefore, the LDPC encoding process for a code block is described below. In the following description, for the sake of brevity, subscripts indicating the index of the code block are used. , excluding (dropping) the code block , the external codeword which is the result of external encoding Let's express it this way.

[0142] The above externally encoded length External codeword of is the sign dimension is encoded with an LDPC code. The LDPC code to be used for encoding is the code dimension of the code. The length of the house can be chosen to be as close as possible to, but greater than, or equal to, the length of the external codeword. A sign dimension If it is smaller than, A number of filler bits can be added to the encoded input bit sequence. If the length of the external codeword is and sign dimension If is equal, the number of filler bits is This is it.

[0143] Filler bits can be used in a variety of ways to externally code words. can be added to. For example, At the end of An appending method that adds filler bits may be used. This filler bit adding method is not limited to a specific method. The filler bits may be determined to have any fixed value, and are generally determined to have a fixed bit value of 0. Therefore, the process of adding the filler bits is also referred to as Zero Filling, Zero Padding, or Zero Appending (530). Since the filler bits have no value as actual information, they may be excluded from the final transmission. The process of excluding the filler bits from the final transmission can be understood as shortening, one of the code modification methods that reduces the code length and code dimension by the same amount. Encoder input vector is the external code word The code dimension of the LDPC code to be used for encoding is determined by performing operations such as zero filling. The result of adjusting the length is shown. The above filler bit is also called a shortened bit, and the expression shortened bit is used in the description of the present disclosure below.

[0144] Input length of LDPC encoding After matching, LDPC encoding is performed (540). LDPC encoding is performed using a parity check matrix determined by the scheduling parameters, code parameters, etc. It is performed based on. Specifically, LDPC encoding is performed based on the encoding input vector given through the above series of processes. The length satisfying mathematical expression 1 based on mother codeword vector is the process of generating a parity check matrix. In other words, LDPC encoding is a parity check matrix Encoding input vector based on A mother code vector satisfying mathematical expression 1 that is mapped to This is the process of obtaining a systematic code. If the bit sequence of the input code block is exactly as it is in the mother code bit sequence, it is called a systematic code, and if not, it is called a non-systematic code.

[0145] Length as output of LDPC encoding The mother tongue vector of is generated, and this mother code is transformed to fit the transmission environment and transmission resources through a rate matching process (550). The length of the coded bit sequence to be finally transmitted for the corresponding code block is called the rate-matching size. , which is a parameter determined by scheduling such as transmission environment, transmission resources, etc. As with other symbols above, The size of the code rate adjustment of the th code block is It can be expressed as, and since the description of the present disclosure deals with a series of encoding processes of one code block, subscripts are used for the sake of simplicity of expression. Except for It should be noted that the code rate adjustment process can be expressed as The mother tongue vector of length from codeword vector It can be understood as a process of generating a codeword vector. to the Mobuho vector To distinguish it more clearly, it is also called a transmitted codeword vector.

[0146] The above code rate adjustment process can be implemented in various ways. For example, the code rate adjustment process can be systematically performed through a simple rule using a circular buffer. The size of the circular buffer to be used He said, is the length of the parentheses may be different. For example, Is can be determined to be equal to or less than a value. For example, in the 3GPP NR LDPC encoding system, if there are no special restrictions, go ( can be determined as a positive integer between 2 and 384, which is the lifting size described later. Length Circular buffer of Then, each bit of the circular buffer is a mother code as shown in the following mathematical expression 2. is determined by the bits of . That is, each bit of the circular buffer is determined to satisfy mathematical expression 2.

[0147] [Equation 2]

[0148]

[0149] Circular buffer as in the above mathematical expression 2 When configuring, the mother tongue The first of The bits of the dog are not stored or recorded in the circular buffer and are therefore excluded from transmission. 3GPP NR LDPC codes are systematic codes with length First in the Mobuho language The bits represent the encoded input bit sequence (i.e., the information bit sequence) as it is. Therefore, in the 3GPP NR LDPC encoding system, among the information bits Systematic puncturing, or information puncturing, occurs when bits are punctured at a fixed rate. In this way, fewer information bits are transmitted, but more parity bits generated during the encoding process are transmitted.

[0150] The code rate adjustment unit is a circular buffer configured as above. A pre-determined starting point From ( sequentially) ), and cycles through (the end of the buffer) When it reaches the first point of the buffer, (Go to) Read on Select the bit of the dog. The point from which to start reading the circular buffer. can be determined by considering the use of Hybrid Automatic Repeat reQuest (HARQ). Also, in the circular buffer When selecting the bit of the dog, (530) added in the process The dog's short bits are not selected. If the code rate adjustment bits are Among the code word bits excluding the shortened bits recorded in the circular buffer, Puncture occurs, which excludes the dog from transmission. If In this case, a repetition occurs in which all or part of the code word bits recorded in the circular buffer are transmitted more than twice.

[0151] Length generated by the above code rate adjustment The bit sequence of may be transmitted via bit interleaved coded modulation (BICM) technique. In this case, interleaving of the rate-adjusted bit sequence may be performed to appropriately map the bits to the modulation symbols (560).

[0152] If the above transmission block is segmented into two or more code blocks, concatenation may be performed (570) to combine the outputs of the above series of encoding processes for each code block into one. Here, the individual results of the code blocks may be simply sequentially concatenated, or the results of the code blocks may be mixed and concatenated according to a predetermined pattern.

[0153] After all bit-level operations are performed, a baseband signal to be transmitted is generated through modulation (580). During the modulation process, various additional operations may be performed to enable a receiving device, which will be described later, to effectively demodulate and restore the signal. The baseband signal may be transmitted on a carrier of the band to be used for transmission. Through the above series of operations, the bits of the transmission block are encoded and modulated and then transmitted.

[0154] Meanwhile, although functional configurations for LDPC encoding are described in FIG. 5, in some cases, the transmitting device (500) may further include configurations for controlling the operation of the transmitting device.

[0155] According to one embodiment, the transmitting device (500) may additionally include a communication unit. The communication unit performs functions for transmitting and receiving signals via a wireless channel. For example, the communication unit performs baseband signal and bit-to-bit conversion functions according to the physical layer specifications of the system. For example, when transmitting data, the communication unit generates a complex symbol by encoding and modulating a transmission bit stream. In addition, when receiving data, the communication unit restores a reception bit stream by demodulating and decoding the baseband signal. In addition, the communication unit up-converts the baseband signal into an RF (radio frequency) band signal and transmits it through an antenna, and down-converts the RF band signal received through the antenna into a baseband signal. According to various embodiments, the transmitting device (500) may transmit an LDPC encoded signal to a receiving device (600) described below.

[0156] To this end, the communication unit may include a transmitting filter, a receiving filter, an amplifier, a mixer, an oscillator, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), etc. In addition, the communication unit may include a plurality of transmitting and receiving paths. Furthermore, the communication unit may include at least one antenna array composed of a plurality of antenna elements. In terms of hardware, the communication unit may be composed of a digital unit and an analog unit, and the analog unit may be composed of a plurality of sub-units according to operating power, operating frequency, etc.

[0157] FIG. 6 is a block diagram of a receiving device according to various embodiments of the present disclosure. More specifically, FIG. 6 illustrates an example of a process of performing channel decoding and a series of operations performed by a receiver according to various embodiments of the present disclosure.

[0158] Referring to FIG. 6, the receiving device (600) (receiver) may include a demodulation unit (610), a de-combining unit (620), a deinterleaving unit (630), a code rate de-adjustment unit (640), an HARQ combining unit (650), an LDPC decoding unit (660), a zero removal unit (670), an outer decoding unit (680), and a de-segmentation unit (690) to estimate accurate information bits from a received signal.

[0159] The receiving device (600), like the transmitting device (500), checks or determines various parameters necessary for the receiving operation based on scheduling information, code parameters, etc. The following series of processes performed by the receiver are performed based on the various parameters checked and determined in this manner.

[0160] The operation of the demodulator (610) may include several processes depending on the case. For example, the demodulator (610) may be subdivided into a process of obtaining a channel estimation result based on the received signal, and a soft demapping process of determining values ​​(e.g., log-likelihood ratio (LLR) or a corresponding value thereof) required for FEC (forward error control) decoding corresponding to the codeword bits transmitted from the demodulated signal or symbol based on the channel estimation result. In this case, the operation within each demodulator may be subdivided into each channel measurement block, soft demapping block, etc. Of course, more diverse subdivisions are possible depending on the structure of the system.

[0161] In the description of one embodiment of the present disclosure below, the operation is described assuming a receiving device (500) that calculates / obtains and processes a log-likelihood ratio (LLR) value for a codeword bit. However, the metric value processed by the receiving device in the present disclosure is not limited to LLR, and any value equivalent thereto may be used.

[0162] If the signal transmitted from the transmitting device (500) is composed of two or more code blocks, the receiving device (600) performs inverse concatenation, which is the reverse process of the concatenation (570) performed by the transmitting device (500), to distinguish the LLR for each code block (620). If the number of code blocks is one, inverse concatenation is not performed. Through this process, the receiving device (600) obtains the LLR sequence for each code block. The LLR sequence length for the th code block is the code rate adjustment size As with the description of the transmitter (500) above, the following describes a series of decoding processes performed by the receiver (600) for one code block, and for the sake of simplicity of expression, the code rate adjustment size is indicated by a subscript. Except for It can be expressed as follows.

[0163] If the transmitting device (500) performs interleaving (560), the receiving device (600) performs deinterleaving (630), which is the reverse process. This process is a process of changing the order of the LLR sequence of the code block into a set pattern, and the sequence length does not change. The LLR sequence obtained by performing de-concatenation and deinterleaving in this way is Let's express it this way.

[0164] Next, the receiving device (600) performs rate dematching as the reverse process of rate adjustment (550) to obtain an LLR sequence or an equivalent value for a codeword that the LDPC decoder can process (640). That is, the rate dematching unit (640) of the receiving device (600) converts the LLR given by the preceding process into a sequence LLR sequence for the mother tongue based on Creates. th LLR is a Mobuho bit It is about.

[0165] For example, when rate adjustment using a circular buffer is performed in a 3GPP NR LDPC encoding system, rate inverse adjustment can be performed through the following process to generate an LLR sequence for the parent codeword.

[0166] 1) LLR sequence for mother tongue Initializes all values ​​to 0.

[0167] 2) Code rate inverse adjustment LLR sequence Position index for Set to the buffer start position is a scheduling parameter that allows the transmitter and receiver to confirm each other through a series of processes. Also, the input LLR sequence Position index for Set to .

[0168] 3) Perform one of the following actions depending on the processing of the mother code bits determined by the encoding process performed by the transmitter: Determines the value of .

[0169] ■ If from the transmitter If it has been shortened (shortened bits with value 0), is determined as the LLR value, or an equivalent value, which indicates the probability of bit value 0 being the maximum. And Increment by , Leave it as is.

[0170] ■ If If it is not a shortened bit, It is decided by. That is, To the existing value of accumulates. If the decoder performs fixed-point operations, appropriate saturation or clipping operations can be performed to prevent overflow. And as, Increment by .

[0171] 4) Code rate inverse adjustment LLR sequence Index for go When this happens (we reach the end), and set it to . And the process of 3) above is repeated. This iterative operation is performed on the input LLR sequence. All LLRs of the code rate inverse LLR sequence Until it is reflected in, that is, go It is performed until it becomes .

[0172] LLR sequence for circular buffer through the above code rate adjustment process is obtained. As a result of the above series of processes, the LLR of the shortened bit position is determined as the LLR value indicating the maximum probability of bit value 0, or a value equivalent thereto. Since no value is accumulated in the LLR of the punctured bit position, the initial value remains 0, which indicates that the probability of bit 0 and bit 1 is the same at 0.5, and thus is not biased toward either one.

[0173] Systematic perforation according to the decoder operation of the above embodiment Length including LLR of the dog The code rate inverse adjustment LLR sequence can be generated. In this case, the code rate adjustment process can be modified and performed as follows.

[0174] 1) LLR sequence for mother tongue Initializes all values ​​to 0.

[0175] 2) Code rate inverse adjustment LLR sequence Position index for Set to the buffer start position is a scheduling parameter that allows the transmitter and receiver to confirm each other through a series of processes. Also, the input LLR sequence Position index for Set to .

[0176] 3) Perform one of the following actions depending on the processing of the mother code bits determined by the encoding process performed by the transmitter: Determines the value of .

[0177] ■ If from the transmitter If it has been shortened (shortened bits with value 0), is determined as the LLR value, or an equivalent value, which indicates the probability of bit value 0 being the maximum. And Increment by , Leave it as is.

[0178] ■ If If it is not a shortened bit, It is decided by. That is, To the existing value of accumulates. If the decoder performs fixed-point operations, appropriate saturation or clipping operations can be performed to prevent overflow. And as, Increment by .

[0179] 4) Code rate inverse adjustment LLR sequence Index for go When this happens (we reach the end), and set it to . And the process of 3) above is repeated. This iterative operation is performed on the input LLR sequence. All LLRs of the code rate inverse LLR sequence Until it is reflected in, that is, go It is performed until it becomes .

[0180] In the following description of an embodiment of the present disclosure, subsequent operations are described assuming that the rate-adjusted LLR sequence is generated so as not to include LLRs for systematic puncturing bits. That is, the rate-adjusted LLR sequence Assuming that it is obtained by . If we consider the systematic perforation bit, the length of in front of Consider the LLR with a value of 0 (prepending). Therefore, choosing one assumption for the sake of simplicity in the above explanation does not make a difference to the final decoding result.

[0181] In a mobile communication system, HARQ operation can be performed to ensure data integrity and efficiently utilize the entire communication transmission resources. In this case, the receiving device (600) transmits a HARQ LLR sequence for each code block. It operates using a separate memory, etc. In addition, the receiving device (600) and Based on this, soft combining for HARQ is performed as follows (650).

[0182] - If this transmission is the first transmission (initial transmission), Is is determined by. That is, all About, The substitution is performed. The code rate inverse adjustment LLR sequence The elements of are not updated separately.

[0183] - If this transmission is a retransmission (second transmission) or a subsequent transmission, class The elements at each position are added to each other. That is, the element-wise addition of the two vectors is performed. Specifically, all About, In the manner of is updated. can be updated to take into account various types of memory operations, usually go is updated (i.e. all About, ) can be rewritten to the corresponding memory.

[0184] If there is no HARQ operation, the above process can be omitted.

[0185] The LDPC decoder generates the LLR sequence through a series of processes as described above. Decryption is performed by receiving the input (660). As described above, the input LLR sequence is It may be a sequence containing LLR for systematic puncturing bits of the dog. At this time, the receiving device (600) may be configured to receive a sign parameter (sign dimension , sign length , code rate adjustment size , code rate And based on this, various parameters and parity check matrix are calculated (size, etc.) based on the input LLR sequence. Modify or Decoding can be performed using only a portion of the parity check matrix. Specifically, when a puncture occurs in the parent code due to a high transmission code rate, the receiving device (600) can reduce the decoding complexity and processing time by not using the portion of the parity check matrix corresponding to the punctured bits for decoding according to conditions.

[0186] Decoding of LDPC codes involves performing belief propagation (BP) based on the LLRs for the codeword bits. BP decoding involves a message-passing operation that iteratively updates the a posteriori LLR (AP-LLR) for the codeword bits. The maximum number of such iterative decoding cycles is determined based on requirements for decoding performance, time, etc.

[0187] Typically, a syndrome check is performed every time the above iterative decoding process is performed once or a specific number of times. This is an estimated bit sequence obtained by making a hard decision based on the updated AP-LLR. is the null space for the parity check matrix, i.e., based on mathematical expression 1, which is the condition of the LDPC code. It is a process to check whether the syndrome test satisfies the estimated bit sequence. It should be noted that only some of them may be considered, and in this case, the above syndrome test formula may also be modified. The estimated bit sequence decoded through the syndrome test The validity of the decryption is checked, and based on that, it is determined whether to terminate the decryption early.

[0188] As explained above, when the bits of the mother code are punctured, the LDPC decoder uses a parity check matrix to reduce the decoding complexity and processing time. A sub parity-check matrix (sub-PCM) consisting of submatrices Decoding can be performed using the sub-parity check matrix. In this case, the above series of BP decoding processes can be modified to fit the modified parity check matrix. The decryption operation using is not mandatory, but can be used to reduce complexity in general.

[0189] The estimated bit sequence for the code block obtained after LDPC decoding may include shortened bits without a fixed amount of information due to zero filling (530) performed by the transmitter (500). Therefore, zero removal (670) may be performed to exclude shortened bits from the estimated bit sequence as a reverse process of the zero filling performed by the transmitter (500).

[0190] If external encoding (520) is performed on the above code block, the bit sequence obtained as a result of LDPC decoding can be decoded based on the external encoding (680). Typically, an error detection code such as a CRC code is often concatenated, and in this case, the validity of the bit sequence obtained by LDPC decoding can be additionally checked.

[0191] If a transmission block is composed of multiple code blocks, inverse segmentation can be performed (690), which concatenates the results of each code block to derive a final result. This process can be understood as the reverse process of segmentation (510) performed in the transmitting device (500).

[0192] The components illustrated in the above drawing 6 are components that perform functions corresponding to the components illustrated in the drawing 6, and this is only an example, and some of them may be omitted or changed depending on the case, and other components may be added.

[0193] One embodiment of the present disclosure relates to an LDPC decoding operation (660) among a series of processes performed by the receiver. As described above, the LDPC decoding operation is performed on a given LLR sequence. It is performed based on. The initial LLR sequence given to the decoding operation in this way is also called the intrinsic LLR sequence (or original LLR / original sequence). This is to distinguish it from the a posteriori LLR (AP-LLR) that is updated by repeated belief propagation during the decoding process.

[0194] LLR represents an estimate of the value of the corresponding codeword bit and the confidence or reliability of that estimate. Specifically, in one embodiment, the codeword bit LLR for The corresponding symbol observed by the receiver Based on this, it can be defined as the following mathematical formula 3. That is, the code word bit LLR for is determined to satisfy mathematical expression 3.

[0195] [Equation 3]

[0196]

[0197] According to the definition in mathematical expression 3, LLR is the code word bit Observed symbols for the values ​​of It is the logarithm of the probability, or the likelihood ratio.

[0198] Code word bit in mathematical expression 3 Likelihood for value 0 is the codeword bit If it is greater than the likelihood for value 1, LLR has a positive value greater than 0. Conversely, the code word bit in Equation 3 Likelihood for value 1 is the codeword bit If it is greater than the likelihood for value 0, LLR has a negative value less than 0. Therefore, the sign of LLR indicates the more likely value among the values ​​that the corresponding code word bit can have.

[0199] In other embodiments, LLR may be defined differently. For example, the numerator and denominator may be switched in the fractional value taking the log of Equation 3. Such LLR is simply a case of switching the signs of the LLR defined as in Equation 3 (i.e., changing + to - and - to +). Although the present disclosure describes an operation according to one embodiment by considering the LLR defined as in Equation 3, it may be applied without any difference if the sign is switched even if the LLR is defined differently.

[0200] Code word bit in mathematical expression 3 Likelihood and codeword bits for value 0 If the difference in likelihood for value 1 is large, LLR absolute value of becomes very large. As an extreme example, The likelihood for value 0 is 1 and the code word bit If the likelihood for value 1 is significantly different from 0, LLR has a positive infinite value. As an extreme example of the opposite, The likelihood for value 0 is 0 and the code word bit If the likelihood for value 1 is significantly different from 1, LLR has a negative infinite value. However, Likelihood and codeword bits for value 0 If the likelihood for value 1 is the same as 0.5 and there is no difference, then LLR has a value of 0. Therefore, the absolute value of LLR can be interpreted as indicating the confidence or reliability of the estimate of the values ​​that the codeword bits can have.

[0201] The process of setting the LLR values ​​for the shortened codeword bits and the punctured codeword bits in the code rate de-tuning unit (640) of the receiving device (600) is based on the reliability expressed as the absolute value of the LLR. The receiving device (600) does not receive the shortened bits, but can clearly know that their value is 0. Therefore, the LLR value for the shortened bits is set to a positive infinite value, which means that the bit value is 0 and that the certainty or reliability thereof is high. In an actual implementation, it can be set to any positive number that the data type used can express. On the other hand, since the receiving device (600) cannot know any information about the punctured bits, the LLR value for the shortened bits is determined to be 0, which means that the probability of the two values ​​that the codeword bits can have is equal to 0.5.

[0202] Intrinsic LLR sequence The absolute value of each element of can be interpreted as a measure of how much the receiver's observation of each codeword bit is corrupted by noise. For example, codeword bit LLR for Absolute value of If is large, it indicates that the corresponding codeword bit has not been corrupted during the series of end-to-end transmission processes (including all related processes at the transmitter and receiver). On the other hand, the codeword bit LLR for Absolute value of If is small enough to be close to 0, it indicates that the corresponding codeword bit has been corrupted during the end-to-end transmission process (including all related processes at the transmitter and receiver).

[0203] The decoding operation (660) of an LDPC code is performed through repeated belief-propagation based on the intrinsic LLR sequence as described above. An example of belief-propagation decoding of an LDPC code is described below. The structure and architecture of the decoder, the algorithm used, etc. can be configured in various ways, and the following does not limit the scope of application of the embodiments of the present disclosure to a specific implementation method. The embodiments of the present disclosure can be applied to various decoding architectures and algorithms, and such application methods will be clearly understood by those skilled in the art to which the present disclosure pertains.

[0204] The decoder uses the intrinsic LLR sequence , and based on this, the AP-LLR sequence is transmitted through a trust-propagation process. Update the Intrinsic LLR sequence go AP-LLR sequence, regardless of whether it includes LLR for the systematically punctured bits Is It should be noted that the initial AP-LLR sequence contains LLRs for the systematically perforated bits of the dog. is the intrinsic LLR sequence is set to .

[0205] In one embodiment, the intrinsic LLR sequence If the LLR for the systematically perforated bits is not included (i.e., ), early AP-LLR can be set as shown in the following mathematical expression 4. That is, the intrinsic LLR sequence If the system does not include LLR for the punctured bits, the initial AP-LLR can be determined to satisfy Equation 4.

[0206] [Equation 4]

[0207]

[0208] In one embodiment, the intrinsic LLR sequence If it contains LLR for systematically perforated bits (i.e., ), early AP-LLR can be set as shown in the following mathematical expression 5. That is, the intrinsic LLR sequence If the LLR for the systematically perforated bits is included, the initial AP-LLR can be determined to satisfy Equation 5.

[0209] [Equation 5]

[0210]

[0211] As described above, the LDPC decoder considers the punctured bits and implements a sub-parity-check matrix (sub-PCM). If , the code length actually considered above is the code length of the mother code. It should be noted that it may be smaller than . Since whether or not a sub-parity check matrix is ​​used is not related to the detailed operation of the decoder, the following description of an embodiment of the present disclosure will focus on the parity check matrix. A decoding operation is described assuming that a sub-parity check matrix is ​​used. An embodiment of the present disclosure can be applied both when a sub-parity check matrix is ​​used and when it is not used.

[0212] The AP-LLR sequence set as above is updated at each iteration by the repeated belief-propagation operation of LDPC decoding. This process can be understood as a message passing operation between a variable node (hereinafter VN) and a check node (hereinafter CN) on a bipartite graph corresponding to a parity check matrix (or sub-parity check matrix).

[0213] First, the message to be transmitted from VN to CN is determined based on the intrinsic LLR sequence or the AP-LLR sequence determined based on it. VN is neighboring A message from VN to CN (variable-to-check message, hereinafter referred to as V2C message) At the beginning of the decoding operation, the V2C message is determined as shown in the mathematical expression 6 below. That is, in the decoding operation, VN is neighboring The first V2C message to be transmitted can be determined to satisfy Equation 6.

[0214] [Equation 6]

[0215]

[0216] In the above mathematical formula 6 is VN is the set of all neighbors CN, Is Represents a set of indices of CNs belonging to .

[0217] Each CN calculates the message to be forwarded to the neighboring VN based on the V2C message received from the neighboring VN. CN This neighboring VN A message from CN to VN (check-to-variable message, hereinafter referred to as C2V message) It is written as follows. The C2V message can be calculated as shown in Equation 7 below. That is, the C2V message can be determined to satisfy Equation 7.

[0218] [Equation 7]

[0219]

[0220] In the above mathematical formula 7 is CN is the set of all neighbors VN, Is It represents the index set of VN belonging to CN as in mathematical formula 7. The neighboring VN C2V message delivered to is VN It is calculated based on V2C messages received from all other neighboring VNs except .

[0221] The C2V message calculation by the above mathematical expression 7 can be approximated and modified in various ways. In one embodiment, the C2V message calculation as in the above mathematical expression 7 can be calculated as in the mathematical expression 8 below using the so-called min-sum approximation method. That is, the C2V message can be determined so as to satisfy the mathematical expression 8.

[0222] [Equation 8]

[0223]

[0224] In the above mathematical formula 8 is the sign of the entered value is a function that outputs . And in the above mathematical expression 8, is a normalization value whose value is greater than 0, is an offset value greater than or equal to 0. The C2V message calculation by Equation 8 is widely used because it is simpler in operation and easier to implement than the C2V message calculation by Equation 7, and it approximates the result well.

[0225] When CNs compute C2V messages for neighboring VNs, each VN updates its AP-LLR and V2C messages based on its intrinsic LLR and the C2V messages received from neighboring CNs. First, VN AP-LLR of can be calculated as shown in the mathematical formula 9 below. That is, VN AP-LLR of is determined as a value that satisfies mathematical expression 9.

[0226] [Equation 9]

[0227]

[0228] And VN This neighboring CN The V2C message transmitted to can be calculated as shown in the mathematical expression 10 below. That is, VN This neighboring CN The V2C message transmitted is determined as a value satisfying mathematical expression 10.

[0229] [Equation 10]

[0230]

[0231] The V2C message calculated as in the above mathematical expression 10 is the AP-LLR calculated in mathematical expression 9. It can be simply calculated as in mathematical expression 11 below. That is, the V2C message can be determined as a value that satisfies mathematical expression 11.

[0232] [Equation 11]

[0233]

[0234] Estimation for each codeword bit can be performed based on the updated AP-LLR as in the above mathematical expression 9. Updated AP-LLR Based on the code word bit Estimation for can be obtained through a hard decision process as shown in the following mathematical expression 12.

[0235] [Equation 12]

[0236]

[0237] The hard decision as in Equation 12 above is based on the definition of LLR in Equation 3. If the definition of LLR is different, the hard decision of Equation 12 can be modified accordingly. If the decoder of the LDPC code is implemented in a fixed-point representation, AP-LLR This can be exactly 0. In this case, the hard decision process of the above mathematical expression 12 is estimated can be determined by a pre-determined rule. In one embodiment, AP-LLR If this is 0, then the estimate can be determined by fixing it to one of the values ​​0 or 1. In one embodiment, AP-LLR If this is 0, then the estimate can be determined by randomly selecting one of the values ​​0 or 1.

[0238] Once all codeword bits are estimated as above, the receiving device generates an estimated codeword vector is valid in terms of a given LDPC code, i.e., Check whether it satisfies the criteria. This process is called syndrome check.

[0239] If the estimated codeword vector Ga syndrome test If , the estimated codeword vector is valid in terms of the LDPC code used, so the receiving device does not perform decoding as many times as the preset maximum number of iterative decodings. It can produce a result and terminate decryption early.

[0240] If the estimated codeword vector Ga syndrome test If not satisfied, the fishery device repeats the above-described series of processes such as C2V message calculation, P-LLR update, V2C message calculation, and hard decision within the preset maximum number of iterations.

[0241] If the syndrome check formula is within the preset maximum number of iterations Estimated codeword vector satisfying If it is not found, the receiving device may consider the decryption failure and terminate the decryption process.

[0242] Syndrome screening formula According to this, a syndrome check can be performed on all elements of the estimated codeword vector. However, since what is of interest from the perspective of the receiving device is the information bits contained in the estimated codeword vector, the receiving device can determine the validity of the decoding result by utilizing only some of the syndrome check formulas, without using the entire estimated codeword vector.

[0243] As in the above series of message exchanges, the initially given intrinsic LLR values ​​are exchanged with neighboring nodes according to the structure of the bipartite graph and used to update the AP-LLR. If the absolute value of the intrinsic LLR value is small, it does not significantly affect the reliable propagation decoding operation. In other words, low-reliability LLR values ​​generated by channel-interfered or corrupted observations do not affect decoding.

[0244] Based on this characteristic of the confidence-propagation process, LDPC code decoders can improve performance by handling low-confidence LLRs (i.e., LLRs with small absolute values) in a specific way. Specifically, LDPC code decoders can experiment with all guesses for bits deemed low-confidence and select one of them.

[0245] For example, a decoder for an LDPC code can identify the locations of p bits that are judged to have low reliability. The reliability of a bit can be determined or evaluated based on various criteria. For example, it can be determined or evaluated based on the absolute value of the LLR generated by receiving a signal from the channel.

[0246] And the decoder of the LDPC code is all possible bit patterns for the p bits that are evaluated or confirmed to have low reliability. After creating a dog and reflecting it in LLR, you can decode each one and synthesize the results to check the final result. For example, Then, all possible bit patterns are Like this A sequence of eight possible bit patterns is given, one of which corresponds to the exact bit transmitted by the transmitter. Therefore, since any one of the eight possible bit patterns is the actual bit transmitted by the transmitter, if all eight possible bit patterns are reflected in the LLR and each is decoded, as described below, the sequence containing the actual bit transmitted by the transmitter increases the probability of repeated reliable-propagation decoding, and thus, by combining the results of each decoding, the actual bit transmitted by the transmitter can be confirmed.

[0247] As an example of how to reflect each bit pattern in the LLR, there may be a method of assigning the LLR of the maximum absolute value corresponding to the bit value to the position of each bit. Based on Equation 3, the LLR of the maximum absolute value for bit 0 can be +∞, and in an actual implementation, the LLR of the maximum absolute value can be any positive number in order to consider the range of representable LLRs and avoid various numerical problems. Based on Equation 3, the LLR of the maximum absolute value for bit 1 can be -∞, and in an actual implementation, the LLR of the maximum absolute value can be any negative number in order to consider the range of representable LLRs and avoid various numerical problems.

[0248] Generated as above Each modified candidate LLR sequence is decoded. The decoding operation, which performs iterative message exchanges such as trusted-propagation decoding, affects the LLR of each bit in updating the AP-LLR of other bits. Therefore, the above Among the candidate LLR sequences modified by the transmitter, those that contain the exact bits transmitted by the transmitter have a positive effect on the improvement of other bits through iterative confidence-propagation decoding, thereby increasing the likelihood of successful decoding. Successful decoding can be verified using the LDPC code and related functions. For example, this can be verified through syndrome checking performed by the LDPC code decoder and decoding of the externally concatenated CRC code.

[0249] The above series of processes reflects all possible guesses about low-confidence bits into the decoder input, and then expects that repeated belief-propagation decoding of the input that reflects the correct guess among them will succeed. This opportunistic decoding operation can be called by various names. For example, it can be called ensemble decoding, quasi maximum-likelihood (quasi-ML, QML) decoding, afterburner decoding, saturate decoding, etc. In the description of one embodiment of the present disclosure, this technique will be referred to as ensemble decoding.

[0250] FIG. 7 illustrates an example of an ensemble decoding procedure to which various embodiments of the present disclosure can be applied. Specifically, FIG. 7 conceptually illustrates the process of an ensemble decoding technique that estimates low-reliability LLRs in all possible ways, as described above, and then trust-propagates the results to verify their validity. That is, FIG. 7 illustrates an ensemble decoding procedure in which a receiver selects the location of a low-reliability LLR in an intrinsic LLR sequence, generates a modified candidate LLR sequence based on the selected location, and performs decoding.

[0251] Referring to Fig. 7, the ensemble decoding operation begins with the process of finding the locations of p LLRs (p least reliable LLRs) with low absolute values ​​(or judged to be low) in all or part of a given intrinsic LLR sequence. This process may involve a sorting process for the absolute values ​​of all or part of a range of the given LLR sequence.

[0252] For example, the number of LLRs within the range (or search range, for short) where the values ​​will change in the intrinsic LLR sequence. If so, then finding p LLRs with the lowest absolute value in this search range is It involves a comparison operation of the values ​​of the number of times. In this way, if p positions of LLR with low absolute values ​​are found, the LLR values ​​of those positions are transformed into preset positive and negative numbers. Generate modified candidate LLR sequences. The above-described pre-set positive and negative numbers can be generally determined as the maximum positive and minimum negative numbers used in LLR representation in the decoder, but are not limited thereto. For example, they can be determined as any positive or negative number in the representable range. For example, as shown in Fig. 7, if p is 3, eight modified candidate LLR sequences (candidate LLR seq. #1,...,#8), which are all possible combinations, can be generated. That is, eight candidate LLR sequences can be generated in which three LLRs are modified as {max, max, max}, {max, max, -max}, {-max, max, max}, {-max, max, -max}, {max, -max, -max}, {-max, -max, max}, {-max, -max, -max}. Here, max is the maximum positive number used in the LLR representation in the decoder described above.

[0253] The candidate LLR sequences modified as described above can be independently decoded. In the example of Fig. 7, eight modified candidate LLR sequences can be independently decoded. As discussed above, the decoding of an LDPC code is performed through a trust-propagation process based on the intrinsic LLR sequence. Since the modified candidate LLR sequences are generated with all possible combinations of codeword bits, it is clear that one of them is for the correct codeword bit. Therefore, the modified candidate LLR sequence, in which the absolute value of the LLR is changed to the maximum or a higher value for the correct codeword bit, transmits the correct message to other codewords through the iterative message exchange decoding operation, thereby increasing the probability of successful decoding. Therefore, After performing each decoding based on the modified candidate LLR sequences, validity checks such as syndrome check and concatenated CRC code check are performed, and if the decoding is successfully completed, the estimate obtained by the decoding can be regarded as the result of the final successful decoding. In this way, the ensemble decoding method and device perform multiple decodings based on multiple modified candidate LLR sequences and collate the results, thereby increasing the probability of successful decoding and improving error-correction performance.

[0254] FIG. 8 is a block diagram illustrating an example of the operation sequence of ensemble decoding to which various embodiments of the present disclosure are applicable.

[0255] Referring to Fig. 8, for a given intrinsic LLR sequence (801), an LLR selection process (810) is performed to find a position to change the value of the LLR. For example, a process of sorting the absolute values ​​of the LLR and finding a position with a predetermined p lower value can be used. Once the LLR position to change the value is found, the maximum for all combinations for this position is An LLR modification process (820) is performed to generate a modified candidate LLR sequence. The decoder decodes (830) each modified candidate LLR sequence and collates the results to produce the final result (802). For example, the decoder may decode the maximum If at least one decryption based on the modified candidate LLR sequence succeeds, the decoder outputs that result as the final output. Although unlikely, if two or more decryptions succeed, the decoder outputs the final output according to a predetermined rule. If none of the decryptions succeeds, the decoder declares the decryption failure.

[0256] The various embodiments of the present disclosure below present methods for improving ensemble decoding methods and devices.

[0257] According to the conventional ensemble decoding method and device, the maximum Independent decoding is performed on the modified candidate LLR sequences of the dog. According to one embodiment of the present disclosure, the following problems or areas for improvement in conventional methods are identified, and solutions and improvement methods for these problems can be provided.

[0258] - Conventional ensemble decoding methods and devices are at most In performing independent decoding on the modified candidate LLR sequences of the dog, hardware and software costs may increase. For example, In order to perform decoding of the modified candidate LLR sequences simultaneously at a specific point in time, A decoder configuration is required, which may lead to increased hardware and software costs. The hardware and software costs may include chip area, power consumption, arithmetic complexity, and implementation complexity.

[0259] - Conventional ensemble decoding methods and devices are at most When performing independent decoding on the modified candidate LLR sequences of the dog, processing time and delay may increase. For example, the above If the decoding of the modified candidate LLR sequences is performed sequentially based on a single decoder (hardware, software, or a combination of the two), the processing time and delay required to process the entire decoding is at most It can increase by a factor of two.

[0260] Various embodiments of the present disclosure improve problems such as increased hardware and software costs, increased processing time and delay caused by the conventional ensemble decoding method and device based on the structure and characteristics of LDPC codes.

[0261] Various embodiments of the present disclosure provide devices and methods for efficiently decoding bits, symbols, signals, etc. transmitted through a channel by encoding them with channel codes such as low-density parity-check (LDPC) codes, turbo codes, etc. in a communication or broadcasting system.

[0262] Various embodiments of the present disclosure provide an apparatus and method for efficiently realizing and implementing ensemble decoding that determines a final result by decoding two or more modified LLR sequences generated by changing the value of at least one element in a log-likelihood ratio (LLR) sequence input to a decoder.

[0263] The decoding method and device according to various embodiments of the present disclosure can effectively improve the utilization factor of a decoder of a reconfigurable LDPC code, thereby minimizing increases in hardware chip area, hardware and software arithmetic complexity, implementation complexity, processing time, and delay.

[0264] According to the decoding method and device according to various embodiments of the present disclosure, at least two modified decoder input sequences are generated based on an original decoder input sequence, decoding is performed based on each of them, and then the results are combined, thereby significantly improving the decoding performance.

[0265] Typically, to decode two or more transformed decoder input sequences, the same number of decoders must be configured, or a single decoder must be operated the same number of times. However, the decoding method and device according to various embodiments of the present disclosure can combine at least two transformed decoder input sequences into a single decoder input sequence and process it with a single decoder. Through this, the decoding method and device according to various embodiments of the present disclosure only require the hardware and software costs, complexity, delay, etc. required for a single decoding even when performing decoding on two or more decoder inputs.

[0266] According to the decoding method and device according to various embodiments of the present disclosure, decoding can be performed with a single decoder structure and architecture for two or more P decoder inputs, thereby achieving the same effect as using P decoders without requiring additional hardware and software costs. According to the decoding method and device according to various embodiments of the present disclosure, by performing only one decoding for two or more P decoder inputs, the same effect as performing P decoding can be achieved without causing additional complexity and delay.

[0267] Hereinafter, various embodiments of the present disclosure will be described. The various embodiments of the present disclosure are not independent, and one or more embodiments may be applied simultaneously or in combination.

[0268] In this disclosure, although the embodiments are described using terms used in certain communication standards (e.g., long term evolution (LTE) and new radio (NR) defined by the 3rd generation partnership project (3GPP)), these are merely examples for illustrative purposes. The embodiments of the present disclosure can be easily modified and applied to other communication systems. That is, the present disclosure is not limited to 5G communication systems or LTE communication systems, and can also be applied to 6G and later communication systems.

[0269] In the following description of the present disclosure, a decoder for a reconfigurable LDPC code is an example of a decoder to which the present disclosure is applicable, and the present disclosure may also be applied to decoders of other configurations.

[0270] An ensemble decoding method and device according to one embodiment of the present disclosure can simultaneously process at least two or more modified LLR sequences with a single decoder. The ensemble decoding method and device according to one embodiment of the present disclosure can be designed based on the specific structure of the LDPC code being used.

[0271] For example, a 5G NR LDPC code can be designed to have a quasi-cyclic structure for efficient configuration and parallel operation of the encoder and decoder. A class of LDPC codes designed to have such a structure is called a QC-LDPC code. Below, embodiments of the present disclosure are described based on the structure and characteristics of such a QC-LDPC code. This is exemplary, and various embodiments of the present disclosure are not limited to a system using a QC-LDPC code, but can be applied to other LDPC codes as well. For example, the present disclosure can be easily modified and applied to various systems that use a structure of an LDPC code similar to a QC-LDPC code (e.g., a vector LDPC code, etc.).

[0272] FIG. 9 illustrates an example of a process for constructing a QC-LDPC code to which various embodiments of the present disclosure are applicable.

[0273] A QC-LDPC code is characterized in that the final LDPC code structure is generated from a small template code or graph called a base graph (BG), base matrix, protograph, proto-matrix, etc. In the following description of various embodiments of the present disclosure, the small template code or graph will be referred to as a protograph.

[0274] 901 of Fig. 9 shows an example of a protograph. The process of constructing a QC-LDPC code based on a protograph begins with copying the protograph at least once, as shown in 902 of Fig. 9. The number of times the protograph is copied can be called the lifting size, and can be expressed mathematically as Z.

[0275] When a protograph is copied as in 902 of Fig. 9, Z independent small graphs that are not connected to each other are created. The next step is to perform a circular permutation on each edge bundle. Through this process, the Z small graphs can be connected to each other to create a single large graph. The single large graph created through this process becomes the bipartite graph of the final QC-LDPC code. As in the relationship of Figs. 3 and 4, these bipartite graphs can be expressed by corresponding parity check matrices with the same meaning.

[0276] The code dimension and code length of the QC-LDPC code configured as above can be adjusted by changing the lifting size Z (i.e., the number of copies of the protograph). That is, the target code dimension and length can be achieved by adjusting the lifting size. Due to these characteristics, QC-LDPC codes are used in various systems such as mobile communication systems that require flexible code dimension and length adjustment. For example, in the 5G NR LDPC code system, the lifting size can be changed to a total of 51 values ​​from a minimum of 2 to 384, and various code dimensions and lengths can be supported.

[0277] The lifting size of the QC-LDPC code configured as above is closely related to the parallelization level of the decoder. As explained above about the decoding operation of LDPC code, the trust-propagation decoding of LDPC code is performed through an iterative message exchange process between VN and CN. Nodes such as VN and CN can be composed of individual components or units. Each node receives the computed message from the connected neighboring node. The decoder that decodes QC-LDPC code can be configured so that Z nodes in each group, also called QC block, are processed simultaneously, i.e., in parallel. Therefore, the lifting size Z also refers to the parallelization level that the decoder of QC-LDPC code can process simultaneously.

[0278] A decoder for decoding QC-LDPC codes designed to support various lifting sizes, such as 5G NR LDPC code systems, can be implemented in various forms and methods. An example of a method for constructing a reconfigurable decoder that supports a frequently changing lifting size Z is the largest lifting size used in the system. It is to configure hardware and / or software based on and operate only some of them according to the actual applied lifting size Z at each point in time.

[0279] FIG. 10 illustrates an example of the configuration of a decoder for a reconfigurable LDPC code to which various embodiments of the present disclosure are applicable.

[0280] FIG. 11 illustrates an example of an operation of a decoder of a reconfigurable LDPC code to which various embodiments of the present disclosure are applicable, for decoding an LDPC code having a lifting size smaller than a maximum lifting size.

[0281] Figures 10 and 11 illustrate examples of reconfigurable decoder configuration operations for a 5G NR LDPC code system.

[0282] In the 5G NR LDPC code system, the lifting size Z can have a total of 51 values ​​from 2 to 384. Therefore, the maximum lifting size supported by the 5G NR LDPC code system is 384. The decoder can be designed to support the cyclic permutation structure of the QC-LDPC code. The cyclic permutation structure of the QC-LDPC code can be composed of, but is not limited to, a Benes network, a Banyan network, a QC-LDPC shifting network, a barrel shifter network, etc. Figures 10 and 11 illustrate an example of a decoder configured based on a barrel shifter. The configuration of the decoder, the size of the network, etc., are the maximum lifting size that can be supported by the system. = can be determined based on 384.

[0283] Figure 10 shows the maximum lifting size Z of the QC-LDPC code used. =384, a conceptual illustration of an example of decoder configuration and operation. Maximum lifting size A decoder built on this can perform decryption by utilizing all components.

[0284] Figure 11 shows the maximum lifting size Z of the QC-LDPC code used. =384 is a conceptual illustration of an example of decoder configuration and operation. Maximum lifting size A decoder based on can operate only some components to decode a QC-LDPC code of actual lifting size Z. In this case, depending on the implementation and configuration of hardware and software, components that do not need to operate can be controlled not to actually operate. Conversely, depending on the implementation and configuration of hardware and software, components that do not need to operate may operate identically based on a kind of dummy input, etc., but the results may not be ultimately used. That is, some components of the decoder may be input with a QC-LDPC code for actual decoding, and the remaining components may be input with a dummy input. In the obtained output, the results corresponding to the dummy inputs can be excluded, and the decoding result can be determined based on the results corresponding to the QC-LDPC code for actual decoding. The method for handling components that do not need to operate can be determined and designed based on the characteristics, requirements, priorities, etc. of the hardware and software used.

[0285] Maximum lifting size A decoder of a reconfigurable LDPC code based on can operate only some components according to the lifting size Z of the code being used. Components that do not need to operate may not actually operate or may operate based on dummy inputs, but as a result, the hardware or software corresponding to the components that do not need to operate do not contribute to producing the final result (decoded result) as described above. Components that do not contribute to producing the final result are called components that do not operate effectively, or invalid components for short.

[0286] Various embodiments of the present disclosure provide the maximum lifting size The present invention relates to a method for increasing the utilization factor of hardware and software by additionally utilizing invalid components that do not need to operate when performing decoding for a lifting size Z that changes frequently in a decoder of a reconfigurable LDPC code constructed based on , and achieving only the complexity, processing time, and delay required for a single decoding even when performing multiple decodings.

[0287] FIG. 12 illustrates an example of an invalid component when a decoder of a reconfigurable LDPC code to which various embodiments of the present disclosure are applicable decodes an LDPC code having a lifting size smaller than the maximum lifting size.

[0288] FIG. 13 illustrates an example of a decoder of a reconfigurable LDPC code decoding an input for at least two LDPC codes having a lifting size smaller than a maximum lifting size according to an ensemble decoding method according to various embodiments of the present disclosure.

[0289] FIG. 12 conceptually illustrates an example of a decoder for a conventional reconfigurable LDPC code, and FIG. 13 conceptually illustrates an example of utilizing a decoder for a reconfigurable LDPC code according to various embodiments of the present disclosure.

[0290] Referring to Figure 12, the decoder of a conventional reconfigurable LDPC code has a maximum lifting size When decoding LDPC codes with smaller lifting size Z, only a portion of the total components are used, with the remaining components becoming invalid. This can increase hardware and software utilization inefficiencies.

[0291] On the other hand, according to various embodiments of the present disclosure, a method and apparatus for decoding an LDPC code can additionally utilize invalid components that have not been utilized in the past when performing ensemble decoding. All of the modified candidate LLR sequences generated for ensemble decoding may be for the same LDPC code and may be processed by the same decoder. In other words, for ensemble decoding, p LLR values ​​of an original LLR sequence are generated by changing them into all possible patterns. The P modified candidate LLR sequences may all be for LDPC codes of the same code dimension and code length. That is, the P modified candidate LLR sequences may have the same code configurations. Therefore, the P modified candidate LLR sequences can be processed by a decoder for the same LDPC code configuration. Based on this fact, an ensemble decoder of an LDPC code constructed according to various embodiments of the present disclosure can receive at least two or more P or fewer modified candidate LLR sequences as input, and process them to generate the same number of outputs (the number of input candidate LLR sequences), as illustrated in FIG. 13.

[0292] According to various embodiments of the present disclosure, the at least two or more modified candidate LLR sequences may be combined to generate / obtain an input sequence to be input to a decoder of an LDPC code. For example, the at least two or more modified candidate LLR sequences may be appropriately combined to suit the configuration of the decoder of the LDPC code. In this way, the process of creating one (or what appears to be one) sequence or vector based on at least two or more sequences or vectors may be viewed as multiplexing.

[0293] For example, one could consider processing four transformed candidate LLR sequences with a single reconfigurable ensemble decoder.

[0294] For example, the four modified candidate LLR sequences can be sequentially concatenated and multiplexed.

[0295] For example, the four modified candidate LLR sequences may be multiplexed in such a way that each element is sequentially selected one by one. The elements selected in the selected order may be arranged in the selected order to generate one sequence. For example, the 1-1 element selected from the first candidate sequence, the 2-1 element selected from the second candidate sequence, the 3-1 element selected from the third candidate sequence, the 4-1 element selected from the fourth candidate sequence, the 1-2 element selected from the first candidate sequence, the 2-2 element selected from the second candidate sequence... may be arranged to generate one sequence.

[0296] For example, among the four modified candidate LLR sequences, interleaving can be performed on each sequence to multiplex them into one sequence.

[0297] The above multiplexing must be in a form suitable for the reconfigurable LDPC decoder being used, and may not necessarily be a unique form. The multiplexing method may vary depending on the LDPC decoder.

[0298] FIG. 14 illustrates an example of the decoder operation of a reconfigurable LDPC code implemented based on an Extended Barrel Shifter (EBS) to which various embodiments of the present disclosure are applicable.

[0299] FIG. 15 illustrates an example of applying an ensemble decoding method according to various embodiments of the present disclosure based on the decoder operation of a reconfigurable LDPC code implemented based on EBS.

[0300] Referring to FIGS. 14 and 15, an example of a method for performing ensemble decoding based on an EBS-based reconfigurable LDPC decoder according to various embodiments of the present disclosure is described. The EBS-based reconfigurable LDPC decoder is an example and the present disclosure is not limited thereto. For example, various embodiments of the present disclosure can be applied to an LDPC decoder in which each element of an input LLR sequence is processed in a uniformly distributed arrangement / allocation manner.

[0301] Referring to Fig. 14, the EBS-based reconfigurable LDPC decoder (or control unit) has a maximum lifting size When decoding an LDPC code with a lifting size Z smaller than (for example, 384), each element of the input LLR sequence can be processed by uniformly distributing / allocating it. Each element of the input LLR sequence can be distributed / allocated to a memory (such as a random access memory (RAM)) or a processing unit (such as a processing unit (PU) or a processing element (PE)). The memory or processing unit where the elements of the input LLR sequence are not allocated becomes an invalid component that does not have a value or has a dummy value. Since the QC-LDPC code is composed of codes by a cyclic permutation, it can be processed by moving cyclically by the given permutation shift value for all components. The decoder can find an actual valid value among the processed values ​​and output it as a result.

[0302] FIG. 15 illustrates the maximum lifting size using an EBS-based reconfigurable LDPC decoder according to various embodiments of the present disclosure. A conceptual illustration of a method for performing decoding of an LDPC code for at least two modified candidate LLR sequences having a smaller lifting size Z.

[0303] Referring to FIG. 15, the EBS-based LDPC code decoder according to various embodiments of the present disclosure can be implemented based on a method of uniformly arranging each element of an input LLR sequence.

[0304] According to various embodiments of the present disclosure, each element of at least two or more modified candidate LLR sequences can be uniformly arranged / assigned without overlapping, as shown in FIG. 15. In FIG. 15, R can be a designated shift value, and an operation can be performed based on it.

[0305] For example, in Fig. 15, a case is illustrated where four candidate sequences are used. The first candidate LLR sequence (1 st candidate block) first element, second candidate LLR sequence (2 nd candidate block) first element, third candidate LLR sequence (3 rd The first element of the candidate block, the first element of the last candidate LLR sequence (last candidate block) can be sequentially placed / allocated in the PE and / or RAM. Next, the first candidate LLR sequence (1 st The second element of the candidate block, the second candidate LLR sequence (2 nd The second element of the candidate block, the third candidate LLR sequence (3 rd The second element of the candidate block, the second element of the last candidate LLR sequence (last candidate block) can be sequentially placed / allocated in PE and / or RAM. In this way, the maximum lifting size Each element of the candidate sequence can be arranged / assigned cyclically / permutated / sequentially to the corresponding region. That is, each element of the candidate sequence has the maximum lifting size Can be discontinuously placed / allocated to the corresponding area.

[0306] As described above, in ensemble decoding, all transformed candidate LLR sequences must be decoded using the same LDPC code. The cyclic permutation operation performed by the EBS-based LDPC decoder can ensure the same operation (i.e., individually identical cyclic permutation operation) for all transformed candidate LLR sequences. Therefore, according to the method according to the above-described embodiment of the present disclosure, two or more transformed candidate LLR sequences can be processed simultaneously based on a single hardware structure.

[0307] FIG. 16 illustrates an example of the decoder operation of a reconfigurable LDPC code implemented based on a QC-LDPC Shifter Network (QSN) to which various embodiments of the present disclosure are applicable.

[0308] FIG. 17 illustrates an example of applying an ensemble decoding method according to various embodiments of the present disclosure based on the decoder operation of a reconfigurable LDPC code implemented based on QSN.

[0309] Referring to FIGS. 16 and 17, an example of a method for performing ensemble decoding according to various embodiments of the present disclosure is described based on a QSN-based reconfigurable LDPC decoder. The QSN-based reconfigured LDPC decoder is an example and the present disclosure is not limited thereto. For example, various embodiments of the present disclosure can be applied to an LDPC decoder in which each element of an input LLR sequence is processed in a sequentially distributed arrangement / allocation manner.

[0310] Referring to Fig. 16, the QSN-based reconfigurable LDPC decoder has a maximum lifting size When decoding an LDPC code with a lifting size Z smaller than (for example, 384), each element of the input LLR sequence is processed by placing it in a designated continuous area. Each element of the input LLR sequence can be placed / allocated in a memory (such as a random access memory (RAM)) or a processing unit (such as a processing unit (PU) or processing element (PE)) corresponding to the designated continuous area. The memory or processing unit where the element of the input LLR sequence is not placed becomes an invalid component that has no value or a dummy value and can correspond to an idle state. Since the QC-LDPC code is composed of codes by cyclic permutation, elements such as LLRs assigned to the designated continuous area can be processed by moving cyclically by the given permutation shift value. The decoder can find an actual valid value among the processed values ​​and output it as a result.

[0311] FIG. 17 illustrates the maximum lifting size using a QSN-based reconfigurable LDPC decoder according to an embodiment of the present disclosure. A conceptual illustration of a method for performing decoding of an LDPC code for at least two modified candidate LLR sequences having a smaller lifting size Z.

[0312] Referring to FIG. 17, a QSN-based LDPC code decoder according to various embodiments of the present disclosure can be implemented based on a method of placing each element of an input LLR sequence in a designated continuous region.

[0313] According to various embodiments of the present disclosure, each element of at least two modified candidate LLR sequences may be placed / assigned to each non-overlapping region as shown in FIG. 17. In FIG. 17, R may be a designated shift value, and an operation may be performed based thereon.

[0314] For example, in Fig. 17, a case is illustrated where one candidate sequence contains four elements. The first candidate LLR sequence (1 st The first, second, third and fourth elements of the candidate block can be sequentially placed / allocated in the PE and / or RAM. Next, the second candidate LLR sequence (2 nd The first, second, third and fourth elements of the candidate block can be sequentially placed / allocated in the PE and / or RAM. In this way, the first, second, third and fourth elements of the last candidate LLR sequence (last candidate block) can be sequentially placed / allocated in the PE and / or RAM. That is, the maximum lifting size Within the corresponding region, each candidate sequence can be sequentially placed / assigned, and the region where each candidate sequence is to be placed / assigned can be a region corresponding to the lifting size Z. In addition, the elements of each candidate sequence can be sequentially placed / assigned within the region corresponding to the lifting size Z.

[0315] As previously described, in ensemble decoding, all transformed candidate LLR sequences must be decoded using the same LDPC code. A QSN-based LDPC decoder can apply the same cyclic permutation operation to each region. Therefore, according to the method according to the above-described embodiment of the present disclosure, two or more transformed candidate LLR sequences can be processed simultaneously based on a single hardware architecture.

[0316] FIG. 18 is a conceptual diagram generally illustrating operations according to various embodiments of the present disclosure. Operations according to various embodiments of the present disclosure will be described with reference to an example of the ensemble decoding procedure described with reference to FIG. 7 .

[0317] Referring to FIG. 18, according to one embodiment, from a given intrinsic LLR sequence A total of eight transformed candidate LLR sequences can be generated. For example, as shown in Fig. 18, if p is 3, eight transformed candidate LLR sequences (candidate LLR seq. #1,...,#8), which are all possible combinations, can be generated. That is, eight candidate LLR sequences can be generated / obtained, in which three LLRs are transformed into {max, max, max}, {max, max, -max}, {-max, max, max}, {-max, max, -max}, {max, -max, -max}, {-max, -max, max}, {-max, -max, -max}. Here, max is the maximum positive integer used in the LLR representation in the decoder described above.

[0318] According to one embodiment, a single input sequence can be generated / obtained based on multiplexing of transformed candidate LLR sequences. That is, the transformed candidate LLR sequences have the same code configurations and can be processed by the same decoder. Therefore, a single input sequence multiplexed with transformed candidate LLR sequences can be processed by a single decoder. A single input sequence is input to the decoder, and the output of the decoder can include decoding results (#1, #2,...,#8) for the transformed candidate LLR sequences. As described above, since the transformed candidate LLR sequences are generated with all possible combinations for the codeword bits, one of them is for the correct codeword bit. Therefore, Based on a single sequence combining the mutated candidate LLR sequences of the dog. The decoding results corresponding to the deformed candidate LLR sequences can be obtained, and a validation check (validity check for each decoding result) can be performed on them to obtain the final decoding result.

[0319] The ensemble decoding method and device according to various embodiments of the present disclosure are capable of processing the maximum lifting size of a decoder of a reconfigurable LDPC code. and the number p of LLRs whose values ​​will be changed based on the actual lifting size Z and the maximum number of transformed candidate LLR sequences. can determine the maximum lifting size. , the number of LLRs to be changed p based on the actual lifting size Z and the number of operations of the decoder of the reconfigurable LDPC code, and the maximum number of transformed candidate LLR sequences. can be decided. The maximum lifting size is due to the relationship between and based on the actual lifting size Z (or maximum lifting size , either the number of LLRs to be changed or the maximum number of transformed candidate LLR sequences is determined (based on the actual lifting size Z and the number of operations of the decoder of the reconfigurable LDPC code), The remaining may also be determined depending on the relationship. Here, and in the description of various embodiments of the present disclosure below, the maximum number of modified candidate LLR sequences may refer to the number of candidate LLR sequences in the description of one embodiment of the present disclosure described above, and the number of candidate LLR sequences in the description of one embodiment of the present disclosure described above may be replaced with the maximum number of modified candidate LLR sequences. According to one embodiment of the present disclosure, the receiving device may perform an operation based on the maximum number of modified candidate LLR sequences or a number less than or equal to the maximum number of modified candidate LLR sequences.

[0320] For example, maximum lifting size If we want to process all transformed candidate LLR sequences by running the decoder of the reconfigurable LDPC code designed to process once, the number of LLRs to be changed p and the maximum number of transformed candidate LLR sequences can be determined as shown in Table 1 below depending on the actual lifting size Z.

[0321] [Table 1: Maximum lifting size Setting according to the lifting size Z of the reconfigurable ensemble decoder based on (assuming one-time decoding)]

[0322]

[0323] Another example is the maximum lifting size If we want to process all transformed candidate LLR sequences by running the decoder of the reconfigurable LDPC code designed to process once, the number of LLRs to be changed p and the maximum number of transformed candidate LLR sequences is the actual lifting size Z ( ) can be determined as shown in Table 2 below.

[0324] [Table 2: Maximum lifting size Setting according to the lifting size Z of the reconfigurable ensemble decoder based on (assuming one-time decoding)]

[0325]

[0326] Another example is the maximum lifting size If we want to process all the transformed candidate LLR sequences by running the decoder of the reconfigurable LDPC code designed to process twice, the number of LLRs to be changed p and the maximum number of transformed candidate LLR sequences can be determined as shown in Table 3 below depending on the actual lifting size Z.

[0327] [Table 3: Maximum lifting size Setting according to the lifting size Z of the reconfigurable ensemble decoder based on (assuming two rounds of decoding)]

[0328]

[0329] The contents of Tables 1, 2, and 3 above can be summarized as in mathematical equation 13 below.

[0330] [Equation 13]

[0331]

[0332] In the above mathematical formula 13 is the maximum lifting size that the reconfigurable LDPC code decoder can handle, and may be the maximum lifting size defined by the communication system and standard used, or may be smaller than that value. In addition, Z is the lifting size of the LDPC code to be decoded. And Q represents the number of operations of the reconfigurable LDPC code decoder. The above Tables 1, 2, and 3 can all be generalized and summarized by mathematical expression 13.

[0333] P can be understood as satisfying mathematical expression 14.

[0334] [Equation 14]

[0335]

[0336] The number of operations of the reconfigurable LDPC code decoder is 1 ( ), mathematical expression 13 can be transformed into mathematical expression 15, and mathematical expression 14 can be transformed into mathematical expression 16.

[0337] [Equation 15]

[0338]

[0339] [Equation 16]

[0340]

[0341] FIG. 19 is a flowchart illustrating an example of the operation of a device according to various embodiments of the present disclosure. Various modifications may be made to the method illustrated in the flowchart of FIG. 19 . For example, although illustrated as a series of steps, various steps in each drawing may overlap, occur in parallel, occur in different orders, or occur multiple times. In other examples, steps may be omitted or replaced with other steps.

[0342] Referring to FIG. 19, in operation 1910 according to one embodiment, the device may obtain an original input sequence based on a received signal. For example, the received signal may be encoded according to a specific channel code (e.g., an LDPC code). For example, the original input sequence may be replaced with, but is not limited to, an original input vector, an original input array, etc. For example, the original input sequence may be, but is not limited to, a log-likelihood ratio (LLR) sequence.

[0343] In operation 1920 according to one embodiment, the device may obtain P candidate input sequences (or modified input sequences) based on the original input sequence. According to one embodiment, P may be 2 or more. According to one embodiment, each of the P candidate input sequences may be one in which at least one of the elements included in the original input sequence is changed to a predefined value.

[0344] In operation 1930 according to one embodiment, the device can obtain a single input sequence based on the P candidate input sequences.

[0345] In operation 1940 according to one embodiment, the device can obtain a decoding result corresponding to the received signal based on an output as the single input sequence is input to the single decoder. For example, the output can include a decoding result for each of the P candidate input sequences, based on which a final decoding result can be determined / obtained.

[0346] For specific details of the operation of the device according to one embodiment of the present disclosure described above, reference may be made to the description of one embodiment of the present disclosure described above.

[0347] The methods according to the embodiments described in the claims or specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

[0348] When implemented in software, a computer-readable storage medium storing one or more programs (software modules) may be provided. The one or more programs stored in the computer-readable storage medium are configured for execution by one or more processors within an electronic device. The one or more programs include instructions that cause the electronic device to execute methods according to embodiments described in the claims or specification of the present disclosure.

[0349] These programs (software modules, software) may be stored in random access memory, non-volatile memory including flash memory, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic disc storage device, compact disc ROM (CD-ROM), digital versatile discs (DVDs) or other forms of optical storage device, magnetic cassette. Or, they may be stored in a memory configured as a combination of some or all of these. In addition, each configuration memory may be included in multiple numbers.

[0350] Additionally, the program may be stored on an attachable storage device that is accessible via a communication network, such as the Internet, an intranet, a local area network (LAN), a wide local area network (WLAN), a storage area network (SAN), or a combination thereof. Such a storage device may be connected to a device implementing an embodiment of the present disclosure via an external port. Additionally, a separate storage device on the communication network may be connected to a device implementing an embodiment of the present disclosure.

[0351] In the specific embodiments of the present disclosure described above, components included in one embodiment are expressed singularly or plurally, depending on the specific embodiment presented. However, the singular or plural expressions are selected to suit the presented situation for convenience of explanation, and the present disclosure is not limited to singular or plural components. Components expressed in plural may be composed of singular elements, or components expressed in singular may be composed of plural elements.

[0352] Meanwhile, the embodiments of the present disclosure disclosed in this specification and drawings are merely specific examples to easily explain the technical content of the present disclosure and facilitate understanding of the present disclosure, and are not intended to limit the scope of the present disclosure. In other words, it will be apparent to those skilled in the art to which the present disclosure pertains that other modifications based on the technical concept of the present disclosure are possible. Furthermore, each of the above embodiments can be combined and operated as needed.

[0353] Meanwhile, the order of description in the drawings explaining the method of the present disclosure does not necessarily correspond to the order of execution, and the order of precedence may be changed or executed in parallel.

[0354] Alternatively, the drawings illustrating the method of the present disclosure may omit some components and include only some components without detracting from the essence of the present disclosure.

[0355] In addition, the method of the present disclosure may be implemented by combining some or all of the contents included in each embodiment within a scope that does not harm the essence of the present disclosure.

[0356] Various embodiments of the present disclosure have been described above. The foregoing description of the present disclosure is for illustrative purposes only, and the embodiments of the present disclosure are not limited to the disclosed embodiments. Those skilled in the art will appreciate that the present disclosure can be readily modified into other specific forms without altering the technical spirit or essential characteristics of the present disclosure. The scope of the present disclosure is indicated by the claims described below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present disclosure.

Claims

1. In a method performed by a device, A step of obtaining an original input sequence based on the received signal; A step of obtaining P candidate input sequences based on the original input sequence, P being 2 or more, and each of the P candidate input sequences having at least one of the elements included in the original input sequence changed to a predefined value; A step of obtaining a single input sequence based on the P candidate input sequences; and A method comprising the step of obtaining a decoding result corresponding to the received signal based on an output according to which the single input sequence is input to a single decoder.

2. In paragraph 1, The above single decoder is for decoding LDPC (low-density parity-check) codes, The lifting size associated with the above LDPC code is set to one of a plurality of predefined lifting sizes, P is determined based on the maximum lifting size among the above predefined multiple lifting sizes and the set lifting size, A method wherein the above-set lifting size corresponds to the size of each of the P candidate input sequences.

3. In paragraph 2, If the above maximum lifting size is 384: If the above set lifting size is 12 or less, P is 32, If the above set lifting size is greater than 12 and less than or equal to 24, P is 16, If the above set lifting size is greater than 24 and less than or equal to 48, P is 8, If the above set lifting size is greater than 48 and less than or equal to 96, P is 4, If the above set lifting size is greater than 96 and less than or equal to 192, P is 2, and If the above maximum lifting size is 192: If the above set lifting size is 12 or less, P is 16, If the above set lifting size is greater than 12 and less than or equal to 24, P is 8, If the above set lifting size is greater than 24 and less than or equal to 48, P is 4, If the above set lifting size is greater than 48 and less than or equal to 96, P is 2, method.

4. In paragraph 2, P is It is decided to satisfy, is the maximum lifting size, A method in which the lifting size is set above.

5. In paragraph 1, The at least one element that has been changed is p elements selected in descending order of absolute value from among the elements included in the original input sequence, The above P candidate input sequences are different sequences obtained by changing each of the p elements to the maximum positive or minimum negative number expressible by the single decoder, A method in which the following is satisfied:

6. In paragraph 1, A method wherein the output is a single output including decoding results of the P candidate input sequences, and the decoding result corresponding to the received signal corresponds to the decoding result of one candidate input sequence identified based on a suitability check of the decoding results of the P candidate input sequences included in the single output.

7. In paragraph 1, When the above single decoder is set to distribute the elements contained in the input sequence: When the single input sequence is input to the single decoder, elements included in any candidate input sequence among the P candidate input sequences included in the single input sequence are discontinuously allocated to one or more of the memories or PEs (processing elements) corresponding to the single decoder within an area corresponding to the maximum lifting size, If the above single decoder is set to sequentially assign elements contained in the input sequence: A method wherein, when the single input sequence is input to the single decoder, elements included in any candidate input sequence among the P candidate input sequences included in the single input sequence are sequentially allocated to one or more of the memories or PEs corresponding to the single decoder within an area corresponding to a set lifting size.

8. In paragraph 1, The above single input sequence is: Obtained by concatenating the above P candidate input sequences, or is obtained based on sequentially selecting elements from each of the above P candidate input sequences and sequentially arranging the selected elements, or A method obtained based on interleaving of the above P candidate input sequences.

9. In the device, Transmitter and receiver; and A processor connected to the transceiver, the processor comprising: Obtain the original input sequence based on the received signal; Obtain P candidate input sequences based on the original input sequence, P being 2 or more, and each of the P candidate input sequences has at least one element included in the original input sequence changed to a predefined value; Obtaining a single input sequence based on the above P candidate input sequences; and A device configured to obtain a decoding result corresponding to the received signal based on an output according to which the single input sequence is input to a single decoder.

10. In paragraph 9, The above single decoder is for decoding LDPC (low-density parity-check) codes, The lifting size associated with the above LDPC code is set to one of a plurality of predefined lifting sizes, P is determined based on the maximum lifting size among the above predefined multiple lifting sizes and the set lifting size, The above set lifting size corresponds to the size of each of the P candidate input sequences.

11. In Article 10, If the above maximum lifting size is 384: If the above set lifting size is 12 or less, P is 32, If the above set lifting size is greater than 12 and less than or equal to 24, P is 16, If the above set lifting size is greater than 24 and less than or equal to 48, P is 8, If the above set lifting size is greater than 48 and less than or equal to 96, P is 4, If the above set lifting size is greater than 96 and less than or equal to 192, P is 2, If the above maximum lifting size is 192: If the above set lifting size is 12 or less, P is 16, If the above set lifting size is greater than 12 and less than or equal to 24, P is 8, If the above set lifting size is greater than 24 and less than or equal to 48, P is 4, If the above set lifting size is greater than 48 and less than or equal to 96, P is 2, device.

12. In paragraph 10, P is It is decided to satisfy, is the maximum lifting size, A device having the above set lifting size.

13. In paragraph 9, The at least one element that has been changed is p elements selected in descending order of absolute value from among the elements included in the original input sequence, The above P candidate input sequences are different sequences obtained by changing each of the p elements to the maximum positive or minimum negative number expressible by the single decoder, A device that satisfies.

14. In paragraph 9, A device wherein the output is a single output including decoding results of the P candidate input sequences, and the decoding result corresponding to the received signal corresponds to the decoding result of one candidate input sequence identified based on a suitability check of the decoding results of the P candidate input sequences included in the single output.

15. In paragraph 9, When the above single decoder is set to distribute the elements contained in the input sequence: When the single input sequence is input to the single decoder, elements included in any candidate input sequence among the P candidate input sequences included in the single input sequence are discontinuously allocated to one or more of the memories or PEs (processing elements) corresponding to the single decoder within an area corresponding to the maximum lifting size, If the above single decoder is set to sequentially assign elements contained in the input sequence: When the single input sequence is input to the single decoder, elements included in any candidate input sequence among the P candidate input sequences included in the single input sequence are sequentially allocated to one or more of the memories or PEs corresponding to the single decoder within an area corresponding to a set lifting size, The above single input sequence is: Obtained by concatenating the above P candidate input sequences, or is obtained based on sequentially selecting elements from each of the above P candidate input sequences and sequentially arranging the selected elements, or A device obtained based on interleaving of the above P candidate input sequences.

Images