Display substrate, display panel and display apparatus

Abstract

Disclosed are a display substrate, a display panel and a display apparatus. The display substrate comprises: a base substrate, comprising: a display area and a fan-out area located on a side of the display area in a first direction; and a plurality of fan-out lines. The plurality of fan-out lines comprise a plurality of first fan-out lines. Each first fan-out line comprises in its extending direction a first sub-fan-out line, a second sub-fan-out line and a third sub-fan-out line. In the same first fan-out line, one of the first sub-fan-out line and the third sub-fan-out line at least comprises a first wire, and the other one of the first sub-fan-out line and the third sub-fan-out line at least comprises a second wire, the first wire being located on a first conductive layer, and the second wire being located on a second conductive layer. The orthographic projections of any two adjacent first fan-out lines on the base substrate have an overlapping area, in which one of the first fan-out lines comprises a first wire, and the other first fan-out line comprises a second wire. The resistivity of each second sub-fan-out line is at least less than the resistivity of one of the first conductive layer and the second conductive layer.

Description

Display substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] In the prior art, the display panel is bound to the driver chip (IC). When there are a large number of ICs, each IC is electrically connected to a set of fan-out lines. The length difference between the fan-out lines is small, and the impedance difference is small. However, when reducing the number of ICs bound to the display panel to save costs, the number of fan-out lines electrically connected to a single IC increases, resulting in a large length difference between the fan-out lines. This, in turn, leads to a large impedance difference between the fan-out lines, which can easily lead to poor display. This affects the display effect and the user experience.

[0003] Summary of the Invention

[0004] An embodiment of the present disclosure provides a display substrate, the display substrate comprising:

[0005] The substrate comprises a display area and a fan-out area located on one side of the display area in a first direction;

[0006] A plurality of fan-out lines are arranged in sequence along a second direction in a fan-out area; the second direction intersects the first direction; the plurality of fan-out lines include: a plurality of first fan-out lines; the first fan-out line includes: a first sub-fan-out line, a second sub-fan-out line, and a third sub-fan-out line in its extension direction; in the same first fan-out line, one of the first sub-fan-out line and the third sub-fan-out line includes at least a first routing line, and the other of the first sub-fan-out line and the third sub-fan-out line includes at least a second routing line, the first routing line is located in a first conductive layer, and the second routing line is located in a second conductive layer; the orthographic projections of any two adjacent first fan-out lines on the substrate have an overlapping area, and in the overlapping area, one of the first fan-out lines includes the first routing line, and the other first fan-out line includes the second routing line; the resistivity of the second sub-fan-out line is at least less than the resistivity of one of the first conductive layer and the second conductive layer.

[0007] In some embodiments, the resistivity of the second conductive layer is less than the resistivity of the first conductive layer, and the second sub-fan-out line is located in the second conductive layer;

[0008] The orthographic projections of the second sub-fan-out lines of different first fan-out lines on the substrate do not overlap with each other.

[0009] In some embodiments, in a direction from the display area to the fan-out area, the first sub-fan-out line, the second sub-fan-out line, and the third sub-fan-out line are electrically connected in sequence.

[0010] In some embodiments, the fan-out region further includes a bonding region;

[0011] The display substrate further includes: a plurality of binding electrodes located in the binding area, and a plurality of signal lines extending from the display area to the fan-out area;

[0012] One end of the first sub-fan-out line away from the third sub-fan-out line is electrically connected to the signal line, and one end of the third sub-fan-out line away from the first sub-fan-out line is electrically connected to the binding electrode; the length of the third sub-fan-out line is greater than that of the first sub-fan-out line.

[0013] In some embodiments, in each first fan-out line, the first sub-fan-out line includes one of the first routing line and the second routing line, and the third sub-fan-out line includes the other of the first routing line and the second routing line;

[0014] Among the plurality of first sub-fan-out lines, in the second direction, the first lines and the second lines are alternately arranged;

[0015] In the plurality of third sub-fan-out lines, the first lines and the second lines are alternately arranged in the second direction;

[0016] The first sub-fan-out line including the first routing line and / or the third sub-fan-out line including the first routing line further includes: a third routing line connected in parallel with the first routing line;

[0017] The third trace is located in the third conductive layer.

[0018] In some embodiments, the second conductive layer is located on a side of the first conductive layer facing away from the base substrate, and the third conductive layer is located between the first conductive layer and the base substrate.

[0019] In some embodiments, the display substrate further comprises:

[0020] a multi-layer insulating layer comprising a first insulating layer located between the first conductive layer and the second conductive layer and a second insulating layer located between the first conductive layer and the third conductive layer;

[0021] A plurality of first vias; the first vias penetrate the first insulating layer, the first routing line and the second insulating layer; the second sub-fan-out line or the second routing line is electrically connected to the first routing line and the third routing line through the first vias.

[0022] In some embodiments, an orthographic projection of the third trace on the substrate substantially overlaps with an orthographic projection of the first trace and the first via on the substrate.

[0023] In some embodiments, the first sub-fan-out line includes: a first portion and a second portion located in different conductive layers and electrically connected; the third sub-fan-out line includes: a third portion and a fourth portion located in different conductive layers and electrically connected;

[0024] One of the first portion and the second portion includes a first trace, and the other of the first portion and the second portion includes a second trace;

[0025] In the plurality of first portions, the first routing lines and the second routing lines are alternately arranged in the second direction; in the plurality of second portions, the first routing lines and the second routing lines are alternately arranged in the second direction;

[0026] One of the third part and the fourth part includes a first routing line, and the other of the third part and the fourth part includes a second routing line; in the multiple third parts, the first routing line and the second routing line are alternately arranged in the second direction; in the multiple fourth parts, the first routing line and the second routing line are alternately arranged in the second direction.

[0027] In some embodiments, the plurality of fan-out lines further include: a plurality of second fan-out lines; in the second direction, the plurality of first fan-out lines are at least located on one side of the plurality of second fan-out lines; the length of the second fan-out line is less than the length of the first fan-out line;

[0028] The second fan-out line includes: a fourth sub-fan-out line and a fifth sub-fan-out line electrically connected in sequence in a direction from the display area to the fan-out area; in each second fan-out line, one of the fourth sub-fan-out line and the fifth sub-fan-out line is a first routing line, and the other of the fourth sub-fan-out line and the fifth sub-fan-out line is a second routing line.

[0029] In some embodiments, in the plurality of first sub-fan-out lines and the plurality of fourth sub-fan-out lines, the first lines and the second lines are alternately arranged in the second direction; the orthographic projections of the first lines and the second lines respectively located in two adjacent first sub-fan-out lines on the substrate have a substantially overlapping area;

[0030] In the plurality of third sub-fan-out lines and the plurality of fifth sub-fan-out lines, the first lines and the second lines are alternately arranged in the second direction; the orthographic projections of the first lines and the second lines in two adjacent third sub-fan-out lines on the substrate have a substantially overlapping area.

[0031] In some embodiments, lengths of the plurality of first fan-out lines gradually increase in a direction away from the second fan-out line.

[0032] In some embodiments, each sub-fan-out line is divided into a plurality of sub-segments along its extension direction; the extension directions of two adjacent sub-segments are different;

[0033] The first sub-fan-out line includes a plurality of sub-segments arranged in sequence in a direction from the display area to the fan-out area, and the second sub-fan-out line includes a plurality of sub-segments arranged in sequence in a direction from the display area to the fan-out area;

[0034] The third sub-fan-out line includes: a first sub-segment, a second sub-segment and a third sub-segment; the first sub-segment is located on the side of the binding area facing the display area, and the end of the first sub-segment away from the second sub-segment is electrically connected to the binding electrode; the second sub-segment is located on the side of the first sub-segment away from the display area, and the third sub-segment is located on the side of the second sub-segment away from the display area.

[0035] In some embodiments, the extension direction of the first subsegment intersects the extension direction of the second subsegment, the angles between the extension directions of the first subsegment, the second subsegment, and the first direction are greater than 0, and the angles between the extension directions of the first subsegment, the second subsegment, and the second direction are greater than 0;

[0036] The third subsection extends along the second direction;

[0037] In the direction away from the second fan-out line, the length of the orthographic projection of the first sub-segment on the base substrate gradually decreases; in the direction from the display area to the fan-out area, the length of the orthographic projection of the third sub-segment on the base substrate gradually increases.

[0038] In some embodiments, in adjacent third sub-fan-out lines, the orthographic projections of the two first sub-segments on the substrate have a substantially overlapping area, the orthographic projections of the two second sub-segments on the substrate have a substantially overlapping area, and the orthographic projections of the two third sub-segments on the substrate have a substantially overlapping area.

[0039] In some embodiments, in each first fan-out line, the first sub-fan-out line includes one of the first routing line and the second routing line, and the third sub-fan-out line includes the other of the first routing line and the second routing line; the third sub-fan-out line further includes a fourth sub-segment located between the first sub-segment and the binding area; and the fourth sub-segment extends along the first direction;

[0040] In a direction away from the second fan-out line, the length of the fourth sub-segment gradually decreases;

[0041] The orthographic projections of the fourth sub-segments of two adjacent third sub-fan-out lines on the substrate do not overlap with each other.

[0042] In some embodiments, the first sub-fan-out line includes: a fifth sub-segment, a sixth sub-segment, and a seventh sub-segment arranged in sequence in the first direction; the fifth sub-segment and the seventh sub-segment extend along the first direction;

[0043] The angle between the extension direction of the sixth sub-segment and the second direction, and the angle between the second directions are both greater than 0;

[0044] One end of the fifth sub-segment facing away from the sixth sub-segment is electrically connected to the signal line, and one end of the seventh sub-segment facing away from the sixth sub-segment is electrically connected to the second sub-fan-out line;

[0045] In two adjacent first sub-fan-out lines, the orthographic projections of the two sixth sub-segments on the base substrate have substantially overlapping areas, the orthographic projections of the two fifth sub-segments on the base substrate do not overlap with each other; and the orthographic projections of the two seventh sub-segments on the base substrate do not overlap with each other.

[0046] In the first fan-out line, an extending direction of the sixth sub-segment is the same as an extending direction of the first sub-segment.

[0047] In some embodiments, the third sub-fan-out line includes a third portion and a fourth portion;

[0048] At least part of the first fan-out line further includes an eighth subsegment, a ninth subsegment, and a tenth subsegment sequentially arranged in the first direction; the eighth subsegment and the tenth subsegment extend along the first direction;

[0049] The third portion includes the first sub-segment, the second sub-segment, and the third sub-segment, and the fourth portion of at least part of the first fan-out line includes: the eighth sub-segment, the ninth sub-segment, and the tenth sub-segment;

[0050] The angle between the extension direction of the ninth sub-segment and the second direction, and the angle between the second directions are both greater than 0;

[0051] An end of the eighth subsegment facing away from the ninth subsegment is electrically connected to the first subsegment, and an end of the tenth subsegment facing away from the ninth subsegment is electrically connected to the binding electrode;

[0052] In two adjacent fourth portions, the orthographic projections of the two ninth sub-segments on the substrate have a substantially overlapping area, the orthographic projections of the two eighth sub-segments on the substrate do not overlap, and the orthographic projections of the two tenth sub-segments on the substrate do not overlap;

[0053] In the first fan-out line, an extending direction of the first sub-segment is the same as an extending direction of the ninth sub-segment.

[0054] In some embodiments, the first sub-fan-out line includes a first portion and a second portion;

[0055] The first sub-fan-out line includes: a fifth sub-segment, two sixth sub-segments, an eleventh sub-segment, and a seventh sub-segment;

[0056] In the first direction, the fifth subsegment, the sixth subsegment, the eleventh subsegment, the sixth subsegment, and the seventh subsegment are arranged in sequence; the first portion includes a partial area of ​​the fifth subsegment, the sixth subsegment, and the eleventh subsegment, which are arranged in sequence; and the second portion includes a partial area of ​​the eleventh subsegment, the sixth subsegment, and the seventh subsegment, which are arranged in sequence;

[0057] The fifth sub-segment, the eleventh sub-segment, and the seventh sub-segment extend along the first direction;

[0058] The angle between the extension direction of the sixth sub-segment and the second direction, and the angle between the second directions are both greater than 0;

[0059] One end of the fifth sub-segment facing away from the sixth sub-segment is electrically connected to the signal line, and one end of the seventh sub-segment facing away from the sixth sub-segment is electrically connected to the second sub-fan-out line;

[0060] In two adjacent first portions, the orthographic projections of the two sixth subsegments on the substrate have a substantially overlapping area, the orthographic projections of the two fifth subsegments on the substrate do not overlap, and the orthographic projections of the two eleventh subsegments on the substrate do not overlap; in two adjacent second portions, the orthographic projections of the two sixth subsegments on the substrate have a substantially overlapping area, the orthographic projections of the two eleventh subsegments on the substrate do not overlap, and the orthographic projections of the two seventh subsegments on the substrate do not overlap.

[0061] In the first fan-out line, an extending direction of the sixth sub-segment is the same as an extending direction of the first sub-segment.

[0062] In some embodiments, among the plurality of first fan-out lines sequentially arranged in a direction away from the second fan-out line, the lengths of the second sub-fan-out lines gradually increase;

[0063] At least a portion of the second sub-fan-out line includes: a twelfth sub-segment;

[0064] The included angle between the extension direction of the twelfth sub-segment and the second direction, and the included angle between the second directions are both greater than 0.

[0065] In some embodiments, the display substrate further comprises:

[0066] A plurality of thin film transistors are located in the display area; the first conductive layer further includes gate electrodes of the thin film transistors, and the second conductive layer further includes source electrodes and drain electrodes of the thin film transistors.

[0067] In some embodiments, the display substrate further comprises:

[0068] A plurality of thin film transistors are located in the display area;

[0069] A plurality of light-emitting devices are located in the display area on a side of the thin film transistor away from the display panel; the light-emitting devices include a stacked anode, a light-emitting functional layer, and a cathode;

[0070] A plurality of connecting electrodes are located between the drain electrode and the anode of the thin film transistor in the display area, and the anode is electrically connected to the drain electrode through the connecting electrodes;

[0071] The first conductive layer also includes a gate electrode of the thin film transistor;

[0072] The second conductive layer includes: a source electrode and a drain electrode of the thin film transistor; or the second conductive layer includes a connecting electrode.

[0073] In some embodiments, the display substrate further comprises:

[0074] A plurality of light shielding portions are located between the thin film transistor and the base substrate in the display area;

[0075] The first fan-out line further includes a third line, and the third line is arranged on the same layer as the light shielding portion.

[0076] An embodiment of the present disclosure provides a display panel, which includes the display substrate provided by the embodiment of the present disclosure.

[0077] An embodiment of the present disclosure provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0079] FIG1 is a schematic structural diagram of a display substrate provided by the related art;

[0080] FIG2 is a schematic diagram of fan-out line resistance distribution of a display substrate provided by related art;

[0081] FIG3 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0082] FIG4 is a schematic diagram of an enlarged structure of area A in FIG3 provided by an embodiment of the present disclosure;

[0083] FIG5 is a cross-sectional view along line BB′ in FIG4 provided by an embodiment of the present disclosure;

[0084] FIG6 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0085] FIG7 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0086] FIG8 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0087] FIG9 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0088] FIG10 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0089] FIG11 is a schematic diagram of fan-out line resistance distribution of a display substrate provided by an embodiment of the present disclosure;

[0090] FIG12 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0091] FIG13 is a cross-sectional view along CC' in FIG12 provided by an embodiment of the present disclosure;

[0092] FIG14 is a cross-sectional view along line EE' in FIG12 provided by an embodiment of the present disclosure;

[0093] FIG15 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0094] FIG16 is a schematic diagram of fan-out line resistance distribution of another display substrate provided by an embodiment of the present disclosure;

[0095] FIG17 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0096] FIG18 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0097] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0098] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0099] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0100] In the related art, as shown in FIG1 , from left to right, half of the fan-out line 2 is the first line 401, and the other half is the second line 402. The first line 401 and the second line 402 are located on different layers and are overlapped by vias to achieve electrical connection between the different lines of the fan-out line. However, the resistivity of the first line is relatively large. Setting half of the fan-out line as the first line will increase the resistance of the fan-out line, thereby increasing the impedance of the fan-out line. Furthermore, as shown in FIG2 , the need for the fan-out line in FIG2 corresponds to the fan-out line 2 from left to right in FIG1 . In FIG1 , the length of the fan-out line 2 from left to right gradually decreases, and the corresponding resistance also gradually decreases. The resistance of the fan-out line on the far left is as high as 8.7 kilo-ohms (KΩ). The difference in resistance between the fan-out lines on the left and right sides is relatively large, which may lead to the risk of insufficient charging. For touch display products, it may also lead to the risk of poor touch.

[0101] The present disclosure provides a display substrate, as shown in FIG3 and FIG4 , which includes:

[0102] The substrate 1 includes a display area 101 and a fan-out area 1021 located on one side of the display area 101 in a first direction Y.

[0103] A plurality of fan-out lines 2 are arranged in sequence along a second direction X in a fan-out area 1021; the second direction X intersects with the first direction Y; the fan-out line 2 includes a plurality of sub-fan-out lines 3, and the sub-fan-out line 3 includes a routing line 4; the plurality of fan-out lines 2 include: a plurality of first fan-out lines 201; the first fan-out line 201 includes: a first sub-fan-out line 301, a second sub-fan-out line 302, and a third sub-fan-out line 303 in its extension direction; in the same first fan-out line 201, one of the first sub-fan-out line 301 and the third sub-fan-out line 303 includes at least a first routing line 401, the first sub-fan-out line 302 includes a first routing line 401, and the first sub-fan-out line 303 includes a first routing line 401. 01 and the other of the third sub-fan-out lines 303 includes at least a second routing line 402, the first routing line 401 is located in the first conductive layer 701, and the second routing line 402 is located in the second conductive layer 702; any two adjacent first fan-out lines 201 have an overlapping area in their orthographic projections on the substrate 1, and in the overlapping area, one of the first fan-out lines 201 includes the first routing line 401, and the other first fan-out line 201 includes the second routing line 402; the resistivity of the second sub-fan-out line 302 is at least less than the resistivity of one of the first conductive layer 701 and the second conductive layer 702.

[0104] In the display substrate provided by the present disclosure, the first fan-out line located in the fan-out area includes a first sub-fan-out line, a second sub-fan-out line, and a third sub-fan-out line. The resistivity of the second sub-fan-out line is at least less than the resistivity of the first conductive layer and the second conductive layer, that is, the resistivity of the second sub-fan-out line is relatively low. Compared with the prior art where half of the fan-out line is the first line and half is the second line, the provision of the second sub-fan-out line can reduce the resistance of the fan-out line, thereby reducing the impedance of the fan-out line, which is beneficial for reducing the resistance difference between different fan-out lines and avoiding problems such as uneven charging or poor touch. In addition, the orthographic projections of any two adjacent first fan-out lines on the substrate have an overlapping area. The routing of the two first fan-out lines in the overlapping area is respectively the first routing and the second routing. That is, the routing of the two first fan-out lines in the overlapping area is located in different conductive layers. Even if there is overlap, short circuit will not occur, which is beneficial for saving wiring space.

[0105] It should be noted that Figure 3 only shows different regions of the substrate, and does not show the fan-out lines. Figure 4 is an enlarged schematic diagram of region A in Figure 3 .

[0106] In some embodiments, as shown in FIG. 3 , the base substrate 1 further includes a peripheral region 102 surrounding the display region 101 , and the fan-out region 1021 is located in the peripheral region 102 .

[0107] In some embodiments, the resistivity of the second conductive layer is less than the resistivity of the first conductive layer;

[0108] As shown in FIG4 , the second sub-fan-out line 302 is located in the second conductive layer 702 ;

[0109] The orthographic projections of the second sub-fan-out lines 302 of different first fan-out lines 201 on the base substrate 1 do not overlap with each other.

[0110] Specifically, in the display substrate provided by the embodiments of the present disclosure, the second sub-fan-out lines included in the plurality of first fan-out lines are located in the same conductive layer, specifically in the second conductive layer having a lower resistivity. In other words, they are arranged on the same layer as the second traces. This allows the second sub-fan-out lines to be directly connected to the second traces, reducing fan-out line resistance while avoiding increasing fan-out line manufacturing complexity.

[0111] In some embodiments, the material of the first conductive layer includes, for example, molybdenum; and the second conductive layer includes, for example, a titanium / aluminum / titanium stack.

[0112] In some embodiments, as shown in FIG. 4 and FIG. 5 , the second conductive layer 702 is located on a side of the first conductive layer 701 facing away from the substrate 1 .

[0113] It should be noted that FIG5 is a cross-sectional view along line BB' in FIG4 .

[0114] In some embodiments, as shown in FIG6 and FIG7 , the display substrate further includes:

[0115] A plurality of thin film transistors 6 are located in the display area 101 ; the first conductive layer 701 further includes a gate G of the thin film transistor 6 , and the second conductive layer 702 further includes a source S and a drain D of the thin film transistor 6 .

[0116] That is, in the display substrate provided by the embodiment of the present disclosure, the first wiring is arranged on the same layer as the gate, and the second wiring is arranged on the same layer as the source and drain. In this way, the distance between the second conductive layer and the first conductive layer is relatively close, and it is easy to overlap the second wiring and the first wiring through the via, which can avoid overlap and wire breakage.

[0117] In some embodiments, in the display area, the display substrate includes a plurality of sub-pixels arranged in an array along a first direction Y and a second direction X; each sub-pixel includes at least one thin-film transistor. The display substrate also includes a plurality of scan lines and a plurality of data lines; the scan lines extend along the first direction Y, and the data lines extend along the second direction X. The scan lines are disposed on the same layer and electrically connected to the gate electrodes of the thin-film transistors, and the data lines are disposed on the same layer and electrically connected to the source electrodes of the thin-film transistors.

[0118] In some embodiments, as shown in Figures 6 and 7, the thin film transistor 6 further includes an active layer 601. Taking the thin film transistor 6 as a top-gate structure as an example, the active layer 601 is located between the base substrate 1 and the gate G, and the source S and the drain D are located on the side of the gate G away from the base substrate 1.

[0119] In some embodiments, as shown in FIG6 and FIG7 , the display substrate further includes:

[0120] The multi-layer insulating layer 11 includes a first insulating layer 1101 located between the first conductive layer 701 and the second conductive layer 702 , wherein the first insulating layer 1101 is an interlayer insulating layer;

[0121] As shown in FIG. 4 and FIG. 5 , in the fan-out region, the first insulating layer 1101 includes a plurality of second vias 15 penetrating the thickness thereof, and the second sub-fan-out line 302 is electrically connected to the first trace 401 through the second vias 15 .

[0122] It should be noted that in FIG4 , in the region of the second via 15, the line width of the second sub-fan-out line 302 is equal to the line width of the first routing line 401, and the line width of this region is equal to the line width of the second sub-fan-out line 302 and the line width of the first routing line 401 in the remaining regions. In a specific implementation, the size of the second via in the direction perpendicular to the extension of the fan-out line does not exceed the line width of the fan-out line. As shown in FIG9 , the line width h1 of the fan-out line 2 in the region of the second via 15 can be set to be greater than the line width h2 in the remaining regions. In FIG9 , the orthographic projection of the second via 15 on the substrate is located within the orthographic projection of the fan-out line 2 in region F on the substrate. In region F, the line width of the second sub-fan-out line 302 is equal to the line width of the first routing line 401. The line width h1 of the second sub-fan-out line 302 in region F is greater than the line width h2 of the second sub-fan-out line 302 outside region F. The line width of the first routing line 401 in region F is greater than the line width of the first routing line 401 outside region F. During implementation, the fan-out line width in region F can be specifically configured based on the routing space. As shown in FIG9 , in some embodiments, the second sub-fan-out line 302 is electrically connected to the first trace 401 via a single second via 15 . Of course, if the fan-out line width in region F is wider, the second sub-fan-out line 302 can also be electrically connected to the first trace 401 via multiple second vias 15 , as shown in FIG10 , further improving the electrical connection between the two.

[0123] The remaining area of ​​the second sub-fan-out line 302 and the first line 401 where they are electrically connected

[0124] In some embodiments, as shown in FIG. 6 and FIG. 7 , the display substrate further includes: a buffer layer 1102 - 1 located between the active layer 601 and the base substrate 1 , and a gate insulating layer 1102 - 2 located between the active layer 601 and the first conductive layer 701 .

[0125] In some embodiments, the display substrate provided by the embodiments of the present disclosure is applied to a liquid crystal display, that is, the display substrate is an array substrate. As shown in FIG6 , the display substrate further includes: a pixel electrode 16 and a common electrode 17. The pixel electrode 16 is electrically connected to the drain electrode D. FIG6 illustrates an example in which the common electrode 17 is located on the side of the pixel electrode 16 facing away from the base substrate 1. The display substrate further includes: a first passivation layer 1103 located between the source electrode S and the drain electrode D and the pixel electrode 16, and a second passivation layer 1104 located between the common electrode 17 and the pixel electrode 16.

[0126] Of course, in a specific implementation, the pixel electrode may be located on the side of the common electrode facing away from the base substrate.

[0127] In some embodiments, as shown in FIG6 , the display substrate further includes: a third conductive layer 703 ; the third conductive layer 703 includes:

[0128] A plurality of light shielding portions 14 are located between the thin film transistor 6 and the base substrate 1 in the display area 101; the orthographic projection of the light shielding portion 14 on the base substrate 1 covers the orthographic projection of the active layer 601 on the base substrate 1;

[0129] Specifically, the third conductive layer 703 is located between the buffer layer 1102 - 1 and the base substrate 1 .

[0130] In some embodiments, when the display substrate is an array substrate, the display substrate may further include touch electrodes and touch signal lines electrically connected to the touch electrodes; the touch electrodes may reuse pixel electrodes, or the touch electrodes may be located in one of the conductive layers as shown in FIG6 , or an additional conductive layer may be added to set the touch electrodes.

[0131] In some embodiments, the display substrate provided by the embodiments of the present disclosure is applied to electroluminescent display. As shown in FIG7 , the display substrate further includes:

[0132] A plurality of light emitting devices 8 are located in the display area 101 on the side of the thin film transistor 6 away from the display panel; the light emitting device 8 includes an anode 801 , a light emitting functional layer 802 , and a cathode 803 that are stacked.

[0133] In some embodiments, as shown in Figure 7, the display substrate also includes: a planarization layer 1105 located between the anode 801 and the drain D, a pixel definition layer 18 located on the side of the planarization layer 1105 away from the base substrate 1 and covering the edge of the anode 801; and an encapsulation layer 19 located on the side of the cathode 803 away from the base substrate 1.

[0134] In a specific implementation, the light-emitting functional layer may include, for example, an organic light-emitting layer, and may further include at least one of the following: an electron transport layer, a hole blocking layer, an electron injection layer, a hole injection layer, and an electron blocking layer. The encapsulation layer may include, for example, a stacked arrangement of an inorganic encapsulation layer / an organic encapsulation layer / an inorganic encapsulation layer.

[0135] Alternatively, the display substrate is applied to an electroluminescent display. In some embodiments, the first insulating layer between the gate and the source and drain electrodes is a first interlayer insulating layer. As shown in FIG8 , the display substrate further includes:

[0136] Multiple connecting electrodes 13 are located between the drain electrode and the anode 801 of the thin film transistor 6 in the display area 101. The anode 801 is electrically connected to the drain electrode D through the connecting electrodes 13. The planarization layer 1105 is located between the connecting electrodes 13 and the anode 801.

[0137] A second interlayer insulating layer 1106 is located between the connecting electrode 13 and the drain electrode D;

[0138] The first conductive layer 701 also includes a gate G of the thin film transistor 6;

[0139] The second conductive layer 702 further includes: a source S and a drain D of the thin film transistor 6. That is, the first wiring is provided in the same layer as the gate, and the second wiring is provided in the same layer as the source and drain.

[0140] Alternatively, in some embodiments, the first conductive layer may further include a gate of a thin film transistor, and the second conductive layer may further include a connecting electrode, that is, the first wiring and the gate are provided on the same layer, and the second wiring and the connecting electrode are provided on the same layer.

[0141] Of course, in specific implementation, the first routing and the second routing can be set respectively from two of the following conductive layers: the conductive layer where the gate is located, the conductive layer where the source and drain are located, the conductive layer where the connecting electrode is located, the conductive layer where the anode is located, and the conductive layer where the cathode is located.

[0142] In a specific implementation, if the display substrate is applied to electroluminescent display, the display substrate may further include touch electrodes and touch signal lines; for example, the display substrate may further include a touch layer located on the side of the packaging layer away from the base substrate, and the touch layer may include touch electrodes and touch signal lines.

[0143] In some embodiments, as shown in FIG4 , in the direction from the display area (not shown) to the fan-out area 1021 , that is, the negative direction Y− of the first direction Y, the first sub-fan-out line 301 , the second sub-fan-out line 302 , and the third sub-fan-out line 303 are electrically connected in sequence.

[0144] In some embodiments, as shown in FIG3 and FIG4 , the fan-out area 1021 further includes a binding area 10211 ;

[0145] The display substrate further includes: a plurality of binding electrodes 9 located in the binding area 10211 (as shown in FIG4 ), and a plurality of signal lines 10 extending from the display area 101 to the fan-out area 1021 (as shown in FIG3 );

[0146] One end of the first sub-fan-out line 301 away from the third sub-fan-out line 303 is electrically connected to the signal line 10 , and one end of the third sub-fan-out line 303 away from the first sub-fan-out line 301 is electrically connected to the binding electrode 9 ; the length of the third sub-fan-out line 303 is greater than that of the first sub-fan-out line 301 .

[0147] It should be noted that the bonding electrodes are used to bond with the driver chip, and the driver chip's orthographic projection on the substrate overlaps with the bonding area. This allows signals from the driver chip to be transmitted via the bonding electrodes and fan-out lines to signal lines. These signal lines include, for example, data lines and touch signal lines.

[0148] In some embodiments, as shown in FIG. 3 , the peripheral area 101 includes a binding area 10211 ; that is, the display substrate is bound to a driver chip.

[0149] It should be noted that, as shown in Figure 3, in the second direction X, the width of the binding area 10211 is significantly smaller than the width of the display area 101; the symmetry axis of the binding area 10211 extending along the first direction Y is co-located with the symmetry axis of the display area 101 extending along the first direction Y. Multiple signal lines 10 extend along the first direction Y and are arranged along the second direction X. Accordingly, in the second direction X, the lengths of the multiple fan-out lines electrically connected to the binding electrodes in a binding area first decrease and then increase in the positive direction X+ of the second direction X.

[0150] In some embodiments, as shown in FIG4 , the plurality of fan-out lines 2 further include: a plurality of second fan-out lines 202 ; in the second direction X, the plurality of first fan-out lines 201 are at least located on one side of the plurality of second fan-out lines 202 ; the length of the second fan-out line 202 is less than the length of the first fan-out line 201 ;

[0151] The second fan-out line 202 includes: a fourth sub-fan-out line 304 and a fifth sub-fan-out line 305 electrically connected in sequence in a direction from the display area to the fan-out area 1021, that is, in the negative direction Y- of the first direction Y; in each second fan-out line 202, one of the fourth sub-fan-out line 304 and the fifth sub-fan-out line 305 is a first routing line 401, and the other of the fourth sub-fan-out line 304 and the fifth sub-fan-out line 305 is a second routing line 402.

[0152] That is, the second fan-out line is divided into two parts located in different conductive layers. It should be noted that Figure 4 only shows part of the first fan-out line 201 and part of the second fan-out line 202. In a specific implementation, in the second direction X, both sides of the plurality of second fan-out lines 202 include a plurality of first fan-out lines 201.

[0153] In a specific implementation, the second fan-out line has a shorter length and a lower resistance, and even if half of the second fan-out line is the first line and the other half is the second line, it will not cause a large difference in resistance between adjacent fan-out lines.

[0154] In the display substrate provided by the present disclosure, the first fan-out line located in the fan-out area includes a first sub-fan-out line, a second sub-fan-out line, and a third sub-fan-out line. The provision of the second sub-fan-out line can reduce the resistance of the fan-out line, thereby reducing the impedance of the fan-out line. This can also reduce the resistance and impedance differences between the first and second fan-out lines, thereby avoiding problems such as uneven charging and poor touch control.

[0155] In a specific implementation, in the same second fan-out line, the second line is electrically connected to the first line through a via hole penetrating the first insulating layer.

[0156] In some embodiments, as shown in FIG4 , in the plurality of first sub-fan-out lines 301 and the plurality of fourth sub-fan-out lines 304 , the first lines 401 and the second lines 402 are alternately arranged in the second direction X; the orthographic projections of the first lines 401 and the second lines 402 located in two adjacent first sub-fan-out lines 301 on the substrate 1 have a substantially overlapping area;

[0157] In the plurality of third sub-fan-out lines 303 and the plurality of fifth sub-fan-out lines 305 , the first routing lines 401 and the second routing lines 402 are alternately arranged in the second direction X; the orthographic projections of the first routing lines 401 and the second routing lines 402 located in two adjacent third sub-fan-out lines 303 on the substrate 1 have a substantially overlapping area.

[0158] That is, the orthographic projections of any two adjacent fan-out lines on the substrate have a roughly overlapping area, and the routes of the two fan-out lines in the roughly overlapping area of ​​the orthographic projections are the first route and the second route respectively. That is, the routes of the two fan-out lines in the roughly overlapping area of ​​the orthographic projections are located in different conductive layers. Even if the orthographic projections roughly overlap, no short circuit will occur, which is beneficial to saving wiring space.

[0159] It should be noted that the area where the orthographic projections of the first route and the second route on the substrate substantially overlap means that: in the area where the orthographic projections of the two route overlap, the distance between the edge of the orthographic projection of the first route on the substrate and the edge of the orthographic projection of the second route on the substrate is less than the error range, and it can be considered that the orthographic projections of the first route and the second route on the substrate have an overlapping area.

[0160] In some embodiments, as shown in FIG. 4 , the lengths of the plurality of first fan-out lines 201 gradually increase in a direction away from the second fan-out line 202 .

[0161] Specifically, as shown in FIG4 , a plurality of first fan-out lines 201 located on one side of a plurality of second fan-out lines 202 in the negative direction X− of the second direction X constitute a first fan-out line group 20. The plurality of first fan-out lines 201 in the first fan-out line group 20 are numbered Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 in the negative direction X− of the second direction X, with the lengths of Q1 to Q8 gradually increasing. A plurality of first fan-out lines (not shown) located on one side of the plurality of second fan-out lines in the positive direction X+ of the second direction X constitute a second fan-out line group. The plurality of first fan-out lines 2 in the second fan-out line group gradually increase in length in the positive direction X+ of the second direction X.

[0162] In some embodiments, as shown in FIG4 , in each first fan-out line 201 , the first sub-fan-out line 301 includes one of a first routing line 401 and a second routing line 402 , and the third sub-fan-out line 303 includes the other of the first routing line 401 and the second routing line 402 ;

[0163] In the plurality of first sub-fan-out lines 301 , in the second direction X, the first lines 401 and the second lines 402 are alternately arranged;

[0164] In the plurality of third sub-fan-out lines 303 , in the second direction X, the first lines 401 and the second lines 402 are alternately arranged.

[0165] That is, in a specific implementation, as shown in FIG4 , in two adjacent first fan-out lines 201 , in one of the first fan-out lines 201 , the first sub-fan-out line 301 is the first routing line 401 , and the third sub-fan-out line 303 is the second routing line 402 ; in the other first fan-out line 201 , the first sub-fan-out line 301 is the second routing line 402 , and the third sub-fan-out line 303 is the first routing line 401 .

[0166] The display substrate provided by the embodiment of the present disclosure as shown in Figure 4 can reduce the resistance of the first fan-out line because the multiple first fan-out lines 201 all include a second sub-fan-out line with a lower resistivity. However, since the multiple first fan-out lines are provided with a second sub-fan-out line located in the middle area of ​​the fan-out area, the second sub-fan-out lines of the multiple first fan-out lines do not overlap with each other in their orthographic projections on the substrate. In this way, compared with the scheme of half first routing and half second routing in the related art, the area corresponding to the multiple second sub-fan-out lines requires an increased space. In order to facilitate wiring, it is necessary to set the third sub-fan-out line to one side of the first binding area, thereby causing the length of the third sub-fan-out line to be longer. The resistance of some of the first fan-out lines and the second fan-out lines provided by the embodiment of the present disclosure is shown in Figure 11, and only some of the fan-out lines are shown in Figure 11. It can be seen from Figure 11 that the overall resistance of the first fan-out line is reduced, and the resistance of the first fan-out line at the farthest end is reduced to 5.07KΩ compared to 8.7KΩ in Figure 2. However, since the middle area of ​​the fan-out area is replaced with a single-layer wiring and the length of the third sub-fan-out line is increased, the length of the first line located in the first sub-fan-out line of the two adjacent first fan-out lines is much smaller than the length of the first line of the third sub-fan-out line of the other fan-out line, which will cause the length difference of the first line of the two adjacent first fan-out lines to be large, and then cause the resistance difference of the two adjacent first fan-out lines to be large, that is, the ΔR area in Figure 11 is generated. For touch display products, the existence of ΔR affects the touch accuracy.

[0167] In some embodiments, as shown in FIG12 , the first sub-fan-out line 301 including the first trace 401 and / or the third sub-fan-out line 303 including the first trace 401 further includes: a third trace 403 connected in parallel with the first trace 401 ;

[0168] The third trace 403 is located in the third conductive layer 703 .

[0169] The display substrate provided by the embodiment of the present disclosure can reduce the resistance of the first routing line by setting the third routing line located in the third conductive layer in parallel with the first routing line compared to when the first routing line is set alone, thereby reducing the resistance difference between two adjacent first fan-out lines.

[0170] FIG12 illustrates an example in which the first sub-fan-out line 301 including the first line 401 and the third sub-fan-out line 303 including the first line 401 both include the third line 403. In some embodiments, as shown in FIG12 , each first line 401 is connected in parallel with the third line 403, that is, the first line 401 included in the second fan-out line 202 is also connected in parallel with the third line 403. This can reduce the resistance of the second fan-out line 202 and help reduce the resistance difference between the second fan-out line 202 and the first fan-out line 201.

[0171] In some embodiments, as shown in FIG. 13 and FIG. 14 , the third conductive layer 703 is located between the first conductive layer 701 and the base substrate 1 .

[0172] It should be noted that FIG13 is a cross-sectional view taken along CC′ in FIG12 , and FIG14 is a cross-sectional view taken along EE′ in FIG12 .

[0173] In some embodiments, when the display substrate is an array substrate, as shown in FIG. 6 , the third traces 403 and the light shielding portions 14 are provided in the same layer; that is, the third conductive layer 703 includes multiple light shielding portions 14 and multiple third traces 403 .

[0174] In the display substrate provided by the embodiment of the present disclosure, the third line is arranged on the same layer as the light-shielding portion, so that the third conductive layer is close to the first conductive layer, making it easy to overlap the third line with the first line through the via hole, thereby avoiding overlap breakage.

[0175] In some embodiments, as shown in FIG13 and FIG14 , the multilayer insulating layer 11 includes: a second insulating layer 1102 located between the first conductive layer 701 and the third conductive layer 703 ; the second insulating layer 1102 includes a buffer layer 1102 - 1 and a gate insulating layer 1102 - 2 ;

[0176] The display substrate also includes:

[0177] Multiple first vias 12 ; the first vias 12 penetrate the first insulating layer 1101 , the first trace 401 and the second insulating layer 1102 ; the second sub-fan-out line 302 or the second trace 402 is electrically connected to the first trace 401 and the third trace 403 through the first vias 12 .

[0178] 13 , the second sub-fan-out line 302 is electrically connected to the first and third traces 401 and 403 through the first via 12 . In FIG. 14 , the second trace 402 of the second fan-out line 202 is electrically connected to the first and third traces 401 and 403 through the first via 12 .

[0179] In a specific implementation, as shown in Figures 13 and 14 , at the first via 12, the first trace 401 includes a first sub-via 4011. After forming the second insulating layer 1102, instead of first forming a via penetrating the second insulating layer 1102 in the region corresponding to the first via 12, the first conductive layer is formed after forming the second insulating layer 1102. This first conductive layer is then patterned to form the pattern of the first trace 401 and the first sub-via 4011. The first insulating layer 1101 is then formed to cover the first sub-via 4011. Finally, the first insulating layer 1101 and the second insulating layer 1102 are patterned in the region corresponding to the first via 12 to form the first via 12. This can simplify the manufacturing process for the first via, saving costs.

[0180] In some embodiments, when the display substrate is an electroluminescent display panel, the first routing is arranged on the same layer as the gate, the second routing is arranged on the same layer as the source and drain, and the third routing is arranged on the same layer as the connecting electrode; when the display substrate is an electroluminescent display panel, the first routing is arranged on the same layer as the gate, the second routing is arranged on the same layer as the connecting electrode, and the third routing is arranged on the same layer as the source and drain.

[0181] In some embodiments, as shown in FIG12 , the orthographic projection of the third trace 403 on the base substrate 1 substantially overlaps with the orthographic projections of the first trace 401 and the first via 12 on the base substrate 1 , thereby saving wiring space.

[0182] In some embodiments, as shown in FIG15 , the first sub-fan-out line 301 includes: a first portion 3011 and a second portion 3012 located on different conductive layers 7 and electrically connected; the third sub-fan-out line 303 includes: a third portion 3031 and a fourth portion 3032 located on different conductive layers 7 and electrically connected;

[0183] One of the first portion 3011 and the second portion 3012 includes the first trace 401 , and the other of the first portion 3011 and the second portion 3012 includes the second trace 402 ; that is, the two portions of the first sub-fan-out line 301 are located in different conductive layers 7 ;

[0184] In the plurality of first portions 3011 , the first traces 401 and the second traces 402 are alternately arranged in the second direction X; in the plurality of second portions 3012 , the first traces 401 and the second traces 402 are alternately arranged in the second direction X;

[0185] One of the third portion 3031 and the fourth portion 3032 includes the first trace 401 , and the other of the third portion 3031 and the fourth portion 3032 includes the second trace 402 ; that is, the two portions of the third sub-fan-out line 303 are located in different conductive layers 7 ;

[0186] In the plurality of third portions 3031 , in the second direction X, the first routing lines 401 and the second routing lines 402 are alternately arranged; in the plurality of fourth portions 3032 , in the second direction X, the first routing lines 401 and the second routing lines 402 are alternately arranged.

[0187] In the display substrate provided by the embodiment of the present disclosure, the first sub-fan-out line and the third sub-fan-out line both include two parts located in different conductive layers, that is, the first sub-fan-out line and the third sub-fan-out line both include a first routing line and a second routing line. In this way, even if the total length of the third sub-fan-out line is longer than the total length of the first sub-fan-out line, the length difference of the first routing line of the two adjacent first fan-out lines can be reduced, thereby reducing the resistance difference and impedance difference of the two adjacent first fan-out lines, thereby improving the touch accuracy.

[0188] The resistance of some of the first and second fan-out lines provided by the embodiments of the present disclosure is shown in Figure 16 , where the first fan-out line includes a first portion, a second portion, a second sub-fan-out line, a third portion, and a fourth portion, and the second fan-out line includes a fourth sub-fan-out line and a fifth sub-fan-out line. Only some of the fan-out lines are shown in Figure 16 . As can be seen from Figure 16 , the overall resistance of the first fan-out line is reduced, with the resistance of the farthest first fan-out line reduced to 4.2KΩ compared to 8.7KΩ in Figure 2 . The resistance difference between adjacent fan-out lines is also greatly reduced compared to Figure 11 .

[0189] In a specific implementation, the first sub-fan-out line includes a first and second routing electrically connected via a via extending through the first insulating layer, and the third sub-fan-out line includes a first and second routing electrically connected via a via extending through the first insulating layer. In a specific implementation, in the sub-fan-out line, because an area for electrically connecting the first and second routings is required, and to avoid the risk of short circuiting between adjacent sub-fan-out lines, the orthographic projections of the two adjacent sub-fan-out lines on the substrate do not overlap at the electrical connection between the first and second routings. Therefore, an area extending along the first direction to the portion serving as the electrical connection between the first and second routings is required. In a specific implementation, in the first direction, the sum of the width of the area where the first and second routings are electrically connected in the first sub-fan-out line and the width of the area where the first and second routings are electrically connected in the third sub-fan-out line is approximately 40 microns.

[0190] In some embodiments, as shown in FIG. 15 , in the same first fan-out line 201 , both ends of the second sub-fan-out line 302 are electrically connected to the same type of traces 4 .

[0191] In some embodiments, as shown in FIG4 , FIG12 , and FIG15 , the fan-out line 2 is divided into a plurality of sub-segments 5 in its extension direction; the extension directions of two adjacent sub-segments 5 are different; that is, the orthographic projection of the sub-fan-out line 3 on the substrate 1 can be divided into a plurality of sub-segments 5 according to the extension direction;

[0192] The multiple sub-segments 5 included in the first sub-fan-out line 301 are arranged in sequence in the direction from the display area (not shown) to the fan-out area 1021 (i.e., the negative direction Y- of the first direction Y), and the multiple sub-segments 5 included in the second sub-fan-out line 302 are arranged in sequence in the direction from the display area (not shown) to the fan-out area 1021 (i.e., the negative direction Y- of the first direction Y).

[0193] In some embodiments, as shown in Figures 4, 12, and 15, the third sub-fan-out line 303 includes: a first sub-segment 501, a second sub-segment 502, and a third sub-segment 503; the first sub-segment 501 is located on the side of the binding area 10211 facing the display area 101, and the end of the first sub-segment 501 away from the second sub-segment 502 is electrically connected to the binding electrode 9; the second sub-segment 502 is located on the side of the first sub-segment 501 away from the display area 101, and the third sub-segment 503 is located on the side of the second sub-segment 502 away from the display area 101.

[0194] It should be noted that Figures 4, 12, and 15 only show part of the second fan-out lines 202, as well as the eight first fan-out lines 201 located on one side of the multiple second fan-out lines 202 in the negative direction X- of the second direction X; in part of the multiple first sub-fan-out lines 301 and part of the multiple third sub-fan-out lines 303, there is an area where the first routing line 401 overlaps with the second routing line 402, so this area only needs to occupy the area of ​​4 routing lines, and the multiple second sub-fan-out lines 302 do not overlap with each other, and the multiple second sub-fan-out lines 302 need to occupy the area of ​​8 routing lines. Compared with the setting method of the first routing line and the second routing line jumper, setting up multiple second sub-fan-out lines requires more wiring space.

[0195] In the display substrate provided by the embodiments of the present disclosure, the third sub-fan-out line includes a first sub-segment, a second sub-segment, and a third sub-segment. Specifically, the third sub-fan-out line extends upward (i.e., in the positive direction Y+ of the first direction Y) from the binding area and then downward (i.e., in the negative direction of the first direction Y). This fully utilizes the wiring space surrounding the binding area, and while providing multiple second sub-fan-out lines, avoids excessively increasing the wiring space, the size of the fan-out area in the first direction, and thus the width of the peripheral area.

[0196] In some embodiments, as shown in FIG. 4 and FIG. 12 , in the second direction X, the orthographic projection of the third sub-segment 503 on the substrate 1 is located on one side of the binding region 10211 .

[0197] In the display substrate provided by the embodiment of the present disclosure, some sub-segments in the third sub-fan-out line are located on one side of the first binding area, which can fully utilize the space on both sides of the binding area, avoid excessive increase in wiring space, avoid increasing the size of the fan-out area in the first direction, and further avoid increasing the width of the peripheral area.

[0198] In some embodiments, as shown in FIG4 , FIG12 , and FIG15 , the extension direction of the first subsegment 501 intersects the extension direction of the second subsegment 502 , and the angles between the extension directions of the first subsegment 501 and the second subsegment 502 and the first direction Y are greater than 0, and the angles between the extension directions of the first subsegment 501 and the second subsegment 502 and the second direction X are greater than 0;

[0199] The third subsection 503 extends along the second direction X;

[0200] In the direction away from the second fan-out line 202, the length of the positive projection of the first sub-segment 501 on the base substrate 1 gradually decreases; in the direction from the display area (not shown) to the fan-out area 1021 (i.e., the negative direction of the first direction Y), the length of the positive projection of the third sub-segment 503 on the base substrate 1 gradually increases.

[0201] It should be noted that, as shown in Figures 4, 12, and 15, for identical sub-segments 5 in the same conductive layer 7, the following conditions are met: the length of the orthographic projection of the first sub-segment 501 on the base substrate 1 gradually decreases in the direction away from the second fan-out line 202, and the length of the orthographic projection of the third sub-segment 503 on the base substrate 1 gradually increases in the direction from the display area (not shown) to the fan-out area 1021 (i.e., the negative direction of the first direction Y). For identical sub-segments 5 located in different conductive layers 7 and whose orthographic projections do not overlap, the following conditions are also met: the length of the orthographic projection of the first sub-segment 501 on the base substrate 1 gradually decreases in the direction away from the second fan-out line 202, and the length of the orthographic projection of the third sub-segment 503 on the base substrate 1 gradually increases in the direction from the display area (not shown) to the fan-out area 1021 (i.e., the negative direction of the first direction Y).

[0202] In some embodiments, as shown in FIG. 4 and FIG. 12 , the third sub-fan-out line 303 further includes a fourth sub-segment 504 ; the fourth sub-segment 504 extends along the first direction Y;

[0203] In the direction away from the second fan-out line 202, the length of the fourth sub-segment 504 gradually decreases;

[0204] The orthographic projections of the fourth sub-segments 504 of two adjacent third sub-fan-out lines 303 on the base substrate 1 do not overlap with each other.

[0205] In the display substrate provided by the embodiment of the present disclosure, multiple fourth sub-segments are arranged along the second direction X, and the length of the fourth sub-segments gradually decreases in the direction away from the second fan-out line. Accordingly, the first sub-segment, whose extension direction intersects both the first direction and the second direction, is connected to the fourth sub-segment. In the direction away from the second fan-out line, the length of the orthographic projection of the first sub-segment on the base substrate gradually decreases. The length changes of the first sub-segment and the fourth sub-segment match each other, which is conducive to the rational use of wiring space and avoids increasing the size of the fan-out area.

[0206] In some embodiments, as shown in FIG4 and FIG12 , the third sub-fan-out line 303 further includes a thirteenth sub-segment 513 ; the thirteenth sub-segment 513 extends along the first direction Y;

[0207] In the direction away from the second fan-out line 202 , the length of the thirteenth sub-segment 513 gradually decreases; the orthographic projections of the thirteenth sub-segments 513 of two adjacent third sub-fan-out lines 303 on the substrate 1 do not overlap each other.

[0208] In the display substrate provided by the embodiment of the present disclosure, a plurality of thirteenth sub-segments are arranged along the second direction X, and the length of the thirteenth sub-segment gradually decreases in the direction away from the second fan-out line. Correspondingly, the third sub-segment extending along the second direction is connected to the thirteenth sub-segment, and the length of the positive projection of the third sub-segment on the base substrate gradually increases in the negative direction of the first direction Y. Thus, the length changes of the third sub-segment and the thirteenth sub-segment match each other, which is conducive to the rational use of wiring space and avoids increasing the size of the fan-out area.

[0209] In some embodiments, as shown in FIG15 , the third sub-fan-out line 303 includes a third portion 3031 and a fourth portion 3032 ; the third portion 3031 includes a first sub-segment 501 , a second sub-segment 502 , and a third sub-segment 503 ;

[0210] The fourth portion 3032 includes a portion extending along the first direction Y; and the length of the fourth portion 3032 gradually decreases in a direction away from the second fan-out line 202 .

[0211] In the display substrate provided by the embodiment of the present disclosure, multiple fourth portions are arranged along the second direction X, and the length of the fourth portions gradually decreases in the direction away from the second fan-out line. Accordingly, a first sub-segment whose extension direction intersects both the first direction and the second direction is connected to the fourth portion, and the length of the orthographic projection of the first sub-segment on the base substrate gradually decreases in the direction away from the second fan-out line. The length changes of the first sub-segment and the fourth portion match each other, which is conducive to the rational use of wiring space and avoids increasing the size of the fan-out area.

[0212] In some embodiments, as shown in FIG15 , the second sub-fan-out line 302 further includes a fourteenth sub-segment 514 ; the fourteenth sub-segment 514 extends along the first direction Y;

[0213] In the direction away from the second fan-out line 202 , the length of the fourteenth sub-segment 514 gradually increases.

[0214] In the display substrate provided by the embodiment of the present disclosure, a plurality of fourteenth sub-segments are arranged along the second direction X, and the length of the fourteenth sub-segment gradually increases in a direction away from the second fan-out line. Correspondingly, the third sub-segment extending along the second direction is connected to the fourteenth sub-segment, and the length of the positive projection of the third sub-segment on the base substrate gradually increases in the negative direction of the first direction Y. Thus, the length changes of the third sub-segment and the fourteenth sub-segment match each other, which is conducive to the rational use of wiring space and avoids increasing the size of the fan-out area.

[0215] In some embodiments, as shown in FIG15 , at least part of the first fan-out line 201 further includes an eighth sub-segment 508 , a ninth sub-segment 509 , and a tenth sub-segment 510 sequentially arranged in the first direction Y; the eighth sub-segment 508 and the tenth sub-segment 510 extend along the first direction Y;

[0216] At least the fourth portion 3032 includes an eighth subsegment 508 , a ninth subsegment 509 , and a tenth subsegment 510 ;

[0217] The angle between the extension direction of the ninth sub-segment 509 and the second direction X, and the angle between the second directions X are both greater than 0;

[0218] One end of the eighth sub-segment 508 facing away from the ninth sub-segment 509 is electrically connected to the first sub-segment 501 , and one end of the tenth sub-segment 510 facing away from the ninth sub-segment 509 is electrically connected to the binding electrode 9 ;

[0219] In two adjacent fourth portions 3032 , the orthographic projections of the two ninth sub-segments 509 on the substrate 1 have approximately overlapping areas, the orthographic projections of the two eighth sub-segments 508 on the substrate 1 do not overlap, and the orthographic projections of the two tenth sub-segments 510 on the substrate 1 do not overlap.

[0220] It should be noted that the orthographic projections of the two sub-segments on the substrate have a roughly overlapping area, which means that the distance between the edges of the orthographic projections of the two sub-segments on the substrate is less than the error range, and the orthographic projections of the two sub-segments on the substrate can be regarded as having an overlapping area.

[0221] It should be noted that, compared to the case where sub-segments extend along the first direction Y, sub-segments extending in a direction that intersects the first direction Y are advantageously configured to reduce the size of the fan-out area in the first direction Y. However, arranging multiple sub-segments whose extension directions intersect the first direction Y sequentially in the second direction X occupies a larger wiring space, resulting in an increase in the size of the fan-out area in the second direction X. In the display substrate provided by the present embodiment, the ninth sub-segments in adjacent third sub-fan-out lines have substantially overlapping areas, which is advantageously configured to save wiring space.

[0222] In some embodiments, as shown in FIG. 15 , in the first fan-out line 201 , the extending direction of the first sub-segment 501 is the same as the extending direction of the ninth sub-segment 509 .

[0223] In some embodiments, as shown in Figures 4, 12, and 15, the first sub-segment 501, the second sub-segment 502, and the third sub-segment 503 are arranged in sequence in a direction away from the second fan-out line 202 (the negative direction X- of the second direction X in the figures), that is, the third sub-fan-out line extends in a direction away from the second fan-out line, so that the space of the fan-out area can be fully utilized.

[0224] In some embodiments, as shown in Figures 4, 12, and 15, in adjacent third sub-fan-out lines 303, the orthographic projections of the two first sub-segments 501 on the substrate 1 have a roughly overlapping area, the orthographic projections of the two second sub-segments 502 on the substrate 1 have a roughly overlapping area, and the orthographic projections of the two third sub-segments 503 on the substrate 1 have a roughly overlapping area.

[0225] In the display substrate provided by the disclosed embodiments, the extension directions of the first, second, and third subsegments all intersect the first direction. Furthermore, within adjacent third sub-fan-out lines, the first subsegments, second subsegments, and third subsegments all have substantially overlapping areas, which helps save wiring space. Taking the eight first fan-out lines 201 shown in Figures 4, 12, and 15 as an example, in the first direction Y, the eight first subsegments 501, the eight second subsegments 502, and the eight third subsegments 503 each only require the wiring space of four traces, thus avoiding an increase in the size of the fan-out area in the first direction Y.

[0226] In some embodiments, as shown in FIG4 and FIG12 , the first sub-fan-out line 301 includes: a fifth sub-segment 505 , a sixth sub-segment 506 , and a seventh sub-segment 507 arranged in sequence in the first direction Y; the fifth sub-segment 505 and the seventh sub-segment 507 extend along the first direction Y;

[0227] The angle between the extension direction of the sixth sub-segment 506 and the second direction X, and the angle between the second directions X are both greater than 0;

[0228] One end of the fifth sub-segment 505 facing away from the sixth sub-segment 506 is electrically connected to the signal line 10 , and one end of the seventh sub-segment 507 facing away from the sixth sub-segment 506 is electrically connected to the second sub-fan-out line 302 ;

[0229] In two adjacent first sub-fan-out lines 301 , the orthographic projections of the two sixth sub-segments 506 on the base substrate 1 have approximately overlapping areas, the orthographic projections of the two fifth sub-segments 505 on the base substrate 1 do not overlap each other; and the orthographic projections of the two seventh sub-segments 507 on the base substrate 1 do not overlap each other.

[0230] In the display substrate provided by the embodiment of the present disclosure, in adjacent first sub-fan-out lines, sixth sub-segments whose extension directions intersect with the first direction Y have substantially overlapping areas, which is beneficial for saving wiring space.

[0231] In some embodiments, as shown in FIG15 , the first sub-fan-out line 301 includes a fifth sub-segment 505 , two sixth sub-segments 506 , an eleventh sub-segment 511 , and a seventh sub-segment 507 ;

[0232] In the first direction Y, the fifth sub-segment 505, the sixth sub-segment 506, the eleventh sub-segment 511, the sixth sub-segment 506, and the seventh sub-segment 507 are arranged in sequence;

[0233] The first portion 3011 includes a partial area of ​​the fifth sub-segment 505, the sixth sub-segment 506, and the eleventh sub-segment 511 arranged in sequence. The second portion 3012 includes a partial area of ​​the eleventh sub-segment 511, the sixth sub-segment 506, and the seventh sub-segment 507 arranged in sequence. The fifth sub-segment 505, the eleventh sub-segment 511, and the seventh sub-segment 507 extend along the first direction Y.

[0234] The angle between the extension direction of the sixth sub-segment 506 and the second direction X, and the angle between the second directions X are both greater than 0;

[0235] One end of the fifth sub-segment 505 facing away from the sixth sub-segment 506 is electrically connected to the signal line 10; one end of the seventh sub-segment 507 facing away from the sixth sub-segment 506 is electrically connected to the second sub-fan-out line 302;

[0236] In two adjacent first portions 3011 , the orthographic projections of the two sixth sub-segments 506 on the substrate 1 have a substantially overlapping area, the orthographic projections of the two fifth sub-segments 505 on the substrate 1 do not overlap, and the orthographic projections of the two eleventh sub-segments 511 on the substrate 1 do not overlap.

[0237] In two adjacent second portions 3012 , the orthographic projections of the two sixth sub-segments 506 on the substrate 1 have approximately overlapping areas, the orthographic projections of the two eleventh sub-segments 511 on the substrate 1 do not overlap, and the orthographic projections of the two seventh sub-segments 507 on the substrate 1 do not overlap.

[0238] In the display substrate provided by the embodiment of the present disclosure, in adjacent first sub-fan-out lines, sixth sub-segments whose extension directions intersect with the first direction Y have substantially overlapping areas, which is beneficial for saving wiring space.

[0239] In some embodiments, as shown in FIG. 4 , FIG. 12 , and FIG. 15 , the extension direction of the sixth sub-segment 506 is the same as the extension direction of the first sub-segment 501 .

[0240] In a specific implementation, as shown in Figures 4, 12, and 15, the second fan-out line 202 includes a fifteenth sub-segment 515 extending in the same direction as the sixth sub-segment 506 of the first sub-fan-out line 301, and the fifteenth sub-segment 515 of the second fan-out line 202 adjacent to the first fan-out line 201 is adjacent to the first sub-segment 501; the sixth sub-segment 506 extends in the same direction as the first sub-segment 501, and the corresponding fifteenth sub-segment 515 extends in the same direction as the first sub-segment 501, which is conducive to the rational use of wiring space.

[0241] In some embodiments, as shown in FIG4 , FIG12 , and FIG15 , among the plurality of first fan-out lines 201 sequentially arranged in a direction away from the second fan-out line 202 , the lengths of the second sub-fan-out lines 302 gradually increase;

[0242] At least part of the second sub-fan-out line 302 includes: a twelfth sub-segment 512;

[0243] The included angle between the extension direction of the twelfth sub-segment 512 and the second direction X, and the included angle between the second directions X are both greater than 0.

[0244] In the display substrate provided by the embodiment of the present disclosure, the second sub-fan-out line includes a twelfth sub-segment, and the extension direction of the twelfth sub-segment intersects with both the first direction and the second direction. By setting the second sub-fan-out line to reduce the resistance of the first fan-out line, it is possible to avoid excessively increasing the size of the fan-out area in the first direction, which is beneficial to saving wiring space.

[0245] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel. As shown in FIG17 , the display panel includes a display substrate 20 provided in an embodiment of the present disclosure.

[0246] The display panel provided by the embodiment of the present disclosure includes the above-mentioned display substrate provided by the embodiment of the present disclosure. The first fan-out line located in the fan-out area includes a first sub-fan-out line, a second sub-fan-out line, and a third sub-fan-out line. The resistivity of the second sub-fan-out line is at least less than the resistivity of the first conductive layer and the second conductive layer, that is, the resistivity of the second sub-fan-out line is relatively low. Compared with the prior art where half of the fan-out line is the first line and half is the second line, the provision of the second sub-fan-out line can reduce the resistance of the fan-out line, thereby reducing the impedance of the fan-out line, which is beneficial for reducing the resistance difference between different fan-out lines and avoiding problems such as uneven charging or poor touch. In addition, the orthographic projections of any two adjacent first fan-out lines on the substrate have an overlapping area. The routing of the two first fan-out lines in the overlapping area are respectively the first routing and the second routing. That is, the routing of the two first fan-out lines in the overlapping area is located in different conductive layers. Even if there is overlap, no short circuit will occur, which is beneficial for saving wiring space.

[0247] In some embodiments, the display panel is a liquid crystal display panel, and the display substrate is an array substrate; as shown in Figure 17, the display panel also includes: an opposing substrate 21 arranged opposite to the display substrate 20, and a liquid crystal layer 22 located between the display substrate 20 and the opposing substrate 21.

[0248] An embodiment of the present disclosure provides a display device, as shown in FIG18 , which includes a display panel 23 provided by an embodiment of the present disclosure.

[0249] In some embodiments, the display panel is a liquid crystal display panel. As shown in FIG18 , the display device further includes a backlight module 24 ; and a display panel 23 located on the light-emitting side of the backlight module 24 .

[0250] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the aforementioned embodiments of the display substrate and display panel, and any repetitive details will not be repeated.

[0251] In summary, the display substrate, display panel, and display device provided by the embodiments of the present disclosure include a first fan-out line located in the fan-out area, including a first sub-fan-out line, a second sub-fan-out line, and a third sub-fan-out line. The resistivity of the second sub-fan-out line is at least less than the resistivity of one of the first conductive layer and the second conductive layer, that is, the resistivity of the second sub-fan-out line is relatively low. Compared with the prior art where half of the fan-out line is the first line and half is the second line, the provision of the second sub-fan-out line can reduce the resistance of the fan-out line, thereby reducing the impedance of the fan-out line, which is beneficial to reducing the resistance difference between different fan-out lines and avoiding problems such as uneven charging or poor touch. In addition, the orthographic projections of any two adjacent first fan-out lines on the substrate have an overlapping area, and the routing of the two first fan-out lines in the overlapping area are the first routing and the second routing, respectively. That is, the routing of the two first fan-out lines in the overlapping area is located in different conductive layers. Even if there is overlap, no short circuit will occur, which is beneficial to saving wiring space.

[0252] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0253] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display substrate, wherein, The display substrate includes: A substrate substrate, including: a display area, and a fan-out area located on one side of the display area in a first direction; A plurality of fan-out lines arranged in sequence in a second direction in the fan-out area; the second direction intersects the first direction; the plurality of fan-out lines includes: a plurality of first fan-out lines; in the extending direction of each first fan-out line, it includes: a first sub-fan-out line, a second sub-fan-out line, and a third sub-fan-out line; in the same first fan-out line, at least one of the first sub-fan-out line and the third sub-fan-out line includes a first trace, and at least one of the other of the first sub-fan-out line and the third sub-fan-out line includes a second trace, the first trace is located in a first conductive layer, and the second trace is located in a second conductive layer; in the orthographic projection of the substrate substrate, any two adjacent first fan-out lines have an overlapping area, and in the overlapping area, one of the first fan-out lines includes the first trace and the other first fan-out line includes the second trace; the resistivity of the second sub-fan-out line is at least less than the resistivity of at least one of the first conductive layer and the second conductive layer.

2. The display substrate according to claim 1, wherein, The resistivity of the second conductive layer is less than the resistivity of the first conductive layer, and the second sub-fan-out line is located in the second conductive layer; The orthographic projections of the second sub-fan-out lines of different first fan-out lines on the substrate substrate do not overlap with each other.

3. The display substrate according to claim 1 or 2, wherein In the direction from the display area to the fan-out area, the first sub-fan-out line, the second sub-fan-out line, and the third sub-fan-out line are electrically connected in sequence.

4. The display substrate according to claim 3, wherein, The fan-out area further includes a bonding area; The display substrate further includes: a plurality of bonding electrodes located in the bonding area, and a plurality of signal lines extending from the display area to the fan-out area; One end of the first sub-fan-out line far from the third sub-fan-out line is electrically connected to the signal line, and one end of the third sub-fan-out line far from the first sub-fan-out line is electrically connected to the bonding electrode; The length of the third sub-fan-out line is greater than the length of the first sub-fan-out line.

5. The display substrate according to claim 4, wherein, In each first fan-out line, the first sub-fan-out line includes one of the first trace and the second trace, and the third sub-fan-out line includes the other of the first trace and the second trace; Among the plurality of first sub-fan-out lines, in the second direction, the first trace and the second trace are alternately arranged; Among the plurality of third sub-fan-out lines, in the second direction, the first trace and the second trace are alternately arranged; The first sub-fan-out line including the first trace and / or the third sub-fan-out line including the first trace further includes: a third trace connected in parallel with the first trace; The third trace is located in a third conductive layer.

6. The display substrate according to claim 5, wherein, The second conductive layer is located on the side of the first conductive layer away from the substrate substrate, and the third conductive layer is located between the first conductive layer and the substrate substrate.

7. The display substrate according to claim 6, wherein, The display substrate further includes: A plurality of insulating layers, including a first insulating layer located between the first conductive layer and the second conductive layer and a second insulating layer located between the first conductive layer and the third conductive layer; Multiple first vias; the first vias penetrate through the first insulating layer, the first trace, and the second insulating layer; the second sub-fan-out line or the second trace is electrically connected to the first trace and the third trace through the first vias.

8. The display substrate according to claim 7, wherein, The orthographic projection of the third trace on the substrate substantially overlaps with the orthographic projections of the first trace and the first vias on the substrate.

9. The display substrate according to claim 4, wherein, The first sub-fan-out line includes a first part and a second part located in different conductive layers and electrically connected; the third sub-fan-out line includes a third part and a fourth part located in different conductive layers and electrically connected; One of the first part and the second part includes the first trace, and the other of the first part and the second part includes the second trace; Among multiple first parts, in the second direction, the first trace and the second trace are alternately arranged; among multiple second parts, in the second direction, the first trace and the second trace are alternately arranged; One of the third part and the fourth part includes the first trace, and the other of the third part and the fourth part includes the second trace; among multiple third parts, in the second direction, the first trace and the second trace are alternately arranged; among multiple fourth parts, in the second direction, the first trace and the second trace are alternately arranged.

10. The display substrate according to any one of claims 1 to 9, wherein, The multiple fan-out lines further include: multiple second fan-out lines; in the second direction, multiple first fan-out lines are at least on one side of the multiple second fan-out lines; the length of the second fan-out line is less than the length of the first fan-out line; The second fan-out line includes a fourth sub-fan-out line and a fifth sub-fan-out line that are electrically connected in sequence in the direction from the display area to the fan-out area; in each second fan-out line, one of the fourth sub-fan-out line and the fifth sub-fan-out line is the first trace, and the other of the fourth sub-fan-out line and the fifth sub-fan-out line is the second trace.

11. The display substrate according to claim 10, wherein, Among multiple first sub-fan-out lines and multiple fourth sub-fan-out lines, in the second direction, the first trace and the second trace are alternately arranged; the orthographic projections of the first trace and the second trace located in adjacent two first sub-fan-out lines on the substrate have a substantially overlapping area; Among multiple third sub-fan-out lines and multiple fifth sub-fan-out lines, in the second direction, the first trace and the second trace are alternately arranged; the orthographic projections of the first trace and the second trace located in adjacent two third sub-fan-out lines on the substrate have a substantially overlapping area.

12. The display substrate according to claim 10 or 11, wherein, In the direction away from the second fan-out line, the lengths of multiple first fan-out lines gradually increase.

13. The display substrate according to claim 12, wherein, Each fan-out line is divided into multiple sub-segments in its extending direction; the extending directions of adjacent two sub-segments are different; The multiple sub-segments included in the first sub-fan-out line are arranged in sequence in the direction from the display area to the fan-out area, and the multiple sub-segments included in the second sub-fan-out line are arranged in sequence in the direction from the display area to the fan-out area; The third sub-fan-out line includes: a first sub-segment, a second sub-segment, and a third sub-segment; the first sub-segment is located on the side of the bonding area facing the display area, and one end of the first sub-segment far from the second sub-segment is electrically connected to the bonding electrode; the second sub-segment is located on the side of the first sub-segment far from the display area, and the third sub-segment is located on the side of the second sub-segment far from the display area.

14. The display substrate according to claim 13, wherein, The extending direction of the first sub-segment intersects with the extending direction of the second sub-segment, the included angles between the extending direction of the first sub-segment, the extending direction of the second sub-segment and the first direction are greater than 0, and the included angles between the extending direction of the first sub-segment, the extending direction of the second sub-segment and the second direction are greater than 0; The third sub-segment extends along the second direction; In the direction away from the second fan-out line, the length of the orthographic projection of the first sub-segment on the substrate gradually decreases; in the direction from the display area to the fan-out area, the length of the orthographic projection of the third sub-segment on the substrate gradually increases.

15. The display substrate according to claim 14, wherein, Among adjacent third sub-fan-out lines, the orthographic projections of the two first sub-segments on the substrate have a substantially overlapping area, the orthographic projections of the two second sub-segments on the substrate have a substantially overlapping area, and the orthographic projections of the two third sub-segments on the substrate have a substantially overlapping area.

16. The display substrate according to claim 14 or 15, wherein In each first fan-out line, the first sub-fan-out line includes one of the first trace and the second trace, and the third sub-fan-out line includes the other of the first trace and the second trace; the third sub-fan-out line further includes a fourth sub-segment located between the first sub-segment and the bonding area; the fourth sub-segment extends along the first direction; In the direction away from the second fan-out line, the length of the fourth sub-segment gradually decreases; The fourth sub-segments of adjacent two third sub-fan-out lines are non-overlapping in the orthographic projection on the substrate.

17. The display substrate according to claim 16, wherein, The first sub-fan-out line includes: a fifth sub-segment, a sixth sub-segment, and a seventh sub-segment arranged in sequence in the first direction; the fifth sub-segment and the seventh sub-segment extend along the first direction; The included angles between the extending direction of the sixth sub-segment and the second direction are both greater than 0; One end of the fifth sub-segment facing away from the sixth sub-segment is electrically connected to the signal line, and one end of the seventh sub-segment facing away from the sixth sub-segment is electrically connected to the second sub-fan-out line; Among adjacent two first sub-fan-out lines, the orthographic projections of the two sixth sub-segments on the substrate have a substantially overlapping area, the orthographic projections of the two fifth sub-segments on the substrate do not overlap; the orthographic projections of the two seventh sub-segments on the substrate do not overlap; In the first fan-out line, the extending direction of the sixth sub-segment is the same as the extending direction of the first sub-segment.

18. The display substrate according to claim 14 or 15, wherein The third sub-fan-out line includes a third part and a fourth part; At least part of the first fan-out line further includes an eighth sub-segment, a ninth sub-segment, and a tenth sub-segment arranged in sequence in the first direction; the eighth sub-segment and the tenth sub-segment extend along the first direction; The third portion includes the first sub-segment, the second sub-segment and the third sub-segment, and at least part of the fourth portion of the first fan-out line includes: the eighth sub-segment, the ninth sub-segment and the tenth sub-segment; The angle between the extension direction of the ninth sub-segment and the second direction, and the angle between the second directions are both greater than 0; One end of the eighth subsegment facing away from the ninth subsegment is electrically connected to the first subsegment, and one end of the tenth subsegment facing away from the ninth subsegment is electrically connected to the binding electrode; In two adjacent fourth portions, the orthographic projections of the two ninth sub-segments on the substrate have substantially overlapping areas, the orthographic projections of the two eighth sub-segments on the substrate do not overlap each other, and the orthographic projections of the two tenth sub-segments on the substrate do not overlap each other; In the first fan-out line, an extending direction of the first sub-segment is the same as an extending direction of the ninth sub-segment.

19. The display substrate according to claim 18, wherein, The first sub-fan-out line includes a first part and a second part; the first sub-fan-out line includes: a fifth sub-segment, two sixth sub-segments, an eleventh sub-segment, and a seventh sub-segment; In the first direction, the fifth subsegment, the sixth subsegment, the eleventh subsegment, the sixth subsegment, and the seventh subsegment are arranged in sequence; the first portion includes a partial area of ​​the fifth subsegment, the sixth subsegment, and the eleventh subsegment arranged in sequence, and the second portion includes a partial area of ​​the eleventh subsegment, the sixth subsegment, and the seventh subsegment arranged in sequence; The fifth sub-segment, the eleventh sub-segment, and the seventh sub-segment extend along the first direction; The angle between the extension direction of the sixth sub-segment and the second direction, and the angle between the second directions are both greater than 0; One end of the fifth sub-segment away from the sixth sub-segment is electrically connected to the signal line, and one end of the seventh sub-segment away from the sixth sub-segment is electrically connected to the second sub-fan-out line; In two adjacent first portions, the orthographic projections of the two sixth sub-segments on the substrate substrate have a substantially overlapping area, the orthographic projections of the two fifth sub-segments on the substrate substrate do not overlap each other, and the orthographic projections of the two eleventh sub-segments on the substrate substrate do not overlap each other; in two adjacent second portions, the orthographic projections of the two sixth sub-segments on the substrate substrate have a substantially overlapping area, the orthographic projections of the two eleventh sub-segments on the substrate substrate do not overlap each other, and the orthographic projections of the two seventh sub-segments on the substrate substrate do not overlap each other; In the first fan-out line, an extending direction of the sixth sub-segment is the same as an extending direction of the first sub-segment.

20. The display substrate according to any one of claims 13 to 19, wherein, Among the plurality of first fan-out lines sequentially arranged in a direction away from the second fan-out line, the lengths of the second sub-fan-out lines gradually increase; At least part of the second sub-fan-out line includes: a twelfth sub-segment; The angle between the extension direction of the twelfth sub-segment and the second direction, the angle between the extension direction of the twelfth sub-segment and the second direction The angles between them are all greater than 0.

21. The display substrate according to any one of claims 1 to 20, wherein, The display substrate further comprises: A plurality of thin film transistors are located in the display area; the first conductive layer further includes a gate electrode of the thin film transistor, and the second conductive layer further includes a source electrode and a drain electrode of the thin film transistor.

22. The display substrate according to any one of claims 1 to 20, wherein, The display substrate further includes: a plurality of thin film transistors located in the display area; a plurality of light emitting devices located on a side of the thin film transistors facing away from the display panel in the display area; the light emitting devices include an anode, a light emitting functional layer, and a cathode which are stacked; a plurality of connection electrodes located between the drain electrodes of the thin film transistors and the anodes in the display area, and the anodes are electrically connected to the drain electrodes through the connection electrodes; the first conductive layer further includes the gate electrodes of the thin film transistors; the second conductive layer includes: the source electrodes and the drain electrodes of the thin film transistors; or, the second conductive layer includes the connection electrodes.

23. The display substrate according to claim 21 or 22, wherein, The display substrate further includes: a plurality of light shielding portions located between the thin film transistors and the substrate in the display area; the first fan-out line further includes a third trace, and the third trace is disposed on the same layer as the light shielding portion.

24. A display panel, wherein, The display panel includes the display substrate according to any one of claims 1 to 23.

25. A display device, wherein, The display device includes the display panel according to claim 24.

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