Broadcast circuit of fuse array, broadcast method of fuse array and memory device

Abstract

The present disclosure provides a broadcast circuit of a fuse array, a broadcast method of a fuse array and a memory device. The broadcast circuit of the fuse array comprises: a broadcast address detector, configured to receive a broadcast fuse address count to generate N enable signals; and N sub-broadcast circuits, each sub-broadcast circuit comprising: a gating circuit which is connected to the fuse array and the broadcast address detector and is configured to: receive an enable signal, a broadcast clock signal, and broadcast data, and output a gated broadcast clock signal and gated broadcast data when the enable signal is effective; and a broadcast bus and a latch circuit, the broadcast bus being connected to the gating circuit and the latch circuit, and the broadcast bus being configured to: transmit the gated broadcast clock signal and the gated broadcast data to the latch circuit. The broadcast circuit of the fuse array of the present disclosure can reduce the winding length of the broadcast bus, and reduce the risk of mismatch of the broadcast data and the broadcast clock signal.

Description

Broadcast circuit of fuse array, broadcast method of fuse array and memory device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 25, 2023, with application number 202311804385.2 and application name “Broadcasting Circuit of Fuse Array and Broadcasting Method of Fuse Array”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor technology, and more particularly to a broadcast circuit of a fuse array, a broadcast method of a fuse array, and a memory device. Background Art

[0003] A memory device may include a memory array and a fuse array. The fuse array can store repair information or other operational information related to the memory array. After the memory device is powered on, fuse broadcasting is required to transmit the data stored in the fuse array to the various local registers of the memory device via a broadcast circuit. However, due to the relatively scattered locations of the local registers in the memory device, the fuse broadcasting process is prone to mismatches between the broadcast data and the broadcast clock signal, resulting in errors in the data ultimately transmitted to the local registers. Therefore, improving the reliability of fuse broadcasting has become a pressing issue.

[0004] Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a broadcast circuit for a fuse array, a broadcast method for a fuse array, and a memory device to solve at least one problem in the prior art.

[0006] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0007] In a first aspect, an embodiment of the present disclosure provides a broadcast circuit of a fuse array, comprising:

[0008] The broadcast address detector is configured to: receive a broadcast fuse address and count and generate N enable signals; wherein N is a positive integer greater than 1;

[0009] N sub-broadcast circuits; each of the sub-broadcast circuits includes:

[0010] a gating circuit connected to the fuse array and the broadcast address detector and configured to: receive the enable signal, the broadcast clock signal, and the broadcast data, and output the gated broadcast clock signal and the gated broadcast data when the enable signal is valid;

[0011] A broadcast bus and a latch circuit, wherein the broadcast bus is connected to the gating circuit and the latch circuit; the broadcast bus is configured to transmit the gated broadcast clock signal and the gated broadcast data to the latch circuit.

[0012] In an optional embodiment, the broadcast circuit of the fuse array further includes:

[0013] a broadcast clock signal generating circuit configured to: generate the broadcast clock signal in response to a fuse broadcast command;

[0014] The broadcast address counting circuit is configured to receive the broadcast clock signal and generate the broadcast fuse address count; the fuse array is configured to receive the broadcast fuse address count and output the broadcast data.

[0015] In an optional implementation, the broadcast address detector is specifically configured to:

[0016] receiving the broadcast fuse address and counting the number of fuses that have been broadcast;

[0017] The broadcasted fuse number is compared with a preset number in a preset list to generate the N enable signals; the preset list includes the N preset numbers; at most one enable signal among the N enable signals is valid.

[0018] In an optional implementation, the gate control circuit includes:

[0019] a clock gating circuit configured to: perform a logic operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal;

[0020] The data gating circuit is configured to perform a logic operation on the enable signal and the broadcast data to generate the gated broadcast data.

[0021] In an optional embodiment, the clock gating circuit and the data gating circuit both include a NAND gate and a NOT gate; the output of the NAND gate is connected to the input of the NOT gate; wherein the NAND gate of the clock gating circuit is configured to: receive the enable signal and the broadcast clock signal, and output an intermediate broadcast clock signal;

[0022] The NOT gate of the clock gating circuit is configured to: receive the intermediate broadcast clock signal and output the gated broadcast clock signal;

[0023] The NAND gate of the data gating circuit is configured to: receive the enable signal and the broadcast data, and output intermediate broadcast data;

[0024] The NOT gate of the data gating circuit is configured to receive the intermediate broadcast data and output the gated broadcast data.

[0025] In an optional embodiment, the latch circuit includes M flip-flops and M latches; the control terminal of each latch is connected to the output terminal of one of the flip-flops; M is a positive integer greater than 1; wherein the M flip-flops are configured to: receive the gated broadcast clock signal and an enable signal, and output M selection control signals when the enable signal is valid; at most one selection control signal among the M selection control signals is valid;

[0026] The latch is configured to receive the selection control signal and the gated broadcast data, and latch and output the gated broadcast data when the selection control signal is valid.

[0027] In an optional embodiment, the M flip-flops are connected in series; a first flip-flop among the M flip-flops includes:

[0028] The first data input terminal is configured to: receive a ground voltage;

[0029] A first clock input terminal is configured to: receive the gated broadcast clock signal;

[0030] The setting end is configured to: receive the enable signal;

[0031] The triggers other than the first trigger among the M triggers include:

[0032] A second data input terminal is connected to the output terminal of the previous trigger;

[0033] A second clock input terminal is configured to: receive the gated broadcast clock signal;

[0034] The reset terminal is configured to receive the enable signal.

[0035] In a second aspect, an embodiment of the present disclosure provides a method for broadcasting a fuse array, comprising:

[0036] The broadcast address detector receives the broadcast fuse address and counts to generate N enable signals; wherein N is a positive integer greater than 1;

[0037] The gating circuit of one of the N sub-broadcasting circuits receives the enable signal, the broadcast clock signal and the broadcast data, and outputs the gated broadcast clock signal and the gated broadcast data when the enable signal is valid;

[0038] The broadcast bus of the one sub-broadcast circuit transmits the gated broadcast clock signal and the gated broadcast data to a latch circuit.

[0039] In an optional implementation, the broadcast address detector receives the broadcast fuse address and counts and generates N enable signals, including:

[0040] The broadcast address detector receives the broadcast fuse address and counts and generates the number of fuses that have been broadcast;

[0041] The broadcasted fuse number is compared with a preset number in a preset list to generate the N enable signals; the preset list includes the N preset numbers; at most one enable signal among the N enable signals is valid.

[0042] In an optional embodiment, the gating circuit of one of the N sub-broadcast circuits receives the enable signal, the broadcast clock signal, and the broadcast data, and outputs the gated broadcast clock signal and the gated broadcast data when the enable signal is valid, comprising:

[0043] The clock gating circuit performs a logic operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal;

[0044] The data gating circuit performs the logic operation on the enable signal and the broadcast data to generate the gated broadcast data.

[0045] In an optional implementation, the clock gating circuit performs a logic operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal, including:

[0046] The NAND gate of the clock gating circuit receives the enable signal and the broadcast clock signal, and outputs an intermediate broadcast clock signal;

[0047] The NOT gate of the clock gating circuit receives the intermediate broadcast clock signal and outputs the gated broadcast clock signal;

[0048] The data gating circuit performs the logic operation on the enable signal and the broadcast data to generate the gated broadcast data, including:

[0049] The NAND gate of the data gating circuit receives the enable signal and the broadcast data, and outputs the intermediate broadcast data;

[0050] The NOT gate of the data gating circuit receives the intermediate broadcast data and outputs the gated broadcast data.

[0051] In an optional implementation, the fuse array broadcasting method further includes:

[0052] The M flip-flops in the latch circuit receive the gated broadcast clock signal and an enable signal, and output M selection control signals when the enable signal is valid; at most one selection control signal among the M selection control signals is valid; and M is a positive integer greater than 1;

[0053] The latch in the latch circuit receives the selection control signal and the gated broadcast data, and latches and outputs the gated broadcast data when the selection control signal is valid.

[0054] In a third aspect, an embodiment of the present disclosure provides a memory device comprising: a memory array, a fuse array, and a broadcast circuit as described in any one of the first aspects, wherein the memory array is configured to store data, the fuse array is configured to store repair information related to the memory array, and the broadcast circuit is configured to broadcast the fuse array after the memory device is powered on, and transmit the repair information stored in the fuse array to each local register of the memory device through the broadcast circuit.

[0055] In the technical solution provided by the present disclosure, a broadcast address detector can generate N enable signals, each of the N sub-broadcast circuits can receive an enable signal, a gating circuit in the sub-broadcast circuit can output gated broadcast data and a gated broadcast clock signal when the enable signal is valid, a broadcast bus in the sub-broadcast circuit can transmit the gated broadcast data and the gated broadcast clock signal to a latch circuit, and the latch circuit can receive the gated broadcast data when the enable signal is valid. At most one enable signal among the N enable signals is valid, so that the broadcast of the fuse array can be completed through the N sub-broadcast circuits respectively. The length of the broadcast bus in the N sub-broadcast circuits is less than the length of a single broadcast bus that needs to pass through all local registers. That is, through the broadcast circuit of the fuse array provided by the present disclosure, the winding length of the broadcast bus can be reduced, and the risk of mismatch between the broadcast data and the broadcast clock signal during the broadcast process of the fuse array can be reduced, thereby improving the reliability of the fuse array broadcast. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] FIG1 is a schematic diagram of a broadcast circuit of a fuse array provided in an embodiment of the present disclosure;

[0057] FIG2 is a schematic diagram of the composition of a gate control circuit provided in an embodiment of the present disclosure;

[0058] FIG3 is a circuit diagram of a gate control circuit provided in an embodiment of the present disclosure;

[0059] FIG4 is a circuit diagram of a latch circuit provided in an embodiment of the present disclosure;

[0060] FIG5 is a first schematic diagram of the arrangement of the broadcast circuit of the fuse array provided in an embodiment of the present disclosure;

[0061] FIG6 is a second schematic diagram of the arrangement of the broadcast circuit of the fuse array provided in an embodiment of the present disclosure;

[0062] FIG7 is a flow chart of a method for broadcasting a fuse array according to an embodiment of the present disclosure;

[0063] FIG8 is a schematic diagram showing the composition of a memory device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0065] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0066] In the drawings, like reference numerals refer to like elements throughout.

[0067] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0068] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0069] A memory device may include a memory array and a fuse array, wherein the memory array is configured to store user data, and the fuse array is configured to store repair information related to the memory array, such as row repair information, column repair information, and other operational information. After the memory device is powered on, fuse broadcasting is required to transmit the data stored in the fuse array to the various local registers of the memory device via a broadcast circuit, so that the memory device can read the data stored in the fuse array when performing operations such as reads and writes. However, since the local registers in the memory device are relatively dispersed, the broadcast bus needs to pass through all the local registers, resulting in a long routing length for the broadcast bus. This makes it easy for the broadcast data and the broadcast clock signal to mismatch during the fuse broadcasting process, resulting in errors in the data ultimately transmitted to the local registers, and reducing the reliability of the fuse broadcasting.

[0070] Therefore, how to improve the reliability of fuse broadcasting has become an urgent problem to be solved. In this regard, the present disclosure proposes the following implementation methods.

[0071] The present disclosure provides a broadcast circuit of a fuse array, comprising: a broadcast address detector, configured to receive a broadcast fuse address count and generate N enable signals; N is a positive integer greater than 1; N sub-broadcast circuits; each sub-broadcast circuit comprises: a gating circuit, connected to the fuse array and the broadcast address detector, and configured to receive an enable signal, a broadcast clock signal and broadcast data, and output a gated broadcast clock signal and gated broadcast data when the enable signal is valid; a broadcast bus and a latch circuit, the broadcast bus being connected to the gating circuit and the latch circuit; the broadcast bus being configured to transmit the gated broadcast clock signal and the gated broadcast data to the latch circuit.

[0072] In the embodiment of the present disclosure, the broadcast circuit of the fuse array includes N sub-broadcast circuits, and the data stored in the fuse array can be broadcasted via the N sub-broadcast circuits. Below, the broadcast circuit of the fuse array provided by the present disclosure will be described in detail using N equal to 2 as an example.

[0073] Figure 1 is a schematic diagram of the broadcast circuit of the fuse array provided in an embodiment of the present disclosure. As shown in Figure 1, the broadcast circuit of the fuse array includes: a broadcast address detector 101 and two sub-broadcast circuits, each sub-broadcast circuit includes a gating circuit, a broadcast bus and a latch circuit, wherein the first sub-broadcast circuit 200 includes a gating circuit 201, a broadcast bus 202 and a latch circuit 203, and the second sub-broadcast circuit 300 includes a gating circuit 301, a broadcast bus 302 and a latch circuit 303.

[0074] In some embodiments, the broadcast circuit of the fuse array further includes a broadcast address counting circuit 102 and a broadcast clock signal generating circuit 103. The broadcast circuit of the fuse array can be enabled in response to a fuse broadcast command, the broadcast clock signal generating circuit 103 can generate a broadcast clock signal, and the broadcast address counting circuit 102 can receive the broadcast clock signal and generate a broadcast fuse address count based on the broadcast clock signal.

[0075] In some specific examples, the fuse array 100 may include multiple areas, each area includes multiple array-arranged fuse storage units, and the broadcast address counting circuit 102 may send multiple groups of broadcast fuse address counts to the fuse array 100 and the broadcast address detector 101 in sequence. A group of broadcast fuse address counts may include an area count, a row address count, and a column address count, and correspond to a fuse storage unit in the fuse array 100. After receiving the broadcast fuse address count, the fuse array 100 may output data stored in a fuse storage unit corresponding to the broadcast fuse address count. The data output by the fuse array 100 is the broadcast data.

[0076] In some embodiments, the broadcast address detector 101 is specifically configured to: receive a broadcast fuse address count to generate a broadcast fuse number; and compare the broadcast fuse number with a preset number in a preset list to generate N enable signals.

[0077] In an embodiment of the present disclosure, the broadcast progress of the fuse array can be controlled by a broadcast address detector 101. The broadcast address detector 101 may include a preset list, and the preset list includes N preset numbers. Taking N as 2 as an example, the number of fuses that can be broadcast by the first sub-broadcast circuit 200 is X, and the number of fuses that can be broadcast by the second sub-broadcast circuit 300 is Y, then the preset list may include two preset numbers, the first preset number may be X, and the second preset number may be X+Y. The broadcast address detector 101 can receive the broadcast fuse address count to generate the number of fuses that have been broadcast, and compare the number of fuses that have been broadcast with the first preset number and the second preset number. The broadcast address detector 101 can generate an enable signal 1 and an enable signal 2 based on the comparison result of the number of fuses that have been broadcast with the preset number. The first sub-broadcast circuit 200 can receive the enable signal 1, and the second sub-broadcast circuit 300 can receive the enable signal 2. Specifically, when the number of fuses that have been broadcast is less than X, the enable signal 1 is valid and the enable signal 2 is invalid, and the broadcast data can be broadcast through the first sub-broadcast circuit 200; when the number of fuses that have been broadcast is greater than or equal to X and less than X+Y, the enable signal 1 is invalid and the enable signal 2 is valid, and the broadcast data can be broadcast through the second sub-broadcast circuit 300; when the number of fuses that have been broadcast is equal to X+Y, both the enable signal 1 and the enable signal 2 are invalid, and the broadcast of the fuse array is completed.

[0078] It should be noted that in the embodiment of the present disclosure, a valid signal means that the signal is at a first logic level, and an invalid signal means that the signal is at a second logic level. The first logic level can be a high level relative to the second logic level, and the second logic level can be a low level relative to the first logic level.

[0079] In some embodiments, the broadcast clock signal generated by the broadcast clock signal generating circuit 103 can also serve as the clock signal for the fuse array 100 to output broadcast data, and the broadcast clock signal and the broadcast data can be output synchronously and can be transmitted to the latch circuit via the gating circuit and the broadcast bus in the sub-broadcast circuit.

[0080] In the embodiment of the present disclosure, the gating circuits in N sub-broadcast circuits may have the same circuit structure. Below, the composition and circuit structure of the gating circuit will be described taking the gating circuit 201 in the first sub-broadcast circuit 200 as an example.

[0081] In some embodiments, Figure 2 is a schematic diagram of the composition of the gating circuit provided in an embodiment of the present disclosure. As shown in Figure 2, the gating circuit 201 includes: a clock gating circuit 2011, configured to: perform logical operations on the enable signal 1 and the broadcast clock signal to generate a gated broadcast clock signal; a data gating circuit 2012, configured to: perform logical operations on the enable signal 1 and the broadcast data to generate gated broadcast data.

[0082] In a specific example, Figure 3 is a circuit diagram of the gating circuit provided by an embodiment of the present disclosure. With reference to Figures 1, 2 and 3, the clock gating circuit 2011 and the data gating circuit 2012 both include a NAND gate and a NOT gate, and the output end of the NAND gate is connected to the input end of the NAND gate; wherein, the NAND gate 2013 of the clock gating circuit 2011 is configured to: receive an enable signal 1 and a broadcast clock signal, and output an intermediate broadcast clock signal; the NOT gate 2014 of the clock gating circuit 2011 is configured to: receive an intermediate broadcast clock signal, and output a gated broadcast clock signal; the NAND gate 2015 of the data gating circuit 2012 is configured to: receive an enable signal 1 and broadcast data, and output intermediate broadcast data; the NOT gate 2016 of the data gating circuit 2012 is configured to: receive intermediate broadcast data, and output gated broadcast data.

[0083] In an embodiment of the present disclosure, a gating circuit in a sub-broadcast circuit receives an enable signal, and the N enable signals generated by the broadcast address detector are output to the N sub-broadcast circuits respectively. Only when the enable signal received by the gating circuit is valid, the gating circuit will output the gated broadcast clock signal and the gated broadcast data. At most only one enable signal among the N enable signals is valid, so that the data stored in the fuse array can be broadcast through different sub-broadcast circuits respectively.

[0084] In some embodiments, the broadcast bus may include a data bus and a clock bus, the data bus may be configured to transmit gated broadcast data to the latch circuit, and the clock bus may be configured to transmit a gated broadcast clock signal to the latch circuit.

[0085] In some embodiments, FIG4 is a circuit diagram of a latch circuit provided by an embodiment of the present disclosure. Referring to FIG1 and FIG4 , the latch circuit 203 in the first sub-broadcast circuit 200 is taken as an example to illustrate the latch circuit in the broadcast circuit provided by the present disclosure.

[0086] In some embodiments, as shown in FIG4 , the latch circuit 203 includes M flip-flops and M latches, and the control terminal of each latch is connected to the output terminal of a flip-flop; M is a positive integer greater than 1. Here, taking M equal to 3 as an example, the latch circuit 203 includes three flip-flops and three latches, wherein the output terminal Q of the first flip-flop 2031 is connected to the control terminal Lat of the first latch 2034, and is connected to the inverting control terminal LatN of the first latch 2034 through an inverter; the output terminal Q of the second flip-flop 2032 is connected to the control terminal Lat of the second latch 2035, and is connected to the inverting control terminal LatN of the second latch 2035 through an inverter; the output terminal Q of the third flip-flop 2033 is connected to the control terminal Lat of the third latch 2036, and is connected to the inverting control terminal LatN of the third latch 2036 through an inverter.

[0087] In an embodiment of the present disclosure, the M triggers in the latch circuit are configured to: receive a gated broadcast clock signal and an enable signal, and output M selection control signals when the enable signal is valid, and at most one selection control signal among the M selection control signals is valid; the latch is configured to: receive the selection control signal and the gated broadcast data, and latch and output the gated broadcast data when the selection control signal is valid.

[0088] In some specific examples, with continued reference to FIG. 4 , the three flip-flops in latch circuit 203 are configured to receive a gated broadcast clock signal and an enable signal 1, and to output three selection control signals when the enable signal 1 is valid. The three flip-flops are connected in series. The first flip-flop 2031 includes a first data input terminal D configured to receive a ground voltage VSS; a first clock input terminal CK configured to receive the gated broadcast clock signal; and a set terminal SN configured to receive the enable signal 1. Each of the three flip-flops, except the first flip-flop 2031, includes a second data input terminal D connected to the output terminal Q of the preceding flip-flop. For example, the data input terminal D of the second flip-flop 2032 is connected to the output terminal Q of the first flip-flop 2031, and the data input terminal D of the third flip-flop 2033 is connected to the output terminal Q of the second flip-flop 2032; a second clock input terminal CK configured to receive the gated broadcast clock signal; and a reset terminal RN configured to receive the enable signal 1.

[0089] In the embodiment of the present disclosure, when the enable signal 1 is valid, the first trigger 2031 can generate the selection control signal 1, the second trigger 2032 can generate the selection control signal 2, and the third trigger 2033 can generate the selection control signal 3. At the same time, at most only one selection control signal is valid, that is, at the same time, at most only one latch is enabled, and the data input terminal D of the enabled latch receives the gated broadcast data, latches it, and outputs one bit of gated broadcast data from the output terminal Q.

[0090] In some specific examples, the latch circuit 303 in the second sub-broadcast circuit 300 may have a circuit structure similar to that of the latch circuit 203 in the first sub-broadcast circuit 200 .

[0091] It should be noted that the above embodiment takes M equal to 3 as an example, but the present disclosure is not limited thereto. In other embodiments, M can be any positive integer greater than 1, such as 4, 7, 16, 32, etc.

[0092] In an embodiment of the present disclosure, a broadcast address detector can generate N enable signals, each of the N sub-broadcast circuits can receive an enable signal, a gating circuit in the sub-broadcast circuit can output gated broadcast data and a gated broadcast clock signal when the enable signal is valid, a broadcast bus in the sub-broadcast circuit can transmit the gated broadcast data and the gated broadcast clock signal to a latch circuit, and the latch circuit can latch and output the gated broadcast data when the enable signal is valid. At most one of the N enable signals is valid, so that the broadcast of the fuse array can be completed through the N sub-broadcast circuits respectively. The length of the broadcast bus in the N sub-broadcast circuits is less than the length of a single broadcast bus that needs to pass through all local registers. That is, the broadcast circuit of the fuse array provided by the present disclosure can reduce the winding length of the broadcast bus, reduce the risk of mismatch between the broadcast data and the broadcast clock signal during the broadcast process of the fuse array, and thus improve the reliability of the fuse array broadcast.

[0093] In some embodiments, multiple latches and multiple triggers in the latch circuit can constitute local registers, such as a local register of a row decoder, a local register of a column decoder, and a test mode register, wherein the local register of the row decoder can store row repair information in the fuse array, the local register of the column decoder can store column repair information in the fuse array, and the test mode register can store relevant parameter information in the fuse array for memory device testing.

[0094] In some specific examples, FIG5 is a schematic diagram illustrating the layout of a broadcast circuit for a fuse array provided in an embodiment of the present disclosure. For ease of observation, the broadcast bus 401 in the first sub-broadcast circuit and the broadcast bus 402 in the second sub-broadcast circuit are shown in perspective. As shown in FIG5 , the fuse array 400 is located in a peripheral circuit on one side of a memory bank 407 in the Y direction. The broadcast circuit of the fuse array includes two sub-broadcast circuits connected to the fuse array 400. The broadcast bus 401 in the first sub-broadcast circuit extends along the X direction and is connected to a plurality of test mode registers 403 located on one side of the fuse array 400 and arranged along the X direction. The broadcast bus 402 in the second sub-broadcast circuit includes a portion extending along the X direction and a portion extending along the Y direction, and is connected to a plurality of registers located between the two memory banks 407. The plurality of registers may include a plurality of local registers 404 for column decoders, a plurality of local registers 405 for row decoders, and a plurality of test mode registers 406. In this example, compared with a single broadcast bus that needs to be connected to multiple test mode registers 403 located on one side of the fuse array 400 and multiple registers located between two storage bodies 407, the broadcast bus 401 in the first sub-broadcast circuit and the broadcast bus 402 in the second sub-broadcast circuit are shorter. At the same time, one of the broadcast bus 401 in the first sub-broadcast circuit and the broadcast bus 402 in the second sub-broadcast circuit is enabled, thereby reducing the winding length of the broadcast bus for transmitting broadcast data and broadcast clock signals, reducing the risk of mismatch between broadcast data and broadcast clock signals during the broadcast process, and improving the reliability of fuse array broadcasting.

[0095] In some specific examples, FIG6 is a schematic diagram of the broadcast circuit layout of a fuse array provided in an embodiment of the present disclosure. For ease of observation, the broadcast bus 501 in the first sub-broadcast circuit and the broadcast bus 502 in the second sub-broadcast circuit are shown in perspective. As shown in FIG6 , the fuse array 500 is located in the peripheral circuit between two memory banks 510. The broadcast circuit of the fuse array includes two sub-broadcast circuits connected to the fuse array 500. The broadcast bus 501 in the first sub-broadcast circuit includes a portion extending along the X direction and a portion extending along the Y direction, and is connected to a test mode register 503 and multiple registers located on one side of the fuse array 500. The multiple registers may include multiple local registers 504 for column decoders, multiple local registers 505 for row decoders, and a test mode register 506. The broadcast bus 502 in the second sub-broadcast circuit also includes a portion extending along the X direction and a portion extending along the Y direction, and is connected to the test mode register 503 and multiple registers located on the other side of the fuse array 500. The multiple registers may include a test mode register 507. In this example, compared with a single broadcast bus that needs to be connected to all registers located on both sides of the fuse array 500, the broadcast bus 501 in the first sub-broadcast circuit and the broadcast bus 502 in the second sub-broadcast circuit are shorter. At the same time, one of the broadcast bus 501 in the first sub-broadcast circuit and the broadcast bus 502 in the second sub-broadcast circuit is enabled, thereby reducing the winding length of the broadcast bus for transmitting broadcast data and broadcast clock signals, reducing the risk of mismatch between broadcast data and broadcast clock signals during the broadcast process, and improving the reliability of fuse array broadcasting.

[0096] It should be noted that some registers in Figures 5 and 6 are not directly connected to the broadcast bus, and the branches connecting these registers to the broadcast bus are omitted. Furthermore, Figures 5 and 6 omit structures such as the broadcast address detector in the broadcast circuit and the gating circuit in the sub-broadcast circuit. Their functions and circuit structures can be found in the descriptions of Figures 1, 2, and 3 in the previous embodiments.

[0097] It should be noted that the above embodiment takes N equal to 2 as an example, but the present disclosure is not limited to this. In other embodiments, N can be any positive integer greater than 1, such as 3, 4, 5, etc. For example, when N is equal to 4, the broadcast circuit of the fuse array may include four sub-broadcast circuits, each of which includes a gating circuit, a broadcast bus and a latch circuit; the broadcast address detector can compare the number of fuses that have been broadcast with the four preset numbers in the preset list and generate four enable signals; the four sub-broadcast circuits respectively receive four enable signals, and at most one of the four enable signals is valid, that is, at most one of the four gating circuits can output gated broadcast data and gated broadcast clock signals, so that the data in the fuse array can be broadcast respectively through the four sub-broadcast circuits. When the number of local registers remains unchanged, the length of each broadcast bus can be further reduced, thereby further reducing the risk of mismatch between the broadcast data and the broadcast clock signal during the broadcast process, and improving the reliability of the fuse array broadcast.

[0098] Based on a concept similar to the above-mentioned broadcast circuit of the fuse array, the present disclosure further provides a method for broadcasting a fuse array. FIG7 is a flow chart of the method for broadcasting a fuse array provided in an embodiment of the present disclosure. As shown in FIG7 , the method for broadcasting a fuse array includes the following steps.

[0099] Step S10: The broadcast address detector receives the broadcast fuse address and counts to generate N enable signals; N is a positive integer greater than 1.

[0100] Step S20: The gating circuit of one of the N sub-broadcasting circuits receives an enable signal, a broadcast clock signal and broadcast data, and outputs a gated broadcast clock signal and gated broadcast data when the enable signal is valid.

[0101] Step S30: The broadcast bus of a sub-broadcast circuit transmits the gated broadcast clock signal and the gated broadcast data to a latch circuit.

[0102] In some embodiments, referring to FIG1 and FIG7 , the specific process of step S10 includes: the broadcast address detector 101 receives the broadcast fuse address count and generates the number of fuses broadcasted; the broadcast fuse number is compared with a preset number in a preset list to generate N enable signals; the preset list includes N preset numbers; at most one enable signal among the N enable signals is valid. Here, taking N equal to 2 as an example, the broadcast address detector 101 can generate enable signal 1 and enable signal 2.

[0103] In some embodiments, in combination with FIG2 and FIG7 , taking the first sub-broadcast circuit 200 performing the broadcast of the fuse array as an example, the specific process of step S20 includes: the clock gating circuit 2011 performs a logical operation on the enable signal 1 and the broadcast clock signal to generate a gated broadcast clock signal; the data gating circuit 2012 performs a logical operation on the enable signal 1 and the broadcast data to generate a gated broadcast data.

[0104] In some embodiments, in combination with reference to Figures 3 and 7, taking the broadcast of the fuse array by the first sub-broadcast circuit 200 as an example, the specific process of step S20 may include: the NAND gate 2013 of the clock gating circuit receives the enable signal 1 and the broadcast clock signal, and outputs the intermediate broadcast clock signal; the NOT gate 2014 of the clock gating circuit receives the intermediate broadcast clock signal, and outputs the gated broadcast clock signal; the NAND gate 2015 of the data gating circuit receives the enable signal 1 and the broadcast data, and outputs the intermediate broadcast data; the NOT gate 2016 of the data gating circuit receives the intermediate broadcast data, and outputs the gated broadcast data.

[0105] In some embodiments, in combination with reference to Figures 4 and 7, taking the broadcasting of the fuse array by the first sub-broadcast circuit 200 as an example, the broadcasting method of the fuse array also includes: M triggers in the latch circuit 203 receive a gated broadcast clock signal and an enable signal, and output M selection control signals when the enable signal is valid; at most one selection control signal among the M selection control signals is valid; M is a positive integer greater than 1; the latch in the latch circuit 203 receives the selection control signal and the gated broadcast data, and latches and outputs the gated broadcast data when the selection control signal is valid.

[0106] In some specific examples, in combination with reference to Figures 1 and 7, before step S10, the broadcast circuit of the fuse array can be enabled in response to the fuse broadcast command, and the broadcast method of the fuse array also includes: the broadcast clock signal generating circuit 103 generates a broadcast clock signal, the broadcast address counting circuit 102 receives the broadcast clock signal, and generates a broadcast fuse address count based on the broadcast clock signal.

[0107] In some specific examples, with reference to FIG1 and FIG7 , the specific process of step S10 may include: the broadcast address detector 101 receives the broadcast fuse address count to generate the number of fuses that have been broadcast; and compares the number of fuses that have been broadcast with preset numbers in a preset list to generate enable signal 1 and enable signal 2. Here, the preset list may include two preset numbers, the first preset number may be the number X of fuses that can be broadcast by the first sub-broadcast circuit 200, and the second preset number may be the sum X+Y of the number of fuses that can be broadcast by the first sub-broadcast circuit 200 and the number of fuses that can be broadcast by the second sub-broadcast circuit 300.

[0108] In some specific examples, in combination with reference to Figures 1 and 7, the broadcasting method of the fuse array may include: when the number of fuses that have been broadcast is less than X, the enable signal 1 is valid and the enable signal 2 is invalid, and the broadcast data can be broadcast through the first sub-broadcast circuit 200, including: step S20, the gating circuit 201 in the first sub-broadcast circuit 200 receives the enable signal 1, the broadcast clock signal and the broadcast data, and outputs the first gated broadcast clock signal and the first gated broadcast data; step S30, the broadcast bus 202 in the first sub-broadcast circuit 200 transmits the first gated broadcast clock signal and the first gated broadcast data to the latch circuit 203; the latch circuit 203 receives the enable signal 1, the first gated broadcast clock signal and the first gated broadcast data, latches and outputs the first gated broadcast data.

[0109] In some specific examples, in combination with reference to Figures 1 and 7, the broadcasting method of the fuse array may include: when the number of fuses that have been broadcast is greater than or equal to X and less than X+Y, the enable signal 1 is invalid, the enable signal 2 is valid, and the broadcast data can be broadcast through the second sub-broadcast circuit 300, including: step S20, the gating circuit 301 in the second sub-broadcast circuit 300 receives the enable signal 2, the broadcast clock signal and the broadcast data, and outputs the second gated broadcast clock signal and the second gated broadcast data; step S30, the broadcast bus 302 in the second sub-broadcast circuit 300 transmits the second gated broadcast clock signal and the second gated broadcast data to the latch circuit 303; the latch circuit 303 receives the enable signal 2, the second gated broadcast clock signal and the second gated broadcast data, latches and outputs the second gated broadcast data.

[0110] In some specific examples, the method for broadcasting the fuse array may include: when the number of fuses that have been broadcasted is equal to X+Y, both the enable signal 1 and the enable signal 2 are invalid, and the broadcasting of the fuse array is completed.

[0111] In an embodiment of the present disclosure, a broadcast address detector can generate N enable signals according to the broadcast progress, each of the N sub-broadcast circuits can receive an enable signal, a gating circuit in the sub-broadcast circuit can output gated broadcast data and a gated broadcast clock signal when the enable signal is valid, a broadcast bus in the sub-broadcast circuit can transmit the gated broadcast data and the gated broadcast clock signal to a latch circuit, and the latch circuit can latch and output the gated broadcast data when the enable signal is valid. At most one enable signal among the N enable signals is valid, so that the broadcast of the fuse array can be completed through the N sub-broadcast circuits respectively, and the length of the broadcast bus in the N sub-broadcast circuits is less than the length of a single broadcast bus that needs to pass through all local registers. That is, the broadcast method of the fuse array provided by the present disclosure can reduce the risk of mismatch between the broadcast data and the broadcast clock signal during the broadcast process of the fuse array, reduce the probability of errors in the broadcast data received by the local registers, and thus improve the reliability of the fuse array broadcast.

[0112] FIG8 is a schematic diagram illustrating the composition of a memory device according to an embodiment of the present disclosure. Referring to FIG8 , an embodiment of the present disclosure further provides a memory device 10 comprising a memory array 2000, a fuse array 100, and the broadcast circuit 3000 described in the above embodiments. The memory array 2000 is configured to store data, the fuse array 100 is configured to store repair information related to the memory array 2000, and the broadcast circuit 3000 is configured to, after the memory device 10 is powered on, broadcast the repair information stored in the fuse array 100 to various local registers of the memory device 10 via the broadcast circuit 3000. The memory device 10 can be a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM). The fuse cells in the fuse array 100 can be either fuse structures or antifuse structures.

[0113] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0114] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0115] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A broadcast circuit of a fuse array (100), characterized in that, Comprising: A broadcast address detector (101), configured to: receive a broadcast fuse address count and generate N enable signals; wherein N is a positive integer greater than 1; N sub-broadcast circuits (200, 300); each of the sub-broadcast circuits comprising: A gating circuit (201, 301), connected to the fuse array (100) and the broadcast address detector (101), and configured to: receive one of the enable signals, a broadcast clock signal, and broadcast data, and output a gated broadcast clock signal and gated broadcast data when the enable signal is valid; A broadcast bus (202, 302) and a latch circuit (203, 303), the broadcast bus (202, 302) being connected to the gating circuit (201, 301) and the latch circuit (203, 303); the broadcast bus (202, 302) being configured to: transmit the gated broadcast clock signal and the gated broadcast data to the latch circuit (203, 303).

2. The broadcast circuit of the fuse array (100) according to claim 1, characterized in that, The broadcast circuit of the fuse array (100) further comprises: A broadcast clock signal generation circuit (103), configured to: generate the broadcast clock signal in response to a fuse broadcast command; A broadcast address counting circuit (102), configured to: receive the broadcast clock signal and generate the broadcast fuse address count; the fuse array (100) being configured to: receive the broadcast fuse address count and output the broadcast data.

3. The broadcast circuit of the fuse array according to claim 1, wherein, The broadcast address detector (101) is specifically configured to: Receive the broadcast fuse address count to generate the number of fuses that have been broadcast; Compare the number of fuses that have been broadcast with a preset number in a preset list to generate the N enable signals; the preset list includes N preset numbers; at most one of the N enable signals is valid.

4. The broadcast circuit of the fuse array (100) according to claim 1, characterized in that, The gating circuit (201, 301) comprises: A clock gating circuit (2011), configured to: perform a logical operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal; A data gating circuit (2012), configured to: perform a logical operation on the enable signal and the broadcast data to generate the gated broadcast data.

5. The broadcast circuit of the fuse array (100) according to claim 4, characterized in that, Both the clock gating circuit (2011) and the data gating circuit (2012) include a NAND gate and a NOT gate; the output terminal of the NAND gate is connected to the input terminal of the NOT gate; wherein, The NAND gate (2013) of the clock gating circuit (2011) is configured to: receive the enable signal and the broadcast clock signal and output an intermediate broadcast clock signal; The NOT gate (2014) of the clock gating circuit (2011) is configured to: receive the intermediate broadcast clock signal and output the gated broadcast clock signal; The NAND gate (2015) of the data gating circuit (2012) is configured to: receive the enable signal and the broadcast data and output intermediate broadcast data; The NOT gate (2016) of the data gating circuit (2012) is configured to: receive the intermediate broadcast data and output the gated broadcast data.

6. The broadcast circuit of the fuse array (100) according to claim 1, characterized in that, The latch circuit (203, 303) includes M flip-flops and M latches; the control terminal of each latch is connected to the output terminal of one flip-flop; M is a positive integer greater than 1; wherein, The M flip-flops are configured to: receive the gated broadcast clock signal and one of the enable signals, and output M selection control signals when the enable signal is valid; at most one of the M selection control signals is valid; The latches are configured to: receive the selection control signal and the gated broadcast data, and latch and output the gated broadcast data when the selection control signal is valid.

7. The broadcast circuit of the fuse array (100) according to claim 6, characterized in that, The M flip-flops are connected in series; The first flip-flop (2031) among the M flip-flops includes: A first data input terminal, configured to: receive a ground voltage; A first clock input terminal, configured to: receive the gated broadcast clock signal; A set terminal, configured to: receive the enable signal; The flip-flops (2032, 2033) among the M flip-flops other than the first flip-flop (2031) include: A second data input terminal, connected to the output terminal of the previous flip-flop; A second clock input terminal, configured to: receive the gated broadcast clock signal; A reset terminal, configured to: receive the enable signal.

8. The broadcast circuit of the fuse array (100) according to claim 1, characterized in that, The broadcast bus (202, 302) includes a data bus and a clock bus. The data bus is configured to transmit the gated broadcast data to the latch circuit (203, 303), and the clock bus is configured to transmit the gated broadcast clock signal to the latch circuit (203, 303).

9. A broadcast method for a fuse array (100), characterized in that, Includes: S10: The broadcast address detector (101) receives the broadcast fuse address count to generate N enable signals; N is a positive integer greater than 1; S20: The gating circuit (201, 301) of one of the N sub-broadcast circuits (200, 300) receives one of the enable signals, the broadcast clock signal, and the broadcast data, and outputs the gated broadcast clock signal and the gated broadcast data when the enable signal is valid; S30: The broadcast bus (202, 302) of the one sub-broadcast circuit transmits the gated broadcast clock signal and the gated broadcast data to one latch circuit (203, 303).

10. The broadcast method of the fuse array (100) according to claim 9, characterized in that, The broadcast address detector (101) receives the broadcast fuse address count to generate N enable signals, including: The broadcast address detector (101) receives the broadcast fuse address count to generate the number of fuses that have been broadcast; Compare the number of fuses that have been broadcast with the preset numbers in the preset list to generate the N enable signals; the preset list includes N preset numbers; at most one of the N enable signals is valid.

11. The broadcast method of the fuse array (100) according to claim 9, characterized in that, A gating circuit (201, 301) of one of the N sub-broadcast circuits (200, 300) receives one of the enable signals, a broadcast clock signal, and broadcast data, and outputs a gated broadcast clock signal and gated broadcast data when the enable signal is valid, including: A clock gating circuit (2011) performs a logical operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal; A data gating circuit (2012) performs the logical operation on the enable signal and the broadcast data to generate the gated broadcast data.

12. The broadcast method of the fuse array (100) according to claim 11, characterized in that, The clock gating circuit (2011) performs a logical operation on the enable signal and the broadcast clock signal to generate the gated broadcast clock signal, including: A NAND gate (2013) of the clock gating circuit (2011) receives the enable signal and the broadcast clock signal and outputs an intermediate broadcast clock signal; A NOT gate (2014) of the clock gating circuit (2011) receives the intermediate broadcast clock signal and outputs the gated broadcast clock signal; The data gating circuit (2012) performs the logical operation on the enable signal and the broadcast data to generate the gated broadcast data, including: A NAND gate (2015) of the data gating circuit (2012) receives the enable signal and the broadcast data and outputs intermediate broadcast data; A NOT gate (2016) of the data gating circuit (2012) receives the intermediate broadcast data and outputs the gated broadcast data.

13. The broadcast method of the fuse array (100) according to claim 9, characterized in that, The broadcast method of the fuse array (100) further includes: M flip-flops in the latch circuit (203, 303) receive the gated broadcast clock signal and one of the enable signals, and output M selection control signals when the enable signal is valid; at most one of the M selection control signals is valid; M is a positive integer greater than 1; Latches in the latch circuit (203, 303) receive the selection control signal and the gated broadcast data, and latch and output the gated broadcast data when the selection control signal is valid.

14. A memory device (10) includes: A storage array (2000), a fuse array (100), and a broadcast circuit (3000) as claimed in claims 1-8, wherein the storage array (2000) is configured to store data, the fuse array (100) is configured to store repair information related to the storage array (2000), and the broadcast circuit (3000) is configured to, after the memory device (10) is powered on, broadcast the fuse array (100) and transmit the repair information stored in the fuse array (100) to respective local registers of the memory device (10) through the broadcast circuit (3000).

Images