Silicon carbide insulated-gate bipolar transistor device and preparation method therefor

Abstract

A silicon carbide (SiC) insulated-gate bipolar transistor device and a preparation method therefor. The method comprises: forming a semiconductor layer (1); forming a gate trench (2) in the semiconductor layer (1); forming a gate dielectric layer (4) on the inner wall of the gate trench (2); forming a heterojunction trench (5) on one side of the gate trench (2); forming a polysilicon layer, wherein the polysilicon layer comprises gate polysilicon (6) located in the gate trench (2) and heterojunction polysilicon (7) located in the heterojunction trench (5), and a polysilicon-SiC heterojunction is formed at the junction of the heterojunction polysilicon (7) and the semiconductor layer (1); forming a protective layer (8) on the top surface of the gate polysilicon (6); forming an emitter metal layer (9) on the semiconductor layer (1); and forming a collector metal layer (10) on the back surface of the semiconductor layer (1).

Description

Silicon carbide insulated gate bipolar transistor device and preparation method thereof

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 202311800852.4, filed on December 25, 2023, entitled “A SiC IGBT device and its preparation method,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present invention belongs to the field of semiconductor technology and relates to a silicon carbide insulated gate bipolar transistor (SiC IGBT) device and a preparation method thereof. Background Art

[0004] Improving the performance of silicon carbide (SiC) insulated-gate bipolar transistors (IGBTs) involves trade-offs between various static characteristics, such as conduction and blocking characteristics. Prior art approaches improve forward conduction characteristics by enhancing the conductivity modulation effect within the IGBT. For example, by adding a Schottky contact to the top of the SiC IGBT, holes emitted from the collector accumulate in the Schottky contact, reducing on-resistance and on-voltage drop.

[0005] Thanks to the conductivity modulation effect, SiC IGBTs have a low on-state voltage drop. However, SiC IGBTs act as switches in circuits, so the device's switching characteristics also require attention. Due to the conductivity modulation effect, excess carriers exist within the SiC IGBT device. When the device transitions from the on state to the off state, these excess carriers must be extracted. This process results in a tail current during the device's turn-off, increasing turn-off time and losses. Improving the conductivity modulation effect further increases the carrier concentration within the device, exacerbating the tail current phenomenon during the turn-off process. Therefore, improving SiC IGBT device performance requires considering a compromise between forward conduction and switching characteristics.

[0006] Therefore, how to provide a SiC IGBT device and a preparation method thereof to reduce the forward conduction voltage drop while improving the turn-off characteristics has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0007] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art.

[0008] Summary of the Invention

[0009] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a silicon carbide insulated gate bipolar transistor (SiC IGBT) device and a preparation method thereof, so as to solve the problem that the prior art reduces the forward conduction voltage drop of the SiC IGBT device while causing degradation of the turn-off characteristics.

[0010] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a SiC IGBT device, comprising the following steps:

[0011] forming a semiconductor layer, wherein the material of the semiconductor layer includes SiC;

[0012] forming a gate trench in the semiconductor layer, wherein the gate trench opens from the top surface of the semiconductor layer and extends downward;

[0013] forming a gate dielectric layer on an inner wall of the gate trench;

[0014] forming a heterojunction trench on one side of the gate trench, the heterojunction trench opening from the top surface of the semiconductor layer and extending downward, one side surface of the heterojunction trench exposing the gate dielectric layer, and a bottom surface of the heterojunction trench being higher than a bottom surface of the gate trench;

[0015] forming a polysilicon layer, wherein the polysilicon layer includes gate polysilicon located in the gate trench and heterojunction polysilicon located in the heterojunction trench, and a polysilicon-SiC heterojunction is formed at a junction of the heterojunction polysilicon and the semiconductor layer;

[0016] forming a protective layer on the top surface of the gate polysilicon;

[0017] forming an emitter metal layer on the semiconductor layer, wherein the emitter metal layer covers the heterojunction polysilicon and the protective layer;

[0018] A collector metal layer is formed on the back side of the semiconductor layer.

[0019] In some embodiments, the semiconductor layer includes a P-type heavily doped SiC collector layer, an N-type lightly doped SiC buffer layer, an N-type doped SiC drift layer, an N-type doped charge storage layer, and a P-well, arranged in order from bottom to top. A P-type heavily doped contact region is provided in the first preset region of the upper surface layer of the P-well, and an N-type heavily doped contact region is provided in the second preset region. The side surface of the P-type heavily doped contact region is adjacent to the side surface of the N-type heavily doped contact region. The gate trench is located on one side of the N-type heavily doped contact region and is adjacent to the N-type heavily doped contact region. The bottom surface of the gate trench is located in the charge storage layer. The heterojunction trench is located on the side of the gate trench away from the N-type heavily doped contact region. The bottom surface of the heterojunction trench is located in the P-well. The emitter metal layer also covers the P-type heavily doped contact region and the N-type heavily doped contact region. The collector metal layer is located on the back side of the P-type heavily doped SiC collector layer.

[0020] In some embodiments, forming the semiconductor layer comprises the following steps:

[0021] Providing an N-type heavily doped SiC substrate, and epitaxially growing the P-type heavily doped SiC collector region layer on the N-type heavily doped SiC substrate;

[0022] Epitaxially growing the N-type lightly doped SiC buffer layer on the P-type heavily doped SiC collector region layer;

[0023] Epitaxially growing the N-type doped SiC drift layer on the N-type lightly doped SiC buffer layer;

[0024] Performing ion implantation on the upper surface layer of the N-type doped SiC drift layer to obtain the N-type doped charge storage layer;

[0025] Performing ion implantation on the upper surface layer of the N-type doped charge storage layer to obtain the P-well;

[0026] Ion implantation is performed on a first predetermined region and a second predetermined region of the upper surface layer of the P-well, respectively, to obtain the P-type heavily doped contact region and the N-type heavily doped contact region.

[0027] In some embodiments, before forming the collector metal layer on the back side of the semiconductor layer, the method further includes removing the N-type heavily doped SiC substrate; the collector metal layer is formed on the back side of the P-type heavily doped SiC collector region layer.

[0028] In some embodiments, the doping concentration of the P-type heavily doped SiC collector layer is in the range of 1×10 18 / cm 3 to 1×10 20 / cm 3, with a thickness of less than 5 microns. The doping concentration range of the N-type lightly doped SiC buffer layer is 1×10 15 / cm 3 to 1×10 16 / cm 3 , with a thickness of less than 3 microns. The doping concentration range of the N-type doped SiC drift layer is 1×10 14 / cm 3 to 1×10 15 / cm 3 , with a thickness of less than 200 microns. The doping concentration of the N-type doped charge storage layer is higher than the doping concentration of the N-type doped SiC drift layer, and the doping concentration range of the N-type doped charge storage layer is 1×10 15 / cm 3 to 1×10 16 / cm 3 , with a thickness of less than 3 microns. The doping concentration range of the P well is 1×10 16 / cm 3 to 1×10 18 / cm 3 , with a thickness of less than 5 microns. The doping concentration range of the P-type heavily doped contact region is 1×10 18 / cm 3 to 1×10 20 / cm 3 The doping concentration range of the N-type heavily doped contact region is 1×10 18 / cm 3 to 1×10 20 / cm 3 .

[0029] In some embodiments, the gate dielectric layer includes a thermal silicon oxide layer, and the thickness of the gate dielectric layer is in a range of 40-60 nanometers.

[0030] In some embodiments, the depth of the heterojunction trench is less than 2 microns.

[0031] In some embodiments, the protective layer includes a silicon oxide layer.

[0032] In some embodiments, the emitter metal layer includes one or more of a Ni layer, a Ti layer, and an Al layer, and the collector metal layer includes one or more of a Ti layer and an Al layer.

[0033] In some embodiments, forming a protective layer on the top surface of the gate polysilicon includes: depositing a silicon oxide layer on the semiconductor layer; and patterning the silicon oxide layer by photolithography and etching to obtain the protective layer.

[0034] In some embodiments, forming an emitter metal layer on the semiconductor layer includes forming the emitter metal layer on the semiconductor layer by sputtering.

[0035] In some embodiments, forming a collector metal layer on the back side of the semiconductor layer includes forming the collector metal layer on the back side of the semiconductor layer by sputtering.

[0036] In some embodiments, ion implantation is performed on the upper surface layer of the N-type doped SiC drift layer to obtain the N-type doped charge storage layer, including implanting N-type ions into the upper surface layer of the N-type doped SiC drift layer to obtain the N-type doped charge storage layer. Ion implantation is performed on the upper surface layer of the N-type doped charge storage layer to obtain the P-well, including implanting P-type ions into the upper surface layer of the N-type doped charge storage layer to obtain the P-well. Ion implantation is performed on a first preset region and a second preset region of the upper surface layer of the P-well to obtain the P-type heavily doped contact region and the N-type heavily doped contact region, including implanting P-type ions into the first preset region of the upper surface layer of the P-well to obtain the P-type heavily doped contact region, and implanting N-type ions into the second preset region of the upper surface layer of the P-well to obtain the N-type heavily doped contact region.

[0037] The present invention also provides a silicon carbide insulated gate bipolar transistor (SiC IGBT) device, comprising: a semiconductor layer, a gate trench, a gate dielectric layer, a heterojunction trench, a polysilicon layer, a protective layer, an emitter metal layer, and a collector metal layer.

[0038] The semiconductor layer is made of SiC.

[0039] The gate trench is located in the semiconductor layer, and the gate trench opens from the top surface of the semiconductor layer and extends downward.

[0040] The gate dielectric layer is located on the inner wall of the gate trench.

[0041] The heterojunction trench is located on one side of the gate trench, the heterojunction trench opens from the top surface of the semiconductor layer and extends downward, one side surface of the heterojunction trench exposes the gate dielectric layer, and the bottom surface of the heterojunction trench is higher than the bottom surface of the gate trench.

[0042] The polysilicon layer includes gate polysilicon located in the gate trench and heterojunction polysilicon located in the heterojunction trench, and a polysilicon-SiC heterojunction is formed at a junction of the heterojunction polysilicon and the semiconductor layer.

[0043] The protection layer is located on the top surface of the gate polysilicon.

[0044] The emitter metal layer is located on the semiconductor layer, and the emitter metal layer covers the heterojunction polysilicon and the protection layer.

[0045] The collector metal layer is located on the back side of the semiconductor layer.

[0046] In some embodiments, the semiconductor layer includes a P-type heavily doped SiC collector layer, an N-type lightly doped SiC buffer layer, an N-type doped SiC drift layer, an N-type doped charge storage layer, and a P-well, arranged in order from bottom to top. A P-type heavily doped contact region is provided in a first preset area of ​​the upper surface layer of the P-well, and an N-type heavily doped contact region is provided in a second preset area. The side surface of the P-type heavily doped contact region is adjacent to the side surface of the N-type heavily doped contact region. The gate trench is located on one side of the N-type heavily doped contact region and is adjacent to the N-type heavily doped contact region. The bottom surface of the gate trench is located in the charge storage layer. The heterojunction trench is located on the side of the gate trench away from the N-type heavily doped contact region. The bottom surface of the heterojunction trench is located in the P-well. The emitter metal layer also covers the P-type heavily doped contact region and the N-type heavily doped contact region. The collector metal layer is located on the back side of the P-type heavily doped SiC collector layer.

[0047] As described above, the SiC IGBT device and its preparation method of the present invention can achieve improved turn-off characteristics while reducing the forward conduction voltage drop of the device. Specifically, a heterojunction polysilicon is introduced into the front structure of the SiC IGBT device. The junction of the heterojunction polysilicon and the semiconductor layer forms a polysilicon-SiC heterojunction. Due to the large band gap width of the two, the energy band on the SiC side bends downward to form a large potential barrier. The downward-bent barrier inhibits holes from flowing out of the device through the emitter. In order to maintain electrical neutrality, the holes induce electrons, thereby enhancing the conductivity modulation effect and reducing the conduction voltage drop. At the same time, when the device is turned on and off, the drain voltage further increases, and the voltage is applied to the heterojunction, flattening the bent energy band. Since the valence band of polysilicon is higher than that of SiC, holes can flow into the polysilicon and eventually flow out of the device through the emitter, suppressing the formation of tail current and enabling the device to be quickly turned off. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] FIG1 is a process flow chart showing a method for manufacturing a silicon carbide insulated gate bipolar transistor (SiC IGBT) device according to the present invention.

[0049] FIG2 is a schematic diagram showing a structure of a SiC IGBT device after a P-type heavily doped SiC collector layer, an N-type lightly doped SiC buffer layer, and an N-type doped SiC drift layer are sequentially epitaxially grown on an N-type heavily doped SiC substrate according to the method for preparing the device of the present invention.

[0050] FIG3 is a schematic diagram showing another structure after an N-type doped charge storage layer is formed on the upper surface of the N-type doped SiC drift layer according to the method for preparing a SiC IGBT device of the present invention.

[0051] FIG4 is a schematic diagram showing another structure obtained after forming a P-well on the upper surface layer of the N-type doped charge storage layer in the method for manufacturing a SiC IGBT device according to the present invention.

[0052] FIG5 is a schematic diagram showing another structure obtained after forming a P-type heavily doped contact region on the upper surface layer of the P-well in the method for manufacturing a SiC IGBT device according to the present invention.

[0053] FIG6 is a schematic diagram showing a semiconductor layer after an N-type heavily doped contact region is formed on the upper surface layer of the P-well in the method for manufacturing a SiC IGBT device according to the present invention.

[0054] FIG. 7 is a schematic diagram showing a structure obtained after a gate trench is formed in a semiconductor layer according to the method for fabricating a SiC IGBT device of the present invention.

[0055] FIG8 is a schematic diagram showing another structure obtained after forming a gate dielectric layer on the inner wall of the gate trench according to the method for manufacturing a SiC IGBT device of the present invention.

[0056] FIG9 is a schematic diagram showing another structure obtained after forming a heterojunction trench on one side of the gate trench according to the method for manufacturing a SiC IGBT device of the present invention.

[0057] FIG. 10 is a schematic diagram showing another structure obtained after forming a polysilicon layer according to the method for manufacturing a SiC IGBT device of the present invention.

[0058] FIG11 shows the energy band diagram of a polysilicon-SiC heterojunction.

[0059] FIG. 12 is a schematic diagram showing a structure obtained after forming a protection layer on the top surface of gate polysilicon according to the method for manufacturing a SiC IGBT device of the present invention.

[0060] FIG. 13 is a schematic diagram showing another structure obtained after forming an emitter metal layer on a semiconductor layer according to the method for manufacturing a SiC IGBT device of the present invention.

[0061] FIG14 is a schematic diagram showing a SiC IGBT device obtained after forming a collector metal layer on the back side of a semiconductor layer according to the method for manufacturing a SiC IGBT device of the present invention.

[0062] Description of Reference Numerals

[0063] Steps S1-S8

[0064] 1 Semiconductor layer

[0065] 101 P-type heavily doped SiC collector layer

[0066] 102 N-type lightly doped SiC buffer layer

[0067] 103 N-type doped SiC drift layer

[0068] 104 N-type doped charge storage layer

[0069] 105 P-well

[0070] 106 P-type heavily doped contact region

[0071] 107 N-type heavily doped contact region

[0072] 2 Gate trench

[0073] 3 N-type heavily doped SiC substrate

[0074] 4 Gate dielectric layer

[0075] 5 Heterojunction trench

[0076] 6 Gate polysilicon

[0077] 7 Heterojunction Polysilicon

[0078] 8 protective layer

[0079] 9 Emitter metal layer

[0080] 10 Collector metal layer DETAILED DESCRIPTION

[0081] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0082] Please refer to Figures 1 to 14. It should be noted that the figures provided in the embodiments of this application are merely schematic illustrations of the basic concept of the present invention. Therefore, the figures only show components relevant to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0083] An embodiment of the present invention provides a method for fabricating a silicon carbide insulated gate bipolar transistor (SiC IGBT) device. FIG1 is a process flow chart of the method. As shown in FIG1 , the method includes the following steps S1-S8.

[0084] S1: forming a semiconductor layer 1, wherein the material of the semiconductor layer 1 includes SiC.

[0085] S2: forming a gate trench 2 in the semiconductor layer 1 , wherein the gate trench 2 opens from the top surface of the semiconductor layer 1 and extends downward.

[0086] S3 : forming a gate dielectric layer 4 on the inner wall of the gate trench 2 .

[0087] S4: forming a heterojunction trench 5 on one side of the gate trench 2, wherein the heterojunction trench 5 opens from the top surface of the semiconductor layer 1 and extends downward, and one side surface of the heterojunction trench 5 exposes the gate dielectric layer 4, and the bottom surface of the heterojunction trench 5 is higher than the bottom surface of the gate trench 2.

[0088] S5: forming a polysilicon layer, wherein the polysilicon layer includes a gate polysilicon 6 located in the gate trench 2 and a heterojunction polysilicon 7 located in the heterojunction trench 5 , wherein a polysilicon-SiC heterojunction is formed at a junction of the heterojunction polysilicon 7 and the semiconductor layer 1 .

[0089] S6 : forming a protection layer 8 on the top surface of the gate polysilicon 6 .

[0090] S7 : forming an emitter metal layer 9 on the semiconductor layer 1 , wherein the emitter metal layer 9 covers the heterojunction polysilicon 7 and the protection layer 8 .

[0091] S8: forming a collector metal layer 10 on the back side of the semiconductor layer 1 .

[0092] The specific implementation of each of the above steps is described in detail below with reference to the structural diagram.

[0093] First, please refer to FIG. 2 to FIG. 7 . In step S1 , a semiconductor layer 1 is formed. The material of the semiconductor layer 1 includes SiC.

[0094] As an example, the semiconductor layer 1 includes a P-type heavily doped SiC collector region layer 101, an N-type lightly doped SiC buffer layer 102, an N-type doped SiC drift layer 103, an N-type doped charge storage layer 104 and a P-well 105 arranged in sequence from bottom to top, and a first preset area of ​​the upper surface layer of the P-well 105 is provided with a P-type heavily doped contact area 106 and a second preset area is provided with an N-type heavily doped contact area 107, the side surface of the P-type heavily doped contact area 106 is adjacent to the side surface of the N-type heavily doped contact area 107, the gate trench 2 is located on one side of the N-type heavily doped contact area 107 and is adjacent to the N-type heavily doped contact area 107, and the bottom surface of the gate trench 2 is located in the charge storage layer 104.

[0095] It should be noted that in the above description, the terms "heavy doping," "doping," and "light doping" are relative concepts. For ion doping of the same conductivity type, the doping concentration corresponding to "heavy doping" is greater than the doping concentration corresponding to "doping," and the doping concentration corresponding to "doping" is greater than the doping concentration corresponding to "light doping." The specific doping concentration can be adjusted based on the performance requirements of the actual device and should not unduly limit the scope of protection of the present invention.

[0096] In some embodiments, the doping concentration of the P-type heavily doped SiC collector layer 101 is in the range of 1×10 18 / cm 3 to 1×10 20 / cm 3 , thickness is less than 5 microns; the doping concentration range of the N-type lightly doped SiC buffer layer 102 is 1×10 15 / cm 3 to 1×10 16 / cm 3 , thickness is less than 3 microns; the doping concentration range of the N-type doped SiC drift layer 103 is 1×10 14 / cm 3 to 1×10 15 / cm 3 , with a thickness of less than 200 microns; the doping concentration of the N-type doped charge storage layer 104 is higher than the doping concentration of the N-type doped SiC drift layer 103, and the doping concentration range of the N-type doped charge storage layer 104 is 1×10 15 / cm 3 to 1×1016 / cm 3 , thickness is less than 3 microns; the doping concentration range of the P well 105 is 1×10 16 / cm 3 to 1×10 18 / cm 3 , thickness is less than 5 microns; the doping concentration range of the P-type heavily doped contact region 106 is 1×10 18 / cm 3 to 1×10 20 / cm 3 The doping concentration range of the N-type heavily doped contact region 107 is 1×10 18 / cm 3 to 1×10 20 / cm 3 .

[0097] In some embodiments, forming the semiconductor layer 1 includes the following steps.

[0098] (1) As shown in FIG2 , an N-type heavily doped SiC substrate 3 is provided, the P-type heavily doped SiC collector region layer 101 is epitaxially grown on the N-type heavily doped SiC substrate 3, the N-type lightly doped SiC buffer layer 102 is epitaxially grown on the P-type heavily doped SiC collector region layer 101, and the N-type doped SiC drift layer 103 is epitaxially grown on the N-type lightly doped SiC buffer layer 102.

[0099] (2) As shown in FIG3 , N-type ions (including but not limited to phosphorus ions) are implanted into the upper surface layer of the N-type doped SiC drift layer 103 to obtain the N-type doped charge storage layer 104 .

[0100] (3) As shown in FIG. 4 , P-type ions (including but not limited to boron ions) are implanted into the upper surface layer of the N-type doped charge storage layer 104 to obtain the P-well 105 .

[0101] (4) As shown in FIG. 5 , P-type ion implantation is performed on a first predetermined region of the upper surface layer of the P-well 105 to obtain the P-type heavily doped contact region 106 .

[0102] (5) As shown in FIG6 , N-type ion implantation is performed on the second predetermined region of the upper surface layer of the P-well 105 to obtain the N-type heavily doped contact region 107 .

[0103] At this point, the semiconductor layer 1 located on the N-type heavily doped SiC substrate 3 is manufactured, wherein the N-type heavily doped SiC substrate 3 will be removed before the subsequent formation of the collector metal layer, so that the collector metal layer is formed on the back side of the P-type heavily doped SiC collector region layer 101.

[0104] Please refer to Figure 7 again. In step S2: dry etching, wet etching or other suitable methods are used to form a gate trench 2 in the semiconductor layer 1. The gate trench 2 opens from the top surface of the semiconductor layer 1 on the side of the N-type heavily doped contact region 107 away from the P-type heavily doped contact region 106 and extends downward into the charge storage layer 104.

[0105] Specifically, the width of the gate trench 2 and the specific position of the bottom surface of the gate trench 2 in the charge storage layer 104 can be adjusted according to the electrical requirements of the actual device, and the scope of protection of the present invention should not be excessively limited here.

[0106] Please refer to FIG. 8 again. In step S3 , a gate dielectric layer 4 is formed on the inner wall of the gate trench 2 .

[0107] As an example, a thermal oxidation method is used to form a thermal silicon oxide layer on the inner wall of the gate trench 2 to serve as the gate dielectric layer 4 . The thickness of the gate dielectric layer 4 is in the range of 40-60 nanometers.

[0108] Please refer to Figure 9 again. In step S4: a heterojunction trench 5 is formed on the side of the gate trench 2 away from the N-type heavily doped contact region 107. The heterojunction trench 5 opens from the top surface of the semiconductor layer 1 and extends downward. One side of the heterojunction trench 5 exposes the gate dielectric layer 4. The bottom surface of the heterojunction trench 5 is higher than the bottom surface of the gate trench 2.

[0109] As an example, the bottom surface of the heterojunction trench 5 is located in the P-well 105 , and the depth of the heterojunction trench 5 is less than 2 microns.

[0110] Please refer to Figure 10 again. In the step S5, a polysilicon layer is formed. The polysilicon layer includes a gate polysilicon 6 located in the gate trench 2 and a heterojunction polysilicon 7 located in the heterojunction trench 5. The junction between the heterojunction polysilicon 7 and the semiconductor layer 1 forms a polysilicon-SiC heterojunction.

[0111] Specifically, the present invention introduces the heterojunction polysilicon 7 into the front structure of the SiC IGBT device for the purpose of forming a polysilicon-SiC heterojunction. FIG11 shows an energy band diagram of the polysilicon-SiC heterojunction. As shown in FIG11, due to the large band gap between polysilicon and SiC, the energy band on the SiC side bends downward, forming a large potential barrier, as shown by the solid line in FIG11. The downward-bending potential barrier inhibits holes from flowing out of the device through the emitter. To maintain electrical neutrality, holes induce electrons, enhancing the conductivity modulation effect and reducing the on-state voltage drop. At the same time, when the device switches from on to off, the drain voltage further increases, and the voltage is applied to the polysilicon-SiC heterojunction, flattening the bent energy band, as shown by the dotted line in FIG11. Since the valence band of polysilicon is higher than that of SiC, holes can flow into the polysilicon and ultimately out of the device through the emitter, suppressing the formation of tail current and enabling the SiC IGBT device to be quickly turned off. That is, the solution of the present invention can achieve the goal of reducing the forward voltage drop of the device while improving the turn-off characteristics. The subsequent steps of the method for preparing the SiC IGBT device of the present invention will be described in detail below.

[0112] Please refer to FIG. 12 , in step S6 : a protection layer 8 is formed on the top surface of the gate polysilicon 6 .

[0113] As an example, the protective layer 8 may be a silicon oxide layer or other suitable material layer, and its thickness may be set according to actual needs, which is not specifically limited in the present invention.

[0114] As an example, a silicon oxide layer may be first deposited on the semiconductor layer 1 , and then photolithography and etching may be performed to pattern the silicon oxide layer to obtain the protective layer 8 to protect the gate polysilicon 6 .

[0115] Please refer to FIG. 13 . In step S7 , an emitter metal layer 9 is formed on the semiconductor layer 1 by sputtering or other suitable methods. The emitter metal layer 9 covers the heterojunction polysilicon 7 and the protective layer 8 .

[0116] Specifically, the emitter metal layer 9 also covers the P-type heavily doped contact region 106 and the N-type heavily doped contact region 107 to be electrically connected to the P-type heavily doped contact region 106 and the N-type heavily doped contact region 107 .

[0117] As an example, the emitter metal layer 9 includes but is not limited to one or more of a Ni layer, a Ti layer, and an Al layer.

[0118] Please refer to FIG. 14 , in step S8 , a collector metal layer 10 is formed on the back side of the semiconductor layer 1 by sputtering or other suitable methods.

[0119] As an example, before forming the collector metal layer 10, the N-type heavily doped SiC substrate 3 on the back side of the semiconductor layer 1 is removed by chemical mechanical polishing or other suitable methods, so that the collector metal layer 10 is formed on the back side of the P-type heavily doped SiC collector region layer 101.

[0120] As an example, the collector metal layer 10 includes but is not limited to one or more of a Ti layer and an Al layer.

[0121] Thus, a SiC IGBT device is manufactured. The preparation method of the SiC IGBT device of the present invention uses a simple method to introduce a polycrystalline silicon-SiC heterojunction on the front side of the device, which can reduce the forward conduction voltage drop of the device while improving the turn-off characteristics.

[0122] An embodiment of the present invention further provides a SiC IGBT device, which can be manufactured using the method for manufacturing the SiC IGBT device described in any of the above embodiments or other suitable methods.

[0123] As an example, FIG14 shows a schematic cross-sectional structure diagram of the SiC IGBT device in some embodiments. As shown in FIG14 , the SiC IGBT device includes a semiconductor layer 1, a gate trench 2, a gate dielectric layer 4, a heterojunction trench 5, a polysilicon layer, a protective layer 8, an emitter metal layer 9, and a collector metal layer 10. The semiconductor layer 1 is made of SiC. The gate trench 2 is located in the semiconductor layer 1 and opens from the top surface of the semiconductor layer 1 and extends downward. The gate dielectric layer 4 is located on the inner wall of the gate trench 2. The heterojunction trench 5 is located on one side of the gate trench 2 and opens from the top surface of the semiconductor layer 1 and extends downward. The gate dielectric layer 4 is exposed on one side of the heterojunction trench 5, and the bottom surface of the heterojunction trench 5 is higher than the bottom surface of the gate trench 2. The polysilicon layer includes gate polysilicon 6 located in the gate trench 2 and heterojunction polysilicon 7 located in the heterojunction trench 5. The junction between the heterojunction polysilicon 7 and the semiconductor layer 1 forms a polysilicon-SiC heterojunction. The protective layer 8 is located on the top surface of the gate polysilicon 6. The emitter metal layer 9 is located on the semiconductor layer 1 and covers the heterojunction polysilicon 7 and the protective layer 8. The collector metal layer 10 is located on the back side of the semiconductor layer 1.

[0124] As an example, the semiconductor layer 1 includes a P-type heavily doped SiC collector layer 101, an N-type lightly doped SiC buffer layer 102, an N-type doped SiC drift layer 103, an N-type doped charge storage layer 104 and a P-well 105, which are sequentially arranged from bottom to top. The first preset area of ​​the upper surface layer of the P-well 105 is provided with a P-type heavily doped contact area 106, and the second preset area is provided with an N-type heavily doped contact area 107. The side surface of the P-type heavily doped contact area 106 is adjacent to the side surface of the N-type heavily doped contact area 107. The gate trench 2 is located in the N-well. The gate trench 2 is located on one side of the N-type heavily doped contact region 107 and is adjacent to the N-type heavily doped contact region 107. The bottom of the gate trench 2 is located in the charge storage layer 104. The heterojunction trench 5 is located on the side of the gate trench 2 away from the N-type heavily doped contact region 107. The bottom of the heterojunction trench 5 is located in the P-well 105. The emitter metal layer 9 also covers the P-type heavily doped contact region 106 and the N-type heavily doped contact region 107. The collector metal layer 10 is located on the back side of the P-type heavily doped SiC collector region layer 101.

[0125] The SiC IGBT device of the present invention has a polycrystalline silicon-SiC heterojunction introduced on the front side, so it not only has a lower forward conduction voltage drop of the device, but also has better turn-off characteristics.

[0126] In summary, the SiC IGBT device of the present invention and its preparation method can achieve the improvement of the turn-off characteristics while reducing the forward conduction voltage drop of the device. In particular, a heterojunction polysilicon is introduced into the front structure of the SiC IGBT device. The junction of the heterojunction polysilicon and the semiconductor layer forms a polysilicon-SiC heterojunction. Due to the large band gap width of the two, the energy band on the SiC side bends downward to form a large potential barrier. The downward-bent potential barrier inhibits holes from flowing out of the device through the emitter. In order to maintain electrical neutrality, the holes induce electrons, thereby enhancing the conductivity modulation effect and reducing the conduction voltage drop. At the same time, when the device is turned on and off, the drain voltage rises further, the voltage is applied to the heterojunction, and the curved energy band becomes flat. Since the valence band of polysilicon is higher than the valence band of SiC, holes can flow into polysilicon and eventually flow out of the device through the emitter, suppressing the formation of tail current, and the device can be turned off quickly. Therefore, the present invention effectively overcomes the defects in the prior art and reduces the forward conduction voltage drop of the SiC IGBT device while improving the turn-off characteristics.

[0127] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for fabricating a silicon carbide insulated gate bipolar transistor (SiC IGBT) device, comprising: Forming a semiconductor layer, the material of the semiconductor layer including SiC; Forming gate trenches in the semiconductor layer, the gate trenches opening from the top surface of the semiconductor layer and extending downward; Forming a gate dielectric layer on the inner walls of the gate trenches; Forming heterojunction trenches on one side of the gate trenches, the heterojunction trenches opening from the top surface of the semiconductor layer and extending downward, one side surface of the heterojunction trenches exposing the gate dielectric layer, and the bottom surface of the heterojunction trenches being higher than the bottom surface of the gate trenches; Forming a polysilicon layer, the polysilicon layer including gate polysilicon located in the gate trenches and heterojunction polysilicon located in the heterojunction trenches, the junction between the heterojunction polysilicon and the semiconductor layer constituting a polysilicon-SiC heterojunction; Forming a protective layer on the top surface of the gate polysilicon; Forming an emitter metal layer on the semiconductor layer, the emitter metal layer covering the heterojunction polysilicon and the protective layer; Forming a collector metal layer on the back surface of the semiconductor layer.

2. The manufacturing method of the SiC IGBT device according to claim 1, characterized in that: The semiconductor layer includes a P-type heavily doped SiC collector region layer, an N-type lightly doped SiC buffer layer, an N-type doped SiC drift layer, an N-type doped charge storage layer, and a P-well, which are sequentially arranged from bottom to top, wherein: A first preset region on the upper surface layer of the P-well is provided with a P-type heavily doped contact region, and a second preset region is provided with an N-type heavily doped contact region, and the side surface of the P-type heavily doped contact region is adjacent to the side surface of the N-type heavily doped contact region; The gate trenches are located on one side of the N-type heavily doped contact region and are adjacent to the N-type heavily doped contact region, and the bottom surface of the gate trenches is located in the charge storage layer; The heterojunction trenches are located on the side of the gate trenches away from the N-type heavily doped contact region, and the bottom surface of the heterojunction trenches is located in the P-well; The emitter metal layer also covers the P-type heavily doped contact region and the N-type heavily doped contact region; The collector metal layer is located on the back surface of the P-type heavily doped SiC collector region layer.

3. The manufacturing method of the SiC IGBT device according to claim 1 or 2, characterized in that, Forming the semiconductor layer includes: Providing an N-type heavily doped SiC substrate, and epitaxially growing the P-type heavily doped SiC collector region layer on the N-type heavily doped SiC substrate; Epitaxially growing the N-type lightly doped SiC buffer layer on the P-type heavily doped SiC collector region layer; Epitaxially growing the N-type doped SiC drift layer on the N-type lightly doped SiC buffer layer; Performing ion implantation on the upper surface layer of the N-type doped SiC drift layer to obtain the N-type doped charge storage layer; Performing ion implantation on the upper surface layer of the N-type doped charge storage layer to obtain the P-well; Performing ion implantation on the first preset region and the second preset region on the upper surface layer of the P-well respectively to obtain the P-type heavily doped contact region and the N-type heavily doped contact region.

4. The manufacturing method of the SiC IGBT device according to any one of claims 1-3, characterized in that, Before forming the collector metal layer on the back surface of the semiconductor layer, the method further includes removing the N-type heavily doped SiC substrate; the collector metal layer is formed on the back surface of the P-type heavily doped SiC collector region layer.

5. The manufacturing method of the SiC IGBT device according to claim 2, wherein: The doping concentration range of the P-type heavily doped SiC collector region layer is 1×10 18 / cm 3 to 1×10 20 / cm 3 , and the thickness is less than 5 microns; the doping concentration range of the N-type lightly doped SiC buffer layer is 1×10 15 / cm 3 to 1×10 16 / cm 3 , and the thickness is less than 3 microns; the doping concentration range of the N-type doped SiC drift layer is 1×10 14 / cm 3 to 1×10 15 / cm 3 , and the thickness is less than 200 microns; the doping concentration of the N-type doped charge storage layer is higher than that of the N-type doped SiC drift layer, and the doping concentration range of the N-type doped charge storage layer is 1×10 15 / cm 3 to 1×10 16 / cm 3 , and the thickness is less than 3 microns; the doping concentration range of the P-well is 1×10 16 / cm 3 to 1×10 18 / cm 3 , and the thickness is less than 5 microns; the doping concentration range of the P-type heavily doped contact region is 1×10 18 / cm 3 to 1×10 20 / cm 3 , and the doping concentration range of the N-type heavily doped contact region is 1×10 18 / cm 3 to 1×10 20 / cm 3 .

6. The manufacturing method of the SiC IGBT device according to any one of claims 1-5, characterized in that: The gate dielectric layer includes a thermally oxidized silicon layer, and the thickness range of the gate dielectric layer is 40 - 60 nanometers.

7. The manufacturing method of the SiC IGBT device according to any one of claims 1-6, characterized in that: The depth of the heterojunction trench is less than 2 micrometers.

8. The manufacturing method of the SiC IGBT device according to any one of claims 1-7, characterized in that: The protective layer includes a silicon oxide layer.

9. The manufacturing method of the SiC IGBT device according to any one of claims 1-9, characterized in that: The emitter metal layer includes one or more of a Ni layer, a Ti layer, and an Al layer, and the collector metal layer includes one or more of a Ti layer and an Al layer.

10. The manufacturing method of the SiC IGBT device according to any one of claims 1-9, characterized in that: Forming a protective layer on the top surface of the gate polysilicon includes: Depositing a layer of silicon oxide layer on the semiconductor layer; Using photolithography and etching to pattern the silicon oxide layer to obtain the protective layer.

11. The manufacturing method of the SiC IGBT device according to any one of claims 1-10, characterized in that: Forming an emitter metal layer on the semiconductor layer includes: using sputtering to form the emitter metal layer on the semiconductor layer.

12. The manufacturing method of the SiC IGBT device according to any one of claims 1-11, characterized in that: Forming a collector metal layer on the back surface of the semiconductor layer includes: using sputtering to form the collector metal layer on the back surface of the semiconductor layer.

13. The method for manufacturing a SiC IGBT device according to claim 3, wherein: Performing ion implantation on the upper surface layer of the N-type doped SiC drift layer to obtain the N-type doped charge storage layer, including: performing N-type ion implantation on the upper surface layer of the N-type doped SiC drift layer to obtain the N-type doped charge storage layer; Performing ion implantation on the upper surface layer of the N-type doped charge storage layer to obtain the P well, including: performing P-type ion implantation on the upper surface layer of the N-type doped charge storage layer to obtain the P well; Performing ion implantation on the first preset region and the second preset region of the upper surface layer of the P well respectively to obtain the P-type heavily doped contact region and the N-type heavily doped contact region, including: performing P-type ion implantation on the first preset region of the upper surface layer of the P well to obtain the P-type heavily doped contact region, and performing N-type ion implantation on the second preset region of the upper surface layer of the P well to obtain the N-type heavily doped contact region.

14. A silicon carbide insulated gate bipolar transistor (SiC IGBT) device, comprising: A semiconductor layer, the material of the semiconductor layer includes SiC; A gate trench, located in the semiconductor layer, the gate trench opens from the top surface of the semiconductor layer and extends downward; A gate dielectric layer, located on the inner wall of the gate trench; A heterojunction trench, located on one side of the gate trench, the heterojunction trench opens from the top surface of the semiconductor layer and extends downward, one side surface of the heterojunction trench exposes the gate dielectric layer, and the bottom surface of the heterojunction trench is higher than the bottom surface of the gate trench; A polysilicon layer, including gate polysilicon located in the gate trench and heterojunction polysilicon located in the heterojunction trench, the junction between the heterojunction polysilicon and the semiconductor layer forms a polysilicon - SiC heterojunction; A protective layer, located on the top surface of the gate polysilicon; An emitter metal layer, located on the semiconductor layer, the emitter metal layer covers the heterojunction polysilicon and the protective layer; A collector metal layer, located on the back surface of the semiconductor layer.

15. The SiC IGBT device according to claim 14, wherein: The semiconductor layer includes a P-type heavily doped SiC collector region layer, an N-type lightly doped SiC buffer layer, an N-type doped SiC drift layer, an N-type doped charge storage layer, and a P well which are sequentially arranged from bottom to top, wherein: A first preset region on the upper surface layer of the P well is provided with a P-type heavily doped contact region, and a second preset region is provided with an N-type heavily doped contact region. The side surface of the P-type heavily doped contact region is adjacent to the side surface of the N-type heavily doped contact region; The gate trench is located on one side of the N-type heavily doped contact region and is adjacent to the N-type heavily doped contact region. The bottom surface of the gate trench is located in the charge storage layer; The heterojunction trench is located on the side of the gate trench away from the N-type heavily doped contact region, and the bottom surface of the heterojunction trench is located in the P well; The emitter metal layer also covers the P-type heavily doped contact region and the N-type heavily doped contact region; The collector metal layer is located on the back surface of the P-type heavily doped SiC collector region layer.

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