Data sending circuit, data receiving circuit, and electronic device

Abstract

The present disclosure provides a data sending circuit, a data receiving circuit, and an electronic device. The data sending circuit comprises a parallel-to-serial conversion circuit, a multi-level modulation circuit and a first transmission path; the parallel-to-serial conversion circuit is configured to convert a plurality of parallel initial data signals into serial data combinations, wherein each data combination comprises an n-bit data signal; the multi-level modulation circuit is configured to generate and output a target data signal on the basis of each data combination; and the first transmission path is coupled with the multi-level modulation circuit and is configured to transmit the target data signal to a second chip. According to the present disclosure, by means of multi-value transmission technology, a one-bit target data signal is used for the transmission of the n-bit data signal, so that the number of transmission paths can be reduced, and the transmission efficiency is improved.

Description

Data sending circuit, data receiving circuit and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2023, with application number 202311868889.0 and application name “A data transmitting circuit, data receiving circuit and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductors, and in particular to a data sending circuit, a data receiving circuit, and an electronic device. Background Art

[0004] With the advancement of semiconductor technology, semiconductor memory has been widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory. Due to its fast access speed, DRAM is often used as cache memory. Currently, there is still significant room for improvement in memory data transmission efficiency.

[0005] Summary of the Invention

[0006] Embodiments of the present disclosure provide a data sending circuit, a data receiving circuit, and an electronic device.

[0007] The technical solution of the present disclosure is achieved as follows:

[0008] In a first aspect, the present disclosure provides a data transmission circuit, applied to a first chip, the data transmission circuit comprising:

[0009] a parallel-to-serial conversion circuit configured to receive a plurality of parallel initial data signals and convert the plurality of parallel initial data signals into a serial data combination based on an initial clock signal; wherein the data combination includes an n-bit data signal, where n is an integer greater than 1;

[0010] a multi-level modulation circuit coupled to the parallel-to-serial conversion circuit, configured to receive and generate and output a target data signal based on each of the data combinations; wherein if the n-bit data signals in the data combination have different signal value combinations, the voltage value of the generated target data signal is different;

[0011] The first transmission path is coupled to the multi-level modulation circuit and configured to output the target data signal from the first chip.

[0012] In some embodiments, the data sending circuit also includes: a first reference voltage generating circuit, configured to receive a reference voltage signal, generate a preset power supply signal and an initial reference voltage signal based on the reference voltage signal, and output the preset power supply signal from its first output terminal and output the initial reference voltage signal from its second output terminal; wherein the voltage value of the preset power supply signal and the voltage value of the initial reference voltage signal are a preset ratio; the multi-level modulation circuit is coupled to the first output terminal of the first reference voltage generating circuit, and is also configured to receive the preset power supply signal, and under the drive of the preset power supply signal, generate the target data signal based on each data combination.

[0013] In some embodiments, the data sending circuit also includes: a clock generating circuit, coupled to the parallel-to-serial conversion circuit, configured to generate the initial clock signal and output it through its output end; a DC isolation circuit, connected to the output end of the clock generating circuit and the second output end of the first reference voltage generating circuit, respectively, configured to isolate the initial clock signal from DC and transmit it to the second output end of the first reference voltage generating circuit, so as to generate a clock / voltage mixed signal after superposition with the initial reference voltage signal; a second transmission path, coupled to the second output end of the first reference voltage generating circuit, configured to output the clock / voltage mixed signal from the first chip.

[0014] In some embodiments, when n=2, the data combination includes a low-order data signal and a high-order data signal; wherein, if the low-order data signal and the high-order data signal are a first signal value combination, the target data signal is a first voltage value; if the low-order data signal and the high-order data signal are a second signal value combination, the target data signal is a second voltage value; if the low-order data signal and the high-order data signal are a third signal value combination, the target data signal is a third voltage value; if the low-order data signal and the high-order data signal are a fourth signal value combination, the target data signal is a ground voltage; the first voltage value, the second voltage value, the third voltage value and the ground voltage decrease in sequence.

[0015] In some embodiments, the multi-level modulation circuit includes a first logic unit, a first pull-up unit, a second pull-up unit, a third pull-up unit, and a pull-down unit; the multi-level modulation circuit further includes a driving source node and an output node, the driving source node receiving the preset power signal; the first pull-up unit, the second pull-up unit, and the third pull-up unit are connected in parallel between the driving source node and the output node; the pull-down unit is connected in series between the output node and a ground terminal, and the output node is connected to the first transmission path; the first logic unit is configured to perform an AND operation on the low-bit data signal and the high-bit data signal to generate a first control signal; and perform a NOR operation on the low-bit data signal and the high-bit data signal to generate a second control signal; wherein the first control signal is used to selectively turn on the first pull-up unit, the high-bit data signal is used to selectively turn on the second pull-up unit, the low-bit data signal is used to selectively turn on the third pull-up unit, and the second control signal is used to selectively turn on the pull-down unit, and the second pull-up unit and the third pull-up unit have different resistance values.

[0016] In some embodiments, the first pull-up unit includes a first switch tube and a first resistor connected in series between the driving source node and the output node, the second pull-up unit includes a second switch tube and a second resistor connected in series between the driving source node and the output node, the third pull-up unit includes a third switch tube and a third resistor connected in series between the driving source node and the output node, and the pull-down unit includes a fourth switch tube and a fourth resistor connected in series; the control end of the first switch tube receives the first control signal, the control end of the second switch tube receives the low-bit data signal, the control end of the third switch tube receives the high-bit data signal, and the control end of the fourth switch tube receives the second control signal.

[0017] In some embodiments, the first voltage value: the second voltage value: the third voltage value = A: B: C; wherein A, B, and C are all positive integers, and A, B, and C decrease in sequence; (R 并 +R 下 ):(R2+R 下 ):(R3+R 下 )=(1 / A):(1 / B):(1 / C); where R 并 Refers to the equivalent resistance formed by the first resistor, the second resistor, and the third resistor connected in parallel, R 下 R2 refers to the resistance of the pull-down resistor that couples the data receiving circuit corresponding to the data sending circuit to the first transmission path, R3 refers to the resistance of the second resistor, and R4 refers to the resistance of the third resistor.

[0018] In some embodiments, the first reference voltage generating circuit includes a first operational amplifier, a fifth resistor and a sixth resistor; the positive input terminal of the first operational amplifier receives the reference voltage signal, the negative input terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier serves as the first output terminal of the first reference voltage generating circuit to output the preset power supply signal; the output terminal of the first operational amplifier is connected to the first terminal of the fifth resistor, the second terminal of the fifth resistor is connected to the first terminal of the sixth resistor, the second terminal of the sixth resistor is connected to the ground terminal, and the second terminal of the fifth resistor serves as the second output terminal of the first reference voltage generating circuit to output the initial reference voltage signal.

[0019] In some embodiments, the first transmission via and the second transmission via both include through silicon vias.

[0020] In a second aspect, an embodiment of the present disclosure provides a data receiving circuit, applied to a second chip, the data receiving circuit comprising:

[0021] a third transmission path configured to receive a target data signal sent to the second chip;

[0022] a data comparison circuit coupled to the third transmission path, configured to receive (2n-1) reference voltages and the target data signal, compare each reference voltage with a voltage value of the target data signal, and generate and output (2n-1) comparison signals;

[0023] A logic processing circuit is coupled to the data comparison circuit and is configured to perform logic processing on (2n-1) comparison signals to generate and output data combinations; wherein each data combination includes an n-bit data signal, where n is an integer greater than 1.

[0024] In some embodiments, the data receiving circuit further includes: a fourth transmission path, configured to receive a clock / voltage mixed signal sent to the second chip; a clock receiver, coupled to the fourth transmission path, configured to receive a clock reference voltage and the clock / voltage mixed signal reference voltage, and compare the clock / voltage mixed signal with the clock reference voltage to generate and output a reference clock signal; a clock processing circuit, connected to the clock receiver, configured to receive the reference clock signal, and generate and output a sampling clock signal after processing the reference clock signal; the logic processing circuit, also connected to the clock processing circuit, configured to sample (2n-1) comparison signals respectively based on the sampling clock signal, and perform logic operations based on the sampling results to generate the data combination.

[0025] In some embodiments, the data receiving circuit further includes: a low-pass filter configured to receive the clock / voltage mixed signal, filter the clock / voltage mixed signal, and generate an initial reference voltage; a second reference voltage generating circuit configured to generate (2 n -1) reference voltage.

[0026] In some embodiments, the data receiving circuit further includes a pull-down resistor; a first end of the pull-down resistor is connected to the third transmission path, and a second end of the pull-down resistor is connected to a ground end.

[0027] In some embodiments, when n=2, (2 n -1) reference voltages are respectively called the first reference voltage, the second reference voltage and the third reference voltage, (2 n -1) comparison signals are respectively called the first comparison signal, the second comparison signal and the third comparison signal; the voltage value of the first reference voltage is between the first voltage value and the second voltage value, the voltage value of the second reference voltage is between the second voltage value and the third voltage value, and the voltage value of the third reference voltage is between the third voltage value and the ground voltage; the first voltage value, the second voltage value and the third voltage value decrease in sequence; the logic processing circuit is specifically configured such that if the first comparison signal indicates that the voltage value of the target data signal is greater than or equal to the voltage value of the first reference voltage, the 2-bit data signal of the data combination is the first signal value combination; or, if the first comparison signal indicates that the target data signal is less than the voltage value of the first reference voltage and the second comparison signal indicates that the voltage value of the target data signal is greater than or equal to the voltage value of the second reference voltage, then the 2-bit data signal of the data combination is the second signal value combination; or, if the second comparison signal indicates that the voltage value of the target data signal is less than the voltage value of the second reference voltage and the third comparison signal indicates that the voltage value of the target data signal is greater than or equal to the voltage value of the third reference voltage, then the 2-bit data signal of the data combination is the third signal value combination; or, if the third comparison signal indicates that the voltage value of the target data signal is less than the voltage value of the third reference voltage, then the 2-bit data signal of the data combination is the fourth signal value combination.

[0028] In some embodiments, the second reference voltage generating circuit includes a second operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor; the positive input terminal of the second operational amplifier receives the initial reference voltage, the output terminal of the second operational amplifier is connected to the first end of the seventh resistor, and the negative input terminal of the second operational amplifier is connected to the second end of the eighth resistor; the second end of the seventh resistor is connected to the first end of the eighth resistor, the second end of the eighth resistor is connected to the first end of the ninth resistor, the second end of the ninth resistor is connected to the first end of the tenth resistor, and the second end of the tenth resistor is connected to the ground terminal; the second end of the seventh resistor outputs the first reference voltage, the second end of the eighth resistor outputs the second reference voltage, and the second end of the ninth resistor outputs the third reference voltage.

[0029] In some embodiments, the second reference voltage is the same as the initial reference voltage, the clock reference voltage is the same as the second reference voltage, and the third transmission path and the fourth transmission path both include through silicon vias.

[0030] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising a first chip and a second chip, wherein the first chip comprises the data sending circuit as described in the first aspect, and the second chip comprises the data receiving circuit as described in the second aspect.

[0031] In some embodiments, the first chip is a logic signal / memory chip, the second chip is a memory chip / logic chip, the first chip and the second chip are stacked along a first direction, and the first direction is perpendicular to the top surface of the chip; the electronic device is a stacked memory.

[0032] In some embodiments, the through silicon vias in the first transmission path in the first chip and the through silicon vias in the third transmission path in the second chip are aligned along the first direction and form a transmission path for the target data signal; the through silicon vias in the second transmission path in the first chip and the through silicon vias in the fourth transmission path in the second chip are aligned along the first direction and form a transmission path for the clock / voltage mixed signal.

[0033] The embodiment of the present disclosure provides a data sending circuit, a data receiving circuit and an electronic device, which transmits an n-bit data signal using a one-bit target data signal through a multi-value transmission technology, and the voltage value of the target data signal has at least 2 n This reduces the number of transmission paths and improves transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a schematic structural diagram of a data sending circuit provided by an embodiment of the present disclosure;

[0035] FIG2 is a schematic diagram of a specific structure of a data sending circuit provided in an embodiment of the present disclosure;

[0036] FIG3 is a voltage diagram of a target data signal provided by an embodiment of the present disclosure;

[0037] FIG4 is a schematic structural diagram of a multi-level modulation circuit provided by an embodiment of the present disclosure;

[0038] FIG5 is a schematic structural diagram of a data receiving circuit provided in an embodiment of the present disclosure;

[0039] FIG6 is a schematic diagram of a specific structure of a data receiving circuit provided in an embodiment of the present disclosure;

[0040] 7A / 7B / 7C are schematic structural diagrams of electronic devices provided by embodiments of the present disclosure;

[0041] FIG8 is a schematic diagram of the specific structure of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0043] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0046] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0047] In one embodiment of the present disclosure, a data transmission circuit 10 is provided. The data transmission circuit is applied to a first chip 51. Referring to FIG. 1 , the data transmission circuit 10 includes:

[0048] The parallel-to-serial conversion circuit 11 is configured to receive a plurality of parallel initial data signals and convert the plurality of parallel initial data signals into a serial data combination based on an initial clock signal; wherein the data combination includes an n-bit data signal, where n is an integer greater than 1;

[0049] The multi-level modulation circuit 12 is coupled to the parallel-to-serial conversion circuit 11 and is configured to receive and generate and output a target data signal based on each data combination; wherein, if the n-bit data signals in the data combination have different signal value combinations, the voltage value of the generated target data signal is different;

[0050] The first transmission path 13 is coupled to the multi-level modulation circuit 12 and configured to output the target data signal from the first chip 51 .

[0051] Exemplarily, the first chip 51 and the second chip 52 are electrically connected, and the first transmission path 13 specifically transmits the target data signal to the second chip 52 .

[0052] It should be noted that the parallel-to-serial conversion circuit 11 is capable of converting parallel initial data signals into serial data combinations, where the number of initial data signals is greater than n. For example, the initial data signal may be DataIn<7:0>, where n=2, i.e., the data combination is represented as Data<1:0>. Parallel-to-serial conversion refers to using DataIn<1:0> as the data combination for clock cycle T0, DataIn<3:2> as the data combination for clock cycle T1, DataIn<5:4> as the data combination for clock cycle T2, and DataIn<7:6> as the data combination for clock cycle T3. For another example, the initial data signal may be DataIn<15:0>, which can also be considered as converting the parallel initial data signal DataIn<7:0> into a serial DataIn<15:0>. <0> , convert the parallel initial data signal DataIn<15:8> into a serial Data <1> The above is only an example, and the number of initial data signals and the value of n can be selected as needed. The parallel-to-serial conversion circuit 11 can be implemented by a flip-flop DFF or a first-in-first-out data storage FIFO.

[0053] It should also be noted that the multi-level modulation circuit 12 can generate a target data signal of a corresponding voltage value according to the specific signal value of the data combination. The target data signal is only a one-bit signal. At the same time, for each data signal in the data combination, its signal value is 1 (high level) or 0 (low level), but the voltage value of the target data signal has at least 2 nThus, only one bit of target data signal can indicate the value of an n-bit data signal, thereby reducing the number of transmission paths and significantly improving transmission efficiency.

[0054] In some embodiments, referring to FIG. 2 , the data sending circuit 10 further includes:

[0055] The first reference voltage generating circuit 14 is configured to receive a reference voltage signal, generate a preset power signal and an initial reference voltage signal based on the reference voltage signal, and output the preset power signal from its first output terminal and the initial reference voltage signal from its second output terminal; wherein the voltage value of the preset power signal and the voltage value of the initial reference voltage signal are in a predetermined ratio;

[0056] The multi-level modulation circuit 12 is coupled to the first output terminal of the first reference voltage generating circuit 14 and is further configured to receive a preset power signal and generate a target data signal based on each data combination under the drive of the preset power signal.

[0057] Here, the voltage value of the target data signal is positively correlated with the voltage value of the preset power signal.

[0058] It should be noted that the initial reference voltage signal needs to be transmitted to the second chip 52 synchronously with the target data signal, so that the second chip 52 generates 2 according to the initial reference voltage signal. n -1 reference voltage, then use 2 n -1 reference voltage is compared with the voltage value of the target data signal, and finally n data signals (ie, specific signal values ​​of the data combination) are decoded according to the comparison result.

[0059] In some embodiments, referring to FIG. 2 , the data sending circuit 10 further includes:

[0060] The clock generating circuit 15 is coupled to the parallel-to-serial conversion circuit 11 and is configured to generate an initial clock signal and output it through its output terminal.

[0061] a DC blocking circuit 16 connected to the output terminal of the clock generating circuit 15 and the second output terminal of the first reference voltage generating circuit 14, respectively, and configured to block the DC power of the initial clock signal and transmit it to the second output terminal of the first reference voltage generating circuit 14, so as to be superimposed with the initial reference voltage signal to generate a clock / voltage mixed signal;

[0062] The second transmission path 18 is coupled to the second output terminal of the first reference voltage generating circuit 14 and is configured to output the clock / voltage mixed signal from the first chip 51 .

[0063] It should be noted that the initial clock signal also needs to be transmitted synchronously with the target data signal to the second chip 52, so that the second chip 52 can sample the target data signal based on the initial clock signal. In order to improve transmission efficiency, the present disclosure superimposes the initial clock signal and the initial reference voltage signal after DC isolation processing to generate a clock / voltage mixed signal and transmits it to the second chip 52. The second chip 52 then processes the clock / voltage mixed signal to obtain the information carried by the initial clock signal and the information carried by the initial reference voltage signal. This is equivalent to using only one transmission path to transmit the information carried by the initial clock signal and the information carried by the initial reference voltage signal to the second chip 52. This not only reduces the number of transmission paths set up and reduces the area occupied by the chip, but also improves transmission efficiency.

[0064] Here, the functions of the DC blocking circuit 16 include at least: (1) preventing the DC reference voltage from being transmitted to the output end of the clock generating circuit; and (2) transmitting the AC clock signal to the output end of the first reference voltage generating circuit while filtering out DC noise.

[0065] Please refer to FIG. 2 , the data sending circuit 20 may further include a buffer 17 . The initial clock signal passes through the buffer 17 and the DC blocking circuit 16 and is then superimposed on the initial reference voltage signal to form a clock / voltage reference signal.

[0066] In some embodiments, when n=2, the data combination includes the low-order data signal Data <0> And high data signal Data <1> At this time, the multi-level modulation circuit 12 can be implemented using the fourth-generation pulse amplitude modulation (4 Pulse Amplitude Modulation, PAM4) technology. By using four different signal levels to transmit logic signals, each clock cycle can transmit the logic information of a two-bit data signal (00, 01, 10, 11). Therefore, at the same baud rate (consistent symbol period), the bit rate of the PAM4 signal is twice that of the conventional signal, doubling the transmission rate. In addition, in some embodiments, when n is a value greater than 2, the multi-level modulation circuit corresponds to other pulse amplitude modulation modes, for example: n = 3 corresponds to PAM8, and n = 4 corresponds to PAM16.

[0067] Please refer to Figure 3. If the low-order data signal and the high-order data signal are a first signal value combination (for example, Data<1:0>=11), the target data signal is a first voltage value V1; if the low-order data signal and the high-order data signal are a second signal value combination (for example, Data<1:0>=10), the target data signal is a second voltage value V2; if the low-order data signal and the high-order data signal are a third signal value combination (for example, Data<1:0>=01), the target data signal is a third voltage value V3; if the low-order data signal and the high-order data signal are a fourth signal value combination (for example, Data<1:0>=00), the target data signal is the ground voltage VSS.

[0068] Exemplarily, the first voltage value V1 , the second voltage value V2 , the third voltage value V3 and the ground voltage VSS decrease in sequence.

[0069] It should be understood that the target data signal is the ground voltage VSS, which can also be simply understood as no signal transmission, thus saving power resources.

[0070] Of course, in other embodiments, if the low-order data signal and the high-order data signal are a fourth signal value combination (eg, Data<1:0>=00), the target data signal may also be set to a fourth voltage value greater than the ground voltage.

[0071] At this time, referring to FIG4 , the multi-level modulation circuit 12 includes a first logic unit 121, a first pull-up unit 122, a second pull-up unit 123, a third pull-up unit 124, and a pull-down unit 125; the multi-level modulation circuit 12 also includes a driving source node and an output node, the driving source node receives a preset power signal; the first pull-up unit 122, the second pull-up unit 123, and the third pull-up unit 124 are connected in parallel between the driving source node and the output node; the pull-down unit 125 is connected in series between the output node and the ground terminal, and the output node is connected to the first transmission path 13; the first logic unit 121 is configured to receive the low-bit data signal Data <0> And high data signal Data <1> Perform AND operation to generate the first control signal; <0> And high data signal Data <1> Performing a NOR operation to generate a second control signal;

[0072] The first control signal is used to selectively turn on the first pull-up unit 122, and the high-bit data signal Data <1> For selectively turning on the second pull-up unit 123, the low-bit data signal Data <0> The second control signal is used to selectively turn on the third pull-up unit 124 , and the second control signal is used to selectively turn on the pull-down unit 125 . The resistance values ​​of the second pull-up unit 123 and the third pull-up unit 124 are different.

[0073] It should be noted that the first logic unit 121 includes an AND gate 201, a first buffer 202, a second buffer 203 and a NOR gate 204. The AND gate 201 is used to <0> And high data signal Data <1> Performing AND operation to generate the first control signal, the NOR gate 204 performs AND operation on the low-order data signal Data <0> And high data signal Data <1> Performing a NOR operation to generate a second control signal, the first buffer 202 is used to process the high-order data signal Data <1> After delaying, the signal is transmitted to the second pull-up unit 123. The second buffer 203 is used to process the low-order data signal Data <0> The signal is transmitted to the third pull-up unit 124 after being delayed. The first buffer 202 and the second buffer 203 are mainly used for signal delay matching.

[0074] In some embodiments, referring to FIG. 4 , the first pull-up unit 122 includes a first switch 211 and a first resistor 212 connected in series between the driving source node and the output node. The second pull-up unit 123 includes a second switch 213 and a second resistor 214 connected in series between the driving source node and the output node. The third pull-up unit 124 includes a third switch 215 and a third resistor 216 connected in series between the driving source node and the output node. The pull-down unit 125 includes a fourth switch 217 and a fourth resistor 218 connected in series.

[0075] The control terminal of the first switch tube 211 receives the first control signal, and the control terminal of the second switch tube 213 receives the (delayed) low-bit data signal Data <0> The control terminal of the third switch tube 215 receives the (delayed) high-bit data signal Data <1> , the control end of the fourth switch tube 217 receives the second control signal.

[0076] In some embodiments, the first voltage value V1: the second voltage value V2: the third voltage value V3 = A: B: C; wherein A, B, and C are all positive integers, and A, B, and C decrease in sequence;

[0077] 1 / (R 并 +R 下 ): 1 / (R2+R 下 ): 1 / (R3+R 下 )=A:B:C;

[0078] Among them, R 并 Refers to the equivalent resistance formed by the first resistor 212, the second resistor 214, and the third resistor 216 connected in parallel, R 下 R2 refers to the resistance of the pull-down resistor that couples the data receiving circuit (in the second chip 52 ) to the first transmission path 13 , R2 refers to the resistance of the second resistor 214 , and R3 refers to the resistance of the third resistor 216 .

[0079] For example, the first voltage value V1: the second voltage value V2: the third voltage value V3 = 3:2:1; in one possible value, R1 = 60Ω, R2 = 100Ω, R3 = 300Ω, R 下 =100Ω, then R 并 =33.33Ω, (R 并 +R 下 ):(R2+R 下 ):(R3+R 下 )=3:2:1; or, R1=170Ω, R2=150Ω, R3=400Ω, R 下 =100Ω, then R 并 =66.45Ω, (R 并 +R 下 ):(R2+R 下 ):(R3+R 下 )=3:2:1.

[0080] In some embodiments, referring to FIG2 , the first reference voltage generating circuit 14 includes a first operational amplifier 221, a fifth resistor 222, and a sixth resistor 223; the positive input terminal of the first operational amplifier 221 receives a reference voltage signal, the negative input terminal of the first operational amplifier 221 is connected to the output terminal of the first operational amplifier 221, and the output terminal of the first operational amplifier 221 serves as the first output terminal of the first reference voltage generating circuit 14 to output a preset power supply signal; the output terminal of the first operational amplifier 221 is connected to the first terminal of the fifth resistor 222, the second terminal of the fifth resistor 222 is connected to the first terminal of the sixth resistor 223, the second terminal of the sixth resistor 223 is connected to the ground terminal, and the second terminal of the fifth resistor 222 serves as the second output terminal of the first reference voltage generating circuit 14 to output an initial reference voltage signal.

[0081] It should be understood that after the first reference voltage generating circuit 14 is balanced, the voltage at the positive input terminal and the voltage at the negative input terminal of the first operational amplifier 221 are the same, that is, the voltage of the preset power signal and the voltage of the reference voltage signal are the same; the voltage of the initial reference voltage signal: the voltage of the preset power signal = the resistance value of the sixth resistor 223: (the resistance value of the fifth resistor 222 + the resistance value of the sixth resistor 223). In addition, the first reference voltage generating circuit 14 can also be implemented using other voltage divider structures.

[0082] Here, the fifth resistor 222 and the sixth resistor 223 are both adjustable resistors. In this case, the voltage of the initial reference voltage signal is adjustable.

[0083] In some embodiments, the first transmission via 13 and the second transmission via 18 both include through silicon vias (TSVs).

[0084] It should be noted that through-silicon vias (TSVs) are a vertical electrical interconnect technology that enables vertical conduction between chips and wafers. Their small size increases stacking density and improves chip speed and power consumption.

[0085] The disclosed embodiments provide a data transmission circuit. Currently, for memory chips, the increase in electrical pads has become a problem due to high-bandwidth data transmission, which leads to increased chip size and inter-chip connection failures. The disclosed embodiments reduce the number of electrical pads by using multi-level modulation technology to perform multi-value transmission using a single signal (target data signal). Simply put, for conventional single-value transmission, one clock cycle transmits one bit of data (half a clock cycle transmits one bit of data in double-speed memory DDR); for multi-value transmission, one clock cycle transmits n bits of data (half a clock cycle transmits n bits of data in DDR), thereby reducing the number of electrical pads and improving transmission efficiency. In addition, the driver (pull-up unit, pull-down unit) of this solution can change the output current value according to the output data. Even if there is no current output, the data is valid; in this case, it is defined as 00 data, thereby saving transmission energy consumption; in addition, the reference voltage signal and the initial clock signal used for multi-value reference are superimposed and transmitted through the same electrical pad (such as the micro-bump pad corresponding to TSV, etc.), and at the same time, the reference voltage of the receiver corresponding to the second chip 52 can be independently adjusted according to the acceptable tolerance, further reducing the number of electrical pads and improving transmission efficiency.

[0086] In another embodiment of the present disclosure, a data receiving circuit 30 is provided. The data receiving circuit 30 is applied to the second chip 52. Referring to FIG. 5 , the data receiving circuit 30 includes:

[0087] The third transmission path 31 is configured to receive the target data signal sent to the second chip 52;

[0088] The data comparison circuit 32 is coupled to the third transmission path 31 and is configured to receive (2 n -1) reference voltage and target data signal, compare the voltage value of each reference voltage and target data signal respectively, generate and output (2 n -1) comparison signal;

[0089] The logic processing circuit 33 is coupled to the data comparison circuit 32 and is configured to (2 n -1) comparison signals are logically processed to generate and output data combinations; wherein each data combination includes an n-bit data signal, and n is an integer greater than 1.

[0090] It should be noted that the voltage value of the target data signal has 2 n The data comparison circuit 32 may include 2n - 1 data comparator, each data comparator receives a target data signal and one of the reference voltages, and outputs a corresponding comparison signal.

[0091] Thus, the data comparison circuit 32 and the logic processing circuit 33 are also called demodulation modules, which can n The target data signal with 0 values ​​is demodulated into an n-bit data signal. The voltage value of each data signal has only two values, namely 0 or 1. Therefore, only one target data signal can indicate the value of the n-bit data signal, occupying only one transmission path, and significantly improving transmission efficiency.

[0092] For example, 2 n -1 comparison signal is all 0, indicating a value of the n-bit data signal in the data combination; 2 n - Only one comparison signal of 1 comparison signal is 1, indicating another value of the n-bit data signal in the data combination; 2 n - Only two comparison signals of one comparison signal are 1, indicating another value of the n-bit data signal in the data combination; ...; 2 n -1 comparison signals are all 1, indicating another value of the n-bit data signal in the data combination.

[0093] In some embodiments, as shown in FIG6 , the data receiving circuit 30 further includes:

[0094] a fourth transmission path 34 configured to receive a clock / voltage mixed signal sent to the second chip 52;

[0095] a clock receiver 35 coupled to the fourth transmission path 34 and configured to receive the clock reference voltage and the clock / voltage mixed signal reference voltage, compare the clock / voltage mixed signal with the clock reference voltage, and generate and output a reference clock signal;

[0096] The clock processing circuit 36 ​​is configured to receive a reference clock signal, process the reference clock signal, and generate and output a sampling clock signal;

[0097] The logic processing circuit 33 is also connected to the clock receiver 35 and is configured to respectively process (2 n -1) comparison signals are sampled, and logic operations are performed based on the sampling results to generate the aforementioned data combination (i.e., restore the data combination sent by the first chip 51). It should be understood that FIG6 takes n=2 as an example, and the data combination is represented as Data<1:0>.

[0098] It should be noted that the clock processing circuit 36 ​​may be a delay locked loop (DLL).

[0099] Here, the logic processing circuit 33 can use the sampling clock signal to sample and latch the comparison signal output by the data comparison circuit 32, and then output the n-bit data signal after logical operation (decoding); in some other embodiments, the sampling clock signal can also be sent to the data comparison circuit 32, and the data comparison circuit 32 samples and compares the serial target data signal sent by the first chip 51 in sequence based on the sampling clock signal, and then outputs the comparison signal, and the logic processing circuit 33 performs a logical operation on the comparison signal and outputs it.

[0100] In some embodiments, referring to FIG6 , the data receiving circuit 30 further includes:

[0101] a low-pass filter 37 configured to receive the clock / voltage mixed signal, filter the clock / voltage mixed signal, and generate an initial reference voltage;

[0102] The second reference voltage generating circuit 38 is configured to generate (2 n -1) reference voltages: When n=2, the reference voltages are Ref-H, Ref-M, and Ref-L.

[0103] It should be noted that the low-pass filter 37 (LPF) is an electronic filtering device that allows signals below the cutoff frequency to pass, but blocks signals above the cutoff frequency. Simply put, the clock / voltage mixed signal carries AC clock information and DC reference voltage information. The low-pass filter 37 can restore the DC initial reference voltage from the clock / voltage mixed signal, and the clock receiver 35 performs comparison processing to restore the AC sampling clock signal from the clock / voltage mixed signal. In this way, the clock information and reference voltage information are transmitted to the second chip 52 via the clock / voltage mixed signal, requiring only a single transmission path, thereby improving transmission efficiency.

[0104] In some embodiments, referring to FIG6 , the data receiving circuit 30 further includes a pull-down resistor 39 ;

[0105] A first end of the pull-down resistor 39 is connected to the third transmission path 31 , and a second end of the pull-down resistor 39 is connected to the ground.

[0106] Here, the resistance of the pull-down resistor 39 is the aforementioned R 下 , that is, the pull-down resistor 39 forms a voltage-dividing relationship with the first pull-up unit, and / or the second pull-up unit, and / or the third pull-up unit in the first chip 51 .

[0107] In some embodiments, when n=2, (2 n-1) reference voltages are respectively called the first reference voltage Ref-H, the second reference voltage Ref-M and the third reference voltage Ref-L, (2 n -1) comparison signals are respectively referred to as the first comparison signal, the second comparison signal and the third comparison signal, and the n-bit data signals are respectively referred to as the high-bit data signals Data <1> and low-order data signal Data <0> Meanwhile, the data comparison circuit 32 includes data comparators 321 to 323. The data comparator 321 is used to compare the voltage of the first reference voltage Ref-H with the target data signal to output a first comparison signal. The data comparator 322 is used to compare the voltage of the second reference voltage Ref-M with the target data signal to output a second comparison signal. The data comparator 323 is used to compare the voltage of the third reference voltage Ref-L with the target data signal to output a third comparison signal.

[0108] Please refer to Figure 3, the voltage value of the first reference voltage Ref-H is between the first voltage value V1 and the second voltage value V2, the voltage value of the second reference voltage Ref-M is between the second voltage value V2 and the third voltage value V3, and the voltage value of the third reference voltage Ref-L is between the third voltage value V3 and the ground voltage (or the fourth voltage value); the first voltage value V1, the second voltage value V2 and the third voltage value V3 decrease in sequence.

[0109] The logic processing circuit 33 is specifically configured to: if the first comparison signal indicates that the voltage value of the target data signal (close to the first voltage value V1) is greater than or equal to the voltage value of the first reference voltage Ref-H, then the 2-bit data signal of the data combination is the first signal value combination Data<1:0>=11; or, if the first comparison signal indicates that the voltage value of the target data signal (close to the second voltage value V2) is less than the voltage value of the first reference voltage Ref-H and the second comparison signal indicates that the voltage value of the target data signal is greater than or equal to the voltage value of the second reference voltage Ref-M, then the 2-bit data signal of the data combination is the second signal value combination Data<1:0>=11. 1:0>=10; or, if the second comparison signal indicates that the voltage value of the target data signal (close to the third voltage value V3) is less than the voltage value of the second reference voltage Ref-M and the third comparison signal indicates that the voltage value of the target data signal is greater than or equal to the voltage value of the third reference voltage Ref-L, then the 2-bit data signal of the data combination is the third signal value combination Data<1:0>=01; or, if the third comparison signal indicates that the voltage value of the target data signal (close to the ground voltage) is less than the voltage value of the third reference voltage Ref-L, then the 2-bit data signal of the data combination is the fourth signal value combination Data<1:0>=00.

[0110] In some embodiments, the second reference voltage generating circuit 38 includes a second operational amplifier 381 , a seventh resistor 382 , an eighth resistor 383 , a ninth resistor 384 , and a tenth resistor 385 ;

[0111] The positive input terminal of the second operational amplifier 381 receives the initial reference voltage, the output terminal of the second operational amplifier 381 is connected to the first terminal of the seventh resistor 382, ​​and the negative input terminal of the second operational amplifier 381 is connected to the second terminal of the eighth resistor 383;

[0112] The second end of the seventh resistor 382 is connected to the first end of the eighth resistor 383 , the second end of the eighth resistor 383 is connected to the first end of the ninth resistor 384 , the second end of the ninth resistor 384 is connected to the first end of the tenth resistor 385 , and the second end of the tenth resistor 385 is connected to the ground.

[0113] The second end of the seventh resistor 382 outputs the first reference voltage Ref-H, the second end of the eighth resistor 383 outputs the second reference voltage Ref-M, and the second end of the ninth resistor 384 outputs the third reference voltage Ref-L.

[0114] It should be noted that the first reference voltage Ref-H: the second reference voltage Ref-M: the third reference voltage Ref-L = (R8+R9+R 10 ):(R9+R 10 ):R 10 , R8 refers to the resistance of the eighth resistor 383, R9 refers to the resistance of the ninth resistor 384, R 10 It refers to the resistance value of the tenth resistor 385 .

[0115] In addition, the seventh resistor 382 to the tenth resistor 385 can be adjustable resistors, so that the specific values ​​of the first reference voltage Ref-H, the second reference voltage Ref-M, and the third reference voltage Ref-L can be flexibly adjusted. The specific value of the third reference voltage Ref-L can also adjust the sensitivity of the data receiving circuit 30. Please refer to Figure 3. If the third reference voltage Ref-L moves down to the dotted line position, the data receiving circuit 30 will be more sensitive to Data<1:0>=01.

[0116] In particular, in the embodiment of the present disclosure, even if the target data signal is the ground voltage, there is still data output, ie, Data<1:0>=00, and sensing 00 is the easiest, ensuring a transition from 00 to 01 with a sensing margin.

[0117] It should be understood that after the second reference voltage generating circuit 38 reaches balance, the voltages at the positive input terminal and the negative input terminal of the second operational amplifier 381 are the same, and are the same as the second reference voltage Ref-M, that is, the second reference voltage Ref-M is the same as the voltage of the initial reference voltage. At this time, the clock reference voltage can reuse the second reference voltage Ref-M, and the circuit logic is simpler.

[0118] In some embodiments, the third transmission via 31 and the fourth transmission via 34 both include through silicon vias.

[0119] The embodiment of the present disclosure provides a data receiving circuit, which reduces the number of pads by transmitting, that is, only receives one bit of target data signal, and the voltage value of the target data signal has at least 2 n By demodulating it, an n-bit data signal is obtained, thereby improving the transmission efficiency; in addition, even if the target data signal has no current output, the data is valid, that is, the 00 state, thereby saving transmission energy consumption; in addition, by receiving the clock / voltage mixed signal and obtaining the clock information and the reference voltage information at the same time, the number of electrical pads is further reduced and the transmission efficiency is improved; in addition, compared with the traditional dual-port differential transmission circuit, the single-ended transmission method is adopted in the present application, which has a small circuit scale, reduces current function, and reduces the consumption of TSV / pads caused by the dual-end transmission.

[0120] In another embodiment of the present disclosure, referring to Figures 7A, 7B, and 7C, a schematic diagram of the structure of an electronic device 50 provided in an embodiment of the present disclosure is shown. As shown in Figures 7A, 7B, and 7C, the electronic device includes a first chip 51 and a second chip 52. The first chip 51 includes the aforementioned data transmission circuit 10, and the second chip 52 includes the aforementioned data reception circuit 30.

[0121] The semiconductor chip may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction intersecting (for example, perpendicular) with the top surface and the bottom surface of the semiconductor chip is defined as the first direction.

[0122] It should be noted that electronic device 50 has a multi-chip stacked structure (i.e., stacked memory), which includes a logic chip and multiple memory chips stacked along a first direction. Referring to Figures 7A, 7B, and 7C, first chip 51 can be a logic chip or any memory chip in the stacked structure, and corresponding second chip 52 can be any memory chip or logic chip in the stacked structure. In this case, first chip 51 and second chip 52 are stacked along the first direction, which is perpendicular to the top surface of the chips.

[0123] In addition, the first chip 51 may also be a single memory chip, and the second chip 52 may be a memory controller.

[0124] It should also be noted that, no matter the first chip 51 or the second chip 52 , both can be provided with the data sending circuit 10 and the data receiving circuit 30 .

[0125] The through silicon vias TSV in the first transmission path in the first chip 51 and the through silicon vias TSV in the third transmission path in the second chip 52 are aligned along a first direction and form a transmission path for a target data signal;

[0126] The through silicon vias TSV in the second transmission path in the first chip 51 and the through silicon vias TSV in the fourth transmission path in the second chip 52 are aligned along a first direction and form a transmission path for a clock / voltage mixed signal.

[0127] The present disclosure relates to semiconductor circuit design and is not limited to specific interface applications. It can be applied to places where signal transmission and signal reception are required.

[0128] Please refer to Figure 8, which provides a schematic diagram of the circuit structure of data transmission and reception of an electronic device. As shown in Figure 8, for the first chip 51, the working process of the data transmission circuit 10 therein is as follows: (1) The clock generation circuit 15 generates an initial clock signal, and the first reference voltage generation circuit 14 uses the reference voltage signal to generate an initial reference voltage signal and a preset power supply signal. The initial reference voltage signal and the initial clock signal after DC isolation are superimposed to form a clock / voltage mixed signal, which is transmitted to the second chip 52 through the first transmission path-the third transmission path; (2) The parallel-to-serial conversion circuit 11 uses the initial clock signal to convert multiple parallel initial data signals into a serial data combination, and the data combination includes an n-bit data signal (n=2 is used as an example for explanation); the multi-level modulation circuit 12 modulates the n-bit data signal into a 2-bit data signal under the drive of the preset power supply signal. n The target data signal having a level value is transmitted to the second chip 52 through the second transmission path, namely the fourth transmission path.

[0129] For the second chip 52, the working process of the data receiving circuit 50 therein is as follows: (1) The clock / voltage mixed signal is filtered by the low-pass filter 37 to generate an initial reference voltage, and the second reference voltage generating circuit 38 generates a first reference voltage Ref-H, a second reference voltage Ref-M, and a third reference voltage Ref-L based on the initial reference voltage, and the second reference voltage Ref-M has the same voltage value as the initial reference voltage; the clock receiver 35 generates a reference clock signal by comparing the clock / voltage mixed signal with the second reference voltage Ref-M, and the clock processing circuit 36 ​​generates a sampling clock signal based on the reference clock signal; (2) the data comparison circuit 32 compares the target data signal with the first reference voltage Ref-H, the second reference voltage Ref-M, and the third reference voltage Ref-L respectively, and the logic processing circuit 33 samples, latches and decodes the voltage comparison result according to the sampling clock signal to obtain the data combination originally sent by the first chip 51.

[0130] The embodiment of the present disclosure provides an electronic device, which uses a one-bit target data signal to transmit an n-bit data signal, and the voltage value of the target data signal has at least 2 n At the same time, even if the target data signal has no current output, the data is valid, that is, the 00 state, thereby saving transmission energy consumption; in addition, the clock information and reference voltage information are transmitted simultaneously through the clock / voltage mixed signal, which further reduces the number of transmission paths and improves the transmission efficiency.

[0131] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0132] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0133] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A data sending circuit (10), characterized in that, Applied to the first chip (51), the data sending circuit (10) includes: A serial-to-parallel conversion circuit (11), configured to receive a plurality of parallel initial data signals and convert the plurality of parallel initial data signals into a serial data combination based on an initial clock signal; wherein, the data combination includes n-bit data signals, and n is an integer greater than 1; A multi-level modulation circuit (12), coupled to the serial-to-parallel conversion circuit (11), configured to receive and generate and output a target data signal based on each of the data combinations; wherein, when the n-bit data signals in the data combination are different signal value combinations, the voltage values of the generated target data signals are different; A first transmission path (13), coupled to the multi-level modulation circuit (12), configured to output the target data signal from the first chip (51).

2. The data sending circuit (10) according to claim 1, wherein The data sending circuit (10) further includes: A first reference voltage generation circuit (14), configured to receive a reference voltage signal, generate a preset power signal and an initial reference voltage signal based on the reference voltage signal, and output the preset power signal from its first output terminal and output the initial reference voltage signal from its second output terminal; wherein, the voltage value of the preset power signal and the voltage value of the initial reference voltage signal are in a preset ratio; The multi-level modulation circuit (12), coupled to the first output terminal of the first reference voltage generation circuit (14), is further configured to receive the preset power signal and generate the target data signal based on each of the data combinations under the drive of the preset power signal.

3. The data sending circuit (10) according to claim 2, characterized in that The data sending circuit (10) further includes: A clock generation circuit (15), coupled to the serial-to-parallel conversion circuit (11), configured to generate the initial clock signal and output it through its output terminal; A DC blocking circuit (16), respectively connected to the output terminal of the clock generation circuit (15) and the second output terminal of the first reference voltage generation circuit (14), configured to perform DC blocking processing on the initial clock signal and transmit it to the second output terminal of the first reference voltage generation circuit (14) to generate a clock / voltage mixed signal after being superimposed with the initial reference voltage signal; A second transmission path (18), coupled to the second output terminal of the first reference voltage generation circuit (14), configured to transmit the clock / voltage mixed signal to be output from the first chip (51).

4. The data sending circuit (10) according to claim 3, characterized in that, When n = 2, the data combination includes a low-bit data signal and a high-bit data signal; Wherein, if the low-order data signal and the high-order data signal are a first signal value combination, the target data signal is a first voltage value; if the low-order data signal and the high-order data signal are a second signal value combination, the target data signal is a second voltage value; if the low-order data signal and the high-order data signal are a third signal value combination, the target data signal is a third voltage value; if the low-order data signal and the high-order data signal are a fourth signal value combination, the target data signal is a ground voltage; the first voltage value, the second voltage value, the third voltage value, and the ground voltage decrease in sequence.

5. The data sending circuit (10) according to claim 4, wherein the multi-level modulation circuit (12) includes a first logic unit (121), a first pull-up unit (122), a second pull-up unit (123), a third pull-up unit (124), and a pull-down unit (125); the multi-level modulation circuit (12) further includes a driving source node and an output node, and the driving source node receives the preset power signal; the first pull-up unit (122), the second pull-up unit (123), and the third pull-up unit (124) are connected in parallel between the driving source node and the output node; the pull-down unit (125) is connected in series between the output node and the ground terminal, and the output node is connected to the first transmission path (13); the first logic unit (121) is configured to perform an AND operation on the low-order data signal and the high-order data signal to generate a first control signal; perform a NOR operation on the low-order data signal and the high-order data signal to generate a second control signal; wherein, the first control signal is used to selectively turn on the first pull-up unit (122), the high-order data signal is used to selectively turn on the second pull-up unit (123), and the low-order data signal is used to selectively turn on the third pull-up unit (124), the second control signal is used to selectively turn on the pull-down unit (125), and the resistance values of the second pull-up unit (123) and the third pull-up unit (124) are different.

6. The data sending circuit (10) according to claim 5, characterized in that, The first pull-up unit (122) includes a first switching tube (211) and a first resistor (212) connected in series between the driving source node and the output node, the second pull-up unit (123) includes a second switching tube (213) and a second resistor (214) connected in series between the driving source node and the output node, the third pull-up unit (124) includes a third switching tube (215) and a third resistor (216) connected in series between the driving source node and the output node, and the pull-down unit (125) includes a fourth switching tube (217) and a fourth resistor (218) connected in series; The control terminal of the first switching transistor (211) receives the first control signal, the control terminal of the second switching transistor (213) receives the low-bit data signal, the control terminal of the third switching transistor (215) receives the high-bit data signal, and the control terminal of the fourth switching transistor (217) receives the second control signal.

7. The data sending circuit (10) according to claim 6, wherein The first voltage value: the second voltage value: the third voltage value = A: B: C; where A, B, and C are all positive integers, and A, B, and C decrease in sequence; (R 并 + R 下 ): (R2 + R 下 ): (R3 + R 下 ) = (1 / A) : (1 / B) : (1 / C); Among them, R 并 refers to the equivalent resistance formed by the parallel connection of the first resistor (212), the second resistor (214), and the third resistor (216). R 下 refers to the resistance value of the pull-down resistor (39) coupled to the first transmission path (13) in the data receiving circuit (30) corresponding to the data sending circuit (10). R2 refers to the resistance value of the second resistor (214), and R3 refers to the resistance value of the third resistor (216).

8. The data sending circuit (10) according to any one of claims 2-7, characterized in that, The first reference voltage generating circuit (14) includes a first operational amplifier (221), a fifth resistor (222), and a sixth resistor (223); The positive input terminal of the first operational amplifier (221) receives the reference voltage signal, the negative input terminal of the first operational amplifier (221) is connected to the output terminal of the first operational amplifier (221), and the output terminal of the first operational amplifier (221) serves as the first output terminal of the first reference voltage generating circuit (14) to output the preset power supply signal; The output terminal of the first operational amplifier (221) is connected to the first terminal of the fifth resistor (222), the second terminal of the fifth resistor (222) is connected to the first terminal of the sixth resistor (223), the second terminal of the sixth resistor (223) is connected to the ground terminal, and the second terminal of the fifth resistor (222) serves as the second output terminal of the first reference voltage generating circuit (14) to output the initial reference voltage signal.

9. The data sending circuit (10) according to any one of claims 3-8, wherein Both the first transmission path (13) and the second transmission path (18) include through-silicon vias.

10. A data receiving circuit (30), characterized in that, Applied to the second chip (52), the data receiving circuit (30) includes: A third transmission path (31) configured to receive the target data signal sent to the second chip (52); A data comparison circuit (32), coupled to the third transmission path (31), configured to receive (2 n -1) reference voltages and the target data signal, respectively compare the voltage values of each reference voltage and the target data signal, and generate and output (2 n -1) comparison signals; The logic processing circuit (33), coupled to the data comparison circuit (32), is configured to perform logic processing on (2 n -1) comparison signals to generate and output a data combination; wherein each data combination includes n data signals, and n is an integer greater than 1.

11. The data receiving circuit (30) according to claim 10, characterized in that, The data receiving circuit (30) further includes: A fourth transmission path (34) configured to receive the clock / voltage mixed signal sent to the second chip (52); A clock receiver (35) coupled to the fourth transmission path (34), configured to receive the clock reference voltage and the clock / voltage mixed signal reference voltage, and compare the clock / voltage mixed signal with the clock reference voltage to generate and output a reference clock signal; A clock processing circuit (36) connected to the clock receiver (35), configured to receive the reference clock signal, and after processing the reference clock signal, generate and output a sampling clock signal; The logic processing circuit (33) is further connected to the clock processing circuit (36), configured to be based on The sampling clock signal samples (2 n - 1) comparison signals respectively, and performs a logical operation based on the sampling result to generate the data combination.

12. The data receiving circuit (30) according to claim 11, wherein, The data receiving circuit (30) further includes: A low-pass filter (37) configured to receive the clock / voltage mixed signal, filter the clock / voltage mixed signal, and generate an initial reference voltage; A second reference voltage generation circuit (38) configured to generate (2 n - 1) reference voltages based on the initial reference voltage.

13. The data receiving circuit (30) according to claim 12, wherein The data receiving circuit (30) further includes a pull-down resistor (39); The first end of the pull - down resistor (39) is connected to the third transmission path (31), and the second end of the pull - down resistor (39) is connected to the ground terminal.

14. The data receiving circuit (30) according to claim 12 or 13, characterized in that, In the case of n = 2, (2 n - 1) reference voltages are respectively referred to as a first reference voltage, a second reference voltage, and a third reference voltage, and (2 n - 1) comparison signals are respectively referred to as a first comparison signal, a second comparison signal, and a third comparison signal; The voltage value of the first reference voltage is between the first voltage value and the second voltage value, the voltage value of the second reference voltage is between the second voltage value and the third voltage value, and the voltage value of the third reference voltage is between the third voltage value and the ground voltage; the first voltage value, the second voltage value, and the third voltage value decrease in sequence; The logic processing circuit (33) is specifically configured such that if the first comparison signal indicates that the voltage value of the target data signal is greater than or equal to the voltage value of the first reference voltage, then the 2 - bit data signal of the data combination is the first signal value combination; or, if the first comparison signal indicates that the voltage value of the target data signal is less than the voltage value of the first reference voltage and the second comparison signal indicates that the voltage value of the target data signal is greater than or equal to the voltage value of the second reference voltage, then the 2 - bit data signal of the data combination is the second signal value combination; or, if the second comparison signal indicates that the voltage value of the target data signal is less than the voltage value of the second reference voltage and the third comparison signal indicates that the voltage value of the target data signal is greater than or equal to the voltage value of the third reference voltage, then the 2 - bit data signal of the data combination is the third signal value combination; or, if the third comparison signal indicates that the voltage value of the target data signal is less than the voltage value of the third reference voltage, then the 2 - bit data signal of the data combination is the fourth signal value combination.

15. The data receiving circuit (30) according to claim 14, characterized in that, The second reference voltage generation circuit (38) includes a second operational amplifier (381), a seventh resistor (382), an eighth resistor (383), a ninth resistor (384), and a tenth resistor (385); The positive input terminal of the second operational amplifier (381) receives the initial reference voltage, the output terminal of the second operational amplifier (381) is connected to the first end of the seventh resistor (382), and the negative input terminal of the second operational amplifier (381) is connected to the second end of the eighth resistor (383); The second end of the seventh resistor (382) is connected to the first end of the eighth resistor (383), the second end of the eighth resistor (383) is connected to the first end of the ninth resistor (384), the second end of the ninth resistor (384) is connected to the first end of the tenth resistor (385), and the second end of the tenth resistor (385) is connected to the ground terminal; The second end of the seventh resistor (382) outputs the first reference voltage, the second end of the eighth resistor (383) outputs the second reference voltage, and the second end of the ninth resistor (384) outputs the third reference voltage.

16. The data receiving circuit (30) according to claim 15, wherein the second reference voltage is the same as the initial reference voltage, and the clock reference voltage is the same voltage as the second reference voltage; Both the third transmission path (31) and the fourth transmission path (34) include through-silicon vias.

17. An electronic device (50), characterized in that, The electronic device (50) includes a first chip (51) and a second chip (52). The first chip (51) includes the data sending circuit (10) as described in any one of claims 1-9, and the second chip (52) includes the data receiving circuit (30) as described in any one of claims 10-16.

18. The electronic device (50) according to claim 17, characterized in that, The first chip (51) is a logic signal / memory chip, and the second chip (52) is a memory chip / logic chip. The first chip (51) and the second chip (52) are stacked along a first direction, and the first direction is perpendicular to the top surface of the chip. The electronic device (50) is a stacked memory.

19. The electronic device (50) according to claim 18, wherein The through-silicon vias in the first transmission path (13) in the first chip (51) and the through-silicon vias in the third transmission path (31) in the second chip (52) are aligned along the first direction and form a transmission path for the target data signal. The through-silicon vias in the second transmission path (18) in the first chip (51) and the through-silicon vias in the fourth transmission path (34) in the second chip (52) are aligned along the first direction and form a transmission path for the clock / voltage mixed signal.

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